/*
 * This devicetree is generated by sopc2dts on Thu Feb 21 05:30:39 EET 2013
 * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
 * in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
 */
/dts-v1/;

/ {
	model = "ALTR,sam_sys";
	compatible = "ALTR,sam_sys";
	#address-cells = < 1 >;
	#size-cells = < 1 >;

	cpus {
		#address-cells = < 1 >;
		#size-cells = < 0 >;

		sam_cpu: cpu@0x0 {
			device_type = "cpu";
			compatible = "ALTR,nios2-11.1";
			reg = < 0x00000000 >;
			interrupt-controller;
			#interrupt-cells = < 1 >;
			clock-frequency = < 50000000 >;	/* embeddedsw.CMacro.CPU_FREQ type NUMBER */
			dcache-line-size = < 32 >;	/* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */
			icache-line-size = < 32 >;	/* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */
			dcache-size = < 2048 >;	/* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */
			icache-size = < 4096 >;	/* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */
			ALTR,implementation = "fast";	/* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/
			ALTR,pid-num-bits = < 8 >;	/* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */
			ALTR,tlb-num-ways = < 16 >;	/* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */
			ALTR,tlb-num-entries = < 256 >;	/* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */
			ALTR,tlb-ptr-sz = < 8 >;	/* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */
			ALTR,has-mul;	/* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/
			ALTR,reset-addr = < 0xc8001000 >;	/* embeddedsw.CMacro.RESET_ADDR type NUMBER */
			ALTR,fast-tlb-miss-addr = < 0xc8003000 >;	/* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */
			ALTR,exception-addr = < 0xc8001020 >;	/* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */
		}; //end cpu@0x0 (sam_cpu)
	}; //end cpus

	memory@0 {
		device_type = "memory";
		reg = < 0x08003000 0x00000400
			0x08001000 0x00001000
			0x00000000 0x08000000 >;
	}; //end memory@0

	sopc@0 {
		device_type = "soc";
		ranges;
		#address-cells = < 1 >;
		#size-cells = < 1 >;
		compatible = "ALTR,avalon", "simple-bus";
		bus-frequency = < 50000000 >;

		jtag_uart: serial@0x8003460 {
			compatible = "ALTR,juart-11.1", "ALTR,juart-1.0";
			reg = < 0x08003460 0x00000008 >;
			interrupt-parent = < &sam_cpu >;
			interrupts = < 0 >;
		}; //end serial@0x8003460 (jtag_uart)

		timer: timer@0x8003400 {
			compatible = "ALTR,timer-11.1", "ALTR,timer-1.0";
			reg = < 0x08003400 0x00000020 >;
			interrupt-parent = < &sam_cpu >;
			interrupts = < 1 >;
			clock-frequency = < 50000000 >;
		}; //end timer@0x8003400 (timer)

		uart: serial@0x8003420 {
			compatible = "ALTR,uart-11.1", "ALTR,uart-1.0";
			reg = < 0x08003420 0x00000020 >;
			interrupt-parent = < &sam_cpu >;
			interrupts = < 3 >;
			current-speed = < 115200 >;	/* embeddedsw.CMacro.BAUD type NUMBER */
			clock-frequency = < 50000000 >;	/* embeddedsw.CMacro.FREQ type NUMBER */
		}; //end serial@0x8003420 (uart)

		spi: spi@0x8003440 {
			compatible = "ALTR,spi-11.1", "ALTR,spi-1.0";
			reg = < 0x08003440 0x00000020 >;
			interrupt-parent = < &sam_cpu >;
			interrupts = < 2 >;
			#address-cells = < 1 >;
			#size-cells = < 0 >;

			mmc-slot@0 {
				compatible = "mmc-spi-slot";
				spi-max-frequency = < 30000000 >;
				reg = < 0x00000000 >;
				voltage-ranges = < 0x0c80 0x0d48 >;
			}; //end mmc-slot@0
		}; //end spi@0x8003440 (spi)

		led_component: unknown@0x8003468 {
			compatible = "unknown,unknown-1.0";
			reg = < 0x08003468 0x00000002 >;
		}; //end unknown@0x8003468 (led_component)
	}; //end sopc@0

	chosen {
		bootargs = "debug console=ttyAL0,115200";
	}; //end chosen
}; //end /