]]> M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0 ]]> cpu.jtag_debug_module Dedicated memory clock phase: Fix read latency at: cycles (0 cycles=minimum latency, non-deterministic) Micron MT47H32M16CC-3 Manual SR Reference (SRT) INTERACTIVE_ASCII_OUTPUT unassigned=unassigned