#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk_clk}] #************************************************************** # Create Generated Clock #************************************************************** create_generated_clock -name {pll|sd1|pll7|clk[0]} -source [get_pins {pll|sd1|pll7|inclk[0]}] -duty_cycle 50.000 -multiply_by 3 -divide_by 2 -master_clock {clk} [get_pins {pll|sd1|pll7|clk[0]}] create_generated_clock -name {pll|sd1|pll7|clk[1]} -source [get_pins {pll|sd1|pll7|inclk[0]}] -duty_cycle 50.000 -multiply_by 3 -divide_by 2 -phase -90.000 -master_clock {clk} [get_pins {pll|sd1|pll7|clk[1]}] create_generated_clock -name {ssram_clk} -source [get_pins {pll|sd1|pll7|clk[1]}] -multiply_by 1 [get_ports {ssram_clk_clk}] #************************************************************** # Set Clock Latency #************************************************************** #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {reset_reset_n}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_ssram_byteenable_n*}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_ssram_byteenable_n*}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_ssram_chipselect_n}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_ssram_chipselect_n}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_ssram_reset_n}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_ssram_reset_n}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[0]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[0]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[1]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[1]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[2]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[2]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[3]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[3]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[4]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[4]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[5]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[5]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[6]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[6]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[7]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[7]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[8]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[8]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[9]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[9]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[10]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[10]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[11]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[11]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[12]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[12]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[13]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[13]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[14]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[14]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[15]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[15]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[16]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[16]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[17]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[17]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[18]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[18]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[19]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[19]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[20]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[20]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[21]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[21]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[22]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[22]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[23]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[23]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[24]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[24]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[25]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[25]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[26]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[26]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[27]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[27]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[28]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[28]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[29]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[29]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[30]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[30]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.000 [get_ports {tristate_bus_data[31]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_data[31]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_ssram_write_n}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_ssram_write_n}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_ssram_outputenable_n}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_ssram_outputenable_n}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_ssram_begintransfer_n}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_ssram_begintransfer_n}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_address[0]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_address[1]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_address[2]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_address[3]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_address[4]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_address[5]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_address[6]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_address[7]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_address[8]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_address[9]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_address[10]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_address[11]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_address[12]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_address[13]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_address[14]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_address[15]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_address[16]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_address[17]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_address[18]}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_address[19]}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_flash_read_n}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_flash_read_n}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_flash_write_n}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_flash_write_n}] set_input_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_flash_chipselect_n}] set_input_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_flash_chipselect_n}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.700 [get_ports {tristate_bus_ssram_byteenable_n*}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_ssram_byteenable_n*}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.700 [get_ports {tristate_bus_ssram_chipselect_n}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_ssram_chipselect_n}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.700 [get_ports {tristate_bus_ssram_reset_n}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_ssram_reset_n}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[0]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[0]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[1]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[1]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[2]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[2]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[3]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[3]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[4]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[4]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[5]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[5]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[6]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[6]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[7]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[7]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[8]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[8]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[9]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[9]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[10]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[10]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[11]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[11]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[12]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[12]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[13]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[13]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[14]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[14]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[15]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[15]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[16]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[16]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[17]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[17]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[18]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[18]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[19]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[19]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[20]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[20]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[21]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[21]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[22]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[22]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[23]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[23]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[24]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[24]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[25]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[25]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[26]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[26]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[27]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[27]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[28]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[28]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[29]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[29]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[30]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[30]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.000 [get_ports {tristate_bus_data[31]}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_data[31]}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.700 [get_ports {tristate_bus_ssram_write_n}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_ssram_write_n}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.700 [get_ports {tristate_bus_ssram_outputenable_n}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_ssram_outputenable_n}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.700 [get_ports {tristate_bus_ssram_begintransfer_n}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_ssram_begintransfer_n}] set_output_delay -add_delay -max -clock [get_clocks {ssram_clk}] 1.700 [get_ports {tristate_bus_address*}] set_output_delay -add_delay -min -clock [get_clocks {ssram_clk}] 0.700 [get_ports {tristate_bus_address*}] set_output_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_flash_read_n}] set_output_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_flash_read_n}] set_output_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_flash_write_n}] set_output_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_flash_write_n}] set_output_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {tristate_bus_flash_chipselect_n}] set_output_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {tristate_bus_flash_chipselect_n}] set_output_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {status_leds_export*}] set_output_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {status_leds_export*}] set_output_delay -add_delay -max -clock [get_clocks {clk}] 1.700 [get_ports {my_pwm_export*}] set_output_delay -add_delay -min -clock [get_clocks {clk}] 0.700 [get_ports {my_pwm_export*}] set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {ssram_clk_clk}] #************************************************************** # Set Clock Groups #************************************************************** #************************************************************** # Set False Path #************************************************************** set_false_path -from [get_ports {reset_reset_n}] set_false_path -from [get_ports {push*}] #************************************************************** # Set Multicycle Path #************************************************************** #************************************************************** # Set Maximum Delay #************************************************************** #************************************************************** # Set Minimum Delay #************************************************************** #************************************************************** # Set Input Transition #************************************************************** #************************************************************** # JTAG Constraints (copied directly from TimeQuest Cookbook) #************************************************************** # Constrain the TCK port create_clock -name tck -period "10MHz" [get_ports altera_reserved_tck] -add # # Cut all paths to and from tck set_clock_groups -group [get_clocks tck] -exclusive # # Constrain the TDI port set_input_delay -clock tck 20 [get_ports altera_reserved_tdi] # # Constrain the TMS port set_input_delay -clock tck 20 [get_ports altera_reserved_tms] # # Constrain the TDO port set_output_delay -clock tck 20 [get_ports altera_reserved_tdo]