//Instantiate NiosII core nios2_core.v //Need Altera NiosII license. //If don't have license, can still generate a time limited SOF file. nios2_core i_nios2_core( // 1) global signals: .altpll_0_c0(CLK50), //PLL output. For NiosII processor and other peripherals on Avalon bus. .pxi_clk_i(CLK10), //PLL input. .reset_n(mstr_resetn), //PLL input. // the_altpll_0 .locked_from_the_altpll_0(pll_locked), //Indicate PLL is locked. .phasedone_from_the_altpll_0(altpll_phasedone), //Phase adj is complete. Ready for next phase step. // the_tri_state_bridge_0_avalon_slave .read_n_to_the_cfi_flash_0(flash_oe_n), .select_n_to_the_cfi_flash_0(flash_ce_n), .tri_state_bridge_0_address(flash_adr[23:0]), //Output address(23:0) .tri_state_bridge_0_data(flash_data), //Bidir data(15:0) .write_n_to_the_cfi_flash_0(flash_we_n) ); //Instantiate SOPC Builder's Common Flash Interface core flash_cfi.v. flash_cfi i_flash_cfi ( // 1) global signals: .LCLK_IN(CLK50), //Clock input. For PC host rd/wr interface. .slow_clk_in(CLK50), //Clock input. For Avalon bus. .reset_n(1'b1), //Reset input. // the_flash_rd_mm_master .control_done_from_the_flash_rd_mm_master(flash_rdone), //Indicate read is done. .control_early_done_from_the_flash_rd_mm_master(flash_early_rdone), //Indicate read is done. .control_fixed_location_to_the_flash_rd_mm_master(1'b0), //When set master address will not increment. .control_go_to_the_flash_rd_mm_master(RD_START_RISE), //Single clk pulse. Tell state machine to start reading. .control_read_base_to_the_flash_rd_mm_master(CFI_RD_ADR[23:0]), //Starting address for read. Bit 0 is ignored. .control_read_length_to_the_flash_rd_mm_master(CFI_RD_LEN[23:0]), //For burst, set burst length to max and then terminate early by asserting reset. .user_buffer_output_data_from_the_flash_rd_mm_master(flash_rdat[15:0]), //Read data. .user_data_available_from_the_flash_rd_mm_master(flash_rdat_avail), //Indicate read data is available. .user_read_buffer_to_the_flash_rd_mm_master(FLASH_BUF_RDEN), //Read enable. // the_flash_wr_mm_master .control_done_from_the_flash_wr_mm_master(flash_wdone), //Indicate write is done. .control_fixed_location_to_the_flash_wr_mm_master(1'b0), //When set master address will not increment. .control_go_to_the_flash_wr_mm_master(WR_START_RISE), //Single clk pulse. Tell state machine to start writing. .control_write_base_to_the_flash_wr_mm_master(CFI_WR_ADR[23:0]), //Starting address for write. Bit 0 is ignored. .control_write_length_to_the_flash_wr_mm_master(CFI_WR_LEN[23:0]), //For burst, set burst length to max and then terminate early by asserting reset. .user_buffer_full_from_the_flash_wr_mm_master(flash_wrbuf_full), //Indicate write buffer is full. .user_buffer_input_data_to_the_flash_wr_mm_master(CFI_WR_DAT), //Write data. .user_write_buffer_to_the_flash_wr_mm_master(CFI_WR_DV), //Write enable. // the_tri_state_bridge_0_avalon_slave. Make sure SOPC Builder settings for access timings are correct for the flash device, check datasheet. .read_n_to_the_cfi_flash_0(flash_oe_n), .select_n_to_the_cfi_flash_0(flash_ce_n), .tri_state_bridge_0_address(flash_adr[23:0]), //Output address(23:0) .tri_state_bridge_0_data(flash_data[15:0]), //Bidir data(15:0) .write_n_to_the_cfi_flash_0(flash_we_n) );