Compiler Command: aoc -o /tmp/simple-add-buffers-0b9718-3ae541.aocx /tmp/icpx-339ce2e70d/simple-add-buffers-7d4799-7d8bfc.spv -sycl -dep-files=/tmp/icpx-339ce2e70d/simple-add-buffers.cpp-808f36.d -output-report-folder=../simple-add-buffers.fpga_sim.prj -g -simulation -ghdl -target=Agilex5
***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries.  Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at
http://fpgasoftware.intel.com/eula.
***************************************************************

2025.03.29.00:48:12 Info: Doing: qsys-script --search-path=../../,$ --quartus-project=none --script=kernel_system.tcl --Xmx512M --XX:+UseSerialGC
2025.03.29.00:48:17 Info: set_validation_property AUTOMATIC_VALIDATION false
2025.03.29.00:48:17 Info: add_instance clk_1x altera_clock_bridge
2025.03.29.00:48:18 Info: set_instance_parameter_value clk_1x EXPLICIT_CLOCK_RATE 0
2025.03.29.00:48:18 Info: set_instance_parameter_value clk_1x NUM_CLOCK_OUTPUTS 1
2025.03.29.00:48:18 Info: add_interface clock_reset clock sink
2025.03.29.00:48:18 Info: set_interface_property clock_reset EXPORT_OF clk_1x.in_clk
2025.03.29.00:48:18 Info: add_instance reset altera_reset_bridge
2025.03.29.00:48:18 Info: set_instance_parameter_value reset ACTIVE_LOW_RESET 1
2025.03.29.00:48:18 Info: set_instance_parameter_value reset SYNCHRONOUS_EDGES deassert
2025.03.29.00:48:18 Info: set_instance_parameter_value reset NUM_RESET_OUTPUTS 1
2025.03.29.00:48:18 Info: add_interface clock_reset_reset reset sink
2025.03.29.00:48:18 Info: set_interface_property clock_reset_reset EXPORT_OF reset.in_reset
2025.03.29.00:48:18 Info: add_connection clk_1x.out_clk reset.clk
2025.03.29.00:48:18 Info: add_instance simple_add_buffers_fpga_sim_sys simple_add_buffers_fpga_sim_sys
2025.03.29.00:48:18 Info: add_connection clk_1x.out_clk simple_add_buffers_fpga_sim_sys.clock_reset
2025.03.29.00:48:18 Info: add_connection reset.out_reset simple_add_buffers_fpga_sim_sys.clock_reset_reset
2025.03.29.00:48:18 Info: add_interface mem0_rw avalon end
2025.03.29.00:48:18 Info: set_interface_property mem0_rw EXPORT_OF simple_add_buffers_fpga_sim_sys.avm_mem_gmem0_0_port_0_0_rw
2025.03.29.00:48:18 Info: add_instance kernel_irq altera_irq_bridge
2025.03.29.00:48:18 Info: set_instance_parameter_value kernel_irq IRQ_WIDTH 1
2025.03.29.00:48:18 Info: set_instance_parameter_value kernel_irq IRQ_N 0
2025.03.29.00:48:18 Info: add_interface kernel_irq irq sender
2025.03.29.00:48:18 Info: set_interface_property kernel_irq EXPORT_OF kernel_irq.sender0_irq
2025.03.29.00:48:18 Info: add_connection clk_1x.out_clk kernel_irq.clk
2025.03.29.00:48:18 Info: add_connection reset.out_reset kernel_irq.clk_reset
2025.03.29.00:48:18 Info: add_connection kernel_irq.receiver_irq simple_add_buffers_fpga_sim_sys.kernel_irq
2025.03.29.00:48:18 Info: add_instance kernel_cra altera_avalon_mm_bridge
2025.03.29.00:48:18 Info: set_instance_parameter_value kernel_cra DATA_WIDTH 64
2025.03.29.00:48:18 Info: set_instance_parameter_value kernel_cra SYMBOL_WIDTH 8
2025.03.29.00:48:18 Info: set_instance_parameter_value kernel_cra ADDRESS_WIDTH 30
2025.03.29.00:48:18 Info: set_instance_parameter_value kernel_cra USE_AUTO_ADDRESS_WIDTH 0
2025.03.29.00:48:18 Info: set_instance_parameter_value kernel_cra ADDRESS_UNITS SYMBOLS
2025.03.29.00:48:18 Info: set_instance_parameter_value kernel_cra MAX_BURST_SIZE 1
2025.03.29.00:48:18 Info: set_instance_parameter_value kernel_cra MAX_PENDING_RESPONSES 1
2025.03.29.00:48:18 Info: set_instance_parameter_value kernel_cra LINEWRAPBURSTS 0
2025.03.29.00:48:18 Info: set_instance_parameter_value kernel_cra PIPELINE_COMMAND 0
2025.03.29.00:48:18 Info: set_instance_parameter_value kernel_cra PIPELINE_RESPONSE 0
2025.03.29.00:48:18 Info: add_connection clk_1x.out_clk kernel_cra.clk
2025.03.29.00:48:18 Info: add_connection reset.out_reset kernel_cra.reset
2025.03.29.00:48:18 Info: add_interface avs_kernel_cra avalon end
2025.03.29.00:48:18 Info: set_interface_property kernel_cra EXPORT_OF kernel_cra.s0
2025.03.29.00:48:18 Info: add_connection kernel_cra.m0 simple_add_buffers_fpga_sim_sys.csr_ring_root_avs
2025.03.29.00:48:18 Info: set_connection_parameter_value kernel_cra.m0/simple_add_buffers_fpga_sim_sys.csr_ring_root_avs baseAddress 0x0
2025.03.29.00:48:18 Info: save_system kernel_system.qsys
2025.03.29.00:48:18 Info: Replacing kernel_system.clk_1x with generic component
2025.03.29.00:48:19 Info: Replacing kernel_system.reset with generic component
2025.03.29.00:48:19 Info: Replacing kernel_system.simple_add_buffers_fpga_sim_sys with generic component
2025.03.29.00:48:19 Info: Replacing kernel_system.kernel_irq with generic component
2025.03.29.00:48:19 Info: Replacing kernel_system.kernel_cra with generic component
2025.03.29.00:48:19 Info: Info: All modules have been converted to Generic Components.
***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries.  Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at
http://fpgasoftware.intel.com/eula.
***************************************************************

2025.03.29.00:48:20 Info: Doing: qsys-script --quartus-project=none --script=aoc_create_msim_system.tcl --Xmx512M --XX:+UseSerialGC --cmd=set component_list const_lambda; set num_agent_interface 6; set host_iface_list mem0_rw; set agent_iface_list {}; set stream_intf_mapping {}; set host_pipe_mapping {}; set sycl_mode 1
2025.03.29.00:48:25 Info: create_system mpsim
2025.03.29.00:48:25 Info: add_instance clk_rst hls_sim_clock_reset
2025.03.29.00:48:25 Info: set_instance_parameter_value clk_rst RESET_CYCLE_HOLD 120
2025.03.29.00:48:25 Info: add_instance oirq aoc_sim_main_dpi_controller
2025.03.29.00:48:25 Info: add_instance ki kernel_interface
2025.03.29.00:48:26 Info: add_instance avmm_agent_cra_inst aoc_sim_mm_master_dpi_bfm
2025.03.29.00:48:26 Info: set_instance_parameter_value avmm_agent_cra_inst COMPONENT_NAME kernel_cra
2025.03.29.00:48:26 Info: set_instance_parameter_value avmm_agent_cra_inst IS_MAIN_CONTROLLER 1
2025.03.29.00:48:26 Info: set_instance_parameter_value avmm_agent_cra_inst KI_AV_ADDRESS_W 14
2025.03.29.00:48:26 Info: set_instance_parameter_value avmm_agent_cra_inst KI_AV_SYMBOL_W 8
2025.03.29.00:48:26 Info: set_instance_parameter_value avmm_agent_cra_inst KI_AV_NUMSYMBOLS 4
2025.03.29.00:48:26 Info: set_instance_parameter_value avmm_agent_cra_inst MBD_AV_ADDRESS_W 31
2025.03.29.00:48:26 Info: set_instance_parameter_value avmm_agent_cra_inst MBD_AV_SYMBOL_W 8
2025.03.29.00:48:26 Info: set_instance_parameter_value avmm_agent_cra_inst MBD_AV_NUMSYMBOLS 4
2025.03.29.00:48:26 Info: set_instance_parameter_value avmm_agent_cra_inst COMMAND_INITIAL_WAIT_CYCLES 1000
2025.03.29.00:48:26 Info: set_instance_parameter_value avmm_agent_cra_inst COMMAND_WAIT_CYCLES 200
2025.03.29.00:48:26 Info: set_instance_parameter_value avmm_agent_cra_inst COMMAND_READ_WRITE_CYCLES 4
2025.03.29.00:48:26 Info: set_instance_parameter_value avmm_agent_cra_inst NUM_COMPONENTS_WITH_CSR 1
2025.03.29.00:48:26 Info: add_instance ks kernel_system
2025.03.29.00:48:27 Info: add_connection clk_rst.clock oirq.clock
2025.03.29.00:48:27 Info: add_connection clk_rst.clock2x oirq.clock2x
2025.03.29.00:48:27 Info: add_connection clk_rst.reset oirq.reset
2025.03.29.00:48:27 Info: add_connection oirq.reset_ctrl clk_rst.reset_ctrl
2025.03.29.00:48:27 Info: add_connection clk_rst.clock ks.clock_reset
2025.03.29.00:48:27 Info: add_connection clk_rst.reset ks.clock_reset_reset
2025.03.29.00:48:27 Info: add_connection ki.kernel_cra ks.kernel_cra
2025.03.29.00:48:27 Info: add_connection ki.kernel_irq_from_kernel ks.kernel_irq
2025.03.29.00:48:27 Info: add_connection clk_rst.clock ki.clk
2025.03.29.00:48:27 Info: add_connection clk_rst.clock ki.kernel_clk
2025.03.29.00:48:27 Info: add_connection clk_rst.reset ki.reset
2025.03.29.00:48:27 Info: add_connection clk_rst.reset ki.sw_reset_in
2025.03.29.00:48:27 Info: add_connection clk_rst.clock avmm_agent_cra_inst.clock
2025.03.29.00:48:27 Info: add_connection clk_rst.reset avmm_agent_cra_inst.reset
2025.03.29.00:48:27 Info: auto_assign_irqs avmm_agent_cra_inst
2025.03.29.00:48:27 Info: add_connection avmm_agent_cra_inst.m_ki ki.ctrl
2025.03.29.00:48:27 Info: add_connection oirq.kernel_interrupt ki.kernel_irq_to_host
2025.03.29.00:48:27 Info: add_component split_component_csr_ready_inst sp_csr_ready.ip avalon_split_multibit_conduit sp_csr_ready
2025.03.29.00:48:27 Info: split_component_csr_ready_inst: Generic Component instance footprint reloaded.
2025.03.29.00:48:27 Info: load_component split_component_csr_ready_inst
2025.03.29.00:48:27 Info: set_component_parameter_value multibit_width 1
2025.03.29.00:48:27 Info: save_component 
2025.03.29.00:48:27 Info: add_connection avmm_agent_cra_inst.done_writes_to_cra split_component_csr_ready_inst.in_conduit
2025.03.29.00:48:27 Info: add_component concat_component_stall_inst cct_comp_stall.ip avalon_concatenate_singlebit_conduits cct_comp_stall
2025.03.29.00:48:27 Info: concat_component_stall_inst: Generic Component instance footprint reloaded.
2025.03.29.00:48:27 Info: load_component concat_component_stall_inst
2025.03.29.00:48:27 Info: set_component_parameter_value multibit_width 1
2025.03.29.00:48:27 Info: save_component 
2025.03.29.00:48:27 Info: add_connection avmm_agent_cra_inst.component_control_not_ready_in concat_component_stall_inst.out_conduit
2025.03.29.00:48:27 Info: add_component master_done_fanout_inst done_cfan.ip avalon_conduit_fanout done_cfan
2025.03.29.00:48:27 Info: master_done_fanout_inst: Generic Component instance footprint reloaded.
2025.03.29.00:48:27 Info: load_component master_done_fanout_inst
2025.03.29.00:48:27 Info: set_component_parameter_value numFanOut 1
2025.03.29.00:48:27 Info: save_component 
2025.03.29.00:48:27 Info: add_connection avmm_agent_cra_inst.sim_done master_done_fanout_inst.in_conduit
2025.03.29.00:48:27 Info: get_instance_interfaces ks
2025.03.29.00:48:27 Info: get_composed_instances ks
2025.03.29.00:48:27 Info: get_composed_instance_assignment ks simple_add_buffers_fpga_sim_sys ipa.report.names
2025.03.29.00:48:27 Info: get_composed_instance_assignment ks simple_add_buffers_fpga_sim_sys ipa.mangled.names
2025.03.29.00:48:27 Info: add_component component_dpi_controller_const_lambda_inst dpic_const_lambda.ip aoc_sim_component_dpi_controller dpic_const_lambda
2025.03.29.00:48:27 Info: component_dpi_controller_const_lambda_inst: Generic Component instance footprint reloaded.
2025.03.29.00:48:27 Info: add_connection clk_rst.clock component_dpi_controller_const_lambda_inst.clock
2025.03.29.00:48:27 Info: add_connection clk_rst.clock2x component_dpi_controller_const_lambda_inst.clock2x
2025.03.29.00:48:27 Info: add_connection clk_rst.reset component_dpi_controller_const_lambda_inst.reset
2025.03.29.00:48:27 Info: load_component component_dpi_controller_const_lambda_inst
2025.03.29.00:48:27 Info: set_component_parameter_value COMPONENT_NAME 'lambda'(auto)
2025.03.29.00:48:27 Info: set_component_parameter_value COMPONENT_MANGLED_NAME const_lambda
2025.03.29.00:48:27 Info: save_component 
2025.03.29.00:48:27 Info: add_component const_lambda_component_dpi_controller_enable_conduit_fanout_inst const_lambda_en_cfan.ip avalon_conduit_fanout const_lambda_en_cfan
2025.03.29.00:48:27 Info: const_lambda_component_dpi_controller_enable_conduit_fanout_inst: Generic Component instance footprint reloaded.
2025.03.29.00:48:27 Info: load_component const_lambda_component_dpi_controller_enable_conduit_fanout_inst
2025.03.29.00:48:27 Info: set_component_parameter_value numFanOut 0
2025.03.29.00:48:27 Info: save_component 
2025.03.29.00:48:27 Info: add_connection component_dpi_controller_const_lambda_inst.dpi_control_enable const_lambda_component_dpi_controller_enable_conduit_fanout_inst.in_conduit
2025.03.29.00:48:27 Info: load_component component_dpi_controller_const_lambda_inst
2025.03.29.00:48:27 Info: set_component_parameter_value COMPONENT_NUM_AGENTS 1
2025.03.29.00:48:27 Info: save_component 
2025.03.29.00:48:27 Info: add_connection split_component_csr_ready_inst.out_conduit_0 component_dpi_controller_const_lambda_inst.dpi_control_agents_ready
2025.03.29.00:48:27 Info: add_connection concat_component_stall_inst.in_conduit_0 component_dpi_controller_const_lambda_inst.master_stall
2025.03.29.00:48:27 Info: add_connection master_done_fanout_inst.out_conduit_0 component_dpi_controller_const_lambda_inst.master_done
2025.03.29.00:48:27 Info: get_instance_interfaces ks
2025.03.29.00:48:27 Info: get_instance_interfaces ks
2025.03.29.00:48:27 Info: get_instance_interface_property ks clock_reset CLASS_NAME
2025.03.29.00:48:27 Info: get_instance_interface_ports ks clock_reset
2025.03.29.00:48:27 Info: get_instance_interface_property ks kernel_cra CLASS_NAME
2025.03.29.00:48:27 Info: get_instance_interface_ports ks kernel_cra
2025.03.29.00:48:27 Info: get_instance_interface_property ks kernel_irq CLASS_NAME
2025.03.29.00:48:27 Info: get_instance_interface_ports ks kernel_irq
2025.03.29.00:48:27 Info: get_instance_interface_property ks clock_reset_reset CLASS_NAME
2025.03.29.00:48:27 Info: get_instance_interface_ports ks clock_reset_reset
2025.03.29.00:48:27 Info: get_instance_interface_property ks mem0_rw CLASS_NAME
2025.03.29.00:48:27 Info: get_instance_interface_ports ks mem0_rw
2025.03.29.00:48:27 Info: add_component osm_0_inst mm_agent_ks_mem0_rw.ip aoc_sim_mm_slave_dpi_bfm mm_agent_ks_mem0_rw
2025.03.29.00:48:27 Info: osm_0_inst: Generic Component instance footprint reloaded.
2025.03.29.00:48:27 Info: get_instance_interface_port_property ks mem0_rw mem0_rw_address WIDTH
2025.03.29.00:48:27 Info: get_instance_interface_port_property ks mem0_rw mem0_rw_readdata WIDTH
2025.03.29.00:48:27 Info: get_instance_interface_parameter_value ks mem0_rw readLatency
2025.03.29.00:48:27 Info: load_component osm_0_inst
2025.03.29.00:48:27 Info: set_component_parameter_value AV_FIX_READ_LATENCY 0
2025.03.29.00:48:27 Info: save_component 
2025.03.29.00:48:27 Info: get_instance_interface_port_property ks mem0_rw mem0_rw_byteenable WIDTH
2025.03.29.00:48:27 Info: get_instance_interface_parameter_value ks mem0_rw addressUnits
2025.03.29.00:48:27 Info: get_instance_interface_ports ks mem0_rw
2025.03.29.00:48:27 Info: get_instance_interface_port_property ks mem0_rw mem0_rw_burstcount WIDTH
2025.03.29.00:48:27 Info: load_component osm_0_inst
2025.03.29.00:48:27 Info: set_component_parameter_value AV_BURSTCOUNT_W 1
2025.03.29.00:48:27 Info: save_component 
2025.03.29.00:48:27 Info: load_component osm_0_inst
2025.03.29.00:48:27 Info: set_component_parameter_value INTERFACE_ID 0
2025.03.29.00:48:27 Info: set_component_parameter_value COMPONENT_NAME avs
2025.03.29.00:48:27 Info: set_component_parameter_value AV_ADDRESS_W 35
2025.03.29.00:48:27 Info: set_component_parameter_value AV_NUMSYMBOLS 8
2025.03.29.00:48:27 Info: set_component_parameter_value AV_SYMBOL_W 8
2025.03.29.00:48:27 Info: set_component_parameter_value ADDRESS_UNITS SYMBOLS
2025.03.29.00:48:27 Info: set_component_parameter_value USE_WAIT_REQUEST 1
2025.03.29.00:48:27 Info: set_component_parameter_value USE_BURSTCOUNT 1
2025.03.29.00:48:28 Info: set_component_parameter_value USE_READ_DATA_VALID 1
2025.03.29.00:48:28 Info: set_component_parameter_value USE_READ 1
2025.03.29.00:48:28 Info: set_component_parameter_value USE_READ_DATA 1
2025.03.29.00:48:28 Info: set_component_parameter_value USE_WRITE 1
2025.03.29.00:48:28 Info: set_component_parameter_value USE_WRITE_DATA 1
2025.03.29.00:48:28 Info: set_component_parameter_value USE_READ_DATA_VALID 1
2025.03.29.00:48:28 Info: set_component_parameter_value AV_MAX_PENDING_READS 256
2025.03.29.00:48:28 Info: save_component 
2025.03.29.00:48:28 Info: add_connection clk_rst.clock osm_0_inst.clock
2025.03.29.00:48:28 Info: add_connection clk_rst.reset osm_0_inst.reset
2025.03.29.00:48:28 Info: add_connection ks.mem0_rw osm_0_inst.s0
2025.03.29.00:48:28 Info: sync_sysinfo_parameters 
2025.03.29.00:48:28 Info: Synchronizing System Information for clk_1x
2025.03.29.00:48:28 Info: Synchronizing System Information for kernel_cra
2025.03.29.00:48:28 Info: Synchronizing System Information for kernel_irq
2025.03.29.00:48:28 Info: Synchronizing System Information for reset
2025.03.29.00:48:28 Info: Synchronizing System Information for simple_add_buffers_fpga_sim_sys
2025.03.29.00:48:28 Info: Synchronizing System Information for split_component_csr_ready_inst
2025.03.29.00:48:28 Info: Synchronizing System Information for concat_component_stall_inst
2025.03.29.00:48:28 Info: Synchronizing System Information for master_done_fanout_inst
2025.03.29.00:48:28 Info: Synchronizing System Information for component_dpi_controller_const_lambda_inst
2025.03.29.00:48:28 Info: Synchronizing System Information for const_lambda_component_dpi_controller_enable_conduit_fanout_inst
2025.03.29.00:48:28 Info: Synchronizing System Information for osm_0_inst
2025.03.29.00:48:28 Info: save_system mpsim
2025.03.29.00:48:28 Info: Replacing mpsim.clk_rst with generic component
2025.03.29.00:48:28 Info: Replacing mpsim.oirq with generic component
2025.03.29.00:48:28 Info: Replacing mpsim.ki with generic component
2025.03.29.00:48:28 Info: Replacing mpsim.avmm_agent_cra_inst with generic component
2025.03.29.00:48:28 Info: Info: All modules have been converted to Generic Components.
***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries.  Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at
http://fpgasoftware.intel.com/eula.
***************************************************************

2025.03.29.00:48:37 Info: Parallel IP Generation is enabled. 
2025.03.29.00:48:37 Info: Platform Designer will attempt to use 6 processors for parallel IP generation based on available number of processors and the total number of IP to be generated.
2025.03.29.00:48:37 Info: 
2025.03.29.00:48:37 Info: Starting: Platform Designer system generation
2025.03.29.00:49:01 Info: 
2025.03.29.00:49:01 Info: Generating on localhost:37475
2025.03.29.00:49:01 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:01 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x/kernel_system_clk_1x_generation.rpt
2025.03.29.00:49:01 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:01 Info: Starting: Create simulation model
2025.03.29.00:49:01 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:01 Info: kernel_system_clk_1x: "Transforming system: kernel_system_clk_1x"
2025.03.29.00:49:01 Info: kernel_system_clk_1x: "Naming system components in system: kernel_system_clk_1x"
2025.03.29.00:49:01 Info: kernel_system_clk_1x: "Processing generation queue"
2025.03.29.00:49:01 Info: kernel_system_clk_1x: "Generating: kernel_system_clk_1x"
2025.03.29.00:49:01 Info: kernel_system_clk_1x: Done "kernel_system_clk_1x" with 1 modules, 1 files
2025.03.29.00:49:01 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:01 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x/sim/ directory:
2025.03.29.00:49:01 Info: common/vcsmx_files.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x/sim/ directory:
2025.03.29.00:49:01 Info: common/modelsim_files.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x/sim/ directory:
2025.03.29.00:49:01 Info: common/xcelium_files.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x/sim/ directory:
2025.03.29.00:49:01 Info: common/riviera_files.tcl
2025.03.29.00:49:01 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x/sim/.
2025.03.29.00:49:01 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:01 Info: Finished: Create simulation model
2025.03.29.00:49:01 Info: Starting: Create simulation script
2025.03.29.00:49:01 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:01 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:01 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x/sim/ directory:
2025.03.29.00:49:01 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:01 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:01 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:01 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x/sim/ directory:
2025.03.29.00:49:01 Info: mentor/msim_setup.tcl
2025.03.29.00:49:01 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x/sim/ directory:
2025.03.29.00:49:01 Info: xcelium/cds.lib
2025.03.29.00:49:01 Info: xcelium/hdl.var
2025.03.29.00:49:01 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:01 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:01 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x/sim/ directory:
2025.03.29.00:49:01 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:01 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:01 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x/sim/.
2025.03.29.00:49:01 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:01 Info: Finished: Create simulation script
2025.03.29.00:49:01 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_clk_1x.ip (kernel_system_clk_1x) took 3601 ms
2025.03.29.00:49:01 Info: 
2025.03.29.00:49:01 Info: Generating on localhost:41565
2025.03.29.00:49:01 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:01 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall/cct_comp_stall_generation.rpt
2025.03.29.00:49:01 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:01 Info: Starting: Create simulation model
2025.03.29.00:49:01 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:01 Info: cct_comp_stall: "Transforming system: cct_comp_stall"
2025.03.29.00:49:01 Info: cct_comp_stall: "Naming system components in system: cct_comp_stall"
2025.03.29.00:49:01 Info: cct_comp_stall: "Processing generation queue"
2025.03.29.00:49:01 Info: cct_comp_stall: "Generating: cct_comp_stall"
2025.03.29.00:49:01 Info: cct_comp_stall: "Generating: cct_comp_stall_avalon_concatenate_singlebit_conduits_10_lrbideq"
2025.03.29.00:49:01 Info: cct_comp_stall: Done "cct_comp_stall" with 2 modules, 2 files
2025.03.29.00:49:01 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:01 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall/sim/ directory:
2025.03.29.00:49:01 Info: common/xcelium_files.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall/sim/ directory:
2025.03.29.00:49:01 Info: common/riviera_files.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall/sim/ directory:
2025.03.29.00:49:01 Info: common/vcsmx_files.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall/sim/ directory:
2025.03.29.00:49:01 Info: common/modelsim_files.tcl
2025.03.29.00:49:01 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall/sim/.
2025.03.29.00:49:01 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:01 Info: Finished: Create simulation model
2025.03.29.00:49:01 Info: Starting: Create simulation script
2025.03.29.00:49:01 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:01 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:01 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall/sim/ directory:
2025.03.29.00:49:01 Info: xcelium/cds.lib
2025.03.29.00:49:01 Info: xcelium/hdl.var
2025.03.29.00:49:01 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:01 Info: 3 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:01 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall/sim/ directory:
2025.03.29.00:49:01 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:01 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall/sim/ directory:
2025.03.29.00:49:01 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:01 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:01 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:01 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall/sim/ directory:
2025.03.29.00:49:01 Info: mentor/msim_setup.tcl
2025.03.29.00:49:01 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:01 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall/sim/.
2025.03.29.00:49:01 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:01 Info: Finished: Create simulation script
2025.03.29.00:49:01 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/cct_comp_stall.ip (cct_comp_stall) took 3378 ms
2025.03.29.00:49:01 Info: 
2025.03.29.00:49:01 Info: Generating on localhost:36235
2025.03.29.00:49:01 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:01 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda/dpic_const_lambda_generation.rpt
2025.03.29.00:49:01 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:01 Info: Starting: Create simulation model
2025.03.29.00:49:01 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:01 Warning: dpic_const_lambda.dpic_const_lambda.dpi_control_stream_writes_active: Interface has no signals
2025.03.29.00:49:01 Info: dpic_const_lambda: "Transforming system: dpic_const_lambda"
2025.03.29.00:49:01 Info: dpic_const_lambda: "Naming system components in system: dpic_const_lambda"
2025.03.29.00:49:01 Info: dpic_const_lambda: "Processing generation queue"
2025.03.29.00:49:01 Info: dpic_const_lambda: "Generating: dpic_const_lambda"
2025.03.29.00:49:01 Info: dpic_const_lambda: "Generating: aoc_sim_component_dpi_controller"
2025.03.29.00:49:01 Info: dpic_const_lambda: Done "dpic_const_lambda" with 2 modules, 4 files
2025.03.29.00:49:01 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:01 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda/sim/ directory:
2025.03.29.00:49:01 Info: common/modelsim_files.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda/sim/ directory:
2025.03.29.00:49:01 Info: common/vcsmx_files.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda/sim/ directory:
2025.03.29.00:49:01 Info: common/riviera_files.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda/sim/ directory:
2025.03.29.00:49:01 Info: common/xcelium_files.tcl
2025.03.29.00:49:01 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda/sim/.
2025.03.29.00:49:01 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:01 Info: Finished: Create simulation model
2025.03.29.00:49:01 Info: Starting: Create simulation script
2025.03.29.00:49:01 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:01 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:01 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda/sim/ directory:
2025.03.29.00:49:01 Info: mentor/msim_setup.tcl
2025.03.29.00:49:01 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda/sim/ directory:
2025.03.29.00:49:01 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:01 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:01 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:01 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda/sim/ directory:
2025.03.29.00:49:01 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:01 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:01 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda/sim/ directory:
2025.03.29.00:49:01 Info: xcelium/cds.lib
2025.03.29.00:49:01 Info: xcelium/hdl.var
2025.03.29.00:49:01 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:01 Info: 3 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:01 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda/sim/.
2025.03.29.00:49:01 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:01 Info: Finished: Create simulation script
2025.03.29.00:49:01 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/dpic_const_lambda.ip (dpic_const_lambda) took 3534 ms
2025.03.29.00:49:02 Info: 
2025.03.29.00:49:02 Info: Generating on localhost:43601
2025.03.29.00:49:02 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:02 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst/mpsim_avmm_agent_cra_inst_generation.rpt
2025.03.29.00:49:02 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:02 Info: Starting: Create simulation model
2025.03.29.00:49:02 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:02 Info: mpsim_avmm_agent_cra_inst: "Transforming system: mpsim_avmm_agent_cra_inst"
2025.03.29.00:49:02 Info: mpsim_avmm_agent_cra_inst: "Naming system components in system: mpsim_avmm_agent_cra_inst"
2025.03.29.00:49:02 Info: mpsim_avmm_agent_cra_inst: "Processing generation queue"
2025.03.29.00:49:02 Info: mpsim_avmm_agent_cra_inst: "Generating: mpsim_avmm_agent_cra_inst"
2025.03.29.00:49:02 Info: mpsim_avmm_agent_cra_inst: "Generating: aoc_sim_mm_master_dpi_bfm"
2025.03.29.00:49:02 Info: /home/yazan/intelFPGA_pro/24.3.1/quartus
2025.03.29.00:49:02 Info: /home/yazan/intelFPGA_pro/24.3.1/quartus/../ip/altera/sopc_builder_ip/verification/
2025.03.29.00:49:02 Info: mpsim_avmm_agent_cra_inst: Done "mpsim_avmm_agent_cra_inst" with 2 modules, 6 files
2025.03.29.00:49:02 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:02 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst/sim/ directory:
2025.03.29.00:49:02 Info: common/xcelium_files.tcl
2025.03.29.00:49:02 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst/sim/ directory:
2025.03.29.00:49:02 Info: common/riviera_files.tcl
2025.03.29.00:49:02 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst/sim/ directory:
2025.03.29.00:49:02 Info: common/modelsim_files.tcl
2025.03.29.00:49:02 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst/sim/ directory:
2025.03.29.00:49:02 Info: common/vcsmx_files.tcl
2025.03.29.00:49:02 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst/sim/.
2025.03.29.00:49:02 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:02 Info: Finished: Create simulation model
2025.03.29.00:49:02 Info: Starting: Create simulation script
2025.03.29.00:49:02 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:02 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:02 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst/sim/ directory:
2025.03.29.00:49:02 Info: xcelium/cds.lib
2025.03.29.00:49:02 Info: xcelium/hdl.var
2025.03.29.00:49:02 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:02 Info: 4 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:02 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst/sim/ directory:
2025.03.29.00:49:02 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:02 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:02 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst/sim/ directory:
2025.03.29.00:49:02 Info: mentor/msim_setup.tcl
2025.03.29.00:49:02 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:02 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst/sim/ directory:
2025.03.29.00:49:02 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:02 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:02 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:02 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst/sim/.
2025.03.29.00:49:02 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:02 Info: Finished: Create simulation script
2025.03.29.00:49:02 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_avmm_agent_cra_inst.ip (mpsim_avmm_agent_cra_inst) took 3293 ms
2025.03.29.00:49:03 Info: 
2025.03.29.00:49:03 Info: Generating on localhost:36235
2025.03.29.00:49:03 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:03 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst/mpsim_clk_rst_generation.rpt
2025.03.29.00:49:03 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:03 Info: Starting: Create simulation model
2025.03.29.00:49:03 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:03 Info: mpsim_clk_rst: "Transforming system: mpsim_clk_rst"
2025.03.29.00:49:03 Info: mpsim_clk_rst: "Naming system components in system: mpsim_clk_rst"
2025.03.29.00:49:03 Info: mpsim_clk_rst: "Processing generation queue"
2025.03.29.00:49:03 Info: mpsim_clk_rst: "Generating: mpsim_clk_rst"
2025.03.29.00:49:03 Info: mpsim_clk_rst: "Generating: hls_sim_clock_reset"
2025.03.29.00:49:03 Info: mpsim_clk_rst: Done "mpsim_clk_rst" with 2 modules, 2 files
2025.03.29.00:49:03 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:03 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst/sim/ directory:
2025.03.29.00:49:03 Info: common/modelsim_files.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst/sim/ directory:
2025.03.29.00:49:03 Info: common/vcsmx_files.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst/sim/ directory:
2025.03.29.00:49:03 Info: common/riviera_files.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst/sim/ directory:
2025.03.29.00:49:03 Info: common/xcelium_files.tcl
2025.03.29.00:49:03 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst/sim/.
2025.03.29.00:49:03 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:03 Info: Finished: Create simulation model
2025.03.29.00:49:03 Info: Starting: Create simulation script
2025.03.29.00:49:03 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:03 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:03 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst/sim/ directory:
2025.03.29.00:49:03 Info: mentor/msim_setup.tcl
2025.03.29.00:49:03 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst/sim/ directory:
2025.03.29.00:49:03 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:03 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:03 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:03 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst/sim/ directory:
2025.03.29.00:49:03 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:03 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst/sim/ directory:
2025.03.29.00:49:03 Info: xcelium/cds.lib
2025.03.29.00:49:03 Info: xcelium/hdl.var
2025.03.29.00:49:03 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:03 Info: 3 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:03 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst/sim/.
2025.03.29.00:49:03 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:03 Info: Finished: Create simulation script
2025.03.29.00:49:03 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_clk_rst.ip (mpsim_clk_rst) took 2064 ms
2025.03.29.00:49:03 Info: 
2025.03.29.00:49:03 Info: Generating on localhost:37475
2025.03.29.00:49:03 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:03 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/kernel_system_simple_add_buffers_fpga_sim_sys_generation.rpt
2025.03.29.00:49:03 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:03 Info: Starting: Create simulation model
2025.03.29.00:49:03 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:03 Info: kernel_system_simple_add_buffers_fpga_sim_sys: "Transforming system: kernel_system_simple_add_buffers_fpga_sim_sys"
2025.03.29.00:49:03 Info: kernel_system_simple_add_buffers_fpga_sim_sys: "Naming system components in system: kernel_system_simple_add_buffers_fpga_sim_sys"
2025.03.29.00:49:03 Info: kernel_system_simple_add_buffers_fpga_sim_sys: "Processing generation queue"
2025.03.29.00:49:03 Info: kernel_system_simple_add_buffers_fpga_sim_sys: "Generating: kernel_system_simple_add_buffers_fpga_sim_sys"
2025.03.29.00:49:03 Info: kernel_system_simple_add_buffers_fpga_sim_sys: "Generating: simple_add_buffers_fpga_sim_sys"
2025.03.29.00:49:03 Info: kernel_system_simple_add_buffers_fpga_sim_sys: Done "kernel_system_simple_add_buffers_fpga_sim_sys" with 2 modules, 110 files
2025.03.29.00:49:03 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:03 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/sim/ directory:
2025.03.29.00:49:03 Info: common/vcsmx_files.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/sim/ directory:
2025.03.29.00:49:03 Info: common/modelsim_files.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/sim/ directory:
2025.03.29.00:49:03 Info: common/xcelium_files.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/sim/ directory:
2025.03.29.00:49:03 Info: common/riviera_files.tcl
2025.03.29.00:49:03 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/sim/.
2025.03.29.00:49:03 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:03 Info: Finished: Create simulation model
2025.03.29.00:49:03 Info: Starting: Create simulation script
2025.03.29.00:49:03 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:03 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:03 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/sim/ directory:
2025.03.29.00:49:03 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:03 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:03 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:03 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/sim/ directory:
2025.03.29.00:49:03 Info: mentor/msim_setup.tcl
2025.03.29.00:49:03 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/sim/ directory:
2025.03.29.00:49:03 Info: xcelium/cds.lib
2025.03.29.00:49:03 Info: xcelium/hdl.var
2025.03.29.00:49:03 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:03 Info: 3 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:03 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/sim/ directory:
2025.03.29.00:49:03 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:03 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:03 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/sim/.
2025.03.29.00:49:03 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:03 Info: Finished: Create simulation script
2025.03.29.00:49:03 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys.ip (kernel_system_simple_add_buffers_fpga_sim_sys) took 2250 ms
2025.03.29.00:49:03 Info: 
2025.03.29.00:49:03 Info: Generating on localhost:41565
2025.03.29.00:49:03 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:03 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq/kernel_system_kernel_irq_generation.rpt
2025.03.29.00:49:03 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:03 Info: Starting: Create simulation model
2025.03.29.00:49:03 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:03 Info: kernel_system_kernel_irq: "Transforming system: kernel_system_kernel_irq"
2025.03.29.00:49:03 Info: kernel_system_kernel_irq: "Naming system components in system: kernel_system_kernel_irq"
2025.03.29.00:49:03 Info: kernel_system_kernel_irq: "Processing generation queue"
2025.03.29.00:49:03 Info: kernel_system_kernel_irq: "Generating: kernel_system_kernel_irq"
2025.03.29.00:49:03 Info: kernel_system_kernel_irq: "Generating: kernel_system_kernel_irq_altera_irq_bridge_2000_mzhkeuq"
2025.03.29.00:49:03 Info: kernel_irq: 1
2025.03.29.00:49:03 Info: kernel_irq: irq_width
2025.03.29.00:49:03 Info: kernel_system_kernel_irq: Done "kernel_system_kernel_irq" with 2 modules, 2 files
2025.03.29.00:49:03 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:03 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq/sim/ directory:
2025.03.29.00:49:03 Info: common/xcelium_files.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq/sim/ directory:
2025.03.29.00:49:03 Info: common/riviera_files.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq/sim/ directory:
2025.03.29.00:49:03 Info: common/vcsmx_files.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq/sim/ directory:
2025.03.29.00:49:03 Info: common/modelsim_files.tcl
2025.03.29.00:49:03 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq/sim/.
2025.03.29.00:49:03 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:03 Info: Finished: Create simulation model
2025.03.29.00:49:03 Info: Starting: Create simulation script
2025.03.29.00:49:03 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:03 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:03 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq/sim/ directory:
2025.03.29.00:49:03 Info: xcelium/cds.lib
2025.03.29.00:49:03 Info: xcelium/hdl.var
2025.03.29.00:49:03 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:03 Info: 3 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:03 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq/sim/ directory:
2025.03.29.00:49:03 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:03 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:03 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq/sim/ directory:
2025.03.29.00:49:03 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:03 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:03 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:03 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq/sim/ directory:
2025.03.29.00:49:03 Info: mentor/msim_setup.tcl
2025.03.29.00:49:03 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:03 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq/sim/.
2025.03.29.00:49:03 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:03 Info: Finished: Create simulation script
2025.03.29.00:49:03 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_irq.ip (kernel_system_kernel_irq) took 2204 ms
2025.03.29.00:49:04 Info: 
2025.03.29.00:49:04 Info: Generating on localhost:43601
2025.03.29.00:49:04 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:04 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset/kernel_system_reset_generation.rpt
2025.03.29.00:49:04 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:04 Info: Starting: Create simulation model
2025.03.29.00:49:04 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:04 Info: kernel_system_reset: "Transforming system: kernel_system_reset"
2025.03.29.00:49:04 Info: kernel_system_reset: "Naming system components in system: kernel_system_reset"
2025.03.29.00:49:04 Info: kernel_system_reset: "Processing generation queue"
2025.03.29.00:49:04 Info: kernel_system_reset: "Generating: kernel_system_reset"
2025.03.29.00:49:04 Info: kernel_system_reset: Done "kernel_system_reset" with 1 modules, 1 files
2025.03.29.00:49:04 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:04 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset/sim/ directory:
2025.03.29.00:49:04 Info: common/xcelium_files.tcl
2025.03.29.00:49:04 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset/sim/ directory:
2025.03.29.00:49:04 Info: common/riviera_files.tcl
2025.03.29.00:49:04 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset/sim/ directory:
2025.03.29.00:49:04 Info: common/modelsim_files.tcl
2025.03.29.00:49:04 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset/sim/ directory:
2025.03.29.00:49:04 Info: common/vcsmx_files.tcl
2025.03.29.00:49:04 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset/sim/.
2025.03.29.00:49:04 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:04 Info: Finished: Create simulation model
2025.03.29.00:49:04 Info: Starting: Create simulation script
2025.03.29.00:49:04 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:04 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:04 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset/sim/ directory:
2025.03.29.00:49:04 Info: xcelium/cds.lib
2025.03.29.00:49:04 Info: xcelium/hdl.var
2025.03.29.00:49:04 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:04 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:04 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset/sim/ directory:
2025.03.29.00:49:04 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:04 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:04 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset/sim/ directory:
2025.03.29.00:49:04 Info: mentor/msim_setup.tcl
2025.03.29.00:49:04 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:04 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset/sim/ directory:
2025.03.29.00:49:04 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:04 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:04 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:04 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset/sim/.
2025.03.29.00:49:04 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:04 Info: Finished: Create simulation script
2025.03.29.00:49:04 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_reset.ip (kernel_system_reset) took 1749 ms
2025.03.29.00:49:05 Info: 
2025.03.29.00:49:05 Info: Generating on localhost:35819
2025.03.29.00:49:05 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:05 Info: mpsim: All Generic Component instances match their respective ip files.
2025.03.29.00:49:05 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/mpsim/mpsim_generation.rpt
2025.03.29.00:49:05 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:05 Info: Starting: Create simulation model
2025.03.29.00:49:05 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/mpsim.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/mpsim --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:05 Info: Loading simple-add-buffers-0b9718-3ae541/mpsim.qsys
2025.03.29.00:49:05 Info: Reading input file
2025.03.29.00:49:05 Info: Parameterizing module avmm_agent_cra_inst
2025.03.29.00:49:05 Info: Parameterizing module clk_rst
2025.03.29.00:49:05 Info: Parameterizing module component_dpi_controller_const_lambda_inst
2025.03.29.00:49:05 Info: Parameterizing module concat_component_stall_inst
2025.03.29.00:49:05 Info: Parameterizing module const_lambda_component_dpi_controller_enable_conduit_fanout_inst
2025.03.29.00:49:05 Info: Parameterizing module ki
2025.03.29.00:49:05 Info: Parameterizing module ks
2025.03.29.00:49:05 Info: Parameterizing module master_done_fanout_inst
2025.03.29.00:49:05 Info: Parameterizing module oirq
2025.03.29.00:49:05 Info: Parameterizing module osm_0_inst
2025.03.29.00:49:05 Info: Parameterizing module split_component_csr_ready_inst
2025.03.29.00:49:05 Info: Building connections
2025.03.29.00:49:05 Info: Parameterizing connections
2025.03.29.00:49:05 Info: Validating
2025.03.29.00:49:05 Info: Done reading input file
2025.03.29.00:49:05 Warning: mpsim.avmm_agent_cra_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.clk_rst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.component_dpi_controller_const_lambda_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.component_dpi_controller_const_lambda_inst: Warnings found in IP parameterization.
2025.03.29.00:49:05 Warning: mpsim.component_dpi_controller_const_lambda_inst.dpi_control_stream_writes_active: Interface has no signals
2025.03.29.00:49:05 Warning: mpsim.concat_component_stall_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.const_lambda_component_dpi_controller_enable_conduit_fanout_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.ki: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.ki: Warnings found in IP parameterization.
2025.03.29.00:49:05 Warning: mpsim.master_done_fanout_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.oirq: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.osm_0_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.split_component_csr_ready_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.ks.clk_1x: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.ks.kernel_cra: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.ks.kernel_irq: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.ks.reset: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.ks.simple_add_buffers_fpga_sim_sys: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:05 Warning: mpsim.clk_rst.clock/ki.clk: ki.clk requires 100000000Hz, but source has frequency of 0Hz
2025.03.29.00:49:05 Warning: mpsim.avmm_agent_cra_inst: avmm_agent_cra_inst.enable must be exported, or connected to a matching conduit as it has unconnected inputs.
2025.03.29.00:49:05 Warning: mpsim.component_dpi_controller_const_lambda_inst: component_dpi_controller_const_lambda_inst.dpi_control_agents_done must be exported, or connected to a matching conduit as it has unconnected inputs.
2025.03.29.00:49:05 Warning: mpsim.component_dpi_controller_const_lambda_inst: component_dpi_controller_const_lambda_inst.component_enabled must be exported, or connected to a matching conduit as it has unconnected inputs.
2025.03.29.00:49:05 Warning: mpsim.component_dpi_controller_const_lambda_inst: component_dpi_controller_const_lambda_inst.agent_busy must be exported, or connected to a matching conduit as it has unconnected inputs.
2025.03.29.00:49:05 Warning: mpsim.component_dpi_controller_const_lambda_inst: component_dpi_controller_const_lambda_inst.component_call must be exported, or connected to a matching conduit as it has unconnected inputs.
2025.03.29.00:49:05 Warning: mpsim.component_dpi_controller_const_lambda_inst: component_dpi_controller_const_lambda_inst.component_return must be exported, or connected to a matching conduit as it has unconnected inputs.
2025.03.29.00:49:05 Warning: mpsim.component_dpi_controller_const_lambda_inst: component_dpi_controller_const_lambda_inst.returndata must be exported, or connected to a matching conduit as it has unconnected inputs.
2025.03.29.00:49:05 Warning: mpsim.avmm_agent_cra_inst.m_mbd: avmm_agent_cra_inst.m_mbd must be connected to a MM agent or exported
2025.03.29.00:49:05 Info: mpsim: "Transforming system: mpsim"
2025.03.29.00:49:05 Warning: oirq.kernel_interrupt: Cannot connect clock for irq_mapper_002.sender
2025.03.29.00:49:05 Warning: oirq.kernel_interrupt: Cannot connect reset for irq_mapper_002.sender
2025.03.29.00:49:05 Info: mpsim: "Naming system components in system: mpsim"
2025.03.29.00:49:05 Info: mpsim: "Processing generation queue"
2025.03.29.00:49:05 Info: mpsim: "Generating: mpsim"
2025.03.29.00:49:05 Info: mpsim: "Generating: mpsim_avmm_agent_cra_inst"
2025.03.29.00:49:05 Info: mpsim: "Generating: mpsim_clk_rst"
2025.03.29.00:49:05 Info: mpsim: "Generating: dpic_const_lambda"
2025.03.29.00:49:05 Info: mpsim: "Generating: cct_comp_stall"
2025.03.29.00:49:05 Info: mpsim: "Generating: const_lambda_en_cfan"
2025.03.29.00:49:05 Info: mpsim: "Generating: mpsim_ki"
2025.03.29.00:49:05 Info: mpsim: "Generating: done_cfan"
2025.03.29.00:49:05 Info: mpsim: "Generating: mpsim_oirq"
2025.03.29.00:49:05 Info: mpsim: "Generating: mm_agent_ks_mem0_rw"
2025.03.29.00:49:05 Info: mpsim: "Generating: sp_csr_ready"
2025.03.29.00:49:05 Info: mpsim: "Generating: mpsim_altera_mm_interconnect_1920_zw4jf7q"
2025.03.29.00:49:05 Info: mpsim: "Generating: mpsim_altera_irq_mapper_2001_rctq6fa"
2025.03.29.00:49:05 Info: mpsim: "Generating: mpsim_altera_irq_mapper_2001_wgtbcyy"
2025.03.29.00:49:05 Info: mpsim: "Generating: mpsim_altera_merlin_master_translator_192_54w642y"
2025.03.29.00:49:05 Info: mpsim: "Generating: mpsim_altera_merlin_slave_translator_191_xg7rzxi"
2025.03.29.00:49:05 Info: mpsim: Done "mpsim" with 17 modules, 6 files
2025.03.29.00:49:05 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:05 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/mpsim/sim/ directory:
2025.03.29.00:49:05 Info: common/xcelium_files.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/mpsim/sim/ directory:
2025.03.29.00:49:05 Info: common/vcsmx_files.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/mpsim/sim/ directory:
2025.03.29.00:49:05 Info: common/riviera_files.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/mpsim/sim/ directory:
2025.03.29.00:49:05 Info: common/modelsim_files.tcl
2025.03.29.00:49:05 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/mpsim/sim/.
2025.03.29.00:49:05 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:05 Info: Finished: Create simulation model
2025.03.29.00:49:05 Info: Starting: Create simulation script
2025.03.29.00:49:05 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/mpsim.qsys --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/mpsim/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:05 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:05 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/mpsim/sim/ directory:
2025.03.29.00:49:05 Info: xcelium/cds.lib
2025.03.29.00:49:05 Info: xcelium/hdl.var
2025.03.29.00:49:05 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:05 Info: 1 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:05 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/mpsim/sim/ directory:
2025.03.29.00:49:05 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:05 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:05 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:05 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/mpsim/sim/ directory:
2025.03.29.00:49:05 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:05 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/mpsim/sim/ directory:
2025.03.29.00:49:05 Info: mentor/msim_setup.tcl
2025.03.29.00:49:05 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:05 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/mpsim/sim/.
2025.03.29.00:49:05 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:05 Info: Finished: Create simulation script
2025.03.29.00:49:05 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/mpsim.qsys (mpsim) took 5449 ms
2025.03.29.00:49:05 Info: 
2025.03.29.00:49:05 Info: Generating on localhost:36235
2025.03.29.00:49:05 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:05 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan/done_cfan_generation.rpt
2025.03.29.00:49:05 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:05 Info: Starting: Create simulation model
2025.03.29.00:49:05 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:05 Info: done_cfan: "Transforming system: done_cfan"
2025.03.29.00:49:05 Info: done_cfan: "Naming system components in system: done_cfan"
2025.03.29.00:49:05 Info: done_cfan: "Processing generation queue"
2025.03.29.00:49:05 Info: done_cfan: "Generating: done_cfan"
2025.03.29.00:49:05 Info: done_cfan: "Generating: done_cfan_avalon_conduit_fanout_10_d5krbyi"
2025.03.29.00:49:05 Info: done_cfan: Done "done_cfan" with 2 modules, 2 files
2025.03.29.00:49:05 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:05 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan/sim/ directory:
2025.03.29.00:49:05 Info: common/modelsim_files.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan/sim/ directory:
2025.03.29.00:49:05 Info: common/vcsmx_files.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan/sim/ directory:
2025.03.29.00:49:05 Info: common/riviera_files.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan/sim/ directory:
2025.03.29.00:49:05 Info: common/xcelium_files.tcl
2025.03.29.00:49:05 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan/sim/.
2025.03.29.00:49:05 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:05 Info: Finished: Create simulation model
2025.03.29.00:49:05 Info: Starting: Create simulation script
2025.03.29.00:49:05 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:05 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:05 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan/sim/ directory:
2025.03.29.00:49:05 Info: mentor/msim_setup.tcl
2025.03.29.00:49:05 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan/sim/ directory:
2025.03.29.00:49:05 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:05 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:05 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:05 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan/sim/ directory:
2025.03.29.00:49:05 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:05 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan/sim/ directory:
2025.03.29.00:49:05 Info: xcelium/cds.lib
2025.03.29.00:49:05 Info: xcelium/hdl.var
2025.03.29.00:49:05 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:05 Info: 3 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:05 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan/sim/.
2025.03.29.00:49:05 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:05 Info: Finished: Create simulation script
2025.03.29.00:49:05 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/done_cfan.ip (done_cfan) took 1757 ms
2025.03.29.00:49:05 Info: 
2025.03.29.00:49:05 Info: Generating on localhost:41565
2025.03.29.00:49:05 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:05 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq/mpsim_oirq_generation.rpt
2025.03.29.00:49:05 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:05 Info: Starting: Create simulation model
2025.03.29.00:49:05 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:05 Info: mpsim_oirq: "Transforming system: mpsim_oirq"
2025.03.29.00:49:05 Info: mpsim_oirq: "Naming system components in system: mpsim_oirq"
2025.03.29.00:49:05 Info: mpsim_oirq: "Processing generation queue"
2025.03.29.00:49:05 Info: mpsim_oirq: "Generating: mpsim_oirq"
2025.03.29.00:49:05 Info: mpsim_oirq: "Generating: aoc_sim_main_dpi_controller"
2025.03.29.00:49:05 Info: mpsim_oirq: Done "mpsim_oirq" with 2 modules, 2 files
2025.03.29.00:49:05 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:05 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq/sim/ directory:
2025.03.29.00:49:05 Info: common/xcelium_files.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq/sim/ directory:
2025.03.29.00:49:05 Info: common/riviera_files.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq/sim/ directory:
2025.03.29.00:49:05 Info: common/vcsmx_files.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq/sim/ directory:
2025.03.29.00:49:05 Info: common/modelsim_files.tcl
2025.03.29.00:49:05 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq/sim/.
2025.03.29.00:49:05 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:05 Info: Finished: Create simulation model
2025.03.29.00:49:05 Info: Starting: Create simulation script
2025.03.29.00:49:05 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:05 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:05 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq/sim/ directory:
2025.03.29.00:49:05 Info: xcelium/cds.lib
2025.03.29.00:49:05 Info: xcelium/hdl.var
2025.03.29.00:49:05 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:05 Info: 3 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:05 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq/sim/ directory:
2025.03.29.00:49:05 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:05 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq/sim/ directory:
2025.03.29.00:49:05 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:05 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:05 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:05 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq/sim/ directory:
2025.03.29.00:49:05 Info: mentor/msim_setup.tcl
2025.03.29.00:49:05 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:05 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq/sim/.
2025.03.29.00:49:05 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:05 Info: Finished: Create simulation script
2025.03.29.00:49:05 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_oirq.ip (mpsim_oirq) took 1688 ms
2025.03.29.00:49:05 Info: 
2025.03.29.00:49:05 Info: Generating on localhost:37475
2025.03.29.00:49:05 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:05 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan/const_lambda_en_cfan_generation.rpt
2025.03.29.00:49:05 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:05 Info: Starting: Create simulation model
2025.03.29.00:49:05 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:05 Info: const_lambda_en_cfan: "Transforming system: const_lambda_en_cfan"
2025.03.29.00:49:05 Info: const_lambda_en_cfan: "Naming system components in system: const_lambda_en_cfan"
2025.03.29.00:49:05 Info: const_lambda_en_cfan: "Processing generation queue"
2025.03.29.00:49:05 Info: const_lambda_en_cfan: "Generating: const_lambda_en_cfan"
2025.03.29.00:49:05 Info: const_lambda_en_cfan: "Generating: const_lambda_en_cfan_avalon_conduit_fanout_10_xkdeykq"
2025.03.29.00:49:05 Info: const_lambda_en_cfan: Done "const_lambda_en_cfan" with 2 modules, 2 files
2025.03.29.00:49:05 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:05 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan/sim/ directory:
2025.03.29.00:49:05 Info: common/vcsmx_files.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan/sim/ directory:
2025.03.29.00:49:05 Info: common/modelsim_files.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan/sim/ directory:
2025.03.29.00:49:05 Info: common/xcelium_files.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan/sim/ directory:
2025.03.29.00:49:05 Info: common/riviera_files.tcl
2025.03.29.00:49:05 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan/sim/.
2025.03.29.00:49:05 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:05 Info: Finished: Create simulation model
2025.03.29.00:49:05 Info: Starting: Create simulation script
2025.03.29.00:49:05 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:05 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:05 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan/sim/ directory:
2025.03.29.00:49:05 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:05 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:05 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:05 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan/sim/ directory:
2025.03.29.00:49:05 Info: mentor/msim_setup.tcl
2025.03.29.00:49:05 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:05 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan/sim/ directory:
2025.03.29.00:49:05 Info: xcelium/cds.lib
2025.03.29.00:49:05 Info: xcelium/hdl.var
2025.03.29.00:49:05 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:05 Info: 3 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:05 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan/sim/ directory:
2025.03.29.00:49:05 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:05 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:05 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan/sim/.
2025.03.29.00:49:05 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:05 Info: Finished: Create simulation script
2025.03.29.00:49:05 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/const_lambda_en_cfan.ip (const_lambda_en_cfan) took 1871 ms
2025.03.29.00:49:07 Info: 
2025.03.29.00:49:07 Info: Generating on localhost:33547
2025.03.29.00:49:07 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:07 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki/mpsim_ki_generation.rpt
2025.03.29.00:49:07 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:07 Info: Starting: Create simulation model
2025.03.29.00:49:07 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:07 Warning: mpsim_ki.ki: add_instance: Component altera_avalon_mm_bridge version 13.1 is not installed - loaded latest installed version 20.1.0 instead.  Please check for parameter mismatches 
2025.03.29.00:49:07 Warning: mpsim_ki.ki: add_instance: Component altera_address_span_extender version 15.0 is not installed - loaded latest installed version 19.2.0 instead.  Please check for parameter mismatches 
2025.03.29.00:49:07 Warning: mpsim_ki.ki: add_instance: Component altera_avalon_mm_bridge version 13.1 is not installed - loaded latest installed version 20.1.0 instead.  Please check for parameter mismatches 
2025.03.29.00:49:07 Warning: mpsim_ki.ki: add_instance: Component clock_source version 13.1 is not installed - loaded latest installed version 24.3 instead.  Please check for parameter mismatches 
2025.03.29.00:49:07 Warning: mpsim_ki.ki: add_instance: Component altera_irq_bridge version 13.1 is not installed - loaded latest installed version 20.0.0 instead.  Please check for parameter mismatches 
2025.03.29.00:49:07 Warning: mpsim_ki.ki: add_instance: Component altera_reset_bridge version 13.1 is not installed - loaded latest installed version 19.2.0 instead.  Please check for parameter mismatches 
2025.03.29.00:49:07 Warning: mpsim_ki.ki: add_instance: Component altera_reset_controller version 13.1 is not installed - loaded latest installed version 19.2.4 instead.  Please check for parameter mismatches 
2025.03.29.00:49:07 Warning: mpsim_ki.ki: add_instance: Component altera_clock_bridge version 13.1 is not installed - loaded latest installed version 19.2.0 instead.  Please check for parameter mismatches 
2025.03.29.00:49:07 Warning: mpsim_ki.ki: add_instance: Component altera_reset_bridge version 13.1 is not installed - loaded latest installed version 19.2.0 instead.  Please check for parameter mismatches 
2025.03.29.00:49:07 Warning: mpsim_ki.ki: add_instance: Component altera_reset_bridge version 13.1 is not installed - loaded latest installed version 19.2.0 instead.  Please check for parameter mismatches 
2025.03.29.00:49:07 Info: mpsim_ki.ki.reset_controller_sw: Deassert with RESET_REQUEST_PRESENT will have Minimum of 4 cycles difference between assertion of reset_req to reset_out
2025.03.29.00:49:07 Info: mpsim_ki: "Transforming system: mpsim_ki"
2025.03.29.00:49:07 Info: Interconnect is inserted between master address_span_extender_0.expanded_master and slave kernel_cra.s0 because they have different clock source.
2025.03.29.00:49:07 Info: Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0
2025.03.29.00:49:07 Info: Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0
2025.03.29.00:49:07 Info: mpsim_ki: "Naming system components in system: mpsim_ki"
2025.03.29.00:49:07 Info: mpsim_ki: "Processing generation queue"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_kernel_interface_151_yqsw7ei"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_avalon_mm_bridge_2010_tex5a4i"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_address_span_extender_1920_vz4724i"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: sw_reset"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: global_routing"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mem_org_mode"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_irq_bridge_2000_mzhkeuq"
2025.03.29.00:49:07 Info: irq_bridge_0: 1
2025.03.29.00:49:07 Info: irq_bridge_0: irq_width
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: version_id"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: altera_reset_controller"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_mm_interconnect_1920_qyya7ny"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_mm_interconnect_1920_cuy7uay"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_master_translator_192_54w642y"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_slave_translator_191_xg7rzxi"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_master_agent_1930_l64uqry"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_slave_agent_1930_jxauz3i"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_avalon_sc_fifo_1932_onpcouq"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_router_1921_462bhxq"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_router_1921_qo376wy"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_demultiplexer_1921_p6jr2wa"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_multiplexer_1922_kqpdb4a"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_multiplexer_1922_zl6mqja"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_hs_clk_xer_1941_ufej3ri"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_router_1921_h3b4hlq"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_router_1921_mndf7xa"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_router_1921_7r3h3sq"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_traffic_limiter_1921_3mmasty"
2025.03.29.00:49:07 Info: my_altera_avalon_sc_fifo_dest_id_fifo: "Generating: my_altera_avalon_sc_fifo_dest_id_fifo"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_demultiplexer_1921_vnl2yiy"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_multiplexer_1922_ia6emmq"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_demultiplexer_1921_pgmvl6a"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_multiplexer_1922_76stkzq"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_width_adapter_1950_45pnevq"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_width_adapter_1950_hbzf6ha"
2025.03.29.00:49:07 Info: mpsim_ki: "Generating: mpsim_ki_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1921_xk7jela"
2025.03.29.00:49:07 Info: mpsim_ki: Done "mpsim_ki" with 34 modules, 54 files
2025.03.29.00:49:07 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:07 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki/sim/ directory:
2025.03.29.00:49:07 Info: common/xcelium_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki/sim/ directory:
2025.03.29.00:49:07 Info: common/riviera_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki/sim/ directory:
2025.03.29.00:49:07 Info: common/modelsim_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki/sim/ directory:
2025.03.29.00:49:07 Info: common/vcsmx_files.tcl
2025.03.29.00:49:07 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki/sim/.
2025.03.29.00:49:07 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:07 Info: Finished: Create simulation model
2025.03.29.00:49:07 Info: Starting: Create simulation script
2025.03.29.00:49:07 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:07 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:07 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki/sim/ directory:
2025.03.29.00:49:07 Info: xcelium/cds.lib
2025.03.29.00:49:07 Info: xcelium/hdl.var
2025.03.29.00:49:07 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:07 Info: 23 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:07 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki/sim/ directory:
2025.03.29.00:49:07 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:07 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki/sim/ directory:
2025.03.29.00:49:07 Info: mentor/msim_setup.tcl
2025.03.29.00:49:07 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki/sim/ directory:
2025.03.29.00:49:07 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:07 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:07 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:07 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki/sim/.
2025.03.29.00:49:07 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:07 Info: Finished: Create simulation script
2025.03.29.00:49:07 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mpsim_ki.ip (mpsim_ki) took 7994 ms
2025.03.29.00:49:07 Info: 
2025.03.29.00:49:07 Info: Generating on localhost:35819
2025.03.29.00:49:07 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:07 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready/sp_csr_ready_generation.rpt
2025.03.29.00:49:07 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:07 Info: Starting: Create simulation model
2025.03.29.00:49:07 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:07 Info: sp_csr_ready: "Transforming system: sp_csr_ready"
2025.03.29.00:49:07 Info: sp_csr_ready: "Naming system components in system: sp_csr_ready"
2025.03.29.00:49:07 Info: sp_csr_ready: "Processing generation queue"
2025.03.29.00:49:07 Info: sp_csr_ready: "Generating: sp_csr_ready"
2025.03.29.00:49:07 Info: sp_csr_ready: "Generating: sp_csr_ready_avalon_split_multibit_conduit_10_6ihlvbi"
2025.03.29.00:49:07 Info: sp_csr_ready: Done "sp_csr_ready" with 2 modules, 2 files
2025.03.29.00:49:07 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:07 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready/sim/ directory:
2025.03.29.00:49:07 Info: common/xcelium_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready/sim/ directory:
2025.03.29.00:49:07 Info: common/vcsmx_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready/sim/ directory:
2025.03.29.00:49:07 Info: common/riviera_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready/sim/ directory:
2025.03.29.00:49:07 Info: common/modelsim_files.tcl
2025.03.29.00:49:07 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready/sim/.
2025.03.29.00:49:07 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:07 Info: Finished: Create simulation model
2025.03.29.00:49:07 Info: Starting: Create simulation script
2025.03.29.00:49:07 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:07 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:07 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready/sim/ directory:
2025.03.29.00:49:07 Info: xcelium/cds.lib
2025.03.29.00:49:07 Info: xcelium/hdl.var
2025.03.29.00:49:07 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:07 Info: 3 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:07 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready/sim/ directory:
2025.03.29.00:49:07 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:07 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:07 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:07 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready/sim/ directory:
2025.03.29.00:49:07 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:07 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready/sim/ directory:
2025.03.29.00:49:07 Info: mentor/msim_setup.tcl
2025.03.29.00:49:07 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:07 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready/sim/.
2025.03.29.00:49:07 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:07 Info: Finished: Create simulation script
2025.03.29.00:49:07 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/sp_csr_ready.ip (sp_csr_ready) took 1515 ms
2025.03.29.00:49:07 Info: 
2025.03.29.00:49:07 Info: Generating on localhost:36235
2025.03.29.00:49:07 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:07 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw/mm_agent_ks_mem0_rw_generation.rpt
2025.03.29.00:49:07 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:07 Info: Starting: Create simulation model
2025.03.29.00:49:07 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:07 Info: mm_agent_ks_mem0_rw: "Transforming system: mm_agent_ks_mem0_rw"
2025.03.29.00:49:07 Info: mm_agent_ks_mem0_rw: "Naming system components in system: mm_agent_ks_mem0_rw"
2025.03.29.00:49:07 Info: mm_agent_ks_mem0_rw: "Processing generation queue"
2025.03.29.00:49:07 Info: mm_agent_ks_mem0_rw: "Generating: mm_agent_ks_mem0_rw"
2025.03.29.00:49:07 Info: mm_agent_ks_mem0_rw: "Generating: aoc_sim_mm_slave_dpi_bfm"
2025.03.29.00:49:07 Info: /home/yazan/intelFPGA_pro/24.3.1/quartus
2025.03.29.00:49:07 Info: /home/yazan/intelFPGA_pro/24.3.1/quartus/../ip/altera/sopc_builder_ip/verification/
2025.03.29.00:49:07 Info: mm_agent_ks_mem0_rw: Done "mm_agent_ks_mem0_rw" with 2 modules, 6 files
2025.03.29.00:49:07 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:07 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw/sim/ directory:
2025.03.29.00:49:07 Info: common/modelsim_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw/sim/ directory:
2025.03.29.00:49:07 Info: common/vcsmx_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw/sim/ directory:
2025.03.29.00:49:07 Info: common/riviera_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw/sim/ directory:
2025.03.29.00:49:07 Info: common/xcelium_files.tcl
2025.03.29.00:49:07 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw/sim/.
2025.03.29.00:49:07 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:07 Info: Finished: Create simulation model
2025.03.29.00:49:07 Info: Starting: Create simulation script
2025.03.29.00:49:07 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:07 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:07 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw/sim/ directory:
2025.03.29.00:49:07 Info: mentor/msim_setup.tcl
2025.03.29.00:49:07 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw/sim/ directory:
2025.03.29.00:49:07 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:07 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:07 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:07 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw/sim/ directory:
2025.03.29.00:49:07 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:07 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw/sim/ directory:
2025.03.29.00:49:07 Info: xcelium/cds.lib
2025.03.29.00:49:07 Info: xcelium/hdl.var
2025.03.29.00:49:07 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:07 Info: 4 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:07 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw/sim/.
2025.03.29.00:49:07 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:07 Info: Finished: Create simulation script
2025.03.29.00:49:07 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/mpsim/mm_agent_ks_mem0_rw.ip (mm_agent_ks_mem0_rw) took 1552 ms
2025.03.29.00:49:07 Info: 
2025.03.29.00:49:07 Info: Generating on localhost:41565
2025.03.29.00:49:07 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:07 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra/kernel_system_kernel_cra_generation.rpt
2025.03.29.00:49:07 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:07 Info: Starting: Create simulation model
2025.03.29.00:49:07 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:07 Info: kernel_system_kernel_cra: "Transforming system: kernel_system_kernel_cra"
2025.03.29.00:49:07 Info: kernel_system_kernel_cra: "Naming system components in system: kernel_system_kernel_cra"
2025.03.29.00:49:07 Info: kernel_system_kernel_cra: "Processing generation queue"
2025.03.29.00:49:07 Info: kernel_system_kernel_cra: "Generating: kernel_system_kernel_cra"
2025.03.29.00:49:07 Info: kernel_system_kernel_cra: "Generating: kernel_system_kernel_cra_altera_avalon_mm_bridge_2010_tex5a4i"
2025.03.29.00:49:07 Info: kernel_system_kernel_cra: Done "kernel_system_kernel_cra" with 2 modules, 4 files
2025.03.29.00:49:07 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:07 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra/sim/ directory:
2025.03.29.00:49:07 Info: common/xcelium_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra/sim/ directory:
2025.03.29.00:49:07 Info: common/riviera_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra/sim/ directory:
2025.03.29.00:49:07 Info: common/vcsmx_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra/sim/ directory:
2025.03.29.00:49:07 Info: common/modelsim_files.tcl
2025.03.29.00:49:07 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra/sim/.
2025.03.29.00:49:07 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:07 Info: Finished: Create simulation model
2025.03.29.00:49:07 Info: Starting: Create simulation script
2025.03.29.00:49:07 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra.ip --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:07 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:07 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra/sim/ directory:
2025.03.29.00:49:07 Info: xcelium/cds.lib
2025.03.29.00:49:07 Info: xcelium/hdl.var
2025.03.29.00:49:07 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:07 Info: 3 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:07 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra/sim/ directory:
2025.03.29.00:49:07 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:07 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra/sim/ directory:
2025.03.29.00:49:07 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:07 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:07 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:07 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra/sim/ directory:
2025.03.29.00:49:07 Info: mentor/msim_setup.tcl
2025.03.29.00:49:07 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:07 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra/sim/.
2025.03.29.00:49:07 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:07 Info: Finished: Create simulation script
2025.03.29.00:49:07 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/ip/kernel_system/kernel_system_kernel_cra.ip (kernel_system_kernel_cra) took 1483 ms
2025.03.29.00:49:07 Info: 
2025.03.29.00:49:07 Info: Generating on localhost:43601
2025.03.29.00:49:07 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2025.03.29.00:49:07 Info: kernel_system: All Generic Component instances match their respective ip files.
2025.03.29.00:49:07 Info: Saving generation log to /tmp/simple-add-buffers-0b9718-3ae541/kernel_system/kernel_system_generation.rpt
2025.03.29.00:49:07 Info: Generated by version: 24.3.1 build 102
2025.03.29.00:49:07 Info: Starting: Create simulation model
2025.03.29.00:49:07 Info: qsys-generate /tmp/simple-add-buffers-0b9718-3ae541/kernel_system.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/kernel_system --family="Agilex 5" --part=A5EC065BB32AE5SR0
2025.03.29.00:49:07 Info: Loading simple-add-buffers-0b9718-3ae541/kernel_system.qsys
2025.03.29.00:49:07 Info: Reading input file
2025.03.29.00:49:07 Info: Parameterizing module clk_1x
2025.03.29.00:49:07 Info: Parameterizing module kernel_cra
2025.03.29.00:49:07 Info: Parameterizing module kernel_irq
2025.03.29.00:49:07 Info: Parameterizing module reset
2025.03.29.00:49:07 Info: Parameterizing module simple_add_buffers_fpga_sim_sys
2025.03.29.00:49:07 Info: Building connections
2025.03.29.00:49:07 Info: Parameterizing connections
2025.03.29.00:49:07 Info: Validating
2025.03.29.00:49:07 Info: Done reading input file
2025.03.29.00:49:07 Warning: kernel_system.clk_1x: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:07 Warning: kernel_system.kernel_cra: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:07 Warning: kernel_system.kernel_irq: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:07 Warning: kernel_system.reset: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:07 Warning: kernel_system.simple_add_buffers_fpga_sim_sys: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2025.03.29.00:49:07 Info: kernel_system: "Transforming system: kernel_system"
2025.03.29.00:49:07 Info: Interconnect is inserted between master kernel_cra.m0 and slave simple_add_buffers_fpga_sim_sys.csr_ring_root_avs because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide.
2025.03.29.00:49:07 Info: Interconnect is inserted between master kernel_cra.m0 and slave simple_add_buffers_fpga_sim_sys.csr_ring_root_avs because the master has address signal 30 bit wide, but the slave is 5 bit wide.
2025.03.29.00:49:07 Info: Interconnect is inserted between master kernel_cra.m0 and slave simple_add_buffers_fpga_sim_sys.csr_ring_root_avs because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2025.03.29.00:49:07 Info: kernel_system: "Naming system components in system: kernel_system"
2025.03.29.00:49:07 Info: kernel_system: "Processing generation queue"
2025.03.29.00:49:07 Info: kernel_system: "Generating: kernel_system"
2025.03.29.00:49:07 Info: kernel_system: "Generating: kernel_system_clk_1x"
2025.03.29.00:49:07 Info: kernel_system: "Generating: kernel_system_kernel_cra"
2025.03.29.00:49:07 Info: kernel_system: "Generating: kernel_system_kernel_irq"
2025.03.29.00:49:07 Info: kernel_system: "Generating: kernel_system_reset"
2025.03.29.00:49:07 Info: kernel_system: "Generating: kernel_system_simple_add_buffers_fpga_sim_sys"
2025.03.29.00:49:07 Info: kernel_system: "Generating: kernel_system_altera_mm_interconnect_1920_erxnzwa"
2025.03.29.00:49:07 Info: kernel_system: "Generating: kernel_system_altera_irq_mapper_2001_wgtbcyy"
2025.03.29.00:49:07 Info: kernel_system: "Generating: kernel_system_altera_merlin_master_translator_192_54w642y"
2025.03.29.00:49:07 Info: kernel_system: "Generating: kernel_system_altera_merlin_slave_translator_191_xg7rzxi"
2025.03.29.00:49:07 Info: kernel_system: Done "kernel_system" with 10 modules, 5 files
2025.03.29.00:49:07 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:07 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/kernel_system/sim/ directory:
2025.03.29.00:49:07 Info: common/xcelium_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/kernel_system/sim/ directory:
2025.03.29.00:49:07 Info: common/riviera_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/kernel_system/sim/ directory:
2025.03.29.00:49:07 Info: common/modelsim_files.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/kernel_system/sim/ directory:
2025.03.29.00:49:07 Info: common/vcsmx_files.tcl
2025.03.29.00:49:07 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/kernel_system/sim/.
2025.03.29.00:49:07 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:07 Info: Finished: Create simulation model
2025.03.29.00:49:07 Info: Starting: Create simulation script
2025.03.29.00:49:07 Info: sim-script-gen --system-file=/tmp/simple-add-buffers-0b9718-3ae541/kernel_system.qsys --output-directory=/tmp/simple-add-buffers-0b9718-3ae541/kernel_system/sim/ --use-relative-paths=true --modelsim-flow=traditional
2025.03.29.00:49:07 Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for Agilex 5 device family
2025.03.29.00:49:07 Info: Generating the following file(s) for XCELIUM simulator in /tmp/simple-add-buffers-0b9718-3ae541/kernel_system/sim/ directory:
2025.03.29.00:49:07 Info: xcelium/cds.lib
2025.03.29.00:49:07 Info: xcelium/hdl.var
2025.03.29.00:49:07 Info: xcelium/xcelium_setup.sh
2025.03.29.00:49:07 Info: 1 .cds.lib files in xcelium/cds_libs/ directory
2025.03.29.00:49:07 Info: Generating the following file(s) for RIVIERA simulator in /tmp/simple-add-buffers-0b9718-3ae541/kernel_system/sim/ directory:
2025.03.29.00:49:07 Info: aldec/rivierapro_setup.tcl
2025.03.29.00:49:07 Info: aldec/run_rivierapro_setup.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for MODELSIM simulator in /tmp/simple-add-buffers-0b9718-3ae541/kernel_system/sim/ directory:
2025.03.29.00:49:07 Info: mentor/msim_setup.tcl
2025.03.29.00:49:07 Info: mentor/run_msim_setup.tcl
2025.03.29.00:49:07 Info: Generating the following file(s) for VCSMX simulator in /tmp/simple-add-buffers-0b9718-3ae541/kernel_system/sim/ directory:
2025.03.29.00:49:07 Info: synopsys/vcsmx/_device_synopsys_sim.setup
2025.03.29.00:49:07 Info: synopsys/vcsmx/synopsys_sim.setup
2025.03.29.00:49:07 Info: synopsys/vcsmx/vcsmx_setup.sh
2025.03.29.00:49:07 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/simple-add-buffers-0b9718-3ae541/kernel_system/sim/.
2025.03.29.00:49:07 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2025.03.29.00:49:07 Info: Finished: Create simulation script
2025.03.29.00:49:07 Info: Generation of /tmp/simple-add-buffers-0b9718-3ae541/kernel_system.qsys (kernel_system) took 3016 ms
2025.03.29.00:49:08 Info: Finished: Platform Designer system generation
# 
# do mpsim/sim/msim_compile.tcl
# Questa Intel Starter FPGA Edition-64 vsim 2024.1 Simulator 2024.04 Apr 19 2024
# mpsim/sim
# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                                         -- Copy ROM/RAM files to simulation directory
# 
# dev_com                                           -- Compile device library files
# 
# com                                               -- Compile the design files in correct order
# 
# elab                                              -- Elaborate top level design
# 
# elab_debug                                        -- Elaborate the top level design with -voptargs=+acc option
# 
# ld                                                -- Compile all the design files and elaborate the top level design
# 
# ld_debug                                          -- Compile all the design files and elaborate the top level design with  -voptargs=+acc
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                                       -- Qsys base simulation directory.
# 
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
# 
# SILENCE                                           -- Set to true to suppress all informational and/or warning messages in the generated simulation script. 
# 
# PRECOMP_DEVICE_LIB_FILE                           -- Precompiled device library file.
#                                                     Use this variable to provide modelsim.ini or tcl containing device library mapping and dev_com will be skipped
#                                                     If value is empty, device libraries will be compiled local
# 
# FORCE_MODELSIM_AE_SELECTION                       -- Set to true to force to select Modelsim AE always.
# +incdir+mpsim/sim +define+COSIM_LIB -suppress 2388 -suppress 14408 -suppress 7061
# [exec] dev_com
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:17 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 /home/yazan/intelFPGA_pro/24.3.1/quartus/eda/sim_lib/simsf_dpi.cpp 
# ** Warning: (vlog-7032) The 64-bit glibc RPM does not appear to be installed on this machine.  Calls to gcc may fail.
# -- Compiling DPI/PLI C++ file /home/yazan/intelFPGA_pro/24.3.1/quartus/eda/sim_lib/simsf_dpi.cpp
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:02
# Errors: 0, Warnings: 1
# [exec] com
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mm_agent_ks_mem0_rw/aoc_sim_mm_slave_dpi_bfm_10/sim/verbosity_pkg.sv -work altera_common_sv_packages 
# -- Compiling package verbosity_pkg
# 
# Top level modules:
# 	--none--
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mm_agent_ks_mem0_rw/aoc_sim_mm_slave_dpi_bfm_10/sim/avalon_mm_pkg.sv -work altera_common_sv_packages 
# -- Compiling package avalon_mm_pkg
# -- Importing package verbosity_pkg
# 
# Top level modules:
# 	--none--
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mm_agent_ks_mem0_rw/aoc_sim_mm_slave_dpi_bfm_10/sim/avalon_utilities_pkg.sv -work altera_common_sv_packages 
# -- Compiling package avalon_utilities_pkg
# 
# Top level modules:
# 	--none--
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/dpic_const_lambda/aoc_sim_component_dpi_controller_10/sim/aoc_sim_stream_sink_dpi_bfm.sv -work aoc_sim_component_dpi_controller_10 
# -- Compiling module aoc_sim_stream_sink_dpi_bfm
# 
# Top level modules:
# 	aoc_sim_stream_sink_dpi_bfm
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/dpic_const_lambda/aoc_sim_component_dpi_controller_10/sim/aoc_sim_stream_source_dpi_bfm.sv -work aoc_sim_component_dpi_controller_10 
# -- Compiling module aoc_sim_stream_source_dpi_bfm
# 
# Top level modules:
# 	aoc_sim_stream_source_dpi_bfm
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/dpic_const_lambda/aoc_sim_component_dpi_controller_10/sim/aoc_sim_component_dpi_controller.sv -work aoc_sim_component_dpi_controller_10 
# -- Compiling module aoc_sim_component_dpi_controller
# 
# Top level modules:
# 	aoc_sim_component_dpi_controller
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/dpic_const_lambda/sim/dpic_const_lambda.v -work dpic_const_lambda 
# -- Compiling module dpic_const_lambda
# 
# Top level modules:
# 	dpic_const_lambda
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/cct_comp_stall/avalon_concatenate_singlebit_conduits_10/sim/cct_comp_stall_avalon_concatenate_singlebit_conduits_10_lrbideq.sv -work avalon_concatenate_singlebit_conduits_10 
# -- Compiling module cct_comp_stall_avalon_concatenate_singlebit_conduits_10_lrbideq
# 
# Top level modules:
# 	cct_comp_stall_avalon_concatenate_singlebit_conduits_10_lrbideq
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/cct_comp_stall/sim/cct_comp_stall.v -work cct_comp_stall 
# -- Compiling module cct_comp_stall
# 
# Top level modules:
# 	cct_comp_stall
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/const_lambda_en_cfan/avalon_conduit_fanout_10/sim/const_lambda_en_cfan_avalon_conduit_fanout_10_xkdeykq.sv -work avalon_conduit_fanout_10 
# -- Compiling module const_lambda_en_cfan_avalon_conduit_fanout_10_xkdeykq
# 
# Top level modules:
# 	const_lambda_en_cfan_avalon_conduit_fanout_10_xkdeykq
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/const_lambda_en_cfan/sim/const_lambda_en_cfan.v -work const_lambda_en_cfan 
# -- Compiling module const_lambda_en_cfan
# 
# Top level modules:
# 	const_lambda_en_cfan
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_oirq/aoc_sim_main_dpi_controller_10/sim/aoc_sim_main_dpi_controller.sv -work aoc_sim_main_dpi_controller_10 
# -- Compiling module aoc_sim_main_dpi_controller
# 
# Top level modules:
# 	aoc_sim_main_dpi_controller
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_oirq/sim/mpsim_oirq.v -work mpsim_oirq 
# -- Compiling module mpsim_oirq
# 
# Top level modules:
# 	mpsim_oirq
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_avmm_agent_cra_inst/aoc_sim_mm_master_dpi_bfm_10/sim/altera_avalon_mm_master_bfm.sv -L altera_common_sv_packages -work aoc_sim_mm_master_dpi_bfm_10 
# -- Compiling module altera_avalon_mm_master_bfm
# -- Importing package altera_common_sv_packages.verbosity_pkg
# -- Importing package altera_common_sv_packages.avalon_mm_pkg
# -- Importing package altera_common_sv_packages.avalon_utilities_pkg
# 
# Top level modules:
# 	altera_avalon_mm_master_bfm
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_avmm_agent_cra_inst/aoc_sim_mm_master_dpi_bfm_10/sim/aoc_sim_mm_master_dpi_bfm.sv -L altera_common_sv_packages -work aoc_sim_mm_master_dpi_bfm_10 
# -- Compiling module aoc_sim_mm_master_dpi_bfm
# -- Importing package altera_common_sv_packages.verbosity_pkg
# -- Importing package altera_common_sv_packages.avalon_mm_pkg
# ** Warning: ip/mpsim/mpsim_avmm_agent_cra_inst/aoc_sim_mm_master_dpi_bfm_10/sim/aoc_sim_mm_master_dpi_bfm.sv(493): (vlog-2240) Treating stand-alone use of function '__ihc_aoc_mm_agent_read' as an implicit VOID cast.
# ** Warning: ip/mpsim/mpsim_avmm_agent_cra_inst/aoc_sim_mm_master_dpi_bfm_10/sim/aoc_sim_mm_master_dpi_bfm.sv(534): (vlog-2240) Treating stand-alone use of function '__ihc_aoc_mm_agent_read' as an implicit VOID cast.
# 
# Top level modules:
# 	aoc_sim_mm_master_dpi_bfm
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 2
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_avmm_agent_cra_inst/sim/mpsim_avmm_agent_cra_inst.v -work mpsim_avmm_agent_cra_inst 
# -- Compiling module mpsim_avmm_agent_cra_inst
# 
# Top level modules:
# 	mpsim_avmm_agent_cra_inst
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_avalon_mm_bridge_2010/sim/mpsim_ki_altera_avalon_mm_bridge_2010_tex5a4i.v -work altera_avalon_mm_bridge_2010 
# -- Compiling module mpsim_ki_altera_avalon_mm_bridge_2010_tex5a4i
# 
# Top level modules:
# 	mpsim_ki_altera_avalon_mm_bridge_2010_tex5a4i
# End time: 00:49:19 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:19 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_avalon_mm_bridge_2010/sim/altera_merlin_waitrequest_adapter.v -work altera_avalon_mm_bridge_2010 
# -- Compiling module altera_merlin_waitrequest_adapter
# 
# Top level modules:
# 	altera_merlin_waitrequest_adapter
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_avalon_mm_bridge_2010/sim/altera_avalon_sc_fifo.v -work altera_avalon_mm_bridge_2010 
# -- Compiling module altera_avalon_sc_fifo
# 
# Top level modules:
# 	altera_avalon_sc_fifo
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_address_span_extender_1920/sim/mpsim_ki_altera_address_span_extender_1920_vz4724i.sv -work altera_address_span_extender_1920 
# -- Compiling module mpsim_ki_altera_address_span_extender_1920_vz4724i
# 
# Top level modules:
# 	mpsim_ki_altera_address_span_extender_1920_vz4724i
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/sw_reset_100/sim/sw_reset.v -work sw_reset_100 
# -- Compiling module sw_reset
# 
# Top level modules:
# 	sw_reset
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/global_routing_reset_100/sim/global_routing_sim_model.v -work global_routing_reset_100 
# -- Compiling module global_routing
# 
# Top level modules:
# 	global_routing
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/mem_org_mode_100/sim/mem_org_mode.v -work mem_org_mode_100 
# -- Compiling module mem_org_mode
# 
# Top level modules:
# 	mem_org_mode
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_irq_bridge_2000/sim/mpsim_ki_altera_irq_bridge_2000_mzhkeuq.v -work altera_irq_bridge_2000 
# -- Compiling module mpsim_ki_altera_irq_bridge_2000_mzhkeuq
# 
# Top level modules:
# 	mpsim_ki_altera_irq_bridge_2000_mzhkeuq
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/version_id_100/sim/version_id.v -work version_id_100 
# -- Compiling module version_id
# 
# Top level modules:
# 	version_id
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_reset_controller_1924/sim/altera_reset_controller.v -work altera_reset_controller_1924 
# -- Compiling module altera_reset_controller
# 
# Top level modules:
# 	altera_reset_controller
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_reset_controller_1924/sim/altera_reset_synchronizer.v -work altera_reset_controller_1924 
# -- Compiling module altera_reset_synchronizer
# 
# Top level modules:
# 	altera_reset_synchronizer
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_master_translator_192/sim/mpsim_ki_altera_merlin_master_translator_192_54w642y.sv -work altera_merlin_master_translator_192 
# -- Compiling module mpsim_ki_altera_merlin_master_translator_192_54w642y
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_master_translator_192_54w642y
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_slave_translator_191/sim/mpsim_ki_altera_merlin_slave_translator_191_xg7rzxi.sv -work altera_merlin_slave_translator_191 
# -- Compiling module mpsim_ki_altera_merlin_slave_translator_191_xg7rzxi
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_slave_translator_191_xg7rzxi
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_master_agent_1930/sim/mpsim_ki_altera_merlin_master_agent_1930_l64uqry.sv -work altera_merlin_master_agent_1930 
# -- Compiling module mpsim_ki_altera_merlin_master_agent_1930_l64uqry
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_master_agent_1930_l64uqry
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_slave_agent_1930/sim/mpsim_ki_altera_merlin_slave_agent_1930_jxauz3i.sv -work altera_merlin_slave_agent_1930 
# -- Compiling module mpsim_ki_altera_merlin_slave_agent_1930_jxauz3i
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_slave_agent_1930_jxauz3i
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv -work altera_merlin_slave_agent_1930 
# -- Compiling module altera_merlin_burst_uncompressor
# 
# Top level modules:
# 	altera_merlin_burst_uncompressor
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_avalon_sc_fifo_1932/sim/mpsim_ki_altera_avalon_sc_fifo_1932_onpcouq.v -work altera_avalon_sc_fifo_1932 
# -- Compiling module mpsim_ki_altera_avalon_sc_fifo_1932_onpcouq
# 
# Top level modules:
# 	mpsim_ki_altera_avalon_sc_fifo_1932_onpcouq
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_router_1921/sim/mpsim_ki_altera_merlin_router_1921_462bhxq.sv -work altera_merlin_router_1921 
# -- Compiling module mpsim_ki_altera_merlin_router_1921_462bhxq_default_decode
# -- Compiling module mpsim_ki_altera_merlin_router_1921_462bhxq
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_router_1921_462bhxq
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_router_1921/sim/mpsim_ki_altera_merlin_router_1921_qo376wy.sv -work altera_merlin_router_1921 
# -- Compiling module mpsim_ki_altera_merlin_router_1921_qo376wy_default_decode
# -- Compiling module mpsim_ki_altera_merlin_router_1921_qo376wy
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_router_1921_qo376wy
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_demultiplexer_1921/sim/mpsim_ki_altera_merlin_demultiplexer_1921_p6jr2wa.sv -work altera_merlin_demultiplexer_1921 
# -- Compiling module mpsim_ki_altera_merlin_demultiplexer_1921_p6jr2wa
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_demultiplexer_1921_p6jr2wa
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_multiplexer_1922/sim/mpsim_ki_altera_merlin_multiplexer_1922_kqpdb4a.sv -work altera_merlin_multiplexer_1922 
# -- Compiling module mpsim_ki_altera_merlin_multiplexer_1922_kqpdb4a
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_multiplexer_1922_kqpdb4a
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv -work altera_merlin_multiplexer_1922 
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_multiplexer_1922/sim/mpsim_ki_altera_merlin_multiplexer_1922_zl6mqja.sv -work altera_merlin_multiplexer_1922 
# -- Compiling module mpsim_ki_altera_merlin_multiplexer_1922_zl6mqja
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_multiplexer_1922_zl6mqja
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv -work altera_merlin_multiplexer_1922 
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:20 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/hs_clk_xer_1941/sim/mpsim_ki_hs_clk_xer_1941_ufej3ri.v -work hs_clk_xer_1941 
# -- Compiling module mpsim_ki_hs_clk_xer_1941_ufej3ri
# 
# Top level modules:
# 	mpsim_ki_hs_clk_xer_1941_ufej3ri
# End time: 00:49:20 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/hs_clk_xer_1941/sim/altera_reset_synchronizer.v -work hs_clk_xer_1941 
# -- Compiling module altera_reset_synchronizer
# 
# Top level modules:
# 	altera_reset_synchronizer
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/hs_clk_xer_1941/sim/altera_avalon_st_clock_crosser.v -work hs_clk_xer_1941 
# -- Compiling module altera_avalon_st_clock_crosser
# 
# Top level modules:
# 	altera_avalon_st_clock_crosser
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/hs_clk_xer_1941/sim/altera_avalon_st_pipeline_base.v -work hs_clk_xer_1941 
# -- Compiling module altera_avalon_st_pipeline_base
# 
# Top level modules:
# 	altera_avalon_st_pipeline_base
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/hs_clk_xer_1941/sim/altera_std_synchronizer_nocut.v -work hs_clk_xer_1941 
# -- Compiling module altera_std_synchronizer_nocut
# 
# Top level modules:
# 	altera_std_synchronizer_nocut
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_mm_interconnect_1920/sim/mpsim_ki_altera_mm_interconnect_1920_qyya7ny.v -work altera_mm_interconnect_1920 
# -- Compiling module mpsim_ki_altera_mm_interconnect_1920_qyya7ny
# 
# Top level modules:
# 	mpsim_ki_altera_mm_interconnect_1920_qyya7ny
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_router_1921/sim/mpsim_ki_altera_merlin_router_1921_h3b4hlq.sv -work altera_merlin_router_1921 
# -- Compiling module mpsim_ki_altera_merlin_router_1921_h3b4hlq_default_decode
# -- Compiling module mpsim_ki_altera_merlin_router_1921_h3b4hlq
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_router_1921_h3b4hlq
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_router_1921/sim/mpsim_ki_altera_merlin_router_1921_mndf7xa.sv -work altera_merlin_router_1921 
# -- Compiling module mpsim_ki_altera_merlin_router_1921_mndf7xa_default_decode
# -- Compiling module mpsim_ki_altera_merlin_router_1921_mndf7xa
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_router_1921_mndf7xa
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_router_1921/sim/mpsim_ki_altera_merlin_router_1921_7r3h3sq.sv -work altera_merlin_router_1921 
# -- Compiling module mpsim_ki_altera_merlin_router_1921_7r3h3sq_default_decode
# -- Compiling module mpsim_ki_altera_merlin_router_1921_7r3h3sq
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_router_1921_7r3h3sq
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_traffic_limiter_1921/sim/mpsim_ki_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1921_xk7jela.v -work altera_merlin_traffic_limiter_1921 
# -- Compiling module mpsim_ki_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1921_xk7jela
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1921_xk7jela
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_traffic_limiter_1921/sim/altera_merlin_reorder_memory.sv -work altera_merlin_traffic_limiter_1921 
# -- Compiling module altera_merlin_reorder_memory
# -- Compiling module memory_pointer_controller
# 
# Top level modules:
# 	altera_merlin_reorder_memory
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_traffic_limiter_1921/sim/altera_avalon_st_pipeline_base.v -work altera_merlin_traffic_limiter_1921 
# -- Compiling module altera_avalon_st_pipeline_base
# 
# Top level modules:
# 	altera_avalon_st_pipeline_base
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_traffic_limiter_1921/sim/mpsim_ki_altera_merlin_traffic_limiter_1921_3mmasty.sv -work altera_merlin_traffic_limiter_1921 
# -- Compiling module mpsim_ki_altera_merlin_traffic_limiter_1921_3mmasty
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_traffic_limiter_1921_3mmasty
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_demultiplexer_1921/sim/mpsim_ki_altera_merlin_demultiplexer_1921_vnl2yiy.sv -work altera_merlin_demultiplexer_1921 
# -- Compiling module mpsim_ki_altera_merlin_demultiplexer_1921_vnl2yiy
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_demultiplexer_1921_vnl2yiy
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_multiplexer_1922/sim/mpsim_ki_altera_merlin_multiplexer_1922_ia6emmq.sv -work altera_merlin_multiplexer_1922 
# -- Compiling module mpsim_ki_altera_merlin_multiplexer_1922_ia6emmq
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_multiplexer_1922_ia6emmq
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv -work altera_merlin_multiplexer_1922 
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_demultiplexer_1921/sim/mpsim_ki_altera_merlin_demultiplexer_1921_pgmvl6a.sv -work altera_merlin_demultiplexer_1921 
# -- Compiling module mpsim_ki_altera_merlin_demultiplexer_1921_pgmvl6a
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_demultiplexer_1921_pgmvl6a
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_multiplexer_1922/sim/mpsim_ki_altera_merlin_multiplexer_1922_76stkzq.sv -work altera_merlin_multiplexer_1922 
# -- Compiling module mpsim_ki_altera_merlin_multiplexer_1922_76stkzq
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_multiplexer_1922_76stkzq
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv -work altera_merlin_multiplexer_1922 
# -- Compiling module altera_merlin_arbitrator
# -- Compiling module altera_merlin_arb_adder
# 
# Top level modules:
# 	altera_merlin_arbitrator
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_width_adapter_1950/sim/mpsim_ki_altera_merlin_width_adapter_1950_45pnevq.sv -work altera_merlin_width_adapter_1950 
# -- Compiling module mpsim_ki_altera_merlin_width_adapter_1950_45pnevq
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_width_adapter_1950_45pnevq
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_width_adapter_1950/sim/altera_merlin_address_alignment.sv -work altera_merlin_width_adapter_1950 
# -- Compiling module altera_merlin_address_alignment
# 
# Top level modules:
# 	altera_merlin_address_alignment
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_width_adapter_1950/sim/altera_merlin_burst_uncompressor.sv -work altera_merlin_width_adapter_1950 
# -- Compiling module altera_merlin_burst_uncompressor
# 
# Top level modules:
# 	altera_merlin_burst_uncompressor
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_width_adapter_1950/sim/mpsim_ki_altera_merlin_width_adapter_1950_hbzf6ha.sv -work altera_merlin_width_adapter_1950 
# -- Compiling module mpsim_ki_altera_merlin_width_adapter_1950_hbzf6ha
# 
# Top level modules:
# 	mpsim_ki_altera_merlin_width_adapter_1950_hbzf6ha
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_width_adapter_1950/sim/altera_merlin_address_alignment.sv -work altera_merlin_width_adapter_1950 
# -- Compiling module altera_merlin_address_alignment
# 
# Top level modules:
# 	altera_merlin_address_alignment
# End time: 00:49:21 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:21 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_merlin_width_adapter_1950/sim/altera_merlin_burst_uncompressor.sv -work altera_merlin_width_adapter_1950 
# -- Compiling module altera_merlin_burst_uncompressor
# 
# Top level modules:
# 	altera_merlin_burst_uncompressor
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/altera_mm_interconnect_1920/sim/mpsim_ki_altera_mm_interconnect_1920_cuy7uay.v -work altera_mm_interconnect_1920 
# -- Compiling module mpsim_ki_altera_mm_interconnect_1920_cuy7uay
# 
# Top level modules:
# 	mpsim_ki_altera_mm_interconnect_1920_cuy7uay
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/kernel_interface_151/sim/mpsim_ki_kernel_interface_151_yqsw7ei.v -work kernel_interface_151 
# -- Compiling module mpsim_ki_kernel_interface_151_yqsw7ei
# 
# Top level modules:
# 	mpsim_ki_kernel_interface_151_yqsw7ei
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_ki/sim/mpsim_ki.v -work mpsim_ki 
# -- Compiling module mpsim_ki
# 
# Top level modules:
# 	mpsim_ki
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_clk_1x/sim/kernel_system_clk_1x.v -work kernel_system_clk_1x 
# -- Compiling module kernel_system_clk_1x
# 
# Top level modules:
# 	kernel_system_clk_1x
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_kernel_irq/altera_irq_bridge_2000/sim/kernel_system_kernel_irq_altera_irq_bridge_2000_mzhkeuq.v -work altera_irq_bridge_2000 
# -- Compiling module kernel_system_kernel_irq_altera_irq_bridge_2000_mzhkeuq
# 
# Top level modules:
# 	kernel_system_kernel_irq_altera_irq_bridge_2000_mzhkeuq
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_kernel_irq/sim/kernel_system_kernel_irq.v -work kernel_system_kernel_irq 
# -- Compiling module kernel_system_kernel_irq
# 
# Top level modules:
# 	kernel_system_kernel_irq
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_reset_handler.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_reset_handler
# 
# Top level modules:
# 	acl_reset_handler
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/simple_add_buffers_fpga_sim_di.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module simple_add_buffers_fpga_sim_di
# -- Compiling module const_lambda_std_ic_partition_wrapper
# -- Compiling module const_lambda_top_wrapper_0
# ** Warning: ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/simple_add_buffers_fpga_sim_di.sv(493): (vlog-13314) Defaulting port 'global_offset' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/simple_add_buffers_fpga_sim_di.sv(497): (vlog-13314) Defaulting port 'global_id' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/simple_add_buffers_fpga_sim_di.sv(498): (vlog-13314) Defaulting port 'local_id' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/simple_add_buffers_fpga_sim_di.sv(499): (vlog-13314) Defaulting port 'group_id' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/simple_add_buffers_fpga_sim_di.sv(500): (vlog-13314) Defaulting port 'global_size' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/simple_add_buffers_fpga_sim_di.sv(501): (vlog-13314) Defaulting port 'local_size' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/simple_add_buffers_fpga_sim_di.sv(502): (vlog-13314) Defaulting port 'num_groups' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# -- Compiling module cra_ring_wrapper
# 
# Top level modules:
# 	simple_add_buffers_fpga_sim_di
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 7
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/simple_add_buffers_fpga_sim_sys.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module simple_add_buffers_fpga_sim_sys
# 
# Top level modules:
# 	simple_add_buffers_fpga_sim_sys
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_work_group_dispatcher.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_work_group_dispatcher
# 
# Top level modules:
# 	acl_work_group_dispatcher
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_kernel_finish_detector.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_kernel_finish_detector
# 
# Top level modules:
# 	acl_kernel_finish_detector
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_multistage_accumulator.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_multistage_accumulator
# 
# Top level modules:
# 	acl_multistage_accumulator
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_std_synchronizer_nocut.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_std_synchronizer_nocut
# 
# Top level modules:
# 	acl_std_synchronizer_nocut
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_fanout_pipeline.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_fanout_pipeline
# 
# Top level modules:
# 	acl_fanout_pipeline
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_ecc_pkg.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling package acl_ecc_pkg
# 
# Top level modules:
# 	--none--
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_id_iterator.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_id_iterator
# 
# Top level modules:
# 	acl_id_iterator
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_work_item_iterator.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_work_item_iterator
# 
# Top level modules:
# 	acl_work_item_iterator
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_multistage_adder.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_multistage_adder
# 
# Top level modules:
# 	acl_multistage_adder
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_shift_register.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_shift_register
# 
# Top level modules:
# 	acl_shift_register
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_fifo
# 
# Top level modules:
# 	acl_fifo
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_fifo_stall_valid_lookahead.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_fifo_stall_valid_lookahead
# 
# Top level modules:
# 	acl_fifo_stall_valid_lookahead
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_scfifo_wrapped.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_scfifo_wrapped
# -- Importing package acl_ecc_pkg
# 
# Top level modules:
# 	acl_scfifo_wrapped
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_ecc_encoder.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_ecc_encoder
# -- Importing package acl_ecc_pkg
# -- Compiling module secded_encoder
# 
# Top level modules:
# 	acl_ecc_encoder
# End time: 00:49:22 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:22 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_ecc_decoder.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_ecc_decoder
# -- Importing package acl_ecc_pkg
# -- Compiling module secded_decoder
# 
# Top level modules:
# 	acl_ecc_decoder
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/dspba_library_ver.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module dspba_delay_ver
# -- Compiling module dspba_sync_reg_ver
# -- Compiling module dspba_pipe
# -- Compiling module dspba_dcfifo_mixed_widths
# 
# Top level modules:
# 	dspba_delay_ver
# 	dspba_sync_reg_ver
# 	dspba_pipe
# 	dspba_dcfifo_mixed_widths
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_data_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_data_fifo
# 
# Top level modules:
# 	--none--
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_altera_syncram_wrapped.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_altera_syncram_wrapped
# -- Importing package acl_ecc_pkg
# 
# Top level modules:
# 	acl_altera_syncram_wrapped
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_ll_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_ll_fifo
# 
# Top level modules:
# 	acl_ll_fifo
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_ll_ram_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_ll_ram_fifo
# 
# Top level modules:
# 	acl_ll_ram_fifo
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_valid_fifo_counter.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_valid_fifo_counter
# 
# Top level modules:
# 	acl_valid_fifo_counter
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_dspba_valid_fifo_counter.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_dspba_valid_fifo_counter
# 
# Top level modules:
# 	acl_dspba_valid_fifo_counter
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_staging_reg.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_staging_reg
# 
# Top level modules:
# 	acl_staging_reg
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_fifo
# 
# Top level modules:
# 	--none--
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_mid_speed_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_mid_speed_fifo
# 
# Top level modules:
# 	acl_mid_speed_fifo
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_latency_one_ram_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_latency_one_ram_fifo
# 
# Top level modules:
# 	acl_latency_one_ram_fifo
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_latency_zero_ram_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_latency_zero_ram_fifo
# 
# Top level modules:
# 	acl_latency_zero_ram_fifo
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_fifo_zero_width.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_fifo_zero_width
# 
# Top level modules:
# 	hld_fifo_zero_width
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_high_speed_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_high_speed_fifo
# -- Compiling module scfifo_to_acl_high_speed_fifo
# 
# Top level modules:
# 	scfifo_to_acl_high_speed_fifo
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_low_latency_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_low_latency_fifo
# 
# Top level modules:
# 	acl_low_latency_fifo
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_zero_latency_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_zero_latency_fifo
# 
# Top level modules:
# 	acl_zero_latency_fifo
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_tessellated_incr_decr_threshold.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_tessellated_incr_decr_threshold
# 
# Top level modules:
# 	acl_tessellated_incr_decr_threshold
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_tessellated_incr_lookahead.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_tessellated_incr_lookahead
# 
# Top level modules:
# 	acl_tessellated_incr_lookahead
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_lfsr.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_lfsr
# -- Compiling module galois_lfsr
# -- Compiling module fibonacci_lfsr
# 
# Top level modules:
# 	acl_lfsr
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_mlab_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_mlab_fifo
# 
# Top level modules:
# 	acl_mlab_fifo
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_parameter_assert.svh -work simple_add_buffers_fpga_sim_sys_140 
# End time: 00:49:23 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:23 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_dspba_buffer.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_dspba_buffer
# 
# Top level modules:
# 	acl_dspba_buffer
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_full_detector.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_full_detector
# 
# Top level modules:
# 	acl_full_detector
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_tessellated_incr_decr_decr.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_tessellated_incr_decr_decr
# -- Compiling module acl_tessellated_incr_decr
# 
# Top level modules:
# 	acl_tessellated_incr_decr_decr
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_top.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_top
# 
# Top level modules:
# 	lsu_top
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_permute_address.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_permute_address
# 
# Top level modules:
# 	lsu_permute_address
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_pipelined.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_pipelined_read
# -- Compiling module lsu_pipelined_write
# 
# Top level modules:
# 	lsu_pipelined_read
# 	lsu_pipelined_write
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_enabled.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_enabled_read
# -- Compiling module lsu_enabled_write
# 
# Top level modules:
# 	lsu_enabled_read
# 	lsu_enabled_write
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_basic_coalescer.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_basic_coalesced_read
# -- Compiling module lsu_basic_coalesced_write
# -- Compiling module lookahead_fifo
# -- Compiling module basic_coalescer
# 
# Top level modules:
# 	lsu_basic_coalesced_read
# 	lsu_basic_coalesced_write
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_simple.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_simple_read
# -- Compiling module lsu_simple_write
# 
# Top level modules:
# 	lsu_simple_read
# 	lsu_simple_write
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_burst_host.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_burst_read_host
# 
# Top level modules:
# 	lsu_burst_read_host
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_bursting_load_stores.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_bursting_read
# -- Compiling module acl_io_pipeline
# -- Compiling module lsu_bursting_pipelined_read
# -- Compiling module acl_stall_free_coalescer
# -- Compiling module lsu_bursting_write
# -- Compiling module lsu_bursting_write_internal
# -- Compiling module bursting_coalescer
# 
# Top level modules:
# 	lsu_bursting_read
# 	lsu_bursting_write
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_non_aligned_write.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_non_aligned_write
# -- Compiling module lsu_non_aligned_write_internal
# 
# Top level modules:
# 	lsu_non_aligned_write
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_read_cache.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_read_cache
# 
# Top level modules:
# 	lsu_read_cache
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_atomic.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_atomic_pipelined
# 
# Top level modules:
# 	lsu_atomic_pipelined
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_prefetch_block.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_prefetch_block
# 
# Top level modules:
# 	lsu_prefetch_block
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_wide_wrapper.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_wide_wrapper
# 
# Top level modules:
# 	lsu_wide_wrapper
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_streaming_prefetch.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_streaming_prefetch_read
# -- Compiling module lsu_streaming_prefetch_fifo
# -- Compiling module lsu_streaming_prefetch_avalon_burst_host
# 
# Top level modules:
# 	lsu_streaming_prefetch_read
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_aligned_burst_coalesced_lsu.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_aligned_burst_coalesced_lsu
# -- Compiling module avalon_interface
# -- Compiling module valid_generator
# -- Compiling module acl_lsu_buffers
# -- Compiling module acl_burst_coalescer
# -- Compiling module acl_registered_comparison
# 
# Top level modules:
# 	acl_aligned_burst_coalesced_lsu
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_toggle_detect.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_toggle_detect
# 
# Top level modules:
# 	acl_toggle_detect
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_debug_mem.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_debug_mem
# ** Warning: ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_debug_mem.sv(38): (vlog-13314) Defaulting port 'data' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# 
# Top level modules:
# 	acl_debug_mem
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_burst_coalesced_pipelined_write.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_burst_coalesced_pipelined_write
# 
# Top level modules:
# 	lsu_burst_coalesced_pipelined_write
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_burst_coalesced_pipelined_read.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_burst_coalesced_pipelined_read
# 
# Top level modules:
# 	lsu_burst_coalesced_pipelined_read
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_global_load_store.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_global_load_store
# 
# Top level modules:
# 	hld_global_load_store
# End time: 00:49:24 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:24 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_lsu.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_lsu
# 
# Top level modules:
# 	hld_lsu
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_lsu_burst_coalescer.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_lsu_burst_coalescer
# 
# Top level modules:
# 	hld_lsu_burst_coalescer
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_lsu_coalescer_dynamic_timeout.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_lsu_coalescer_dynamic_timeout
# 
# Top level modules:
# 	hld_lsu_coalescer_dynamic_timeout
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_lsu_data_aligner.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_lsu_data_aligner
# 
# Top level modules:
# 	hld_lsu_data_aligner
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_lsu_read_cache.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_lsu_read_cache
# -- Compiling module hld_lsu_read_cache_simple_dual_port_ram
# 
# Top level modules:
# 	hld_lsu_read_cache
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_lsu_read_data_alignment.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_lsu_read_data_alignment
# 
# Top level modules:
# 	hld_lsu_read_data_alignment
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_lsu_unaligned_controller.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_lsu_unaligned_controller
# 
# Top level modules:
# 	hld_lsu_unaligned_controller
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_lsu_word_coalescer.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_lsu_word_coalescer
# 
# Top level modules:
# 	hld_lsu_word_coalescer
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_lsu_write_data_alignment.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_lsu_write_data_alignment
# 
# Top level modules:
# 	hld_lsu_write_data_alignment
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_lsu_write_kernel_downstream.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_lsu_write_kernel_downstream
# 
# Top level modules:
# 	hld_lsu_write_kernel_downstream
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_shift_register_no_reset.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_shift_register_no_reset
# 
# Top level modules:
# 	acl_shift_register_no_reset
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_sync.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_sync
# -- Compiling module acl_sync_predicate_nonblocking
# -- Compiling module acl_sync_stall_latency
# 
# Top level modules:
# 	acl_sync
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/hld_sim_latency_tracker.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module hld_sim_latency_tracker
# 
# Top level modules:
# 	hld_sim_latency_tracker
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_function_wrapper.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_function_wrapper
# 
# Top level modules:
# 	const_lambda_function_wrapper
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_function.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_function
# 
# Top level modules:
# 	const_lambda_function
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_bb_B0.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_bb_B0
# 
# Top level modules:
# 	const_lambda_bb_B0
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_bb_B0_stall_region.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_bb_B0_stall_region
# 
# Top level modules:
# 	const_lambda_bb_B0_stall_region
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_i_llvm_fpga_mem_unnamed_1_const_lambda_124_0gr.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_i_llvm_fpga_mem_unnamed_1_const_lambda_124_0gr
# 
# Top level modules:
# 	const_lambda_i_llvm_fpga_mem_unnamed_1_const_lambda_124_0gr
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_i_sfc_s_c0_in_entry_s_c0_enter_const_lambda_41_1gr.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_i_sfc_s_c0_in_entry_s_c0_enter_const_lambda_41_1gr
# 
# Top level modules:
# 	const_lambda_i_sfc_s_c0_in_entry_s_c0_enter_const_lambda_41_1gr
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_i_llvm_fpga_sfc_exit_s_c0_o0000const_lambda_113_0gr.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_i_llvm_fpga_sfc_exit_s_c0_o0000const_lambda_113_0gr
# 
# Top level modules:
# 	const_lambda_i_llvm_fpga_sfc_exit_s_c0_o0000const_lambda_113_0gr
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_i_llvm_fpga_sfc_exit_s_c0_o000048_1gr_full_detector.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_i_llvm_fpga_sfc_exit_s_c0_o000048_1gr_full_detector
# 
# Top level modules:
# 	const_lambda_i_llvm_fpga_sfc_exit_s_c0_o000048_1gr_full_detector
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_i_llvm_fpga_sfc_exit_s_c0_o0000da_113_1gr_data_fifo.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_i_llvm_fpga_sfc_exit_s_c0_o0000da_113_1gr_data_fifo
# 
# Top level modules:
# 	const_lambda_i_llvm_fpga_sfc_exit_s_c0_o0000da_113_1gr_data_fifo
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_i_sfc_logic_s_c0_in_entry_s0000_const_lambda_48_0gr.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_i_sfc_logic_s_c0_in_entry_s0000_const_lambda_48_0gr
# 
# Top level modules:
# 	const_lambda_i_sfc_logic_s_c0_in_entry_s0000_const_lambda_48_0gr
# End time: 00:49:25 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:25 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_i_llvm_fpga_sync_buffer_i320000e_sync_buffer_96_0gr.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_i_llvm_fpga_sync_buffer_i320000e_sync_buffer_96_0gr
# 
# Top level modules:
# 	const_lambda_i_llvm_fpga_sync_buffer_i320000e_sync_buffer_96_0gr
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_i_llvm_fpga_sync_buffer_p100000a_sync_buffer_81_0gr.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_i_llvm_fpga_sync_buffer_p100000a_sync_buffer_81_0gr
# 
# Top level modules:
# 	const_lambda_i_llvm_fpga_sync_buffer_p100000a_sync_buffer_81_0gr
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_i_llvm_fpga_sync_buffer_s_c00004_sync_buffer_56_0gr.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_i_llvm_fpga_sync_buffer_s_c00004_sync_buffer_56_0gr
# 
# Top level modules:
# 	const_lambda_i_llvm_fpga_sync_buffer_s_c00004_sync_buffer_56_0gr
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_B0_branch.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_B0_branch
# 
# Top level modules:
# 	const_lambda_B0_branch
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_B0_branch_branch_storage.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_B0_branch_branch_storage
# 
# Top level modules:
# 	const_lambda_B0_branch_branch_storage
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_B0_merge.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_B0_merge
# 
# Top level modules:
# 	const_lambda_B0_merge
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_B0_merge_storage.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_B0_merge_storage
# 
# Top level modules:
# 	const_lambda_B0_merge_storage
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/const_lambda_function_cra_agent.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module const_lambda_function_cra_agent
# 
# Top level modules:
# 	const_lambda_function_cra_agent
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_start_signal_chain_element.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_start_signal_chain_element
# 
# Top level modules:
# 	acl_start_signal_chain_element
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_ic_top.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_ic_top
# -- Compiling module debug_io_cnt
# -- Compiling module address_permuter
# 
# Top level modules:
# 	lsu_ic_top
# 	debug_io_cnt
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_ic_hybrid.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_ic_hybrid
# 
# Top level modules:
# 	lsu_ic_hybrid
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_ic_token.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_ic_token
# 
# Top level modules:
# 	lsu_ic_token
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_ic_unbalance.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_ic_unbalance
# 
# Top level modules:
# 	lsu_ic_unbalance
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_n_fast.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_n_fast
# 
# Top level modules:
# 	lsu_n_fast
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_n_token.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_n_token
# 
# Top level modules:
# 	lsu_n_token
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_rd_back.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_rd_back
# 
# Top level modules:
# 	lsu_rd_back
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_rd_back_n.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_rd_back_n
# 
# Top level modules:
# 	lsu_rd_back_n
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_swdimm_token_ring.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_swdimm_token_ring
# 
# Top level modules:
# 	lsu_swdimm_token_ring
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/lsu_token_ring.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module lsu_token_ring
# 
# Top level modules:
# 	lsu_token_ring
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_skid_buffer.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_skid_buffer
# 
# Top level modules:
# 	acl_skid_buffer
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/cra_ring_node.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module cra_ring_node
# 
# Top level modules:
# 	cra_ring_node
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/cra_ring_root.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module cra_ring_root
# 
# Top level modules:
# 	cra_ring_root
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/cra_ring_rom.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module cra_ring_rom
# 
# Top level modules:
# 	cra_ring_rom
# End time: 00:49:26 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:26 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/simple_add_buffers_fpga_sim_sys_140/sim/acl_rom_module.sv -work simple_add_buffers_fpga_sim_sys_140 
# -- Compiling module acl_rom_module
# 
# Top level modules:
# 	acl_rom_module
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_simple_add_buffers_fpga_sim_sys/sim/kernel_system_simple_add_buffers_fpga_sim_sys.v -work kernel_system_simple_add_buffers_fpga_sim_sys 
# -- Compiling module kernel_system_simple_add_buffers_fpga_sim_sys
# 
# Top level modules:
# 	kernel_system_simple_add_buffers_fpga_sim_sys
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_reset/sim/kernel_system_reset.v -work kernel_system_reset 
# -- Compiling module kernel_system_reset
# 
# Top level modules:
# 	kernel_system_reset
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_kernel_cra/altera_avalon_mm_bridge_2010/sim/kernel_system_kernel_cra_altera_avalon_mm_bridge_2010_tex5a4i.v -work altera_avalon_mm_bridge_2010 
# -- Compiling module kernel_system_kernel_cra_altera_avalon_mm_bridge_2010_tex5a4i
# 
# Top level modules:
# 	kernel_system_kernel_cra_altera_avalon_mm_bridge_2010_tex5a4i
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_kernel_cra/altera_avalon_mm_bridge_2010/sim/altera_merlin_waitrequest_adapter.v -work altera_avalon_mm_bridge_2010 
# -- Compiling module altera_merlin_waitrequest_adapter
# 
# Top level modules:
# 	altera_merlin_waitrequest_adapter
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_kernel_cra/altera_avalon_mm_bridge_2010/sim/altera_avalon_sc_fifo.v -work altera_avalon_mm_bridge_2010 
# -- Compiling module altera_avalon_sc_fifo
# 
# Top level modules:
# 	altera_avalon_sc_fifo
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/kernel_system/kernel_system_kernel_cra/sim/kernel_system_kernel_cra.v -work kernel_system_kernel_cra 
# -- Compiling module kernel_system_kernel_cra
# 
# Top level modules:
# 	kernel_system_kernel_cra
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 kernel_system/altera_merlin_master_translator_192/sim/kernel_system_altera_merlin_master_translator_192_54w642y.sv -work altera_merlin_master_translator_192 
# -- Compiling module kernel_system_altera_merlin_master_translator_192_54w642y
# 
# Top level modules:
# 	kernel_system_altera_merlin_master_translator_192_54w642y
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 kernel_system/altera_merlin_slave_translator_191/sim/kernel_system_altera_merlin_slave_translator_191_xg7rzxi.sv -work altera_merlin_slave_translator_191 
# -- Compiling module kernel_system_altera_merlin_slave_translator_191_xg7rzxi
# 
# Top level modules:
# 	kernel_system_altera_merlin_slave_translator_191_xg7rzxi
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 kernel_system/altera_mm_interconnect_1920/sim/kernel_system_altera_mm_interconnect_1920_erxnzwa.v -work altera_mm_interconnect_1920 
# -- Compiling module kernel_system_altera_mm_interconnect_1920_erxnzwa
# 
# Top level modules:
# 	kernel_system_altera_mm_interconnect_1920_erxnzwa
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 kernel_system/altera_irq_mapper_2001/sim/kernel_system_altera_irq_mapper_2001_wgtbcyy.sv -work altera_irq_mapper_2001 
# -- Compiling module kernel_system_altera_irq_mapper_2001_wgtbcyy
# 
# Top level modules:
# 	kernel_system_altera_irq_mapper_2001_wgtbcyy
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 kernel_system/sim/kernel_system.v -work kernel_system 
# -- Compiling module kernel_system
# 
# Top level modules:
# 	kernel_system
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/sp_csr_ready/avalon_split_multibit_conduit_10/sim/sp_csr_ready_avalon_split_multibit_conduit_10_6ihlvbi.sv -work avalon_split_multibit_conduit_10 
# -- Compiling module sp_csr_ready_avalon_split_multibit_conduit_10_6ihlvbi
# 
# Top level modules:
# 	sp_csr_ready_avalon_split_multibit_conduit_10_6ihlvbi
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/sp_csr_ready/sim/sp_csr_ready.v -work sp_csr_ready 
# -- Compiling module sp_csr_ready
# 
# Top level modules:
# 	sp_csr_ready
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mm_agent_ks_mem0_rw/aoc_sim_mm_slave_dpi_bfm_10/sim/altera_avalon_mm_slave_bfm.sv -L altera_common_sv_packages -work aoc_sim_mm_slave_dpi_bfm_10 
# -- Compiling module altera_avalon_mm_slave_bfm
# -- Importing package altera_common_sv_packages.verbosity_pkg
# -- Importing package altera_common_sv_packages.avalon_mm_pkg
# -- Importing package altera_common_sv_packages.avalon_utilities_pkg
# 
# Top level modules:
# 	altera_avalon_mm_slave_bfm
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mm_agent_ks_mem0_rw/aoc_sim_mm_slave_dpi_bfm_10/sim/aoc_sim_mm_slave_dpi_bfm.sv -L altera_common_sv_packages -work aoc_sim_mm_slave_dpi_bfm_10 
# -- Compiling module aoc_sim_mm_slave_dpi_bfm
# -- Importing package altera_common_sv_packages.verbosity_pkg
# -- Importing package altera_common_sv_packages.avalon_mm_pkg
# 
# Top level modules:
# 	aoc_sim_mm_slave_dpi_bfm
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mm_agent_ks_mem0_rw/sim/mm_agent_ks_mem0_rw.v -work mm_agent_ks_mem0_rw 
# -- Compiling module mm_agent_ks_mem0_rw
# 
# Top level modules:
# 	mm_agent_ks_mem0_rw
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_clk_rst/hls_sim_clock_reset_10/sim/hls_sim_clock_reset.sv -work hls_sim_clock_reset_10 
# -- Compiling module hls_sim_clock_reset
# 
# Top level modules:
# 	hls_sim_clock_reset
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/mpsim_clk_rst/sim/mpsim_clk_rst.v -work mpsim_clk_rst 
# -- Compiling module mpsim_clk_rst
# 
# Top level modules:
# 	mpsim_clk_rst
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/done_cfan/avalon_conduit_fanout_10/sim/done_cfan_avalon_conduit_fanout_10_d5krbyi.sv -work avalon_conduit_fanout_10 
# -- Compiling module done_cfan_avalon_conduit_fanout_10_d5krbyi
# 
# Top level modules:
# 	done_cfan_avalon_conduit_fanout_10_d5krbyi
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 ip/mpsim/done_cfan/sim/done_cfan.v -work done_cfan 
# -- Compiling module done_cfan
# 
# Top level modules:
# 	done_cfan
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 mpsim/altera_merlin_master_translator_192/sim/mpsim_altera_merlin_master_translator_192_54w642y.sv -work altera_merlin_master_translator_192 
# -- Compiling module mpsim_altera_merlin_master_translator_192_54w642y
# 
# Top level modules:
# 	mpsim_altera_merlin_master_translator_192_54w642y
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 mpsim/altera_merlin_slave_translator_191/sim/mpsim_altera_merlin_slave_translator_191_xg7rzxi.sv -work altera_merlin_slave_translator_191 
# -- Compiling module mpsim_altera_merlin_slave_translator_191_xg7rzxi
# 
# Top level modules:
# 	mpsim_altera_merlin_slave_translator_191_xg7rzxi
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 mpsim/altera_mm_interconnect_1920/sim/mpsim_altera_mm_interconnect_1920_zw4jf7q.v -work altera_mm_interconnect_1920 
# -- Compiling module mpsim_altera_mm_interconnect_1920_zw4jf7q
# 
# Top level modules:
# 	mpsim_altera_mm_interconnect_1920_zw4jf7q
# End time: 00:49:27 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:27 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 mpsim/altera_irq_mapper_2001/sim/mpsim_altera_irq_mapper_2001_rctq6fa.sv -work altera_irq_mapper_2001 
# -- Compiling module mpsim_altera_irq_mapper_2001_rctq6fa
# 
# Top level modules:
# 	mpsim_altera_irq_mapper_2001_rctq6fa
# End time: 00:49:28 on Mar 29,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:28 on Mar 29,2025
# vlog -sv "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 mpsim/altera_irq_mapper_2001/sim/mpsim_altera_irq_mapper_2001_wgtbcyy.sv -work altera_irq_mapper_2001 
# -- Compiling module mpsim_altera_irq_mapper_2001_wgtbcyy
# 
# Top level modules:
# 	mpsim_altera_irq_mapper_2001_wgtbcyy
# End time: 00:49:28 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2024.1 Compiler 2024.04 Apr 19 2024
# Start time: 00:49:28 on Mar 29,2025
# vlog "+incdir+mpsim/sim" "+define+COSIM_LIB" -suppress 2388 -suppress 14408 -suppress 7061 mpsim/sim/mpsim.v -work mpsim 
# -- Compiling module mpsim
# 
# Top level modules:
# 	mpsim
# End time: 00:49:28 on Mar 29,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Errors: 0, Warnings: 0