Info: ******************************************************************* Info: Running Quartus II Fitter Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Full Version Info: Processing started: Wed Sep 01 16:29:33 2010 Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off pod32 -c pod32 Info: Selected device EP2C35F484C8 for design "pod32" Warning: Compensate clock of PLL "altpll0:inst3|altpll:altpll_component|pll" has been set to clock2 Info: Implemented PLL "altpll0:inst3|altpll:altpll_component|pll" as Cyclone II PLL type Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 180 degrees (18519 ps) for altpll0:inst3|altpll:altpll_component|_clk2 port Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning: Feature LogicLock is not available with your current license Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info: Device EP2C15AF484C8 is compatible Info: Device EP2C15AF484I8 is compatible Info: Device EP2C20F484C8 is compatible Info: Device EP2C20F484I8 is compatible Info: Device EP2C20AF484I8 is compatible Info: Device EP2C35F484I8 is compatible Info: Device EP2C50F484C8 is compatible Info: Device EP2C50F484I8 is compatible Info: Fitter converted 2 user pins into dedicated programming pins Info: Pin ~ASDO~ is reserved at location C4 Info: Pin ~nCSO~ is reserved at location C3 Warning: No exact pin location assignment(s) for 2 pins of 95 total pins Info: Pin SMPTE_BYPASS31 not assigned to an exact location on the device Info: Pin altera8 not assigned to an exact location on the device Info: Fitter is using the TimeQuest Timing Analyzer Info: Evaluating HDL-embedded SDC commands Info: Entity dcfifo_1sk1 Info: set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_hd9:dffpipe11|dffe12a* Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_gd9:dffpipe6|dffe7a* Info: Entity dcfifo_uab1 Info: set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_ed9:dffpipe10|dffe11a* Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_dd9:dffpipe7|dffe8a* Warning: At least one of the filters had some problems and could not be matched. Warning: *rdptr_g* could not be matched with a clock or keeper or register or port or pin or cell or partition. Warning: At least one of the filters had some problems and could not be matched. Warning: *ws_dgrp|dffpipe_hd9:dffpipe11|dffe12a* could not be matched with a clock or keeper or register or port or pin or cell or partition. Warning: Ignored assignment: set_false_path -from [get_clocks {*rdptr_g*}] -to [get_clocks {*ws_dgrp|dffpipe_hd9:dffpipe11|dffe12a*}] Warning: Argument -from with value *rdptr_g* could not match any element of the following types: ( clk kpr reg port pin cell partition ) Warning: Argument -to with value *ws_dgrp|dffpipe_hd9:dffpipe11|dffe12a* could not match any element of the following types: ( clk kpr reg port pin cell partition ) Warning: At least one of the filters had some problems and could not be matched. Warning: *delayed_wrptr_g* could not be matched with a clock or keeper or register or port or pin or cell or partition. Warning: At least one of the filters had some problems and could not be matched. Warning: *rs_dgwp|dffpipe_gd9:dffpipe6|dffe7a* could not be matched with a clock or keeper or register or port or pin or cell or partition. Warning: Ignored assignment: set_false_path -from [get_clocks {*delayed_wrptr_g*}] -to [get_clocks {*rs_dgwp|dffpipe_gd9:dffpipe6|dffe7a*}] Warning: Argument -from with value *delayed_wrptr_g* could not match any element of the following types: ( clk kpr reg port pin cell partition ) Warning: Argument -to with value *rs_dgwp|dffpipe_gd9:dffpipe6|dffe7a* could not match any element of the following types: ( clk kpr reg port pin cell partition ) Warning: At least one of the filters had some problems and could not be matched. Warning: *ws_dgrp|dffpipe_ed9:dffpipe10|dffe11a* could not be matched with a clock or keeper or register or port or pin or cell or partition. Warning: Ignored assignment: set_false_path -from [get_clocks {*rdptr_g*}] -to [get_clocks {*ws_dgrp|dffpipe_ed9:dffpipe10|dffe11a*}] Warning: Argument -from with value *rdptr_g* could not match any element of the following types: ( clk kpr reg port pin cell partition ) Warning: Argument -to with value *ws_dgrp|dffpipe_ed9:dffpipe10|dffe11a* could not match any element of the following types: ( clk kpr reg port pin cell partition ) Warning: At least one of the filters had some problems and could not be matched. Warning: *rs_dgwp|dffpipe_dd9:dffpipe7|dffe8a* could not be matched with a clock or keeper or register or port or pin or cell or partition. Warning: Ignored assignment: set_false_path -from [get_clocks {*delayed_wrptr_g*}] -to [get_clocks {*rs_dgwp|dffpipe_dd9:dffpipe7|dffe8a*}] Warning: Argument -from with value *delayed_wrptr_g* could not match any element of the following types: ( clk kpr reg port pin cell partition ) Warning: Argument -to with value *rs_dgwp|dffpipe_dd9:dffpipe7|dffe8a* could not match any element of the following types: ( clk kpr reg port pin cell partition ) Info: Reading SDC File: 'pod32.sdc' Info: Deriving PLL Clocks Info: create_generated_clock -source {inst3|altpll_component|pll|inclk[0]} -phase 180.00 -duty_cycle 50.00 -name {altpll0:inst3|altpll:altpll_component|_clk2} {inst3|altpll_component|pll|clk[2]} Warning: Ignored assignment: create_generated_clock -name {pclk_in_a} -source [get_pins {inst3|altpll_component|pll|inclk[0]}]50.000 -multiply_by 1 -phase 180.000 [get_pins {inst3|altpll_component|pll|clk[2]}] Warning: Incorrect assignment for clock. Source node: inst3|altpll_component|pll|clk[2] already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated. Warning: At least one of the filters had some problems and could not be matched. Warning: pclk_in_a could not be matched with a clock. Warning: Ignored assignment: create_generated_clock -name {ref662} -source [get_pins {inst3|altpll_component|pll|clk[2]}] [get_ports {ref662}] Warning: Argument: -master_clock must contain exactly one valid clock. Warning: At least one of the filters had some problems and could not be matched. Warning: ref662 could not be matched with a clock. Warning: Ignored assignment: create_generated_clock -name {clock662_27} -source [get_ports {ref662}] -divide_by 3 [get_ports {clock662_27}] Warning: Argument: -master_clock must contain exactly one valid clock. Warning: At least one of the filters had some problems and could not be matched. Warning: clock662_27 could not be matched with a clock. Warning: Ignored assignment: create_generated_clock -name {pll1705_27_a} -source [get_ports {clock662_27}] [get_ports {pll1705_27}] Warning: Argument: -master_clock must contain exactly one valid clock. Warning: At least one of the filters had some problems and could not be matched. Warning: pll_1705_mclk could not be matched with a port. Warning: At least one of the filters had some problems and could not be matched. Warning: pll1705_27_a could not be matched with a clock. Warning: Ignored assignment: create_generated_clock -name {pll_1705_mclk_a} -source [get_ports {pll1705_27}] -divide_by 2 [get_ports {pll_1705_mclk}] Warning: Argument is an empty collection Warning: Argument: -master_clock must contain exactly one valid clock. Warning: Ignored assignment: create_generated_clock -name {pll_1705_mclk_b} -source [get_ports {pll1705_27}] -divide_by 2 [get_ports {pll_1705_mclk}] -add Warning: Argument is an empty collection Warning: At least one of the filters had some problems and could not be matched. Warning: inst35|FSYNCH|regout could not be matched with a pin. Warning: At least one of the filters had some problems and could not be matched. Warning: pll_1705_mclk_a could not be matched with a clock. Warning: Ignored assignment: create_generated_clock -name {lrclk_a} -source [get_ports {pll_1705_mclk}] -divide_by 256 [get_pins {inst35|FSYNCH|regout}] Warning: Argument is an empty collection Warning: Argument -source is an empty collection Warning: Argument: -master_clock must contain exactly one valid clock. Warning: At least one of the filters had some problems and could not be matched. Warning: pll_1705_mclk_b could not be matched with a clock. Warning: Ignored assignment: create_generated_clock -name {lrclk_b} -source [get_ports {pll_1705_mclk}] -divide_by 256 [get_pins {inst35|FSYNCH|regout}] -add Warning: Argument is an empty collection Warning: Argument -source is an empty collection Warning: Argument: -master_clock must contain exactly one valid clock. Warning: At least one of the filters had some problems and could not be matched. Warning: inst35|SCLK|regout could not be matched with a pin. Warning: Ignored assignment: create_generated_clock -name {sclk_a} -source [get_ports {pll_1705_mclk}] -divide_by 4 [get_pins {inst35|SCLK|regout}] Warning: Argument is an empty collection Warning: Argument -source is an empty collection Warning: Argument: -master_clock must contain exactly one valid clock. Warning: Ignored assignment: create_generated_clock -name {sclk_b} -source [get_ports {pll_1705_mclk}] -divide_by 4 [get_pins {inst35|SCLK|regout}] -add Warning: Argument is an empty collection Warning: Argument -source is an empty collection Warning: Argument: -master_clock must contain exactly one valid clock. Warning: At least one of the filters had some problems and could not be matched. Warning: clock662_27 could not be matched with a clock. Warning: lrclk_a could not be matched with a clock. Warning: pclk_in_a could not be matched with a clock. Warning: pll_1705_mclk_a could not be matched with a clock. Warning: sclk_a could not be matched with a clock. Warning: At least one of the filters had some problems and could not be matched. Warning: lrclk_b could not be matched with a clock. Warning: pll_1705_mclk_b could not be matched with a clock. Warning: sclk_b could not be matched with a clock. Warning: The master clock for this clock assignment could not be derived. Clock: altpll0:inst3|altpll:altpll_component|_clk2 was not created. Warning: Clock: pclk_in_pin_a found as a potential master clock candidate Warning: Clock: pclk_in_pin_b found as a potential master clock candidate Warning: Node: hd274_296_decoder:inst15|h_int was determined to be a clock but was found without an associated clock assignment. Info: PLL cross checking found inconsistent PLL clock settings: Info: Clock: pclk_in_b with master clock period: 37.040 found on PLL node: inst3|altpll_component|pll|clk[2] does not match the master clock period requirement: 37.037 Info: Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info: Found 4 clocks Info: Period Clock Name Info: ======== ============ Info: 37.040 pclk_in_b Info: 13.468 pclk_in_pin_a Info: 37.040 pclk_in_pin_b Info: 37.040 pll1705_27_b Info: Automatically promoted node altpll0:inst3|altpll:altpll_component|_clk2 (placed in counter C0 of PLL_2) Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7 Info: Automatically promoted node hd274_296_decoder:inst15|h_int Info: Automatically promoted destinations to use location or clock signal Global Clock Info: Following destination nodes may be non-global or may not use global or regional clocks Info: Destination node hd274_296_decoder:inst15|h_int~0 Info: Starting register packing Info: Finished register packing Extra Info: No registers were packed into other blocks Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement Info: Number of I/O pins in group: 2 (unused VREF, 3.3V VCCIO, 1 input, 1 output, 0 bidirectional) Info: I/O standards used: 3.3-V LVTTL. Info: I/O bank details before I/O pin placement Info: Statistics of I/O banks Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used -- 31 pins available Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 22 total pin(s) used -- 17 pins available Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 10 total pin(s) used -- 29 pins available Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 1 total pin(s) used -- 35 pins available Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 12 total pin(s) used -- 32 pins available Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 25 total pin(s) used -- 18 pins available Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available Info: I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 9 total pin(s) used -- 30 pins available Warning: PLL "altpll0:inst3|altpll:altpll_component|pll" output port clk[2] feeds output pin "pclk_out" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance Warning: PLL "altpll0:inst3|altpll:altpll_component|pll" output port clk[2] feeds output pin "ref662" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance Warning: Ignored locations or region assignments to the following nodes Warning: Node "Cout[0]" is assigned to location or region, but does not exist in design Warning: Node "Cout[1]" is assigned to location or region, but does not exist in design Warning: Node "Cout[2]" is assigned to location or region, but does not exist in design Warning: Node "Cout[3]" is assigned to location or region, but does not exist in design Warning: Node "Cout[4]" is assigned to location or region, but does not exist in design Warning: Node "Cout[5]" is assigned to location or region, but does not exist in design Warning: Node "Cout[6]" is assigned to location or region, but does not exist in design Warning: Node "Cout[7]" is assigned to location or region, but does not exist in design Warning: Node "Cout[8]" is assigned to location or region, but does not exist in design Warning: Node "Cout[9]" is assigned to location or region, but does not exist in design Warning: Node "TP6" is assigned to location or region, but does not exist in design Warning: Node "Yout[0]" is assigned to location or region, but does not exist in design Warning: Node "Yout[1]" is assigned to location or region, but does not exist in design Warning: Node "Yout[2]" is assigned to location or region, but does not exist in design Warning: Node "Yout[3]" is assigned to location or region, but does not exist in design Warning: Node "Yout[4]" is assigned to location or region, but does not exist in design Warning: Node "Yout[5]" is assigned to location or region, but does not exist in design Warning: Node "Yout[6]" is assigned to location or region, but does not exist in design Warning: Node "Yout[7]" is assigned to location or region, but does not exist in design Warning: Node "Yout[8]" is assigned to location or region, but does not exist in design Warning: Node "Yout[9]" is assigned to location or region, but does not exist in design Info: Fitter preparation operations ending: elapsed time is 00:00:02 Info: Fitter placement preparation operations beginning Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 Info: Fitter placement operations beginning Info: Fitter placement was successful Info: Fitter placement operations ending: elapsed time is 00:00:01 Info: Fitter routing operations beginning Info: Average interconnect usage is 0% of the available device resources Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X55_Y12 to location X65_Y23 Info: Fitter routing operations ending: elapsed time is 00:00:00 Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info: Optimizations that may affect the design's routability were skipped Info: Optimizations that may affect the design's timing were skipped Info: Started post-fitting delay annotation Warning: Found 46 output pins without output pin load capacitance assignment Info: Pin "TP1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "TP2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "TP3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "TP4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "TP5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "SRC_BYPASS1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "SRC_BYPASS2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "SRC_BYPASS3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "SRC_BYPASS4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "rmck1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "rmck2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "rmck3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "rmck4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "lrck_scr1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "lrck_scr2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "lrck_scr3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "lrck_scr4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "sclk_scr1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "sclk_scr2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "sclk_scr3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "sclk_scr4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "pclk_out" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "SDO_EN31" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "sd/hd_31" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "20/10_31" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "DVB_ASI_31" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "SMPTE_BYPASS31" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "proc_31" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "altera0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "altera1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "sd/hd_1528" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "20/10_59" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "AES1_8416" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "AES2_8416" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "AES3_8416" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "AES4_8416" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "AES_OUT1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "AES_OUT2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "AES_OUT3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "AES_OUT4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "sel662_0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "sel662_1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "sel662_2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "sel662_3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "ref662" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "pll1705_27" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Delay annotation completed successfully Warning: Following 28 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results Info: Pin TP1 has GND driving its datain port Info: Pin TP2 has GND driving its datain port Info: Pin TP3 has GND driving its datain port Info: Pin TP4 has GND driving its datain port Info: Pin SRC_BYPASS1 has GND driving its datain port Info: Pin SRC_BYPASS2 has GND driving its datain port Info: Pin SRC_BYPASS3 has GND driving its datain port Info: Pin SRC_BYPASS4 has GND driving its datain port Info: Pin rmck1 has GND driving its datain port Info: Pin rmck2 has GND driving its datain port Info: Pin rmck3 has GND driving its datain port Info: Pin rmck4 has GND driving its datain port Info: Pin lrck_scr1 has GND driving its datain port Info: Pin lrck_scr2 has GND driving its datain port Info: Pin lrck_scr3 has GND driving its datain port Info: Pin lrck_scr4 has GND driving its datain port Info: Pin sclk_scr1 has GND driving its datain port Info: Pin sclk_scr2 has GND driving its datain port Info: Pin sclk_scr3 has GND driving its datain port Info: Pin sclk_scr4 has GND driving its datain port Info: Pin SDO_EN31 has VCC driving its datain port Info: Pin DVB_ASI_31 has GND driving its datain port Info: Pin SMPTE_BYPASS31 has VCC driving its datain port Info: Pin proc_31 has VCC driving its datain port Info: Pin altera0 has GND driving its datain port Info: Pin sel662_0 has VCC driving its datain port Info: Pin sel662_1 has VCC driving its datain port Info: Pin sel662_2 has VCC driving its datain port Info: Quartus II Fitter was successful. 0 errors, 114 warnings Info: Peak virtual memory: 271 megabytes Info: Processing ended: Wed Sep 01 16:29:49 2010 Info: Elapsed time: 00:00:16 Info: Total CPU time (on all processors): 00:00:09