library ieee; use ieee.std_logic_1164.all; Use ieee.numeric_std.all; Entity shift_detector is PORT( clk : IN STD_LOGIC; done : IN STD_LOGIC; hex : IN STD_LOGIC_VECTOR(7 DOWNTO 0); shift : OUT STD_LOGIC ); End shift_detector; Architecture arch of shift_detector is type statetype is ( MAKE, BREAK_RECEIVED); signal next_state, current_state : statetype; signal left_pressed : std_logic:='0'; signal right_pressed : std_logic:='0'; -- left is 12 0001 0010 -- break code is 1111 0000 0001 0010 F012 -- right is 59 0101 1001 -- break code is 1111 0000 0101 1001 F059 begin shift <= left_pressed or right_pressed; state_reg: process(clk) begin if(rising_edge(clk)) then current_state <= next_state; end if; end process; process(done, hex, current_state) begin next_state <= current_state; case current_state is when MAKE => if( hex /= "11110000" and done = '1') then if(hex = "00010010") then left_pressed <= '1'; elsif(hex = "01011001") then right_pressed <= '1'; end if; -- if F0 is read instead elsif( hex = "11110000" and done = '1') then next_state <= BREAK_RECEIVED; else next_state <= MAKE; end if; when BREAK_RECEIVED => if(hex = "00010010" and done = '1') then left_pressed <= '0'; elsif(hex = "01011001" and done = '1') then right_pressed <= '0'; end if; next_state <= MAKE; -- transition back to MAKE (reading) end case; end process; end arch;