Info (332115): Path #1: Setup slack is -0.210 (VIOLATED) Info (332115): =================================================================== Info (332115): From Node : _instancelocation_|ordertableupdate:ordertable|out_data[103]_OTERM3089 Info (332115): To Node : _instancelocation_|ordertableupdate:ordertable|out_data[191]_OTERM11918 Info (332115): Launch Clock : i_pll|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk Info (332115): Latch Clock : i_pll|pll_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk Info (332115): Info (332115): Data Arrival Path: Info (332115): Info (332115): Total (ns) Incr (ns) Type HS/LP Element Info (332115): ========== ========= == ==== ========== =================================== Info (332115): 0.000 0.000 launch edge time Info (332115): 2.149 2.149 R clock network delay Info (332115): 2.149 0.000 uTco _instancelocation_|ordertableupdate:ordertable|out_data[103]_OTERM3089 Info (332115): 2.149 0.000 FF CELL High Speed _instancelocation_|ordertable|out_data[103]_NEW_REG3088|q Info (332115): 2.959 0.810 FF IC High Speed _instancelocation_|ordertable|Selector2841~0|datad Info (332115): 3.093 0.134 FF CELL High Speed _instancelocation_|ordertable|Selector2841~0|combout Info (332115): 3.279 0.186 FF IC High Speed _instancelocation_|ordertable|Add9~161|datab Info (332115): 3.512 0.233 FF CELL High Speed _instancelocation_|ordertable|Add9~161|combout Info (332115): 4.563 1.051 FF IC High Speed _instancelocation_|ordertable|Add9~93|datab Info (332115): 5.003 0.440 FR CELL High Speed _instancelocation_|ordertable|Add9~93|cout Info (332115): 5.003 0.000 RR IC _instancelocation_|ordertable|Add9~97|cin Info (332115): 5.026 0.023 RR CELL High Speed _instancelocation_|ordertable|Add9~97|cout Info (332115): 5.026 0.000 RR IC _instancelocation_|ordertable|Add9~101|cin Info (332115): 5.026 0.000 RR CELL High Speed _instancelocation_|ordertable|Add9~101|cout Info (332115): 5.026 0.000 RR IC _instancelocation_|ordertable|Add9~105|cin Info (332115): 5.049 0.023 RR CELL High Speed _instancelocation_|ordertable|Add9~105|cout Info (332115): 5.049 0.000 RR IC _instancelocation_|ordertable|Add9~109|cin Info (332115): 5.153 0.104 RF CELL High Speed _instancelocation_|ordertable|Add9~109|sumout Info (332115): 5.912 0.759 FF IC High Speed _instancelocation_|ordertable|Add9~29|datac Info (332115): 6.233 0.321 FR CELL High Speed _instancelocation_|ordertable|Add9~29|cout Info (332115): 6.233 0.000 RR IC _instancelocation_|ordertable|Add9~33|cin Info (332115): 6.256 0.023 RR CELL High Speed _instancelocation_|ordertable|Add9~33|cout Info (332115): 6.256 0.000 RR IC _instancelocation_|ordertable|Add9~41|cin Info (332115): 6.360 0.104 RR CELL High Speed _instancelocation_|ordertable|Add9~41|sumout Info (332115): 6.697 0.337 RR IC High Speed _instancelocation_|ordertable|Add12~37|dataf Info (332115): 7.008 0.311 RR CELL High Speed _instancelocation_|ordertable|Add12~37|cout Info (332115): 7.008 0.000 RR IC _instancelocation_|ordertable|Add12~41|cin Info (332115): 7.031 0.023 RR CELL High Speed _instancelocation_|ordertable|Add12~41|cout Info (332115): 7.031 0.000 RR IC _instancelocation_|ordertable|Add12~45|cin Info (332115): 7.031 0.000 RR CELL High Speed _instancelocation_|ordertable|Add12~45|cout Info (332115): 7.031 0.000 RR IC _instancelocation_|ordertable|Add12~49|cin Info (332115): 7.054 0.023 RR CELL High Speed _instancelocation_|ordertable|Add12~49|cout Info (332115): 7.054 0.000 RR IC _instancelocation_|ordertable|Add12~53|cin Info (332115): 7.054 0.000 RR CELL High Speed _instancelocation_|ordertable|Add12~53|cout Info (332115): 7.054 0.000 RR IC _instancelocation_|ordertable|Add12~57|cin Info (332115): 7.077 0.023 RR CELL High Speed _instancelocation_|ordertable|Add12~57|cout Info (332115): 7.077 0.000 RR IC _instancelocation_|ordertable|Add12~61|cin Info (332115): 7.077 0.000 RR CELL High Speed _instancelocation_|ordertable|Add12~61|cout Info (332115): 7.077 0.000 RR IC _instancelocation_|ordertable|Add12~1|cin Info (332115): 7.106 0.029 RR CELL High Speed _instancelocation_|ordertable|Add12~1|cout Info (332115): 7.106 0.000 RR IC _instancelocation_|ordertable|Add12~5|cin Info (332115): 7.106 0.000 RR CELL High Speed _instancelocation_|ordertable|Add12~5|cout Info (332115): 7.106 0.000 RR IC _instancelocation_|ordertable|Add12~9|cin Info (332115): 7.166 0.060 RR CELL High Speed _instancelocation_|ordertable|Add12~9|cout Info (332115): 7.166 0.000 RR IC _instancelocation_|ordertable|Add12~13|cin Info (332115): 7.166 0.000 RR CELL High Speed _instancelocation_|ordertable|Add12~13|cout Info (332115): 7.166 0.000 RR IC _instancelocation_|ordertable|Add12~17|cin Info (332115): 7.189 0.023 RR CELL High Speed _instancelocation_|ordertable|Add12~17|cout Info (332115): 7.189 0.000 RR IC _instancelocation_|ordertable|Add12~21|cin Info (332115): 7.189 0.000 RR CELL High Speed _instancelocation_|ordertable|Add12~21|cout Info (332115): 7.189 0.000 RR IC _instancelocation_|ordertable|Add12~25|cin Info (332115): 7.212 0.023 RR CELL High Speed _instancelocation_|ordertable|Add12~25|cout Info (332115): 7.212 0.000 RR IC _instancelocation_|ordertable|Add12~29|cin Info (332115): 7.316 0.104 RR CELL High Speed _instancelocation_|ordertable|Add12~29|sumout Info (332115): 7.316 0.000 RR IC _instancelocation_|ordertable|out_data[191]_NEW_REG11917|d Info (332115): 7.443 0.127 RR CELL High Speed _instancelocation_|ordertableupdate:ordertable|out_data[191]_OTERM11918 Info (332115): Info (332115): Data Required Path: Info (332115): Info (332115): Total (ns) Incr (ns) Type HS/LP Element Info (332115): ========== ========= == ==== ========== =================================== Info (332115): 5.000 5.000 latch edge time Info (332115): 6.554 1.554 R clock network delay Info (332115): 7.138 0.584 clock pessimism removed Info (332115): 7.058 -0.080 clock uncertainty Info (332115): 7.233 0.175 uTsu _instancelocation_|ordertableupdate:ordertable|out_data[191]_OTERM11918 Info (332115): Info (332115): Data Arrival Time : 7.443 Info (332115): Data Required Time : 7.233 Info (332115): Slack : -0.210 (VIOLATED) Info (332115): ===================================================================