Synthesis report Fri Jan 19 10:36:24 2018 Quartus Prime Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition --------------------- ; Table of Contents ; --------------------- 1. Synthesis Summary 2. Synthesis Settings 3. Parallel Compilation 4. Synthesis Source Files Read 5. Synthesis Partition Summary 6. Partition "root_partition" Resource Utilization by Entity 7. General Register Statistics for Partition "root_partition" 8. Inverted Register Statistics 9. Multiplexer Restructuring Statistics (Restructuring Performed) 10. Post-Synthesis Netlist Statistics for Partition "root_partition" 11. Synthesis Resource Usage Summary for Partition "root_partition" 12. Synthesis Messages +---------------------------------------------------------------+ ; Synthesis Summary ; +-----------------------+---------------------------------------+ ; Synthesis Status ; Successful - Fri Jan 19 10:36:24 2018 ; ; Revision Name ; correlator ; ; Top-level Entity Name ; correlator ; ; Family ; Arria 10 ; +-----------------------+---------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------+ ; Synthesis Settings ; +---------------------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +---------------------------------------------------------------------------------+--------------------+--------------------+ ; Device ; 10AS066N3F40E2SG ; ; ; Top-level entity name ; correlator ; correlator ; ; Family name ; Arria 10 ; Cyclone 10 GX ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Optimization Mode ; Balanced ; Balanced ; ; Allow Register Merging ; On ; On ; ; Allow Register Duplication ; On ; On ; ; Allow Register Retiming ; On ; On ; ; Restructure Multiplexers ; Auto ; Auto ; ; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Infer RAMs from Raw Logic ; On ; On ; ; DSP Block Balancing ; Auto ; Auto ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto DSP Block Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Strict RAM Replacement ; Off ; Off ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Timing-Driven Synthesis ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 3 ; 3 ; ; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Protected Registers Reported in Synthesis Report ; 100 ; 100 ; ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Auto Gated Clock Conversion ; Off ; Off ; ; Block Design Naming ; Auto ; Auto ; ; SDC constraint protection ; Off ; Off ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Resource Aware Inference For Block RAM ; On ; On ; ; Automatic Parallel Synthesis ; On ; On ; ; Partial Reconfiguration Bitstream ID ; Off ; Off ; ; Disable DSP Negate Inferencing ; Off ; Off ; ; Report Parameter Settings ; On ; On ; ; Report Source Assignments ; On ; On ; ; Size of the Latch Report ; 100 ; 100 ; ; Enable State Machines Inference ; On ; On ; ; Enable formal verification support during compilation ; Off ; Off ; +---------------------------------------------------------------------------------+--------------------+--------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 8 ; ; Maximum allowed ; 8 ; ; ; ; ; Average used ; 1.02 ; ; Maximum used ; 8 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processors 2-8 ; 0.3% ; +----------------------------+-------------+ +------------------------------------------------------------------------------------------------------------------------------------+ ; Synthesis Source Files Read ; +----------------------------------+-----------------+------------------------------+--------------------------------------+---------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; +----------------------------------+-----------------+------------------------------+--------------------------------------+---------+ ; correlator.v ; yes ; Auto-Found Verilog HDL File ; /home/nyholku/focusscan/correlator.v ; work ; +----------------------------------+-----------------+------------------------------+--------------------------------------+---------+ +----------------------------------------------------------------------------------+ ; Synthesis Partition Summary ; +----------------+----------------+--------------+-------+-------------------------+ ; Partition Name ; Hierarchy Path ; Preservation ; Empty ; Partition Database File ; +----------------+----------------+--------------+-------+-------------------------+ ; root_partition ; | ; ; ; ; +----------------+----------------+--------------+-------+-------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Partition "root_partition" Resource Utilization by Entity ; +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+--------+---------------------+-------------+--------------+ ; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; IOPLLs ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+--------+---------------------+-------------+--------------+ ; | ; 19 (19) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; | ; correlator ; work ; +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+--------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +------------------------------------------------------------+ ; General Register Statistics for Partition "root_partition" ; +----------------------------------------------+-------------+ ; Statistic ; Value ; +----------------------------------------------+-------------+ ; Total registers ; 9 ; ; Number of registers using Synchronous Clear ; 0 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 7 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------------+ +--------------------------------------------------+ ; Inverted Register Statistics ; +----------------------------------------+---------+ ; Inverted Register ; Fan out ; +----------------------------------------+---------+ ; counter[5] ; 2 ; ; counter[6] ; 2 ; ; counter[7] ; 11 ; ; counter[0] ; 2 ; ; counter[1] ; 2 ; ; counter[2] ; 2 ; ; counter[3] ; 2 ; ; counter[4] ; 2 ; ; Total number of inverted registers = 8 ; ; +----------------------------------------+---------+ +------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Restructuring Statistics (Restructuring Performed) ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; counter[0] ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +------------------------------------------------------------------+ ; Post-Synthesis Netlist Statistics for Partition "root_partition" ; +-----------------------+------------------------------------------+ ; Type ; Count ; +-----------------------+------------------------------------------+ ; boundary_port ; 50 ; ; twentynm_ff ; 9 ; ; ENA ; 7 ; ; plain ; 2 ; ; twentynm_lcell_comb ; 19 ; ; arith ; 8 ; ; 1 data inputs ; 8 ; ; normal ; 11 ; ; 4 data inputs ; 1 ; ; 5 data inputs ; 9 ; ; 6 data inputs ; 1 ; ; ; ; ; Max LUT depth ; 2.70 ; ; Average LUT depth ; 2.19 ; +-----------------------+------------------------------------------+ +-----------------------------------------------------------------+ ; Synthesis Resource Usage Summary for Partition "root_partition" ; +---------------------------------------------+-------------------+ ; Resource ; Usage ; +---------------------------------------------+-------------------+ ; Estimate of Logic utilization (ALMs needed) ; 10 ; ; ; ; ; Combinational ALUT usage for logic ; 19 ; ; -- 7 input functions ; 0 ; ; -- 6 input functions ; 1 ; ; -- 5 input functions ; 9 ; ; -- 4 input functions ; 1 ; ; -- <=3 input functions ; 8 ; ; ; ; ; Dedicated logic registers ; 9 ; ; ; ; ; I/O pins ; 50 ; ; ; ; ; Total DSP Blocks ; 0 ; ; -- Total Fixed Point DSP Blocks ; 0 ; ; -- Total Floating Point DSP Blocks ; 0 ; ; ; ; ; Maximum fan-out node ; oe~reg0 ; ; Maximum fan-out ; 11 ; ; Total fan-out ; 96 ; ; Average fan-out ; 1.23 ; +---------------------------------------------+-------------------+ +--------------------+ ; Synthesis Messages ; +--------------------+ Info: ******************************************************************* Info: Running Quartus Prime Synthesis Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition Info: Processing started: Fri Jan 19 10:36:20 2018 Info: Command: quartus_syn --read_settings_files=off --write_settings_files=off correlator -c correlator Info: qis_default_flow_script.tcl version: #1 Info: Initializing Synthesis... Info: Project = "correlator" Info: Revision = "correlator" Info: Analyzing source files Info: Elaborating from top-level entity "correlator" Info: Found 1 design entities Info: There are 1 partitions after elaboration. Info: Creating instance-specific data models and dissolving soft partitions Info (18299): Expanding entity and wildcard assignments. Info (18300): Expanded entity and wildcard assignments. Elapsed time: 00:00:00 Info: found pre-synthesis snapshots for 1 partition(s) Info: Synthesizing partition "root_partition" Info (286030): Timing-Driven Synthesis is running Info (21057): Implemented 69 device resources after synthesis - the final resource count might be different Info (21058): Implemented 49 input pins Info (21059): Implemented 1 output pins Info (21061): Implemented 19 logic cells Info: Successfully synthesized partition Info: Saving post-synthesis snapshots for 1 partition(s) Info: Quartus Prime Synthesis was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1039 megabytes Info: Processing ended: Fri Jan 19 10:36:24 2018 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04