******************************************************* i++ debug log file This file contains diagnostic information. Any errors or unexpected behavior encountered when running i++ should be reported as bugs. Thank you. ******************************************************* Compiler Command: i++ counter.cpp -march=Arria 10 --quartus-compile -o counterDUT1 2018.07.23.08:59:12 Info: Doing: qsys-script --script=count.tcl --quartus-project=none 2018.07.23.08:59:16 Info: create_system count 2018.07.23.08:59:16 Info: set_project_property HIDE_FROM_IP_CATALOG false 2018.07.23.08:59:16 Info: set_project_property DEVICE_FAMILY Arria 10 2018.07.23.08:59:16 Info: set_project_property DEVICE 10AX115U1F45I1SG 2018.07.23.08:59:16 Info: add_instance count_internal_inst count_internal 2018.07.23.08:59:17 Info: set_instance_property count_internal_inst AUTO_EXPORT true 2018.07.23.08:59:17 Info: save_system count.ip 2018.07.23.08:59:34 Info: count: All Generic Component instances match their respective ip files. 2018.07.23.08:59:34 Info: Saving generation log to /home/tempuser11/counter/counterDUT1.prj/components/count/count/count_generation.rpt 2018.07.23.08:59:34 Info: Generated by version: 17.1 build 240 2018.07.23.08:59:34 Info: Starting: Create HDL design files for synthesis 2018.07.23.08:59:34 Info: qsys-generate /home/tempuser11/counter/counterDUT1.prj/components/count/count.ip --synthesis=VERILOG --output-directory=/home/tempuser11/counter/counterDUT1.prj/components/count/count --family="Arria 10" --part=10AX115U1F45I1SG 2018.07.23.08:59:35 Info: count: "Transforming system: count" 2018.07.23.08:59:35 Info: count: Running transform generation_view_transform 2018.07.23.08:59:35 Info: count: Running transform generation_view_transform took 0.001s 2018.07.23.08:59:35 Info: count_internal_inst: Running transform generation_view_transform 2018.07.23.08:59:35 Info: count_internal_inst: Running transform generation_view_transform took 0.000s 2018.07.23.08:59:35 Info: count: Running transform interconnect_transform_chooser 2018.07.23.08:59:35 Info: count: Running transform interconnect_transform_chooser took 0.083s 2018.07.23.08:59:35 Info: count: "Naming system components in system: count" 2018.07.23.08:59:35 Info: count: "Processing generation queue" 2018.07.23.08:59:35 Info: count: "Generating: count" 2018.07.23.08:59:35 Info: count: "Generating: count_internal" 2018.07.23.08:59:35 Info: count: Done "count" with 2 modules, 60 files 2018.07.23.08:59:35 Info: qsys-generate succeeded. 2018.07.23.08:59:35 Info: Finished: Create HDL design files for synthesis 2018.07.23.08:59:35 Info: Starting: IP-XACT 2018.07.23.08:59:35 Info: qsys-generate /home/tempuser11/counter/counterDUT1.prj/components/count/count.ip --synthesis=VERILOG --ipxact --output-directory=/home/tempuser11/counter/counterDUT1.prj/components/count/count --family="Arria 10" --part=10AX115U1F45I1SG 2018.07.23.08:59:35 Info: Finished: IP-XACT 2018.07.23.08:59:46 Info: Doing: qsys-script --quartus-project=none --search-path=/D/intelFPGA_pro/17.1/hls/ip/,.,../components/**/*,$ --script=/D/intelFPGA_pro/17.1/hls/share/lib/tcl/hls_sim_generate_qsys.tcl --cmd=set quartus_pro 1; set num_reset_cycles 4; set sim_qsys tb; set component_list count; set component_call_count_filename . 2018.07.23.08:59:51 Info: create_system tb Generating qsys simulation system: tb 2018.07.23.08:59:51 Info: add_component clock_reset_inst clock_reset.ip hls_sim_clock_reset clock_reset 2018.07.23.08:59:54 Info: clock_reset_inst: Generic Component validation successful. 2018.07.23.08:59:54 Info: load_component clock_reset_inst 2018.07.23.08:59:54 Info: set_component_parameter_value RESET_CYCLE_HOLD 4 2018.07.23.08:59:54 Info: save_component 2018.07.23.08:59:54 Info: add_instance count_inst altera_generic_component 2018.07.23.08:59:54 Info: load_instantiation count_inst 2018.07.23.08:59:54 Info: set_instantiation_property IP_FILE ../components/count/count.ip 2018.07.23.08:59:54 Info: set_instantiation_property HDL_ENTITY_NAME count 2018.07.23.08:59:54 Info: set_instantiation_property HDL_COMPILATION_LIBRARY count 2018.07.23.08:59:54 Info: save_instantiation 2018.07.23.08:59:54 Info: reload_component_footprint count_inst 2018.07.23.08:59:54 Warning: tb: count.ip declares module assignment hls.cosim.name which is missing in module count_inst 2018.07.23.08:59:54 Info: count_inst: Generic Component validation successful. 2018.07.23.08:59:54 Info: load_component count_inst 2018.07.23.08:59:54 Info: get_component_assignment hls.cosim.name 2018.07.23.08:59:54 Info: add_component main_dpi_controller_inst main_dpi_controller.ip hls_sim_main_dpi_controller main_dpi_controller 2018.07.23.08:59:54 Info: main_dpi_controller_inst: Generic Component validation successful. 2018.07.23.08:59:54 Info: load_component main_dpi_controller_inst 2018.07.23.08:59:54 Info: set_component_parameter_value NUM_COMPONENTS 1 2018.07.23.08:59:54 Info: set_component_parameter_value COMPONENT_NAMES_STR count 2018.07.23.08:59:54 Info: set_component_parameter_value SIM_COMPONENT_CALL_COUNT_LOG_FILE . 2018.07.23.08:59:54 Info: save_component 2018.07.23.08:59:54 Info: add_connection clock_reset_inst.clock main_dpi_controller_inst.clock 2018.07.23.08:59:54 Info: add_connection clock_reset_inst.clock2x main_dpi_controller_inst.clock2x 2018.07.23.08:59:54 Info: add_connection clock_reset_inst.reset main_dpi_controller_inst.reset 2018.07.23.08:59:54 Info: add_connection main_dpi_controller_inst.reset_ctrl clock_reset_inst.reset_ctrl 2018.07.23.08:59:54 Info: add_connection clock_reset_inst.clock count_inst.clock 2018.07.23.08:59:54 Info: add_connection clock_reset_inst.reset count_inst.reset 2018.07.23.08:59:54 Info: get_instance_interfaces count_inst 2018.07.23.08:59:54 Info: get_instance_interface_property count_inst call DESCRIPTION 2018.07.23.08:59:54 Info: get_instance_interface_property count_inst call CLASS_NAME 2018.07.23.08:59:54 Info: get_instance_interface_ports count_inst call 2018.07.23.08:59:54 Info: get_instance_interface_property count_inst clock DESCRIPTION 2018.07.23.08:59:54 Info: get_instance_interface_property count_inst clock CLASS_NAME 2018.07.23.08:59:54 Info: get_instance_interface_ports count_inst clock 2018.07.23.08:59:54 Info: get_instance_interface_property count_inst reset DESCRIPTION 2018.07.23.08:59:54 Info: get_instance_interface_property count_inst reset CLASS_NAME 2018.07.23.08:59:54 Info: get_instance_interface_ports count_inst reset 2018.07.23.08:59:54 Info: get_instance_interface_property count_inst return DESCRIPTION 2018.07.23.08:59:54 Info: get_instance_interface_property count_inst return CLASS_NAME 2018.07.23.08:59:54 Info: get_instance_interface_ports count_inst return 2018.07.23.08:59:54 Info: get_instance_interface_property count_inst returndata DESCRIPTION 2018.07.23.08:59:54 Info: get_instance_interface_property count_inst returndata CLASS_NAME 2018.07.23.08:59:54 Info: get_instance_interface_ports count_inst returndata 2018.07.23.08:59:54 Info: load_component count_inst 2018.07.23.08:59:54 Info: get_component_assignment hls.cosim.name 2018.07.23.08:59:54 Info: add_component component_dpi_controller_count_inst dpic_count.ip hls_sim_component_dpi_controller dpic_count 2018.07.23.08:59:54 Info: component_dpi_controller_count_inst: Generic Component validation successful. 2018.07.23.08:59:54 Info: add_connection clock_reset_inst.clock component_dpi_controller_count_inst.clock 2018.07.23.08:59:54 Info: add_connection clock_reset_inst.clock2x component_dpi_controller_count_inst.clock2x 2018.07.23.08:59:54 Info: add_connection clock_reset_inst.reset component_dpi_controller_count_inst.reset 2018.07.23.08:59:54 Info: add_connection component_dpi_controller_count_inst.component_call count_inst.call 2018.07.23.08:59:54 Info: add_connection count_inst.return component_dpi_controller_count_inst.component_return 2018.07.23.08:59:54 Info: get_instance_interfaces count_inst 2018.07.23.08:59:54 Info: get_instance_interface_port_property count_inst returndata returndata WIDTH 2018.07.23.08:59:54 Info: load_component component_dpi_controller_count_inst 2018.07.23.08:59:54 Info: set_component_parameter_value RETURN_DATAWIDTH 32 2018.07.23.08:59:54 Info: save_component 2018.07.23.08:59:54 Info: add_connection count_inst.returndata component_dpi_controller_count_inst.returndata 2018.07.23.08:59:54 Info: load_component component_dpi_controller_count_inst 2018.07.23.08:59:54 Info: set_component_parameter_value COMPONENT_NAME count 2018.07.23.08:59:54 Info: save_component 2018.07.23.08:59:55 Info: add_component count_component_dpi_controller_bind_conduit_fanout_inst count_cfan.ip avalon_conduit_fanout count_cfan 2018.07.23.08:59:55 Info: count_component_dpi_controller_bind_conduit_fanout_inst: Generic Component validation successful. 2018.07.23.08:59:55 Info: load_component count_component_dpi_controller_bind_conduit_fanout_inst 2018.07.23.08:59:55 Info: set_component_parameter_value numFanOut 0 2018.07.23.08:59:55 Info: save_component 2018.07.23.08:59:55 Info: add_component count_component_dpi_controller_enable_conduit_fanout_inst count_en_cfan.ip avalon_conduit_fanout count_en_cfan 2018.07.23.08:59:55 Info: count_component_dpi_controller_enable_conduit_fanout_inst: Generic Component validation successful. 2018.07.23.08:59:55 Info: load_component count_component_dpi_controller_enable_conduit_fanout_inst 2018.07.23.08:59:55 Info: set_component_parameter_value numFanOut 0 2018.07.23.08:59:55 Info: save_component 2018.07.23.08:59:55 Info: add_connection component_dpi_controller_count_inst.dpi_control_bind count_component_dpi_controller_bind_conduit_fanout_inst.in_conduit 2018.07.23.08:59:55 Info: add_connection component_dpi_controller_count_inst.dpi_control_enable count_component_dpi_controller_enable_conduit_fanout_inst.in_conduit 2018.07.23.08:59:55 Info: get_instance_interfaces count_inst 2018.07.23.08:59:55 Info: get_instance_interface_ports count_inst call 2018.07.23.08:59:55 Info: get_instance_interface_ports count_inst clock 2018.07.23.08:59:55 Info: get_instance_interface_ports count_inst reset 2018.07.23.08:59:55 Info: get_instance_interface_ports count_inst return 2018.07.23.08:59:55 Info: get_instance_interface_ports count_inst returndata 2018.07.23.08:59:55 Info: add_component split_component_start_inst sp_cstart.ip avalon_split_multibit_conduit sp_cstart 2018.07.23.08:59:55 Info: split_component_start_inst: Generic Component validation successful. 2018.07.23.08:59:55 Info: load_component split_component_start_inst 2018.07.23.08:59:55 Info: set_component_parameter_value multibit_width 1 2018.07.23.08:59:55 Info: save_component 2018.07.23.08:59:55 Info: add_connection main_dpi_controller_inst.component_enabled split_component_start_inst.in_conduit 2018.07.23.08:59:55 Info: add_connection split_component_start_inst.out_conduit_0 component_dpi_controller_count_inst.component_enabled 2018.07.23.08:59:55 Info: add_component concatenate_component_done_inst cat_done.ip avalon_concatenate_singlebit_conduits cat_done 2018.07.23.08:59:55 Info: concatenate_component_done_inst: Generic Component validation successful. 2018.07.23.08:59:55 Info: load_component concatenate_component_done_inst 2018.07.23.08:59:55 Info: set_component_parameter_value multibit_width 1 2018.07.23.08:59:55 Info: save_component 2018.07.23.08:59:55 Info: add_connection concatenate_component_done_inst.out_conduit main_dpi_controller_inst.component_done 2018.07.23.08:59:55 Info: add_component concatenate_component_wait_for_stream_writes_inst cat_cwfsw.ip avalon_concatenate_singlebit_conduits cat_cwfsw 2018.07.23.08:59:55 Info: concatenate_component_wait_for_stream_writes_inst: Generic Component validation successful. 2018.07.23.08:59:55 Info: load_component concatenate_component_wait_for_stream_writes_inst 2018.07.23.08:59:55 Info: set_component_parameter_value multibit_width 1 2018.07.23.08:59:55 Info: save_component 2018.07.23.08:59:55 Info: add_connection concatenate_component_wait_for_stream_writes_inst.out_conduit main_dpi_controller_inst.component_wait_for_stream_writes 2018.07.23.08:59:55 Info: add_connection component_dpi_controller_count_inst.component_done concatenate_component_done_inst.in_conduit_0 2018.07.23.08:59:55 Info: add_connection component_dpi_controller_count_inst.component_wait_for_stream_writes concatenate_component_wait_for_stream_writes_inst.in_conduit_0 2018.07.23.08:59:55 Info: save_system tb.qsys 2018.07.23.08:59:56 Info: Info: All modules have been converted to Generic Components. 2018.07.23.09:00:06 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision. 2018.07.23.09:00:15 Warning: tb: count.ip declares module assignment hls.cosim.name which is missing in module count_inst 2018.07.23.09:00:15 Info: tb: Generic Component validation completed with warnings. 2018.07.23.09:00:15 Info: cat_done: All Generic Component instances match their respective ip files. 2018.07.23.09:00:15 Info: Saving generation log to /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/cat_done/cat_done_generation.rpt 2018.07.23.09:00:15 Info: Generated by version: 17.1 build 240 2018.07.23.09:00:15 Info: Starting: Create simulation model 2018.07.23.09:00:15 Info: qsys-generate /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/cat_done.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/cat_done --family="Arria 10" --part=10AX115U1F45I1SG 2018.07.23.09:00:15 Info: cat_done: "Transforming system: cat_done" 2018.07.23.09:00:15 Info: cat_done: Running transform generation_view_transform 2018.07.23.09:00:15 Info: cat_done: Running transform generation_view_transform took 0.001s 2018.07.23.09:00:15 Info: cat_done: Running transform generation_view_transform 2018.07.23.09:00:15 Info: cat_done: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:15 Info: cat_done: Running transform interconnect_transform_chooser 2018.07.23.09:00:16 Info: cat_done: Running transform interconnect_transform_chooser took 0.098s 2018.07.23.09:00:16 Info: cat_done: "Naming system components in system: cat_done" 2018.07.23.09:00:16 Info: cat_done: "Processing generation queue" 2018.07.23.09:00:16 Info: cat_done: "Generating: cat_done" 2018.07.23.09:00:16 Info: cat_done: "Generating: cat_done_avalon_concatenate_singlebit_conduits_10_bjzeuhq" 2018.07.23.09:00:16 Info: cat_done: Done "cat_done" with 2 modules, 2 files 2018.07.23.09:00:16 Info: qsys-generate succeeded. 2018.07.23.09:00:16 Info: Finished: Create simulation model 2018.07.23.09:00:16 Info: 2018.07.23.09:00:16 Info: count_cfan: All Generic Component instances match their respective ip files. 2018.07.23.09:00:16 Info: Saving generation log to /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/count_cfan/count_cfan_generation.rpt 2018.07.23.09:00:16 Info: Generated by version: 17.1 build 240 2018.07.23.09:00:16 Info: Starting: Create simulation model 2018.07.23.09:00:16 Info: qsys-generate /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/count_cfan.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/count_cfan --family="Arria 10" --part=10AX115U1F45I1SG 2018.07.23.09:00:16 Info: count_cfan: "Transforming system: count_cfan" 2018.07.23.09:00:16 Info: count_cfan: Running transform generation_view_transform 2018.07.23.09:00:16 Info: count_cfan: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:16 Info: count_cfan: Running transform generation_view_transform 2018.07.23.09:00:16 Info: count_cfan: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:16 Info: count_cfan: Running transform interconnect_transform_chooser 2018.07.23.09:00:16 Info: count_cfan: Running transform interconnect_transform_chooser took 0.008s 2018.07.23.09:00:16 Info: count_cfan: "Naming system components in system: count_cfan" 2018.07.23.09:00:16 Info: count_cfan: "Processing generation queue" 2018.07.23.09:00:16 Info: count_cfan: "Generating: count_cfan" 2018.07.23.09:00:16 Info: count_cfan: "Generating: count_cfan_avalon_conduit_fanout_10_wcpjniy" 2018.07.23.09:00:16 Info: count_cfan: Done "count_cfan" with 2 modules, 2 files 2018.07.23.09:00:16 Info: qsys-generate succeeded. 2018.07.23.09:00:16 Info: Finished: Create simulation model 2018.07.23.09:00:16 Info: 2018.07.23.09:00:16 Info: dpic_count: All Generic Component instances match their respective ip files. 2018.07.23.09:00:16 Info: Saving generation log to /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/dpic_count/dpic_count_generation.rpt 2018.07.23.09:00:16 Info: Generated by version: 17.1 build 240 2018.07.23.09:00:16 Info: Starting: Create simulation model 2018.07.23.09:00:16 Info: qsys-generate /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/dpic_count.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/dpic_count --family="Arria 10" --part=10AX115U1F45I1SG 2018.07.23.09:00:16 Warning: dpic_count.dpic_count.dpi_control_slaves_ready: Interface has no signals 2018.07.23.09:00:16 Warning: dpic_count.dpic_count.dpi_control_slaves_done: Interface has no signals 2018.07.23.09:00:16 Warning: dpic_count.dpic_count.dpi_control_stream_writes_active: Interface has no signals 2018.07.23.09:00:16 Info: dpic_count: "Transforming system: dpic_count" 2018.07.23.09:00:16 Info: dpic_count: Running transform generation_view_transform 2018.07.23.09:00:16 Info: dpic_count: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:16 Info: dpic_count: Running transform generation_view_transform 2018.07.23.09:00:16 Info: dpic_count: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:16 Info: dpic_count: Running transform interconnect_transform_chooser 2018.07.23.09:00:16 Info: dpic_count: Running transform interconnect_transform_chooser took 0.010s 2018.07.23.09:00:16 Info: dpic_count: "Naming system components in system: dpic_count" 2018.07.23.09:00:16 Info: dpic_count: "Processing generation queue" 2018.07.23.09:00:16 Info: dpic_count: "Generating: dpic_count" 2018.07.23.09:00:16 Info: dpic_count: "Generating: hls_sim_component_dpi_controller" 2018.07.23.09:00:16 Info: dpic_count: Done "dpic_count" with 2 modules, 4 files 2018.07.23.09:00:16 Info: qsys-generate succeeded. 2018.07.23.09:00:16 Info: Finished: Create simulation model 2018.07.23.09:00:16 Info: 2018.07.23.09:00:16 Info: count_en_cfan: All Generic Component instances match their respective ip files. 2018.07.23.09:00:16 Info: Saving generation log to /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/count_en_cfan/count_en_cfan_generation.rpt 2018.07.23.09:00:16 Info: Generated by version: 17.1 build 240 2018.07.23.09:00:16 Info: Starting: Create simulation model 2018.07.23.09:00:16 Info: qsys-generate /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/count_en_cfan.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/count_en_cfan --family="Arria 10" --part=10AX115U1F45I1SG 2018.07.23.09:00:16 Info: count_en_cfan: "Transforming system: count_en_cfan" 2018.07.23.09:00:16 Info: count_en_cfan: Running transform generation_view_transform 2018.07.23.09:00:16 Info: count_en_cfan: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:16 Info: count_en_cfan: Running transform generation_view_transform 2018.07.23.09:00:16 Info: count_en_cfan: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:16 Info: count_en_cfan: Running transform interconnect_transform_chooser 2018.07.23.09:00:16 Info: count_en_cfan: Running transform interconnect_transform_chooser took 0.008s 2018.07.23.09:00:16 Info: count_en_cfan: "Naming system components in system: count_en_cfan" 2018.07.23.09:00:16 Info: count_en_cfan: "Processing generation queue" 2018.07.23.09:00:16 Info: count_en_cfan: "Generating: count_en_cfan" 2018.07.23.09:00:16 Info: count_en_cfan: "Generating: count_en_cfan_avalon_conduit_fanout_10_wcpjniy" 2018.07.23.09:00:16 Info: count_en_cfan: Done "count_en_cfan" with 2 modules, 2 files 2018.07.23.09:00:16 Info: qsys-generate succeeded. 2018.07.23.09:00:16 Info: Finished: Create simulation model 2018.07.23.09:00:16 Info: 2018.07.23.09:00:16 Info: clock_reset: All Generic Component instances match their respective ip files. 2018.07.23.09:00:16 Info: Saving generation log to /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/clock_reset/clock_reset_generation.rpt 2018.07.23.09:00:16 Info: Generated by version: 17.1 build 240 2018.07.23.09:00:16 Info: Starting: Create simulation model 2018.07.23.09:00:16 Info: qsys-generate /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/clock_reset.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/clock_reset --family="Arria 10" --part=10AX115U1F45I1SG 2018.07.23.09:00:16 Info: clock_reset: "Transforming system: clock_reset" 2018.07.23.09:00:16 Info: clock_reset: Running transform generation_view_transform 2018.07.23.09:00:16 Info: clock_reset: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:16 Info: clock_reset: Running transform generation_view_transform 2018.07.23.09:00:16 Info: clock_reset: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:16 Info: clock_reset: Running transform interconnect_transform_chooser 2018.07.23.09:00:16 Info: clock_reset: Running transform interconnect_transform_chooser took 0.009s 2018.07.23.09:00:16 Info: clock_reset: "Naming system components in system: clock_reset" 2018.07.23.09:00:16 Info: clock_reset: "Processing generation queue" 2018.07.23.09:00:16 Info: clock_reset: "Generating: clock_reset" 2018.07.23.09:00:16 Info: clock_reset: "Generating: hls_sim_clock_reset" 2018.07.23.09:00:16 Info: clock_reset: Done "clock_reset" with 2 modules, 2 files 2018.07.23.09:00:16 Info: qsys-generate succeeded. 2018.07.23.09:00:16 Info: Finished: Create simulation model 2018.07.23.09:00:16 Info: 2018.07.23.09:00:16 Info: cat_cwfsw: All Generic Component instances match their respective ip files. 2018.07.23.09:00:16 Info: Saving generation log to /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/cat_cwfsw/cat_cwfsw_generation.rpt 2018.07.23.09:00:16 Info: Generated by version: 17.1 build 240 2018.07.23.09:00:16 Info: Starting: Create simulation model 2018.07.23.09:00:16 Info: qsys-generate /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/cat_cwfsw.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/cat_cwfsw --family="Arria 10" --part=10AX115U1F45I1SG 2018.07.23.09:00:17 Info: cat_cwfsw: "Transforming system: cat_cwfsw" 2018.07.23.09:00:17 Info: cat_cwfsw: Running transform generation_view_transform 2018.07.23.09:00:17 Info: cat_cwfsw: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:17 Info: cat_cwfsw: Running transform generation_view_transform 2018.07.23.09:00:17 Info: cat_cwfsw: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:17 Info: cat_cwfsw: Running transform interconnect_transform_chooser 2018.07.23.09:00:17 Info: cat_cwfsw: Running transform interconnect_transform_chooser took 0.008s 2018.07.23.09:00:17 Info: cat_cwfsw: "Naming system components in system: cat_cwfsw" 2018.07.23.09:00:17 Info: cat_cwfsw: "Processing generation queue" 2018.07.23.09:00:17 Info: cat_cwfsw: "Generating: cat_cwfsw" 2018.07.23.09:00:17 Info: cat_cwfsw: "Generating: cat_cwfsw_avalon_concatenate_singlebit_conduits_10_bjzeuhq" 2018.07.23.09:00:17 Info: cat_cwfsw: Done "cat_cwfsw" with 2 modules, 2 files 2018.07.23.09:00:17 Info: qsys-generate succeeded. 2018.07.23.09:00:17 Info: Finished: Create simulation model 2018.07.23.09:00:17 Info: 2018.07.23.09:00:17 Info: sp_cstart: All Generic Component instances match their respective ip files. 2018.07.23.09:00:17 Info: Saving generation log to /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/sp_cstart/sp_cstart_generation.rpt 2018.07.23.09:00:17 Info: Generated by version: 17.1 build 240 2018.07.23.09:00:17 Info: Starting: Create simulation model 2018.07.23.09:00:17 Info: qsys-generate /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/sp_cstart.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/sp_cstart --family="Arria 10" --part=10AX115U1F45I1SG 2018.07.23.09:00:17 Info: sp_cstart: "Transforming system: sp_cstart" 2018.07.23.09:00:17 Info: sp_cstart: Running transform generation_view_transform 2018.07.23.09:00:17 Info: sp_cstart: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:17 Info: sp_cstart: Running transform generation_view_transform 2018.07.23.09:00:17 Info: sp_cstart: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:17 Info: sp_cstart: Running transform interconnect_transform_chooser 2018.07.23.09:00:17 Info: sp_cstart: Running transform interconnect_transform_chooser took 0.008s 2018.07.23.09:00:17 Info: sp_cstart: "Naming system components in system: sp_cstart" 2018.07.23.09:00:17 Info: sp_cstart: "Processing generation queue" 2018.07.23.09:00:17 Info: sp_cstart: "Generating: sp_cstart" 2018.07.23.09:00:17 Info: sp_cstart: "Generating: sp_cstart_avalon_split_multibit_conduit_10_dlmo3na" 2018.07.23.09:00:17 Info: sp_cstart: Done "sp_cstart" with 2 modules, 2 files 2018.07.23.09:00:17 Info: qsys-generate succeeded. 2018.07.23.09:00:17 Info: Finished: Create simulation model 2018.07.23.09:00:17 Info: 2018.07.23.09:00:17 Info: main_dpi_controller: All Generic Component instances match their respective ip files. 2018.07.23.09:00:17 Info: Saving generation log to /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/main_dpi_controller/main_dpi_controller_generation.rpt 2018.07.23.09:00:17 Info: Generated by version: 17.1 build 240 2018.07.23.09:00:17 Info: Starting: Create simulation model 2018.07.23.09:00:17 Info: qsys-generate /home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/main_dpi_controller.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/main_dpi_controller --family="Arria 10" --part=10AX115U1F45I1SG 2018.07.23.09:00:17 Info: main_dpi_controller: "Transforming system: main_dpi_controller" 2018.07.23.09:00:17 Info: main_dpi_controller: Running transform generation_view_transform 2018.07.23.09:00:17 Info: main_dpi_controller: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:17 Info: main_dpi_controller: Running transform generation_view_transform 2018.07.23.09:00:17 Info: main_dpi_controller: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:17 Info: main_dpi_controller: Running transform interconnect_transform_chooser 2018.07.23.09:00:17 Info: main_dpi_controller: Running transform interconnect_transform_chooser took 0.010s 2018.07.23.09:00:17 Info: main_dpi_controller: "Naming system components in system: main_dpi_controller" 2018.07.23.09:00:17 Info: main_dpi_controller: "Processing generation queue" 2018.07.23.09:00:17 Info: main_dpi_controller: "Generating: main_dpi_controller" 2018.07.23.09:00:17 Info: main_dpi_controller: "Generating: hls_sim_main_dpi_controller" 2018.07.23.09:00:17 Info: main_dpi_controller: Done "main_dpi_controller" with 2 modules, 2 files 2018.07.23.09:00:17 Info: qsys-generate succeeded. 2018.07.23.09:00:17 Info: Finished: Create simulation model 2018.07.23.09:00:17 Info: 2018.07.23.09:00:17 Info: count: All Generic Component instances match their respective ip files. 2018.07.23.09:00:17 Info: Saving generation log to /home/tempuser11/counter/counterDUT1.prj/components/count/count/count_generation.rpt 2018.07.23.09:00:17 Info: Generated by version: 17.1 build 240 2018.07.23.09:00:17 Info: Starting: Create simulation model 2018.07.23.09:00:17 Info: qsys-generate /home/tempuser11/counter/counterDUT1.prj/components/count/count.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/tempuser11/counter/counterDUT1.prj/components/count/count --family="Arria 10" --part=10AX115U1F45I1SG 2018.07.23.09:00:17 Info: count: "Transforming system: count" 2018.07.23.09:00:17 Info: count: Running transform generation_view_transform 2018.07.23.09:00:17 Info: count: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:17 Info: count_internal_inst: Running transform generation_view_transform 2018.07.23.09:00:17 Info: count_internal_inst: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:17 Info: count: Running transform interconnect_transform_chooser 2018.07.23.09:00:17 Info: count: Running transform interconnect_transform_chooser took 0.009s 2018.07.23.09:00:17 Info: count: "Naming system components in system: count" 2018.07.23.09:00:17 Info: count: "Processing generation queue" 2018.07.23.09:00:17 Info: count: "Generating: count" 2018.07.23.09:00:17 Info: count: "Generating: count_internal" 2018.07.23.09:00:17 Info: count: Done "count" with 2 modules, 60 files 2018.07.23.09:00:17 Info: qsys-generate succeeded. 2018.07.23.09:00:17 Info: Finished: Create simulation model 2018.07.23.09:00:17 Info: 2018.07.23.09:00:17 Info: Saving generation log to /home/tempuser11/counter/counterDUT1.prj/verification/tb/tb_generation.rpt 2018.07.23.09:00:17 Info: Generated by version: 17.1 build 240 2018.07.23.09:00:17 Info: Starting: Create simulation model 2018.07.23.09:00:17 Info: qsys-generate /home/tempuser11/counter/counterDUT1.prj/verification/tb.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/tempuser11/counter/counterDUT1.prj/verification/tb --family="Arria 10" --part=10AX115U1F45I1SG 2018.07.23.09:00:17 Info: Loading verification/tb.qsys 2018.07.23.09:00:17 Info: Reading input file 2018.07.23.09:00:17 Info: Adding clock_reset_inst [altera_generic_component 1.0] 2018.07.23.09:00:17 Info: Parameterizing module clock_reset_inst 2018.07.23.09:00:17 Info: Adding component_dpi_controller_count_inst [altera_generic_component 1.0] 2018.07.23.09:00:17 Info: Parameterizing module component_dpi_controller_count_inst 2018.07.23.09:00:17 Info: Adding concatenate_component_done_inst [altera_generic_component 1.0] 2018.07.23.09:00:17 Info: Parameterizing module concatenate_component_done_inst 2018.07.23.09:00:17 Info: Adding concatenate_component_wait_for_stream_writes_inst [altera_generic_component 1.0] 2018.07.23.09:00:17 Info: Parameterizing module concatenate_component_wait_for_stream_writes_inst 2018.07.23.09:00:17 Info: Adding count_component_dpi_controller_bind_conduit_fanout_inst [altera_generic_component 1.0] 2018.07.23.09:00:17 Info: Parameterizing module count_component_dpi_controller_bind_conduit_fanout_inst 2018.07.23.09:00:17 Info: Adding count_component_dpi_controller_enable_conduit_fanout_inst [altera_generic_component 1.0] 2018.07.23.09:00:17 Info: Parameterizing module count_component_dpi_controller_enable_conduit_fanout_inst 2018.07.23.09:00:17 Info: Adding count_inst [altera_generic_component 1.0] 2018.07.23.09:00:17 Info: Parameterizing module count_inst 2018.07.23.09:00:17 Info: Adding main_dpi_controller_inst [altera_generic_component 1.0] 2018.07.23.09:00:17 Info: Parameterizing module main_dpi_controller_inst 2018.07.23.09:00:17 Info: Adding split_component_start_inst [altera_generic_component 1.0] 2018.07.23.09:00:17 Info: Parameterizing module split_component_start_inst 2018.07.23.09:00:17 Info: Building connections 2018.07.23.09:00:17 Info: Parameterizing connections 2018.07.23.09:00:17 Info: Validating 2018.07.23.09:00:17 Info: Done reading input file 2018.07.23.09:00:18 Warning: tb.clock_reset_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. 2018.07.23.09:00:18 Warning: tb.component_dpi_controller_count_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. 2018.07.23.09:00:18 Warning: tb.component_dpi_controller_count_inst: Warnings found in IP parameterization. 2018.07.23.09:00:18 Warning: tb.component_dpi_controller_count_inst.dpi_control_slaves_done: Interface has no signals 2018.07.23.09:00:18 Warning: tb.component_dpi_controller_count_inst.dpi_control_slaves_ready: Interface has no signals 2018.07.23.09:00:18 Warning: tb.component_dpi_controller_count_inst.dpi_control_stream_writes_active: Interface has no signals 2018.07.23.09:00:18 Warning: tb.concatenate_component_done_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. 2018.07.23.09:00:18 Warning: tb.concatenate_component_wait_for_stream_writes_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. 2018.07.23.09:00:18 Warning: tb.count_component_dpi_controller_bind_conduit_fanout_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. 2018.07.23.09:00:18 Warning: tb.count_component_dpi_controller_enable_conduit_fanout_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. 2018.07.23.09:00:18 Warning: tb.main_dpi_controller_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. 2018.07.23.09:00:18 Warning: tb.split_component_start_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. 2018.07.23.09:00:18 Info: tb: "Transforming system: tb" 2018.07.23.09:00:18 Info: tb: Running transform generation_view_transform 2018.07.23.09:00:18 Info: tb: Running transform generation_view_transform took 0.000s 2018.07.23.09:00:18 Info: tb: Running transform interconnect_transform_chooser 2018.07.23.09:00:18 Info: tb: Running transform interconnect_transform_chooser took 0.062s 2018.07.23.09:00:18 Info: tb: "Naming system components in system: tb" 2018.07.23.09:00:18 Info: tb: "Processing generation queue" 2018.07.23.09:00:18 Info: tb: "Generating: tb" 2018.07.23.09:00:18 Info: tb: "Generating: clock_reset" 2018.07.23.09:00:18 Info: tb: "Generating: dpic_count" 2018.07.23.09:00:18 Info: tb: "Generating: cat_done" 2018.07.23.09:00:18 Info: tb: "Generating: cat_cwfsw" 2018.07.23.09:00:18 Info: tb: "Generating: count_cfan" 2018.07.23.09:00:18 Info: tb: "Generating: count_en_cfan" 2018.07.23.09:00:18 Info: tb: "Generating: count" 2018.07.23.09:00:18 Info: tb: "Generating: main_dpi_controller" 2018.07.23.09:00:18 Info: tb: "Generating: sp_cstart" 2018.07.23.09:00:18 Info: tb: "Generating: tb_altera_irq_mapper_171_e3f7koy" 2018.07.23.09:00:18 Info: tb: Done "tb" with 11 modules, 2 files 2018.07.23.09:00:18 Info: qsys-generate succeeded. 2018.07.23.09:00:18 Info: Finished: Create simulation model 2018.07.23.09:00:18 Info: Starting: Create Modelsim Project. 2018.07.23.09:00:18 Info: sim-script-gen --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/cat_done/cat_done.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/count_cfan/count_cfan.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/dpic_count/dpic_count.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/count_en_cfan/count_en_cfan.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/clock_reset/clock_reset.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/cat_cwfsw/cat_cwfsw.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/sp_cstart/sp_cstart.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/main_dpi_controller/main_dpi_controller.spd --spd=/home/tempuser11/counter/counterDUT1.prj/components/count/count/count.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/tb/tb.spd --output-directory=/home/tempuser11/counter/counterDUT1.prj/verification/tb/sim/ --use-relative-paths=true 2018.07.23.09:00:18 Info: Doing: ip-make-simscript --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/cat_done/cat_done.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/count_cfan/count_cfan.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/dpic_count/dpic_count.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/count_en_cfan/count_en_cfan.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/clock_reset/clock_reset.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/cat_cwfsw/cat_cwfsw.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/sp_cstart/sp_cstart.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/ip/tb/main_dpi_controller/main_dpi_controller.spd --spd=/home/tempuser11/counter/counterDUT1.prj/components/count/count/count.spd --spd=/home/tempuser11/counter/counterDUT1.prj/verification/tb/tb.spd --output-directory=/home/tempuser11/counter/counterDUT1.prj/verification/tb/sim/ --use-relative-paths=true 2018.07.23.09:00:21 Info: Generating the following file(s) for MODELSIM simulator in /home/tempuser11/counter/counterDUT1.prj/verification/tb/sim/ directory: 2018.07.23.09:00:21 Info: mentor/msim_setup.tcl 2018.07.23.09:00:21 Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation 2018.07.23.09:00:21 Info: Generating the following file(s) for VCSMX simulator in /home/tempuser11/counter/counterDUT1.prj/verification/tb/sim/ directory: 2018.07.23.09:00:21 Info: synopsys/vcsmx/synopsys_sim.setup 2018.07.23.09:00:21 Info: synopsys/vcsmx/vcsmx_setup.sh 2018.07.23.09:00:21 Info: Generating the following file(s) for NCSIM simulator in /home/tempuser11/counter/counterDUT1.prj/verification/tb/sim/ directory: 2018.07.23.09:00:21 Info: cadence/cds.lib 2018.07.23.09:00:21 Info: cadence/hdl.var 2018.07.23.09:00:21 Info: cadence/ncsim_setup.sh 2018.07.23.09:00:21 Info: 18 .cds.lib files in cadence/cds_libs/ directory 2018.07.23.09:00:21 Info: Generating the following file(s) for RIVIERA simulator in /home/tempuser11/counter/counterDUT1.prj/verification/tb/sim/ directory: 2018.07.23.09:00:21 Info: aldec/rivierapro_setup.tcl 2018.07.23.09:00:21 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/tempuser11/counter/counterDUT1.prj/verification/tb/sim/. 2018.07.23.09:00:21 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. 2018.07.23.09:00:21 Info: Finished: Create Modelsim Project. # # do tb/sim/mentor/msim_compile.tcl # Model Technology ModelSim ALTERA STARTER EDITION vsim 10.5c Simulator 2017.01 Jan 23 2017 # tb/sim # [exec] file_copy # List Of Command Line Aliases # # file_copy -- Copy ROM/RAM files to simulation directory # # dev_com -- Compile device library files # # com -- Compile the design files in correct order # # elab -- Elaborate top level design # # elab_debug -- Elaborate the top level design with novopt option # # ld -- Compile all the design files and elaborate the top level design # # ld_debug -- Compile all the design files and elaborate the top level design with -novopt # # # # List Of Variables # # TOP_LEVEL_NAME -- Top level module name. # For most designs, this should be overridden # to enable the elab/elab_debug aliases. # # SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module. # # QSYS_SIMDIR -- Qsys base simulation directory. # # QUARTUS_INSTALL_DIR -- Quartus installation directory. # # USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases. # # USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases. # # USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases. # # USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases. # # FORCE_MODELSIM_AE_SELECTION -- Set to true to force to select Modelsim AE always. # +nowarnTFMPC # [exec] dev_com # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:00:28 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/altera_primitives.v -work altera_ver # -- Compiling module global # -- Compiling module carry # -- Compiling module cascade # -- Compiling module carry_sum # -- Compiling module exp # -- Compiling module soft # -- Compiling module opndrn # -- Compiling module row_global # -- Compiling module TRI # -- Compiling module lut_input # -- Compiling module lut_output # -- Compiling module latch # -- Compiling module dlatch # -- Compiling module prim_gdff # -- Compiling module dff # -- Compiling module dffe # -- Compiling module dffea # -- Compiling module dffeas # -- Compiling module prim_gtff # -- Compiling module tff # -- Compiling module tffe # -- Compiling module prim_gjkff # -- Compiling module jkff # -- Compiling module jkffe # -- Compiling module prim_gsrff # -- Compiling module srff # -- Compiling module srffe # -- Compiling module clklock # -- Compiling module alt_inbuf # -- Compiling module alt_outbuf # -- Compiling module alt_outbuf_tri # -- Compiling module alt_iobuf # -- Compiling module alt_inbuf_diff # -- Compiling module alt_outbuf_diff # -- Compiling module alt_outbuf_tri_diff # -- Compiling module alt_iobuf_diff # -- Compiling module alt_bidir_diff # -- Compiling module alt_bidir_buf # -- Compiling UDP PRIM_GDFF_LOW # -- Compiling UDP PRIM_GDFF_LOW_SCLR_PRIORITY # -- Compiling UDP PRIM_GDFF_HIGH # -- Compiling UDP PRIM_GDFF_HIGH_SCLR_PRIORITY # # Top level modules: # global # carry # cascade # carry_sum # exp # soft # opndrn # row_global # TRI # lut_input # lut_output # latch # dlatch # dff # dffe # dffea # dffeas # tff # tffe # jkff # jkffe # srff # srffe # clklock # alt_inbuf # alt_outbuf # alt_outbuf_tri # alt_iobuf # alt_inbuf_diff # alt_outbuf_diff # alt_outbuf_tri_diff # alt_iobuf_diff # alt_bidir_diff # alt_bidir_buf # End time: 09:00:29 on Jul 23,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:00:29 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/220model.v -work lpm_ver # -- Compiling module LPM_MEMORY_INITIALIZATION # -- Compiling module LPM_HINT_EVALUATION # -- Compiling module LPM_DEVICE_FAMILIES # -- Compiling module lpm_constant # -- Compiling module lpm_inv # -- Compiling module lpm_and # -- Compiling module lpm_or # -- Compiling module lpm_xor # -- Compiling module lpm_bustri # -- Compiling module lpm_mux # -- Compiling module lpm_decode # -- Compiling module lpm_clshift # -- Compiling module lpm_add_sub # -- Compiling module lpm_compare # -- Compiling module lpm_mult # -- Compiling module lpm_divide # -- Compiling module lpm_abs # -- Compiling module lpm_counter # -- Compiling module lpm_latch # -- Compiling module lpm_ff # -- Compiling module lpm_shiftreg # -- Compiling module lpm_ram_dq # -- Compiling module lpm_ram_dp # -- Compiling module lpm_ram_io # -- Compiling module lpm_rom # -- Compiling module lpm_fifo # -- Compiling module lpm_fifo_dc_dffpipe # -- Compiling module lpm_fifo_dc_fefifo # -- Compiling module lpm_fifo_dc_async # -- Compiling module lpm_fifo_dc # -- Compiling module lpm_inpad # -- Compiling module lpm_outpad # -- Compiling module lpm_bipad # # Top level modules: # lpm_constant # lpm_inv # lpm_and # lpm_or # lpm_xor # lpm_bustri # lpm_mux # lpm_decode # lpm_clshift # lpm_add_sub # lpm_compare # lpm_mult # lpm_divide # lpm_abs # lpm_counter # lpm_latch # lpm_ff # lpm_shiftreg # lpm_ram_dq # lpm_ram_dp # lpm_ram_io # lpm_rom # lpm_fifo # lpm_fifo_dc # lpm_inpad # lpm_outpad # lpm_bipad # End time: 09:00:29 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:00:29 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/sgate.v -work sgate_ver # -- Compiling module oper_add # -- Compiling module oper_addsub # -- Compiling module mux21 # -- Compiling module io_buf_tri # -- Compiling module io_buf_opdrn # -- Compiling module oper_mult # -- Compiling module tri_bus # -- Compiling module oper_div # -- Compiling module oper_mod # -- Compiling module oper_left_shift # -- Compiling module oper_right_shift # -- Compiling module oper_rotate_left # -- Compiling module oper_rotate_right # -- Compiling module oper_less_than # -- Compiling module oper_mux # -- Compiling module oper_selector # -- Compiling module oper_decoder # -- Compiling module oper_bus_mux # -- Compiling module oper_latch # # Top level modules: # oper_add # oper_addsub # mux21 # io_buf_tri # io_buf_opdrn # oper_mult # tri_bus # oper_div # oper_mod # oper_left_shift # oper_right_shift # oper_rotate_left # oper_rotate_right # oper_less_than # oper_mux # oper_selector # oper_decoder # oper_bus_mux # oper_latch # End time: 09:00:29 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:00:29 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/altera_mf.v -work altera_mf_ver # -- Compiling module lcell # -- Compiling module ALTERA_MF_MEMORY_INITIALIZATION # -- Compiling module ALTERA_MF_HINT_EVALUATION # -- Compiling module ALTERA_DEVICE_FAMILIES # -- Compiling module dffp # -- Compiling module pll_iobuf # -- Compiling module stx_m_cntr # -- Compiling module stx_n_cntr # -- Compiling module stx_scale_cntr # -- Compiling module MF_pll_reg # -- Compiling module MF_stratix_pll # -- Compiling module arm_m_cntr # -- Compiling module arm_n_cntr # -- Compiling module arm_scale_cntr # -- Compiling module MF_stratixii_pll # -- Compiling module ttn_m_cntr # -- Compiling module ttn_n_cntr # -- Compiling module ttn_scale_cntr # -- Compiling module MF_stratixiii_pll # -- Compiling module cda_m_cntr # -- Compiling module cda_n_cntr # -- Compiling module cda_scale_cntr # -- Compiling module MF_cycloneiii_pll # -- Compiling module MF_cycloneiiigl_m_cntr # -- Compiling module MF_cycloneiiigl_n_cntr # -- Compiling module MF_cycloneiiigl_scale_cntr # -- Compiling module cycloneiiigl_post_divider # -- Compiling module MF_cycloneiiigl_pll # -- Compiling module altpll # -- Compiling module altlvds_rx # -- Compiling module stratix_lvds_rx # -- Compiling module stratixgx_dpa_lvds_rx # -- Compiling module stratixii_lvds_rx # -- Compiling module flexible_lvds_rx # -- Compiling module stratixiii_lvds_rx # -- Compiling module stratixiii_lvds_rx_channel # -- Compiling module stratixiii_lvds_rx_dpa # -- Compiling module altlvds_tx # -- Compiling module stratixv_local_clk_divider # -- Compiling module stratix_tx_outclk # -- Compiling module stratixii_tx_outclk # -- Compiling module flexible_lvds_tx # -- Compiling module dcfifo_dffpipe # -- Compiling module dcfifo_fefifo # -- Compiling module dcfifo_async # -- Compiling module dcfifo_sync # -- Compiling module dcfifo_low_latency # -- Compiling module dcfifo_mixed_widths # -- Compiling module dcfifo # -- Compiling module altera_syncram_derived # -- Compiling module altera_syncram_derived_forwarding_logic # -- Compiling module altaccumulate # -- Compiling module altmult_accum # -- Compiling module altmult_add # -- Compiling module altfp_mult # -- Compiling module altsqrt # -- Compiling module altclklock # -- Compiling module altddio_in # -- Compiling module altddio_out # -- Compiling module altddio_bidir # -- Compiling module altdpram # -- Compiling module altsyncram # -- Compiling module altsyncram_body # -- Compiling module alt3pram # -- Compiling module parallel_add # -- Compiling module scfifo # -- Compiling module altshift_taps # -- Compiling module a_graycounter # -- Compiling module altsquare # -- Compiling module altera_std_synchronizer # -- Compiling module altera_std_synchronizer_bundle # -- Compiling module alt_cal # -- Compiling module alt_cal_mm # -- Compiling module alt_cal_c3gxb # -- Compiling module alt_cal_sv # -- Compiling module alt_cal_av # -- Compiling module alt_aeq_s4 # -- Compiling module alt_eyemon # -- Compiling module alt_dfe # -- Compiling module signal_gen # -- Compiling module jtag_tap_controller # -- Compiling module dummy_hub # -- Compiling module sld_virtual_jtag # -- Compiling module sld_signaltap # -- Compiling module altstratixii_oct # -- Compiling module altparallel_flash_loader # -- Compiling module altserial_flash_loader # -- Compiling module alt_fault_injection # -- Compiling module sld_virtual_jtag_basic # -- Compiling module altsource_probe # # Top level modules: # lcell # altpll # altlvds_rx # altlvds_tx # dcfifo # altaccumulate # altmult_accum # altmult_add # altfp_mult # altsqrt # altclklock # altddio_bidir # altdpram # alt3pram # parallel_add # scfifo # altshift_taps # a_graycounter # altsquare # altera_std_synchronizer_bundle # alt_cal # alt_cal_mm # alt_cal_c3gxb # alt_cal_sv # alt_cal_av # alt_aeq_s4 # alt_eyemon # alt_dfe # sld_virtual_jtag # sld_signaltap # altstratixii_oct # altparallel_flash_loader # altserial_flash_loader # alt_fault_injection # sld_virtual_jtag_basic # altsource_probe # End time: 09:00:31 on Jul 23,2018, Elapsed time: 0:00:02 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:00:31 on Jul 23,2018 # vlog -sv /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/altera_lnsim.sv -work altera_lnsim_ver # -- Compiling package altera_lnsim_functions # -- Compiling package altera_generic_pll_functions # -- Compiling module generic_pll # -- Importing package altera_lnsim_functions # -- Importing package altera_generic_pll_functions # -- Compiling module generic_cdr # -- Compiling module common_28nm_ram_pulse_generator # -- Compiling module common_28nm_ram_register # -- Compiling module common_28nm_ram_block # -- Compiling module generic_m20k # -- Compiling module generic_m10k # -- Compiling module common_28nm_mlab_cell_pulse_generator # -- Compiling module common_28nm_mlab_latch # -- Compiling module common_28nm_mlab_cell_core # -- Compiling module common_porta_latches # -- Compiling module generic_28nm_hp_mlab_cell_impl # -- Compiling module common_porta_registers # -- Compiling module generic_28nm_lc_mlab_cell_impl # -- Compiling module common_28nm_lutram_register # -- Compiling module generic_14nm_mlab_cell_impl # -- Compiling module common_14nm_lutram_register # -- Compiling module generic_mux # -- Compiling module generic_device_pll # -- Compiling module altera_mult_add # -- Compiling module altera_mult_add_rtl # -- Compiling module ama_signed_extension_function # -- Compiling module ama_dynamic_signed_function # -- Compiling module ama_register_function # -- Compiling module ama_register_with_ext_function # -- Compiling module ama_data_split_reg_ext_function # -- Compiling module ama_coef_reg_ext_function # -- Compiling module ama_adder_function # -- Compiling module ama_multiplier_function # -- Compiling module ama_preadder_function # -- Compiling module ama_chainout_adder_accumulator_function # -- Compiling module ama_systolic_adder_function # -- Compiling module ama_scanchain # -- Compiling module ama_latency_function # -- Compiling module altera_pll_reconfig_tasks # -- Compiling module altera_syncram # -- Compiling module altera_syncram_forwarding_logic # -- Compiling module ALTERA_LNSIM_MEMORY_INITIALIZATION # -- Compiling module altera_stratixv_pll # -- Compiling module altera_arriav_pll # -- Compiling module altera_arriavgz_pll # -- Compiling module altera_cyclonev_pll # -- Compiling module altera_pll # -- Compiling module dps_extra_kick # -- Compiling module dprio_init # -- Compiling module dps_pulse_gen # -- Compiling module altera_iopll # -- Compiling module dps_pulse_gen_iopll # -- Compiling module twentynm_iopll_arlol # -- Compiling package fourteennm_iopll_functions # -- Compiling module fourteennm_simple_iopll # -- Importing package fourteennm_iopll_functions # -- Compiling module fourteennm_sub_iopll # -- Compiling module twentynm_iopll_ip # -- Compiling module cyclone10gx_iopll_ip # -- Compiling module altera_iopll_rotation_lcells # -- Compiling module altera_pll_dps_lcell_comb # -- Compiling module iopll_bootstrap # -- Compiling module dffeas_pr # -- Compiling module fourteennm_ff_pr # -- Compiling package twentynm_prblock_test_pkg # -- Compiling interface twentynm_prblock_if # -- Compiling module twentynm_prblock # -- Importing package twentynm_prblock_test_pkg # -- Compiling interface altera_pr_persona_if # -- Compiling module altera_pr_wrapper_mux_out # -- Compiling module altera_pr_wrapper_mux_in # -- Compiling module lcell_comb_generic # -- Compiling module ff_generic # # Top level modules: # generic_cdr # generic_m20k # generic_m10k # common_porta_latches # generic_28nm_hp_mlab_cell_impl # generic_28nm_lc_mlab_cell_impl # generic_14nm_mlab_cell_impl # generic_mux # generic_device_pll # altera_mult_add # altera_pll_reconfig_tasks # altera_syncram # altera_pll # altera_iopll # fourteennm_simple_iopll # fourteennm_ff_pr # twentynm_prblock # altera_pr_wrapper_mux_out # altera_pr_wrapper_mux_in # lcell_comb_generic # ff_generic # End time: 09:00:31 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:00:31 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/twentynm_atoms.v -work twentynm_ver # -- Compiling UDP TWENTYNM_PRIM_DFFE # -- Compiling UDP TWENTYNM_PRIM_DFFEAS # -- Compiling UDP TWENTYNM_PRIM_DFFEAS_HIGH # -- Compiling module twentynm_dffe # -- Compiling module twentynm_mux21 # -- Compiling module twentynm_mux41 # -- Compiling module twentynm_and1 # -- Compiling module twentynm_and16 # -- Compiling module twentynm_bmux21 # -- Compiling module twentynm_b17mux21 # -- Compiling module twentynm_nmux21 # -- Compiling module twentynm_b5mux21 # -- Compiling module twentynm_ff # -- Compiling module twentynm_lcell_comb # -- Compiling module twentynm_routing_wire # -- Compiling module twentynm_ram_block # -- Compiling module twentynm_mlab_cell # -- Compiling module twentynm_io_ibuf # -- Compiling module twentynm_io_obuf # -- Compiling module twentynm_pseudo_diff_out # -- Compiling module twentynm_io_pad # -- Compiling module twentynm_bias_logic # -- Compiling module twentynm_bias_generator # -- Compiling module twentynm_bias_block # -- Compiling module twentynm_clk_phase_select # -- Compiling module twentynm_clkena # -- Compiling module twentynm_clkselect # -- Compiling module twentynm_delay_chain # -- Compiling module twentynm_dll_offset_ctrl # -- Compiling module twentynm_dll # -- Compiling module twentynm_dqs_config # -- Compiling module twentynm_dqs_delay_chain # -- Compiling module twentynm_dqs_enable_ctrl # -- Compiling module twentynm_duty_cycle_adjustment # -- Compiling module twentynm_half_rate_input # -- Compiling module twentynm_input_phase_alignment # -- Compiling module twentynm_io_clock_divider # -- Compiling module twentynm_io_config # -- Compiling module twentynm_leveling_delay_chain # -- Compiling module twentynm_termination_logic # -- Compiling module twentynm_termination # -- Compiling module twentynm_asmiblock # -- Compiling module twentynm_crcblock # -- Compiling module twentynm_opregblock # -- Compiling module twentynm_jtag # -- Compiling module twentynm_jtagblock # -- Compiling module twentynm_rublock # -- Compiling module twentynm_tsdblock # -- Compiling module twentynm_vsblock # -- Compiling module twentynm_read_fifo # -- Compiling module twentynm_read_fifo_read_enable # -- Compiling module twentynm_phy_clkbuf # -- Compiling module twentynm_io_serdes_dpa # -- Compiling module twentynm_lvds_clock_tree # -- Compiling module twentynm_ir_fifo_userdes # -- Compiling module twentynm_read_fifo_read_clock_select # -- Compiling module twentynm_lfifo # -- Compiling module twentynm_vfifo # -- Compiling module twentynm_fp_mac # -- Compiling module twentynm_mac # -- Compiling module twentynm_mem_phy # -- Compiling module twentynm_oscillator # -- Compiling module twentynm_iopll # -- Compiling module twentynm_io_12_lane # -- Compiling module twentynm_tile_ctrl # -- Compiling module twentynm_refclk_input # -- Compiling module twentynm_io_aux # -- Compiling module twentynm_ddio_in # -- Compiling module twentynm_ddio_out # # Top level modules: # twentynm_dffe # twentynm_mux21 # twentynm_mux41 # twentynm_and1 # twentynm_and16 # twentynm_bmux21 # twentynm_b17mux21 # twentynm_nmux21 # twentynm_b5mux21 # twentynm_ff # twentynm_lcell_comb # twentynm_routing_wire # twentynm_ram_block # twentynm_mlab_cell # twentynm_io_ibuf # twentynm_io_obuf # twentynm_pseudo_diff_out # twentynm_io_pad # twentynm_bias_block # twentynm_clk_phase_select # twentynm_clkena # twentynm_clkselect # twentynm_delay_chain # twentynm_dll_offset_ctrl # twentynm_dll # twentynm_dqs_config # twentynm_dqs_delay_chain # twentynm_dqs_enable_ctrl # twentynm_duty_cycle_adjustment # twentynm_half_rate_input # twentynm_input_phase_alignment # twentynm_io_clock_divider # twentynm_io_config # twentynm_leveling_delay_chain # twentynm_termination_logic # twentynm_termination # twentynm_asmiblock # twentynm_crcblock # twentynm_opregblock # twentynm_jtag # twentynm_jtagblock # twentynm_rublock # twentynm_tsdblock # twentynm_vsblock # twentynm_read_fifo # twentynm_read_fifo_read_enable # twentynm_phy_clkbuf # twentynm_io_serdes_dpa # twentynm_lvds_clock_tree # twentynm_ir_fifo_userdes # twentynm_read_fifo_read_clock_select # twentynm_lfifo # twentynm_vfifo # twentynm_fp_mac # twentynm_mac # twentynm_mem_phy # twentynm_oscillator # twentynm_iopll # twentynm_io_12_lane # twentynm_tile_ctrl # twentynm_refclk_input # twentynm_io_aux # twentynm_ddio_in # twentynm_ddio_out # End time: 09:00:32 on Jul 23,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:00:32 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/mentor/twentynm_atoms_ncrypt.v -work twentynm_ver # # Top level modules: # End time: 09:00:49 on Jul 23,2018, Elapsed time: 0:00:17 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:00:49 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/mentor/twentynm_hssi_atoms_ncrypt.v -work twentynm_hssi_ver # # Top level modules: # End time: 09:00:59 on Jul 23,2018, Elapsed time: 0:00:10 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:00:59 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/twentynm_hssi_atoms.v -work twentynm_hssi_ver # -- Compiling module twentynm_atx_pll # -- Compiling module twentynm_cmu_fpll_refclk_select # -- Compiling module twentynm_cmu_fpll # -- Compiling module twentynm_hssi_10g_rx_pcs # -- Compiling module twentynm_hssi_10g_tx_pcs # -- Compiling module twentynm_hssi_8g_rx_pcs # -- Compiling module twentynm_hssi_8g_tx_pcs # -- Compiling module twentynm_hssi_common_pcs_pma_interface # -- Compiling module twentynm_hssi_common_pld_pcs_interface # -- Compiling module twentynm_hssi_fifo_rx_pcs # -- Compiling module twentynm_hssi_fifo_tx_pcs # -- Compiling module twentynm_hssi_gen3_rx_pcs # -- Compiling module twentynm_hssi_gen3_tx_pcs # -- Compiling module twentynm_hssi_krfec_rx_pcs # -- Compiling module twentynm_hssi_krfec_tx_pcs # -- Compiling module twentynm_hssi_pipe_gen1_2 # -- Compiling module twentynm_hssi_pipe_gen3 # -- Compiling module twentynm_hssi_pma_adaptation # -- Compiling module twentynm_hssi_pma_aux # -- Compiling module twentynm_hssi_pma_cdr_refclk_select_mux # -- Compiling module twentynm_hssi_pma_cgb_master # -- Compiling module twentynm_hssi_pma_channel_pll # -- Compiling module twentynm_hssi_pma_lc_refclk_select_mux # -- Compiling module twentynm_hssi_pma_rx_buf # -- Compiling module twentynm_hssi_pma_rx_deser # -- Compiling module twentynm_hssi_pma_rx_dfe # -- Compiling module twentynm_hssi_pma_rx_odi # -- Compiling module twentynm_hssi_pma_rx_sd # -- Compiling module twentynm_hssi_pma_tx_buf # -- Compiling module twentynm_hssi_pma_tx_cgb # -- Compiling module twentynm_hssi_pma_tx_ser # -- Compiling module twentynm_hssi_pma_uc # -- Compiling module twentynm_hssi_refclk_divider # -- Compiling module twentynm_hssi_rx_pcs_pma_interface # -- Compiling module twentynm_hssi_rx_pld_pcs_interface # -- Compiling module twentynm_hssi_tx_pcs_pma_interface # -- Compiling module twentynm_hssi_tx_pld_pcs_interface # -- Compiling module twentynm_hssi_avmm_if # # Top level modules: # twentynm_atx_pll # twentynm_cmu_fpll_refclk_select # twentynm_cmu_fpll # twentynm_hssi_10g_rx_pcs # twentynm_hssi_10g_tx_pcs # twentynm_hssi_8g_rx_pcs # twentynm_hssi_8g_tx_pcs # twentynm_hssi_common_pcs_pma_interface # twentynm_hssi_common_pld_pcs_interface # twentynm_hssi_fifo_rx_pcs # twentynm_hssi_fifo_tx_pcs # twentynm_hssi_gen3_rx_pcs # twentynm_hssi_gen3_tx_pcs # twentynm_hssi_krfec_rx_pcs # twentynm_hssi_krfec_tx_pcs # twentynm_hssi_pipe_gen1_2 # twentynm_hssi_pipe_gen3 # twentynm_hssi_pma_adaptation # twentynm_hssi_pma_aux # twentynm_hssi_pma_cdr_refclk_select_mux # twentynm_hssi_pma_cgb_master # twentynm_hssi_pma_channel_pll # twentynm_hssi_pma_lc_refclk_select_mux # twentynm_hssi_pma_rx_buf # twentynm_hssi_pma_rx_deser # twentynm_hssi_pma_rx_dfe # twentynm_hssi_pma_rx_odi # twentynm_hssi_pma_rx_sd # twentynm_hssi_pma_tx_buf # twentynm_hssi_pma_tx_cgb # twentynm_hssi_pma_tx_ser # twentynm_hssi_pma_uc # twentynm_hssi_refclk_divider # twentynm_hssi_rx_pcs_pma_interface # twentynm_hssi_rx_pld_pcs_interface # twentynm_hssi_tx_pcs_pma_interface # twentynm_hssi_tx_pld_pcs_interface # twentynm_hssi_avmm_if # End time: 09:00:59 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:00:59 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/mentor/twentynm_hip_atoms_ncrypt.v -work twentynm_hip_ver # # Top level modules: # End time: 09:01:06 on Jul 23,2018, Elapsed time: 0:00:07 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:06 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/twentynm_hip_atoms.v -work twentynm_hip_ver # -- Compiling module twentynm_hssi_gen3_x8_pcie_hip # # Top level modules: # twentynm_hssi_gen3_x8_pcie_hip # End time: 09:01:07 on Jul 23,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:07 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/altera_syn_attributes.vhd -work altera # -- Loading package STANDARD # -- Compiling package altera_syn_attributes # End time: 09:01:07 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:07 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/altera_standard_functions.vhd -work altera # -- Loading package STANDARD # -- Compiling package altera_standard_functions # -- Compiling package body altera_standard_functions # -- Loading package altera_standard_functions # End time: 09:01:07 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:07 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/alt_dspbuilder_package.vhd -work altera # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Compiling package alt_dspbuilder_package # -- Compiling package body alt_dspbuilder_package # -- Loading package alt_dspbuilder_package # End time: 09:01:07 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:07 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/altera_europa_support_lib.vhd -work altera # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package std_logic_arith # -- Loading package STD_LOGIC_UNSIGNED # -- Compiling package altera_europa_support_lib # -- Compiling package body altera_europa_support_lib # -- Loading package altera_europa_support_lib # End time: 09:01:07 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:07 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/altera_primitives_components.vhd -work altera # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Compiling package dffeas_pack # -- Loading package dffeas_pack # -- Compiling package altera_primitives_components # End time: 09:01:07 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:07 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/altera_primitives.vhd -work altera # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling entity GLOBAL # -- Compiling architecture BEHAVIOR of GLOBAL # -- Compiling entity CARRY # -- Compiling architecture BEHAVIOR of CARRY # -- Compiling entity CASCADE # -- Compiling architecture BEHAVIOR of CASCADE # -- Compiling entity CARRY_SUM # -- Compiling architecture BEHAVIOR of CARRY_SUM # -- Compiling entity EXP # -- Compiling architecture BEHAVIOR of EXP # -- Compiling entity SOFT # -- Compiling architecture BEHAVIOR of SOFT # -- Compiling entity OPNDRN # -- Compiling architecture BEHAVIOR of OPNDRN # -- Compiling entity ROW_GLOBAL # -- Compiling architecture BEHAVIOR of ROW_GLOBAL # -- Compiling entity TRI # -- Compiling architecture BEHAVIOR of TRI # -- Compiling entity LUT_INPUT # -- Compiling architecture BEHAVIOR of LUT_INPUT # -- Compiling entity LUT_OUTPUT # -- Compiling architecture BEHAVIOR of LUT_OUTPUT # -- Compiling entity latch # -- Compiling architecture BEHAVIOR of latch # -- Compiling entity dlatch # -- Compiling architecture BEHAVIOR of dlatch # -- Compiling entity PRIM_GDFF # -- Compiling architecture BEHAVIOR of PRIM_GDFF # -- Loading entity PRIM_GDFF # -- Compiling entity DFF # -- Compiling architecture BEHAVIOR of DFF # -- Compiling entity DFFE # -- Compiling architecture BEHAVIOR of DFFE # -- Compiling entity DFFEA # -- Compiling architecture BEHAVIOR of DFFEA # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package dffeas_pack # -- Compiling entity DFFEAS # -- Compiling architecture vital_dffeas of dffeas # -- Compiling entity PRIM_GTFF # -- Compiling architecture BEHAVIOR of PRIM_GTFF # -- Loading entity PRIM_GTFF # -- Compiling entity TFF # -- Compiling architecture BEHAVIOR of TFF # -- Compiling entity TFFE # -- Compiling architecture BEHAVIOR of TFFE # -- Compiling entity PRIM_GJKFF # -- Compiling architecture BEHAVIOR of PRIM_GJKFF # -- Loading entity PRIM_GJKFF # -- Compiling entity JKFF # -- Compiling architecture BEHAVIOR of JKFF # -- Compiling entity JKFFE # -- Compiling architecture BEHAVIOR of JKFFE # -- Compiling entity PRIM_GSRFF # -- Compiling architecture BEHAVIOR of PRIM_GSRFF # -- Loading entity PRIM_GSRFF # -- Compiling entity SRFF # -- Compiling architecture BEHAVIOR of SRFF # -- Compiling entity SRFFE # -- Compiling architecture BEHAVIOR of SRFFE # -- Compiling entity clklock # -- Compiling architecture behavior of clklock # -- Compiling entity alt_inbuf # -- Compiling architecture BEHAVIOR of alt_inbuf # -- Compiling entity alt_outbuf # -- Compiling architecture BEHAVIOR of alt_outbuf # -- Compiling entity alt_outbuf_tri # -- Compiling architecture BEHAVIOR of alt_outbuf_tri # -- Compiling entity alt_iobuf # -- Compiling architecture BEHAVIOR of alt_iobuf # -- Compiling entity alt_inbuf_diff # -- Compiling architecture BEHAVIOR of alt_inbuf_diff # -- Compiling entity alt_outbuf_diff # -- Compiling architecture BEHAVIOR of alt_outbuf_diff # -- Compiling entity alt_outbuf_tri_diff # -- Compiling architecture BEHAVIOR of alt_outbuf_tri_diff # -- Compiling entity alt_iobuf_diff # -- Compiling architecture BEHAVIOR of alt_iobuf_diff # -- Compiling entity alt_bidir_diff # -- Compiling architecture BEHAVIOR of alt_bidir_diff # -- Compiling entity alt_bidir_buf # -- Compiling architecture BEHAVIOR of alt_bidir_buf # End time: 09:01:07 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:07 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/220pack.vhd -work lpm # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling package LPM_COMPONENTS # End time: 09:01:07 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:07 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/220model.vhd -work lpm # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling package LPM_COMMON_CONVERSION # -- Compiling package body LPM_COMMON_CONVERSION # -- Loading package LPM_COMMON_CONVERSION # -- Compiling package LPM_HINT_EVALUATION # -- Compiling package body LPM_HINT_EVALUATION # -- Loading package LPM_HINT_EVALUATION # -- Compiling package LPM_DEVICE_FAMILIES # -- Compiling package body LPM_DEVICE_FAMILIES # -- Loading package LPM_DEVICE_FAMILIES # -- Loading package std_logic_arith # -- Loading package STD_LOGIC_UNSIGNED # -- Loading package LPM_COMPONENTS # -- Compiling entity LPM_CONSTANT # -- Compiling architecture LPM_SYN of LPM_CONSTANT # -- Compiling entity LPM_INV # -- Compiling architecture LPM_SYN of LPM_INV # -- Compiling entity lpm_and # -- Compiling architecture LPM_SYN of lpm_and # -- Compiling entity LPM_OR # -- Compiling architecture LPM_SYN of LPM_OR # -- Compiling entity LPM_XOR # -- Compiling architecture LPM_SYN of LPM_XOR # -- Compiling entity LPM_BUSTRI # -- Compiling architecture LPM_SYN of LPM_BUSTRI # -- Compiling entity LPM_MUX # -- Compiling architecture LPM_SYN of LPM_MUX # -- Compiling entity LPM_DECODE # -- Compiling architecture LPM_SYN of LPM_DECODE # -- Compiling entity LPM_CLSHIFT # -- Compiling architecture LPM_SYN of LPM_CLSHIFT # -- Loading package STD_LOGIC_SIGNED # -- Compiling entity LPM_ADD_SUB_SIGNED # -- Compiling architecture LPM_SYN of LPM_ADD_SUB_SIGNED # -- Compiling entity LPM_ADD_SUB_UNSIGNED # -- Compiling architecture LPM_SYN of LPM_ADD_SUB_UNSIGNED # -- Loading entity LPM_ADD_SUB_SIGNED # -- Loading entity LPM_ADD_SUB_UNSIGNED # -- Compiling entity LPM_ADD_SUB # -- Compiling architecture LPM_SYN of LPM_ADD_SUB # -- Compiling entity LPM_COMPARE_SIGNED # -- Compiling architecture LPM_SYN of LPM_COMPARE_SIGNED # -- Compiling entity LPM_COMPARE_UNSIGNED # -- Compiling architecture LPM_SYN of LPM_COMPARE_UNSIGNED # -- Loading entity LPM_COMPARE_SIGNED # -- Loading entity LPM_COMPARE_UNSIGNED # -- Compiling entity LPM_COMPARE # -- Compiling architecture LPM_SYN of LPM_COMPARE # -- Loading package LPM_HINT_EVALUATION # -- Compiling entity LPM_MULT # -- Compiling architecture LPM_SYN of LPM_MULT # -- Compiling entity LPM_DIVIDE # -- Compiling architecture behave of lpm_divide # -- Compiling entity lpm_abs # -- Compiling architecture LPM_SYN of LPM_ABS # -- Loading package LPM_COMMON_CONVERSION # -- Compiling entity LPM_COUNTER # -- Compiling architecture LPM_SYN of LPM_COUNTER # -- Compiling entity LPM_LATCH # -- Compiling architecture LPM_SYN of LPM_LATCH # -- Compiling entity LPM_FF # -- Compiling architecture LPM_SYN of LPM_FF # -- Compiling entity LPM_SHIFTREG # -- Compiling architecture LPM_SYN of LPM_SHIFTREG # -- Loading package LPM_DEVICE_FAMILIES # -- Compiling entity LPM_RAM_DQ # -- Compiling architecture LPM_SYN of lpm_ram_dq # -- Compiling entity LPM_RAM_DP # -- Compiling architecture LPM_SYN of LPM_RAM_DP # -- Compiling entity LPM_RAM_IO # -- Compiling architecture LPM_SYN of lpm_ram_io # -- Compiling entity LPM_ROM # -- Compiling architecture LPM_SYN of lpm_rom # -- Compiling entity LPM_FIFO # -- Compiling architecture behavior of LPM_FIFO # -- Compiling entity LPM_FIFO_DC_DFFPIPE # -- Compiling architecture behavior of LPM_FIFO_DC_DFFPIPE # -- Compiling entity LPM_FIFO_DC_FEFIFO # -- Compiling architecture behavior of LPM_FIFO_DC_FEFIFO # -- Loading entity LPM_FIFO_DC_FEFIFO # -- Loading entity LPM_FIFO_DC_DFFPIPE # -- Compiling entity LPM_FIFO_DC_ASYNC # -- Compiling architecture behavior of LPM_FIFO_DC_ASYNC # -- Loading entity LPM_FIFO_DC_ASYNC # -- Compiling entity LPM_FIFO_DC # -- Compiling architecture behavior of LPM_FIFO_DC # -- Compiling entity LPM_INpad # -- Compiling architecture LPM_SYN of LPM_INpad # -- Compiling entity LPM_OUTpad # -- Compiling architecture LPM_SYN of LPM_OUTpad # -- Compiling entity LPM_BIpad # -- Compiling architecture LPM_SYN of LPM_BIpad # End time: 09:01:07 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:07 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/sgate_pack.vhd -work sgate # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling package sgate_pack # -- Compiling package body sgate_pack # -- Loading package sgate_pack # End time: 09:01:07 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:07 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/sgate.vhd -work sgate # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package STD_LOGIC_SIGNED # -- Compiling entity oper_add # -- Compiling architecture sim_arch of oper_add # -- Compiling entity oper_addsub # -- Compiling architecture sim_arch of oper_addsub # -- Compiling entity mux21 # -- Compiling architecture sim_arch of mux21 # -- Compiling entity io_buf_tri # -- Compiling architecture sim_arch of io_buf_tri # -- Compiling entity io_buf_opdrn # -- Compiling architecture sim_arch of io_buf_opdrn # -- Compiling entity tri_bus # -- Compiling architecture sim_arch of tri_bus # -- Compiling entity oper_mult # -- Compiling architecture sim_arch of oper_mult # -- Loading package LPM_COMPONENTS # -- Compiling entity oper_div # -- Compiling architecture sim_arch of oper_div # -- Compiling entity oper_mod # -- Compiling architecture sim_arch of oper_mod # -- Loading package STD_LOGIC_UNSIGNED # -- Compiling entity oper_left_shift # -- Compiling architecture sim_arch of oper_left_shift # -- Compiling entity oper_right_shift # -- Compiling architecture sim_arch of oper_right_shift # -- Compiling entity oper_rotate_left # -- Compiling architecture sim_arch of oper_rotate_left # -- Compiling entity oper_rotate_right # -- Compiling architecture sim_arch of oper_rotate_right # -- Compiling entity oper_less_than # -- Compiling architecture sim_arch of oper_less_than # -- Loading package sgate_pack # -- Compiling entity oper_mux # -- Compiling architecture sim_arch of oper_mux # -- Compiling entity oper_selector # -- Compiling architecture sim_arch of oper_selector # -- Compiling entity oper_prio_selector # -- Compiling architecture sim_arch of oper_prio_selector # -- Compiling entity oper_decoder # -- Compiling architecture sim_arch of oper_decoder # -- Compiling entity oper_bus_mux # -- Compiling architecture sim_arch of oper_bus_mux # -- Compiling entity oper_latch # -- Compiling architecture sim_arch of oper_latch # End time: 09:01:07 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:07 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/altera_mf_components.vhd -work altera_mf # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling package altera_mf_components # End time: 09:01:07 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:07 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/altera_mf.vhd -work altera_mf # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling entity LCELL # -- Compiling architecture BEHAVIOR of LCELL # -- Compiling package ALTERA_COMMON_CONVERSION # -- Compiling package body ALTERA_COMMON_CONVERSION # -- Loading package ALTERA_COMMON_CONVERSION # -- Compiling package ALTERA_MF_HINT_EVALUATION # -- Compiling package body ALTERA_MF_HINT_EVALUATION # -- Loading package ALTERA_MF_HINT_EVALUATION # -- Compiling package ALTERA_DEVICE_FAMILIES # -- Compiling package body ALTERA_DEVICE_FAMILIES # -- Loading package ALTERA_DEVICE_FAMILIES # -- Compiling package MF_pllpack # -- Compiling package body MF_pllpack # -- Loading package MF_pllpack # -- Compiling entity DFFP # -- Compiling architecture behave of DFFP # -- Compiling entity pll_iobuf # -- Compiling architecture BEHAVIOR of pll_iobuf # -- Compiling entity MF_m_cntr # -- Compiling architecture behave of MF_m_cntr # -- Compiling entity MF_n_cntr # -- Compiling architecture behave of MF_n_cntr # -- Compiling entity stx_scale_cntr # -- Compiling architecture behave of stx_scale_cntr # -- Compiling entity MF_pll_reg # -- Compiling architecture behave of MF_pll_reg # -- Loading package MF_pllpack # -- Loading entity MF_m_cntr # -- Loading entity MF_n_cntr # -- Loading entity stx_scale_cntr # -- Loading entity DFFP # -- Loading entity MF_pll_reg # -- Compiling entity MF_stratix_pll # -- Compiling architecture vital_pll of MF_stratix_pll # -- Compiling entity arm_m_cntr # -- Compiling architecture behave of arm_m_cntr # -- Compiling entity arm_n_cntr # -- Compiling architecture behave of arm_n_cntr # -- Compiling entity arm_scale_cntr # -- Compiling architecture behave of arm_scale_cntr # -- Loading entity arm_m_cntr # -- Loading entity arm_n_cntr # -- Loading entity arm_scale_cntr # -- Compiling entity MF_stratixii_pll # -- Compiling architecture vital_pll of MF_stratixii_pll # -- Loading package std_logic_arith # -- Loading package STD_LOGIC_UNSIGNED # -- Compiling entity MF_ttn_mn_cntr # -- Compiling architecture behave of MF_ttn_mn_cntr # -- Compiling entity MF_ttn_scale_cntr # -- Compiling architecture behave of MF_ttn_scale_cntr # -- Loading entity MF_ttn_mn_cntr # -- Loading entity MF_ttn_scale_cntr # -- Compiling entity MF_stratixiii_pll # -- Compiling architecture vital_pll of MF_stratixiii_pll # -- Compiling entity MF_cda_mn_cntr # -- Compiling architecture behave of MF_cda_mn_cntr # -- Compiling entity MF_cda_scale_cntr # -- Compiling architecture behave of MF_cda_scale_cntr # -- Loading entity MF_cda_mn_cntr # -- Loading entity MF_cda_scale_cntr # -- Compiling entity MF_cycloneiii_pll # -- Compiling architecture vital_pll of MF_cycloneiii_pll # -- Compiling entity MF_stingray_mn_cntr # -- Compiling architecture behave of MF_stingray_mn_cntr # -- Compiling entity MF_stingray_post_divider # -- Compiling architecture behave of MF_stingray_post_divider # -- Compiling entity MF_stingray_scale_cntr # -- Compiling architecture behave of MF_stingray_scale_cntr # -- Loading entity MF_stingray_mn_cntr # -- Loading entity MF_stingray_scale_cntr # -- Compiling entity MF_cycloneiiigl_pll # -- Compiling architecture vital_pll of MF_cycloneiiigl_pll # -- Loading package ALTERA_DEVICE_FAMILIES # -- Loading entity MF_stratix_pll # -- Loading entity MF_stratixii_pll # -- Loading entity MF_stratixiii_pll # -- Loading entity MF_cycloneiii_pll # -- Loading entity MF_cycloneiiigl_pll # -- Loading entity pll_iobuf # -- Compiling entity altpll # -- Compiling architecture behavior of altpll # -- Compiling entity altaccumulate # -- Compiling architecture behaviour of altaccumulate # -- Compiling entity altmult_accum # -- Compiling architecture behaviour of altmult_accum # -- Compiling entity altmult_add # -- Compiling architecture behaviour of altmult_add # -- Loading package ALTERA_COMMON_CONVERSION # -- Compiling entity altfp_mult # -- Compiling architecture behavior of altfp_mult # -- Compiling entity altsqrt # -- Compiling architecture behavior of altsqrt # -- Compiling entity altclklock # -- Compiling architecture behavior of altclklock # -- Compiling entity altddio_in # -- Compiling architecture behave of altddio_in # -- Compiling entity altddio_out # -- Compiling architecture behave of altddio_out # -- Loading entity altddio_in # -- Loading entity altddio_out # -- Compiling entity altddio_bidir # -- Compiling architecture struct of altddio_bidir # -- Compiling entity stratixii_lvds_rx # -- Compiling architecture behavior of stratixii_lvds_rx # -- Compiling entity flexible_lvds_rx # -- Compiling architecture behavior of flexible_lvds_rx # -- Compiling entity stratixiii_lvds_rx_dpa # -- Compiling architecture behavior of stratixiii_lvds_rx_dpa # -- Compiling entity stratixv_local_clk_divider # -- Compiling architecture behavior of stratixv_local_clk_divider # -- Loading entity stratixiii_lvds_rx_dpa # -- Loading entity stratixv_local_clk_divider # -- Compiling entity stratixiii_lvds_rx_channel # -- Compiling architecture behavior of stratixiii_lvds_rx_channel # -- Loading entity stratixiii_lvds_rx_channel # -- Compiling entity stratixiii_lvds_rx # -- Compiling architecture behavior of stratixiii_lvds_rx # -- Loading entity stratixii_lvds_rx # -- Loading entity flexible_lvds_rx # -- Loading entity stratixiii_lvds_rx # -- Compiling entity altlvds_rx # -- Compiling architecture behavior of altlvds_rx # -- Compiling entity stratix_tx_outclk # -- Compiling architecture behavior of stratix_tx_outclk # -- Compiling entity stratixii_tx_outclk # -- Compiling architecture behavior of stratixii_tx_outclk # -- Compiling entity flexible_lvds_tx # -- Compiling architecture behavior of flexible_lvds_tx # -- Loading entity stratix_tx_outclk # -- Loading entity stratixii_tx_outclk # -- Loading entity flexible_lvds_tx # -- Compiling entity altlvds_tx # -- Compiling architecture behavior of altlvds_tx # -- Compiling entity altdpram # -- Compiling architecture behavior of altdpram # -- Compiling entity altsyncram # -- Compiling architecture translated of altsyncram # -- Loading entity altsyncram # -- Loading package ALTERA_MF_HINT_EVALUATION # -- Compiling entity alt3pram # -- Compiling architecture behavior of alt3pram # -- Loading package altera_mf_components # -- Compiling entity parallel_add # -- Compiling architecture behaviour of parallel_add # -- Compiling entity SCFIFO # -- Compiling architecture behavior of SCFIFO # -- Compiling entity DCFIFO_DFFPIPE # -- Compiling architecture behavior of DCFIFO_DFFPIPE # -- Compiling entity DCFIFO_FEFIFO # -- Compiling architecture behavior of DCFIFO_FEFIFO # -- Loading entity DCFIFO_FEFIFO # -- Loading entity DCFIFO_DFFPIPE # -- Compiling entity DCFIFO_ASYNC # -- Compiling architecture behavior of DCFIFO_ASYNC # -- Compiling entity DCFIFO_SYNC # -- Compiling architecture behavior of DCFIFO_SYNC # -- Compiling entity DCFIFO_LOW_LATENCY # -- Compiling architecture behavior of DCFIFO_LOW_LATENCY # -- Loading entity DCFIFO_ASYNC # -- Loading entity DCFIFO_SYNC # -- Loading entity DCFIFO_LOW_LATENCY # -- Compiling entity DCFIFO_MIXED_WIDTHS # -- Compiling architecture behavior of DCFIFO_MIXED_WIDTHS # -- Loading entity DCFIFO_MIXED_WIDTHS # -- Compiling entity DCFIFO # -- Compiling architecture behavior of DCFIFO # -- Compiling entity altshift_taps # -- Compiling architecture behavioural of altshift_taps # -- Compiling entity A_GRAYCOUNTER # -- Compiling architecture behavior of A_GRAYCOUNTER # -- Compiling entity altsquare # -- Compiling architecture altsquare_syn of altsquare # -- Compiling entity altera_std_synchronizer # -- Compiling architecture behavioral of altera_std_synchronizer # -- Compiling entity altera_std_synchronizer_bundle # -- Compiling architecture behavioral of altera_std_synchronizer_bundle # -- Compiling entity alt_cal # -- Compiling architecture RTL of alt_cal # -- Compiling entity alt_cal_mm # -- Compiling architecture RTL of alt_cal_mm # -- Compiling entity alt_cal_c3gxb # -- Compiling architecture RTL of alt_cal_c3gxb # -- Compiling entity alt_cal_sv # -- Compiling architecture RTL of alt_cal_sv # -- Compiling entity alt_cal_av # -- Compiling architecture RTL of alt_cal_av # -- Compiling package alt_aeq_s4_func # -- Compiling package body alt_aeq_s4_func # -- Loading package alt_aeq_s4_func # -- Loading package alt_aeq_s4_func # -- Compiling entity alt_aeq_s4 # -- Compiling architecture trans of alt_aeq_s4 # -- Compiling package alt_eyemon_func # -- Compiling package body alt_eyemon_func # -- Loading package alt_eyemon_func # -- Loading package alt_eyemon_func # -- Compiling entity alt_eyemon # -- Compiling architecture trans of alt_eyemon # -- Compiling package alt_dfe_func # -- Compiling package body alt_dfe_func # -- Loading package alt_dfe_func # -- Loading package alt_dfe_func # -- Compiling entity alt_dfe # -- Compiling architecture trans of alt_dfe # -- Compiling package SLD_NODE # -- Compiling package body SLD_NODE # -- Loading package SLD_NODE # -- Loading package SLD_NODE # -- Compiling entity signal_gen # -- Compiling architecture simModel of signal_gen # -- Compiling entity jtag_tap_controller # -- Compiling architecture FSM of jtag_tap_controller # -- Compiling entity dummy_hub # -- Compiling architecture behavior of dummy_hub # -- Loading entity signal_gen # -- Loading entity jtag_tap_controller # -- Loading entity dummy_hub # -- Compiling entity sld_virtual_jtag # -- Compiling architecture structural of sld_virtual_jtag # -- Compiling entity sld_signaltap # -- Compiling architecture sim_sld_signaltap of sld_signaltap # -- Compiling entity altstratixii_oct # -- Compiling architecture sim_altstratixii_oct of altstratixii_oct # -- Compiling entity altparallel_flash_loader # -- Compiling architecture sim_altparallel_flash_loader of altparallel_flash_loader # -- Compiling entity altserial_flash_loader # -- Compiling architecture sim_altserial_flash_loader of altserial_flash_loader # -- Compiling entity alt_fault_injection # -- Compiling architecture sim_alt_fault_injection of alt_fault_injection # -- Compiling entity sld_virtual_jtag_basic # -- Compiling architecture sim_sld_virtual_jtag_basic of sld_virtual_jtag_basic # -- Compiling entity altsource_probe # -- Compiling architecture sim_altsource_probe of altsource_probe # End time: 09:01:09 on Jul 23,2018, Elapsed time: 0:00:02 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:09 on Jul 23,2018 # vlog -sv /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv -work altera_lnsim # # Top level modules: # End time: 09:01:10 on Jul 23,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:10 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/altera_lnsim_components.vhd -work altera_lnsim # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling package altera_lnsim_components # End time: 09:01:10 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:10 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/mentor/twentynm_atoms_ncrypt.v -work twentynm # # Top level modules: # End time: 09:01:27 on Jul 23,2018, Elapsed time: 0:00:17 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:27 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/twentynm_atoms.vhd -work twentynm # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Compiling package twentynm_atom_pack # -- Compiling package body twentynm_atom_pack # -- Loading package twentynm_atom_pack # -- Compiling package twentynm_pllpack # -- Compiling package body twentynm_pllpack # -- Loading package twentynm_pllpack # -- Loading package twentynm_atom_pack # -- Compiling entity twentynm_dffe # -- Compiling architecture behave of twentynm_dffe # -- Compiling entity twentynm_mux21 # -- Compiling architecture AltVITAL of twentynm_mux21 # -- Compiling entity twentynm_mux41 # -- Compiling architecture AltVITAL of twentynm_mux41 # -- Compiling entity twentynm_and1 # -- Compiling architecture AltVITAL of twentynm_and1 # -- Loading entity twentynm_and1 # -- Compiling entity twentynm_ff # -- Compiling architecture vital_lcell_ff of twentynm_ff # -- Compiling entity twentynm_lcell_comb # -- Compiling architecture vital_lcell_comb of twentynm_lcell_comb # -- Compiling entity twentynm_routing_wire # ** Warning: /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/twentynm_atoms.vhd(2123): (vcom-1288) VITAL timing generic "tpd_datainglitch_dataout" port specification "datainglitch" does not denote a port. # (1076.4 section 4.3.2.1.3) # -- Compiling architecture behave of twentynm_routing_wire # -- Loading package altera_lnsim_components # -- Compiling entity twentynm_ram_block # -- Compiling architecture block_arch of twentynm_ram_block # -- Loading package std_logic_arith # -- Loading package STD_LOGIC_UNSIGNED # -- Compiling entity twentynm_mlab_cell # -- Compiling architecture trans of twentynm_mlab_cell # -- Compiling entity twentynm_io_ibuf # -- Compiling architecture arch of twentynm_io_ibuf # -- Compiling entity twentynm_io_obuf # -- Compiling architecture arch of twentynm_io_obuf # -- Compiling entity twentynm_pseudo_diff_out # -- Compiling architecture arch of twentynm_pseudo_diff_out # -- Compiling entity twentynm_io_pad # -- Compiling architecture arch of twentynm_io_pad # -- Compiling entity twentynm_bias_logic # -- Compiling architecture vital_bias_logic of twentynm_bias_logic # -- Compiling entity twentynm_bias_generator # -- Compiling architecture vital_bias_generator of twentynm_bias_generator # -- Compiling entity twentynm_bias_block # -- Compiling architecture vital_bias_block of twentynm_bias_block # -- Compiling entity twentynm_clk_phase_select # -- Compiling architecture behavior of twentynm_clk_phase_select # -- Compiling entity twentynm_clkena # -- Compiling architecture behavior of twentynm_clkena # -- Compiling entity twentynm_clkselect # -- Compiling architecture behavior of twentynm_clkselect # -- Compiling entity twentynm_delay_chain # -- Compiling architecture behavior of twentynm_delay_chain # -- Compiling entity twentynm_dll_offset_ctrl # -- Compiling architecture behavior of twentynm_dll_offset_ctrl # -- Compiling entity twentynm_dll # -- Compiling architecture behavior of twentynm_dll # -- Compiling entity twentynm_dqs_config # -- Compiling architecture behavior of twentynm_dqs_config # -- Compiling entity twentynm_dqs_delay_chain # -- Compiling architecture behavior of twentynm_dqs_delay_chain # -- Compiling entity twentynm_dqs_enable_ctrl # -- Compiling architecture behavior of twentynm_dqs_enable_ctrl # -- Compiling entity twentynm_duty_cycle_adjustment # -- Compiling architecture behavior of twentynm_duty_cycle_adjustment # -- Compiling entity twentynm_half_rate_input # -- Compiling architecture behavior of twentynm_half_rate_input # -- Compiling entity twentynm_input_phase_alignment # -- Compiling architecture behavior of twentynm_input_phase_alignment # -- Compiling entity twentynm_io_clock_divider # -- Compiling architecture behavior of twentynm_io_clock_divider # -- Compiling entity twentynm_io_config # -- Compiling architecture behavior of twentynm_io_config # -- Compiling entity twentynm_ir_fifo_userdes # -- Compiling architecture behavior of twentynm_ir_fifo_userdes # -- Compiling entity twentynm_leveling_delay_chain # -- Compiling architecture behavior of twentynm_leveling_delay_chain # -- Compiling entity twentynm_lfifo # -- Compiling architecture behavior of twentynm_lfifo # -- Compiling entity twentynm_vfifo # -- Compiling architecture behavior of twentynm_vfifo # -- Compiling entity twentynm_mem_phy # -- Compiling architecture behavior of twentynm_mem_phy # -- Compiling entity twentynm_phy_clkbuf # -- Compiling architecture behavior of twentynm_phy_clkbuf # -- Compiling entity twentynm_read_fifo_read_clock_select # -- Compiling architecture behavior of twentynm_read_fifo_read_clock_select # -- Compiling entity twentynm_lvds_rx # -- Compiling architecture behavior of twentynm_lvds_rx # -- Compiling entity twentynm_lvds_tx # -- Compiling architecture behavior of twentynm_lvds_tx # -- Compiling entity twentynm_output_alignment # -- Compiling architecture behavior of twentynm_output_alignment # -- Compiling entity twentynm_termination_logic # -- Compiling architecture behavior of twentynm_termination_logic # -- Compiling entity twentynm_termination # -- Compiling architecture behavior of twentynm_termination # -- Compiling entity twentynm_asmiblock # -- Compiling architecture behavior of twentynm_asmiblock # -- Compiling entity twentynm_crcblock # -- Compiling architecture behavior of twentynm_crcblock # -- Compiling entity twentynm_opregblock # -- Compiling architecture behavior of twentynm_opregblock # -- Compiling entity twentynm_jtag # -- Compiling architecture behavior of twentynm_jtag # -- Compiling entity twentynm_jtagblock # -- Compiling architecture behavior of twentynm_jtagblock # -- Compiling entity twentynm_rublock # -- Compiling architecture behavior of twentynm_rublock # -- Compiling entity twentynm_tsdblock # -- Compiling architecture behavior of twentynm_tsdblock # -- Compiling entity twentynm_vsblock # -- Compiling architecture behavior of twentynm_vsblock # -- Compiling entity twentynm_read_fifo # -- Compiling architecture behavior of twentynm_read_fifo # -- Compiling entity twentynm_read_fifo_read_enable # -- Compiling architecture behavior of twentynm_read_fifo_read_enable # -- Compiling entity twentynm_fp_mac # -- Compiling architecture behavior of twentynm_fp_mac # -- Compiling entity twentynm_mac # -- Compiling architecture behavior of twentynm_mac # -- Compiling entity twentynm_serdes_dpa # -- Compiling architecture behavior of twentynm_serdes_dpa # -- Compiling entity twentynm_lvds_clock_tree # -- Compiling architecture behavior of twentynm_lvds_clock_tree # -- Compiling entity twentynm_oscillator # -- Compiling architecture behavior of twentynm_oscillator # -- Compiling entity twentynm_iopll # -- Compiling architecture behavior of twentynm_iopll # -- Compiling entity twentynm_ddio_out # -- Compiling architecture behavior of twentynm_ddio_out # -- Compiling entity twentynm_ddio_in # -- Compiling architecture behavior of twentynm_ddio_in # -- Compiling entity twentynm_io_serdes_dpa # -- Compiling architecture behavior of twentynm_io_serdes_dpa # -- Compiling entity twentynm_io_12_lane # -- Compiling architecture behavior of twentynm_io_12_lane # -- Compiling entity twentynm_tile_ctrl # -- Compiling architecture behavior of twentynm_tile_ctrl # -- Compiling entity twentynm_refclk_input # -- Compiling architecture behavior of twentynm_refclk_input # -- Compiling entity twentynm_io_aux # -- Compiling architecture behavior of twentynm_io_aux # End time: 09:01:27 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:27 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/twentynm_components.vhd -work twentynm # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Compiling package twentynm_components # End time: 09:01:28 on Jul 23,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:28 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/mentor/twentynm_hssi_atoms_ncrypt.v -work twentynm_hssi # # Top level modules: # End time: 09:01:37 on Jul 23,2018, Elapsed time: 0:00:09 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:37 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/twentynm_hssi_components.vhd -work twentynm_hssi # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling package TWENTYNM_HSSI_COMPONENTS # -- Compiling package body TWENTYNM_HSSI_COMPONENTS # -- Loading package TWENTYNM_HSSI_COMPONENTS # End time: 09:01:37 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:37 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/twentynm_hssi_atoms.vhd -work twentynm_hssi # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package TWENTYNM_HSSI_COMPONENTS # -- Compiling entity twentynm_atx_pll # -- Compiling architecture behavior of twentynm_atx_pll # -- Compiling entity twentynm_cmu_fpll_refclk_select # -- Compiling architecture behavior of twentynm_cmu_fpll_refclk_select # -- Compiling entity twentynm_cmu_fpll # -- Compiling architecture behavior of twentynm_cmu_fpll # -- Compiling entity twentynm_hssi_10g_rx_pcs # -- Compiling architecture behavior of twentynm_hssi_10g_rx_pcs # -- Compiling entity twentynm_hssi_10g_tx_pcs # -- Compiling architecture behavior of twentynm_hssi_10g_tx_pcs # -- Compiling entity twentynm_hssi_8g_rx_pcs # -- Compiling architecture behavior of twentynm_hssi_8g_rx_pcs # -- Compiling entity twentynm_hssi_8g_tx_pcs # -- Compiling architecture behavior of twentynm_hssi_8g_tx_pcs # -- Compiling entity twentynm_hssi_common_pcs_pma_interface # -- Compiling architecture behavior of twentynm_hssi_common_pcs_pma_interface # -- Compiling entity twentynm_hssi_common_pld_pcs_interface # -- Compiling architecture behavior of twentynm_hssi_common_pld_pcs_interface # -- Compiling entity twentynm_hssi_fifo_rx_pcs # -- Compiling architecture behavior of twentynm_hssi_fifo_rx_pcs # -- Compiling entity twentynm_hssi_fifo_tx_pcs # -- Compiling architecture behavior of twentynm_hssi_fifo_tx_pcs # -- Compiling entity twentynm_hssi_gen3_rx_pcs # -- Compiling architecture behavior of twentynm_hssi_gen3_rx_pcs # -- Compiling entity twentynm_hssi_gen3_tx_pcs # -- Compiling architecture behavior of twentynm_hssi_gen3_tx_pcs # -- Compiling entity twentynm_hssi_gen3_x8_pcie_hip # -- Compiling architecture behavior of twentynm_hssi_gen3_x8_pcie_hip # -- Compiling entity twentynm_hssi_krfec_rx_pcs # -- Compiling architecture behavior of twentynm_hssi_krfec_rx_pcs # -- Compiling entity twentynm_hssi_krfec_tx_pcs # -- Compiling architecture behavior of twentynm_hssi_krfec_tx_pcs # -- Compiling entity twentynm_hssi_pipe_gen1_2 # -- Compiling architecture behavior of twentynm_hssi_pipe_gen1_2 # -- Compiling entity twentynm_hssi_pipe_gen3 # -- Compiling architecture behavior of twentynm_hssi_pipe_gen3 # -- Compiling entity twentynm_hssi_pma_adaptation # -- Compiling architecture behavior of twentynm_hssi_pma_adaptation # -- Compiling entity twentynm_hssi_pma_aux # -- Compiling architecture behavior of twentynm_hssi_pma_aux # -- Compiling entity twentynm_hssi_pma_cdr_refclk_select_mux # -- Compiling architecture behavior of twentynm_hssi_pma_cdr_refclk_select_mux # -- Compiling entity twentynm_hssi_pma_cgb_master # -- Compiling architecture behavior of twentynm_hssi_pma_cgb_master # -- Compiling entity twentynm_hssi_pma_channel_pll # -- Compiling architecture behavior of twentynm_hssi_pma_channel_pll # -- Compiling entity twentynm_hssi_pma_lc_refclk_select_mux # -- Compiling architecture behavior of twentynm_hssi_pma_lc_refclk_select_mux # -- Compiling entity twentynm_hssi_pma_rx_buf # -- Compiling architecture behavior of twentynm_hssi_pma_rx_buf # -- Compiling entity twentynm_hssi_pma_rx_deser # -- Compiling architecture behavior of twentynm_hssi_pma_rx_deser # -- Compiling entity twentynm_hssi_pma_rx_dfe # -- Compiling architecture behavior of twentynm_hssi_pma_rx_dfe # -- Compiling entity twentynm_hssi_pma_rx_odi # -- Compiling architecture behavior of twentynm_hssi_pma_rx_odi # -- Compiling entity twentynm_hssi_pma_rx_sd # -- Compiling architecture behavior of twentynm_hssi_pma_rx_sd # -- Compiling entity twentynm_hssi_pma_tx_buf # -- Compiling architecture behavior of twentynm_hssi_pma_tx_buf # -- Compiling entity twentynm_hssi_pma_tx_cgb # -- Compiling architecture behavior of twentynm_hssi_pma_tx_cgb # -- Compiling entity twentynm_hssi_pma_tx_ser # -- Compiling architecture behavior of twentynm_hssi_pma_tx_ser # -- Compiling entity twentynm_hssi_pma_uc # -- Compiling architecture behavior of twentynm_hssi_pma_uc # -- Compiling entity twentynm_hssi_refclk_divider # -- Compiling architecture behavior of twentynm_hssi_refclk_divider # -- Compiling entity twentynm_hssi_rx_pcs_pma_interface # -- Compiling architecture behavior of twentynm_hssi_rx_pcs_pma_interface # -- Compiling entity twentynm_hssi_rx_pld_pcs_interface # -- Compiling architecture behavior of twentynm_hssi_rx_pld_pcs_interface # -- Compiling entity twentynm_hssi_tx_pcs_pma_interface # -- Compiling architecture behavior of twentynm_hssi_tx_pcs_pma_interface # -- Compiling entity twentynm_hssi_tx_pld_pcs_interface # -- Compiling architecture behavior of twentynm_hssi_tx_pld_pcs_interface # -- Compiling entity twentynm_hssi_avmm_if # -- Compiling architecture behavior of twentynm_hssi_avmm_if # End time: 09:01:38 on Jul 23,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:38 on Jul 23,2018 # vlog /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/mentor/twentynm_hip_atoms_ncrypt.v -work twentynm_hip # # Top level modules: # End time: 09:01:45 on Jul 23,2018, Elapsed time: 0:00:07 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:45 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/twentynm_hip_components.vhd -work twentynm_hip # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling package TWENTYNM_HIP_COMPONENTS # -- Compiling package body TWENTYNM_HIP_COMPONENTS # -- Loading package TWENTYNM_HIP_COMPONENTS # End time: 09:01:45 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:45 on Jul 23,2018 # vcom /D/intelFPGA_pro/17.1/quartus/eda/sim_lib/twentynm_hip_atoms.vhd -work twentynm_hip # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package TWENTYNM_HIP_COMPONENTS # -- Compiling entity twentynm_hssi_gen3_x8_pcie_hip # -- Compiling architecture behavior of twentynm_hssi_gen3_x8_pcie_hip # End time: 09:01:45 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # [exec] com # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:45 on Jul 23,2018 # vlog -sv tb/sim/../../ip/tb/cat_done/avalon_concatenate_singlebit_conduits_10/sim/cat_done_avalon_concatenate_singlebit_conduits_10_bjzeuhq.sv -work avalon_concatenate_singlebit_conduits_10 # -- Compiling module cat_done_avalon_concatenate_singlebit_conduits_10_bjzeuhq # # Top level modules: # cat_done_avalon_concatenate_singlebit_conduits_10_bjzeuhq # End time: 09:01:45 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:45 on Jul 23,2018 # vlog tb/sim/../../ip/tb/cat_done/sim/cat_done.v -work cat_done # -- Compiling module cat_done # # Top level modules: # cat_done # End time: 09:01:45 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:45 on Jul 23,2018 # vlog -sv tb/sim/../../ip/tb/count_cfan/avalon_conduit_fanout_10/sim/count_cfan_avalon_conduit_fanout_10_wcpjniy.sv -work avalon_conduit_fanout_10 # -- Compiling module count_cfan_avalon_conduit_fanout_10_wcpjniy # # Top level modules: # count_cfan_avalon_conduit_fanout_10_wcpjniy # End time: 09:01:45 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:45 on Jul 23,2018 # vlog tb/sim/../../ip/tb/count_cfan/sim/count_cfan.v -work count_cfan # -- Compiling module count_cfan # # Top level modules: # count_cfan # End time: 09:01:45 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:45 on Jul 23,2018 # vlog -sv tb/sim/../../ip/tb/dpic_count/hls_sim_component_dpi_controller_10/sim/hls_sim_stream_sink_dpi_bfm.sv -work hls_sim_component_dpi_controller_10 # -- Compiling module hls_sim_stream_sink_dpi_bfm # # Top level modules: # hls_sim_stream_sink_dpi_bfm # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog -sv tb/sim/../../ip/tb/dpic_count/hls_sim_component_dpi_controller_10/sim/hls_sim_stream_source_dpi_bfm.sv -work hls_sim_component_dpi_controller_10 # -- Compiling module hls_sim_stream_source_dpi_bfm # # Top level modules: # hls_sim_stream_source_dpi_bfm # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog -sv tb/sim/../../ip/tb/dpic_count/hls_sim_component_dpi_controller_10/sim/hls_sim_component_dpi_controller.sv -work hls_sim_component_dpi_controller_10 # -- Compiling module hls_sim_component_dpi_controller # # Top level modules: # hls_sim_component_dpi_controller # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog tb/sim/../../ip/tb/dpic_count/sim/dpic_count.v -work dpic_count # -- Compiling module dpic_count # # Top level modules: # dpic_count # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog -sv tb/sim/../../ip/tb/count_en_cfan/avalon_conduit_fanout_10/sim/count_en_cfan_avalon_conduit_fanout_10_wcpjniy.sv -work avalon_conduit_fanout_10 # -- Compiling module count_en_cfan_avalon_conduit_fanout_10_wcpjniy # # Top level modules: # count_en_cfan_avalon_conduit_fanout_10_wcpjniy # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog tb/sim/../../ip/tb/count_en_cfan/sim/count_en_cfan.v -work count_en_cfan # -- Compiling module count_en_cfan # # Top level modules: # count_en_cfan # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog -sv tb/sim/../../ip/tb/clock_reset/hls_sim_clock_reset_10/sim/hls_sim_clock_reset.sv -work hls_sim_clock_reset_10 # -- Compiling module hls_sim_clock_reset # # Top level modules: # hls_sim_clock_reset # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog tb/sim/../../ip/tb/clock_reset/sim/clock_reset.v -work clock_reset # -- Compiling module clock_reset # # Top level modules: # clock_reset # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog -sv tb/sim/../../ip/tb/cat_cwfsw/avalon_concatenate_singlebit_conduits_10/sim/cat_cwfsw_avalon_concatenate_singlebit_conduits_10_bjzeuhq.sv -work avalon_concatenate_singlebit_conduits_10 # -- Compiling module cat_cwfsw_avalon_concatenate_singlebit_conduits_10_bjzeuhq # # Top level modules: # cat_cwfsw_avalon_concatenate_singlebit_conduits_10_bjzeuhq # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog tb/sim/../../ip/tb/cat_cwfsw/sim/cat_cwfsw.v -work cat_cwfsw # -- Compiling module cat_cwfsw # # Top level modules: # cat_cwfsw # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog -sv tb/sim/../../ip/tb/sp_cstart/avalon_split_multibit_conduit_10/sim/sp_cstart_avalon_split_multibit_conduit_10_dlmo3na.sv -work avalon_split_multibit_conduit_10 # -- Compiling module sp_cstart_avalon_split_multibit_conduit_10_dlmo3na # # Top level modules: # sp_cstart_avalon_split_multibit_conduit_10_dlmo3na # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog tb/sim/../../ip/tb/sp_cstart/sim/sp_cstart.v -work sp_cstart # -- Compiling module sp_cstart # # Top level modules: # sp_cstart # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog -sv tb/sim/../../ip/tb/main_dpi_controller/hls_sim_main_dpi_controller_10/sim/hls_sim_main_dpi_controller.sv -work hls_sim_main_dpi_controller_10 # -- Compiling module hls_sim_main_dpi_controller # # Top level modules: # hls_sim_main_dpi_controller # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog tb/sim/../../ip/tb/main_dpi_controller/sim/main_dpi_controller.v -work main_dpi_controller # -- Compiling module main_dpi_controller # # Top level modules: # main_dpi_controller # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/dspba_library_package.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling package dspba_library_package # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/dspba_library.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package dspba_library_package # -- Compiling entity dspba_delay # -- Compiling architecture delay of dspba_delay # -- Loading package NUMERIC_STD # -- Compiling entity dspba_sync_reg # -- Compiling architecture sync_reg of dspba_sync_reg # -- Compiling entity dspba_pipe # -- Compiling architecture rtl of dspba_pipe # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_data_fifo.v -work count_internal_10 # -- Compiling module acl_data_fifo # # Top level modules: # --none-- # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_fifo.v -work count_internal_10 # -- Compiling module acl_fifo # # Top level modules: # acl_fifo # End time: 09:01:46 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:46 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_ll_fifo.v -work count_internal_10 # -- Compiling module acl_ll_fifo # # Top level modules: # acl_ll_fifo # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_ll_ram_fifo.v -work count_internal_10 # -- Compiling module acl_ll_ram_fifo # # Top level modules: # acl_ll_ram_fifo # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_valid_fifo_counter.v -work count_internal_10 # -- Compiling module acl_valid_fifo_counter # # Top level modules: # acl_valid_fifo_counter # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_dspba_valid_fifo_counter.v -work count_internal_10 # -- Compiling module acl_dspba_valid_fifo_counter # # Top level modules: # acl_dspba_valid_fifo_counter # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_staging_reg.v -work count_internal_10 # -- Compiling module acl_staging_reg # # Top level modules: # acl_staging_reg # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/hld_fifo.sv -work count_internal_10 # -- Compiling module hld_fifo # -- Compiling module earliness_delay # # Top level modules: # hld_fifo # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/hld_fifo_zero_width.sv -work count_internal_10 # -- Compiling module hld_fifo_zero_width # # Top level modules: # hld_fifo_zero_width # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_high_speed_fifo.sv -work count_internal_10 # -- Compiling module acl_high_speed_fifo # -- Compiling module scfifo_to_acl_high_speed_fifo # # Top level modules: # scfifo_to_acl_high_speed_fifo # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_low_latency_fifo.sv -work count_internal_10 # -- Compiling module acl_low_latency_fifo # ** Warning: tb/sim/../../../components/count/count/count_internal_10/sim/acl_low_latency_fifo.sv(222): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: tb/sim/../../../components/count/count/count_internal_10/sim/acl_low_latency_fifo.sv(223): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: tb/sim/../../../components/count/count/count_internal_10/sim/acl_low_latency_fifo.sv(223): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: tb/sim/../../../components/count/count/count_internal_10/sim/acl_low_latency_fifo.sv(224): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: tb/sim/../../../components/count/count/count_internal_10/sim/acl_low_latency_fifo.sv(226): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # # Top level modules: # acl_low_latency_fifo # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 5 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_zero_latency_fifo.sv -work count_internal_10 # -- Compiling module acl_zero_latency_fifo # # Top level modules: # acl_zero_latency_fifo # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_fanout_pipeline.sv -work count_internal_10 # -- Compiling module acl_fanout_pipeline # # Top level modules: # acl_fanout_pipeline # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_std_synchronizer_nocut.v -work count_internal_10 # -- Compiling module acl_std_synchronizer_nocut # # Top level modules: # acl_std_synchronizer_nocut # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_tessellated_incr_decr_threshold.sv -work count_internal_10 # -- Compiling module acl_tessellated_incr_decr_threshold # -- Compiling module acl_tessellated_incr_decr # # Top level modules: # acl_tessellated_incr_decr_threshold # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_tessellated_incr_lookahead.sv -work count_internal_10 # -- Compiling module acl_tessellated_incr_lookahead # # Top level modules: # acl_tessellated_incr_lookahead # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_reset_handler.sv -work count_internal_10 # -- Compiling module acl_reset_handler # -- Compiling module acl_reset_fanout_pipeline_with_synchronizer_and_pulse_extender # -- Compiling module acl_reset_pulse_extender # # Top level modules: # acl_reset_handler # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_lfsr.sv -work count_internal_10 # -- Compiling module acl_lfsr # -- Compiling module galois_lfsr # -- Compiling module fibonacci_lfsr # # Top level modules: # acl_lfsr # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_pop.v -work count_internal_10 # -- Compiling module acl_pop # # Top level modules: # acl_pop # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_push.v -work count_internal_10 # -- Compiling module acl_push # # Top level modules: # acl_push # End time: 09:01:47 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:47 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_token_fifo_counter.v -work count_internal_10 # -- Compiling module acl_token_fifo_counter # # Top level modules: # acl_token_fifo_counter # End time: 09:01:48 on Jul 23,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:48 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_pipeline.v -work count_internal_10 # -- Compiling module acl_pipeline # # Top level modules: # acl_pipeline # End time: 09:01:48 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:48 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_dspba_buffer.v -work count_internal_10 # -- Compiling module acl_dspba_buffer # # Top level modules: # acl_dspba_buffer # End time: 09:01:48 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:48 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_enable_sink.v -work count_internal_10 # -- Compiling module acl_enable_sink # # Top level modules: # acl_enable_sink # End time: 09:01:48 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:48 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/st_top.v -work count_internal_10 # -- Compiling module init_reg # ** Warning: tb/sim/../../../components/count/count/count_internal_10/sim/st_top.v(33): (vlog-2600) [RDGN] - Redundant digits in numeric literal. # -- Compiling module st_read # -- Compiling module st_write # # Top level modules: # st_read # st_write # End time: 09:01:48 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:48 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/acl_reset_wire.v -work count_internal_10 # -- Compiling module acl_reset_wire # # Top level modules: # acl_reset_wire # End time: 09:01:48 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:48 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/count_function_wrapper.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity count_function_wrapper # -- Compiling architecture normal of count_function_wrapper # End time: 09:01:48 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:48 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/count_function.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity count_function # -- Compiling architecture normal of count_function # End time: 09:01:48 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:48 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/bb_count_B0_runOnce.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity bb_count_B0_runOnce # -- Compiling architecture normal of bb_count_B0_runOnce # End time: 09:01:48 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:48 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/bb_count_B0_runOnce_stall_region.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity bb_count_B0_runOnce_stall_region # -- Compiling architecture normal of bb_count_B0_runOnce_stall_region # End time: 09:01:48 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:48 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/count_B0_runOnce_merge_reg.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity count_B0_runOnce_merge_reg # -- Compiling architecture normal of count_B0_runOnce_merge_reg # End time: 09:01:48 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:48 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_acl_pop_i1_wt_limpop_count0.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_acl_pop_i1_wt_limpop_count0 # -- Compiling architecture normal of i_acl_pop_i1_wt_limpop_count0 # End time: 09:01:49 on Jul 23,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:49 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_acl_pop_i1_wt_limpop_count_reg.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_acl_pop_i1_wt_limpop_count_reg # -- Compiling architecture normal of i_acl_pop_i1_wt_limpop_count_reg # End time: 09:01:49 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:49 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_acl_push_i1_wt_limpush_count2.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_acl_push_i1_wt_limpush_count2 # -- Compiling architecture normal of i_acl_push_i1_wt_limpush_count2 # End time: 09:01:49 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:49 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_acl_push_i1_wt_limpush_count_reg.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_acl_push_i1_wt_limpush_count_reg # -- Compiling architecture normal of i_acl_push_i1_wt_limpush_count_reg # End time: 09:01:49 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:49 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/count_B0_runOnce_branch.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity count_B0_runOnce_branch # -- Compiling architecture normal of count_B0_runOnce_branch # End time: 09:01:49 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:49 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/count_B0_runOnce_merge.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity count_B0_runOnce_merge # -- Compiling architecture normal of count_B0_runOnce_merge # End time: 09:01:49 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:49 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/bb_count_B1_start.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity bb_count_B1_start # -- Compiling architecture normal of bb_count_B1_start # End time: 09:01:49 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:49 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/bb_count_B1_start_stall_region.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity bb_count_B1_start_stall_region # -- Compiling architecture normal of bb_count_B1_start_stall_region # End time: 09:01:49 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:49 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/count_B1_start_merge_reg.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity count_B1_start_merge_reg # -- Compiling architecture normal of count_B1_start_merge_reg # End time: 09:01:49 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:49 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_sfc_c0_wt_entry_count_c0_enter_count.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_sfc_c0_wt_entry_count_c0_enter_count # -- Compiling architecture normal of i_sfc_c0_wt_entry_count_c0_enter_count # End time: 09:01:50 on Jul 23,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:50 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_acl_sfc_exit_c0_wt_entry_count_c0_exit_count10.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_acl_sfc_exit_c0_wt_entry_count_c0_exit_count10 # -- Compiling architecture normal of i_acl_sfc_exit_c0_wt_entry_count_c0_exit_count10 # End time: 09:01:50 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:50 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_sfc_logic_c0_wt_entry_count_c0_enter_count4.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_sfc_logic_c0_wt_entry_count_c0_enter_count4 # -- Compiling architecture normal of i_sfc_logic_c0_wt_entry_count_c0_enter_count4 # End time: 09:01:50 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:50 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_acl_pipeline_keep_going_count6.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_acl_pipeline_keep_going_count6 # -- Compiling architecture normal of i_acl_pipeline_keep_going_count6 # End time: 09:01:50 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:50 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_acl_push_i1_notexitcond_count8.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_acl_push_i1_notexitcond_count8 # -- Compiling architecture normal of i_acl_push_i1_notexitcond_count8 # End time: 09:01:50 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:50 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_sfc_c1_wt_entry_count_c1_enter_count.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_sfc_c1_wt_entry_count_c1_enter_count # -- Compiling architecture normal of i_sfc_c1_wt_entry_count_c1_enter_count # End time: 09:01:50 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:50 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_acl_sfc_exit_c1_wt_entry_count_c1_exit_count19.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_acl_sfc_exit_c1_wt_entry_count_c1_exit_count19 # -- Compiling architecture normal of i_acl_sfc_exit_c1_wt_entry_count_c1_exit_count19 # End time: 09:01:50 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:50 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_sfc_logic_c1_wt_entry_count_c1_enter_count13.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_sfc_logic_c1_wt_entry_count_c1_enter_count13 # -- Compiling architecture normal of i_sfc_logic_c1_wt_entry_count_c1_enter_count13 # End time: 09:01:50 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:51 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_acl_pop_i32_zz5counte3cnt_addr_0_pop3_count15.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_acl_pop_i32_zz5counte3cnt_addr_0_pop3_count15 # -- Compiling architecture normal of i_acl_pop_i32_zz5counte3cnt_addr_0_pop3_count15 # End time: 09:01:51 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:51 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_acl_push_i32_zz5counte3cnt_addr_0_push3_count17.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_acl_push_i32_zz5counte3cnt_addr_0_push3_count17 # -- Compiling architecture normal of i_acl_push_i32_zz5counte3cnt_addr_0_push3_count17 # End time: 09:01:51 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:51 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_iord_bl_do_unnamed_count1_count12.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_iord_bl_do_unnamed_count1_count12 # -- Compiling architecture normal of i_iord_bl_do_unnamed_count1_count12 # End time: 09:01:51 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:51 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_iowr_bl_return_unnamed_count2_count21.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_iowr_bl_return_unnamed_count2_count21 # -- Compiling architecture normal of i_iowr_bl_return_unnamed_count2_count21 # End time: 09:01:51 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:51 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/count_B1_start_branch.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity count_B1_start_branch # -- Compiling architecture normal of count_B1_start_branch # End time: 09:01:51 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:51 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/count_B1_start_merge.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity count_B1_start_merge # -- Compiling architecture normal of count_B1_start_merge # End time: 09:01:51 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:51 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_acl_pipeline_keep_going_count_sr.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_acl_pipeline_keep_going_count_sr # -- Compiling architecture normal of i_acl_pipeline_keep_going_count_sr # End time: 09:01:51 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:51 on Jul 23,2018 # vcom tb/sim/../../../components/count/count/count_internal_10/sim/i_acl_pipeline_keep_going_count_valid_fifo.vhd -work count_internal_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_library_package # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Loading package LPM_COMPONENTS # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package twentynm_atom_pack # -- Loading package twentynm_components # -- Compiling entity i_acl_pipeline_keep_going_count_valid_fifo # -- Compiling architecture normal of i_acl_pipeline_keep_going_count_valid_fifo # End time: 09:01:52 on Jul 23,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:52 on Jul 23,2018 # vlog -sv tb/sim/../../../components/count/count/count_internal_10/sim/count_internal.v -work count_internal_10 # -- Compiling module count_internal # # Top level modules: # count_internal # End time: 09:01:52 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:52 on Jul 23,2018 # vlog tb/sim/../../../components/count/count/sim/count.v -work count # -- Compiling module count # # Top level modules: # count # End time: 09:01:52 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:52 on Jul 23,2018 # vlog -sv tb/sim/../altera_irq_mapper_171/sim/tb_altera_irq_mapper_171_e3f7koy.sv -work altera_irq_mapper_171 # -- Compiling module tb_altera_irq_mapper_171_e3f7koy # # Top level modules: # tb_altera_irq_mapper_171_e3f7koy # End time: 09:01:52 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 # Start time: 09:01:52 on Jul 23,2018 # vlog tb/sim/tb.v -work tb # -- Compiling module tb # # Top level modules: # tb # End time: 09:01:52 on Jul 23,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # [exec] elab # vsim -t ps "+nowarnTFMPC" -L work -L work_lib -L avalon_concatenate_singlebit_conduits_10 -L cat_done -L avalon_conduit_fanout_10 -L count_cfan -L hls_sim_component_dpi_controller_10 -L dpic_count -L count_en_cfan -L hls_sim_clock_reset_10 -L clock_reset -L cat_cwfsw -L avalon_split_multibit_conduit_10 -L sp_cstart -L hls_sim_main_dpi_controller_10 -L main_dpi_controller -L count_internal_10 -L count -L altera_irq_mapper_171 -L tb -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L twentynm_ver -L twentynm_hssi_ver -L twentynm_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L twentynm -L twentynm_hssi -L twentynm_hip tb.tb # Start time: 09:00:24 on Jul 23,2018 # Loading /tmp/tempuser11@shark.perc.com_dpi_7111/linuxpe_gcc-4.4.7/export_tramp.so # Loading tb.tb # Loading clock_reset.clock_reset # Loading sv_std.std # Loading hls_sim_clock_reset_10.hls_sim_clock_reset # Loading dpic_count.dpic_count # Loading hls_sim_component_dpi_controller_10.hls_sim_component_dpi_controller # Loading hls_sim_component_dpi_controller_10.hls_sim_stream_source_dpi_bfm # Loading cat_done.cat_done # Loading avalon_concatenate_singlebit_conduits_10.cat_done_avalon_concatenate_singlebit_conduits_10_bjzeuhq # Loading cat_cwfsw.cat_cwfsw # Loading avalon_concatenate_singlebit_conduits_10.cat_cwfsw_avalon_concatenate_singlebit_conduits_10_bjzeuhq # Loading count_cfan.count_cfan # Loading avalon_conduit_fanout_10.count_cfan_avalon_conduit_fanout_10_wcpjniy # Loading count_en_cfan.count_en_cfan # Loading avalon_conduit_fanout_10.count_en_cfan_avalon_conduit_fanout_10_wcpjniy # Loading count.count # Loading count_internal_10.count_internal # Loading main_dpi_controller.main_dpi_controller # Loading hls_sim_main_dpi_controller_10.hls_sim_main_dpi_controller # Loading sp_cstart.sp_cstart # Loading avalon_split_multibit_conduit_10.sp_cstart_avalon_split_multibit_conduit_10_dlmo3na # Loading altera_irq_mapper_171.tb_altera_irq_mapper_171_e3f7koy # Loading hls_sim_component_dpi_controller_10.hls_sim_stream_sink_dpi_bfm # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading ieee.math_real(body) # Loading count_internal_10.dspba_library_package # Loading altera_mf.altera_mf_components # Loading altera_lnsim.altera_lnsim_components # Loading lpm.lpm_components # Loading ieee.vital_timing(body) # Loading ieee.vital_primitives(body) # Loading twentynm.twentynm_atom_pack(body) # Loading twentynm.twentynm_components # Loading count_internal_10.count_function_wrapper(normal) # Loading count_internal_10.count_function(normal) # Loading count_internal_10.i_acl_pipeline_keep_going_count_valid_fifo(normal) # Loading count_internal_10.acl_data_fifo # Loading count_internal_10.i_acl_pipeline_keep_going_count_sr(normal) # Loading count_internal_10.bb_count_b1_start(normal) # Loading count_internal_10.count_b1_start_branch(normal) # Loading count_internal_10.count_b1_start_merge(normal) # Loading count_internal_10.bb_count_b1_start_stall_region(normal) # Loading count_internal_10.i_sfc_c1_wt_entry_count_c1_enter_count(normal) # Loading count_internal_10.i_sfc_logic_c1_wt_entry_count_c1_enter_count13(normal) # Loading count_internal_10.i_acl_push_i32_zz5counte3cnt_addr_0_push3_count17(normal) # Loading count_internal_10.acl_push # Loading count_internal_10.i_acl_pop_i32_zz5counte3cnt_addr_0_pop3_count15(normal) # Loading count_internal_10.acl_pop # Loading count_internal_10.i_acl_sfc_exit_c1_wt_entry_count_c1_exit_count19(normal) # Loading count_internal_10.acl_enable_sink # Loading count_internal_10.i_sfc_c0_wt_entry_count_c0_enter_count(normal) # Loading count_internal_10.i_sfc_logic_c0_wt_entry_count_c0_enter_count4(normal) # Loading count_internal_10.i_acl_pipeline_keep_going_count6(normal) # Loading count_internal_10.acl_pipeline # Loading count_internal_10.acl_staging_reg # Loading count_internal_10.acl_dspba_buffer # Loading count_internal_10.i_acl_push_i1_notexitcond_count8(normal) # Loading count_internal_10.i_acl_sfc_exit_c0_wt_entry_count_c0_exit_count10(normal) # Loading count_internal_10.count_b1_start_merge_reg(normal) # Loading count_internal_10.i_iowr_bl_return_unnamed_count2_count21(normal) # Loading count_internal_10.st_write # Loading count_internal_10.i_iord_bl_do_unnamed_count1_count12(normal) # Loading count_internal_10.st_read # Loading count_internal_10.bb_count_b0_runonce(normal) # Loading count_internal_10.count_b0_runonce_branch(normal) # Loading count_internal_10.bb_count_b0_runonce_stall_region(normal) # Loading count_internal_10.count_b0_runonce_merge_reg(normal) # Loading count_internal_10.i_acl_push_i1_wt_limpush_count2(normal) # Loading count_internal_10.acl_token_fifo_counter # Loading count_internal_10.i_acl_push_i1_wt_limpush_count_reg(normal) # Loading count_internal_10.i_acl_pop_i1_wt_limpop_count0(normal) # Loading count_internal_10.i_acl_pop_i1_wt_limpop_count_reg(normal) # Loading count_internal_10.count_b0_runonce_merge(normal) # Loading count_internal_10.acl_reset_wire # ** Warning: (vsim-3015) tb/sim/../../../components/count/count/count_internal_10/sim/acl_push.v(151): [PCDPC] - Port size (1) does not match connection size (8) for port 'data_out'. The port definition is at: tb/sim/../../../components/count/count/count_internal_10/sim/acl_token_fifo_counter.v(38). # Time: 0 ps Iteration: 0 Instance: /tb/count_inst/count_internal_inst/count_internal/thecount_function/thebb_count_B0_runOnce/thebb_count_B0_runOnce_stall_region/thei_acl_push_i1_wt_limpush_count/thei_acl_push_i1_wt_limpush_count3/genblk1/genblk2/fifo File: tb/sim/../../../components/count/count/count_internal_10/sim/acl_token_fifo_counter.v # Compiling /tmp/tempuser11@shark.perc.com_dpi_7111/linuxpe_gcc-4.7.4/exportwrapper.c # Compiling /tmp/tempuser11@shark.perc.com_dpi_7111/linuxpe_gcc-4.4.7/exportwrapper.c # Loading /tmp/tempuser11@shark.perc.com_dpi_7111/linuxpe_gcc-4.4.7/vsim_auto_compile.so # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_dbgs' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/clock_reset_inst/clock_reset File: tb/sim/../../ip/tb/clock_reset/hls_sim_clock_reset_10/sim/hls_sim_clock_reset.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_dbgs' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/clock_reset_inst/clock_reset File: tb/sim/../../ip/tb/clock_reset/hls_sim_clock_reset_10/sim/hls_sim_clock_reset.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_register_component_invocation_info' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/component_dpi_controller_count_inst/dpic_count File: tb/sim/../../ip/tb/dpic_count/hls_sim_component_dpi_controller_10/sim/hls_sim_component_dpi_controller.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_dbgs' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/clock_reset_inst/clock_reset File: tb/sim/../../ip/tb/clock_reset/hls_sim_clock_reset_10/sim/hls_sim_clock_reset.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_get_stream_obj_ptr_for_component_interface' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/component_dpi_controller_count_inst/dpic_count/implicit_input_stream File: tb/sim/../../ip/tb/dpic_count/hls_sim_component_dpi_controller_10/sim/hls_sim_stream_source_dpi_bfm.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_stream_front' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/component_dpi_controller_count_inst/dpic_count/implicit_input_stream File: tb/sim/../../ip/tb/dpic_count/hls_sim_component_dpi_controller_10/sim/hls_sim_stream_source_dpi_bfm.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_stream_read' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/component_dpi_controller_count_inst/dpic_count/implicit_input_stream File: tb/sim/../../ip/tb/dpic_count/hls_sim_component_dpi_controller_10/sim/hls_sim_stream_source_dpi_bfm.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_register_stream_data_rate_info' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/component_dpi_controller_count_inst/dpic_count/implicit_input_stream File: tb/sim/../../ip/tb/dpic_count/hls_sim_component_dpi_controller_10/sim/hls_sim_stream_source_dpi_bfm.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_get_stream_obj_ptr_for_component_interface' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/component_dpi_controller_count_inst/dpic_count/implicit_input_stream File: tb/sim/../../ip/tb/dpic_count/hls_sim_component_dpi_controller_10/sim/hls_sim_stream_source_dpi_bfm.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_stream_ready' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/component_dpi_controller_count_inst/dpic_count/genblk1/implicit_output_stream File: tb/sim/../../ip/tb/dpic_count/hls_sim_component_dpi_controller_10/sim/hls_sim_stream_sink_dpi_bfm.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_stream_write' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/component_dpi_controller_count_inst/dpic_count/genblk1/implicit_output_stream File: tb/sim/../../ip/tb/dpic_count/hls_sim_component_dpi_controller_10/sim/hls_sim_stream_sink_dpi_bfm.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_dbgs' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/clock_reset_inst/clock_reset File: tb/sim/../../ip/tb/clock_reset/hls_sim_clock_reset_10/sim/hls_sim_clock_reset.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_register_stream_data_rate_info' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/component_dpi_controller_count_inst/dpic_count/implicit_input_stream File: tb/sim/../../ip/tb/dpic_count/hls_sim_component_dpi_controller_10/sim/hls_sim_stream_source_dpi_bfm.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_run_tb' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/main_dpi_controller_inst/main_dpi_controller File: tb/sim/../../ip/tb/main_dpi_controller/hls_sim_main_dpi_controller_10/sim/hls_sim_main_dpi_controller.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_stream_empty' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/main_dpi_controller_inst/main_dpi_controller File: tb/sim/../../ip/tb/main_dpi_controller/hls_sim_main_dpi_controller_10/sim/hls_sim_main_dpi_controller.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_get_component_call_count' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/main_dpi_controller_inst/main_dpi_controller File: tb/sim/../../ip/tb/main_dpi_controller/hls_sim_main_dpi_controller_10/sim/hls_sim_main_dpi_controller.sv # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_dbgs' in DPI C/C++ source files. # Time: 0 ps Iteration: 0 Instance: /tb/clock_reset_inst/clock_reset File: tb/sim/../../ip/tb/clock_reset/hls_sim_clock_reset_10/sim/hls_sim_clock_reset.sv # End time: 09:01:54 on Jul 23,2018, Elapsed time: 0:01:30 # Errors: 0, Warnings: 25 Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Mon Jul 23 09:02:00 2018 Info: Command: quartus_sh --flow compile quartus_compile Info: Quartus(args): compile quartus_compile Info: Using INI file /home/tempuser11/counter/counterDUT1.prj/quartus/quartus.ini Info: Project Name = /home/tempuser11/counter/counterDUT1.prj/quartus/quartus_compile Info: Revision Name = quartus_compile Info: ******************************************************************* Info: Running Quartus Prime IP Generation Tool Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition Info: Processing started: Mon Jul 23 09:02:04 2018 Info: Command: quartus_ipgenerate quartus_compile -c quartus_compile --run_default_mode_op Info: Using INI file /home/tempuser11/counter/counterDUT1.prj/quartus/quartus.ini Info: Found 1 IP file(s) in the project. Info: IP file /home/tempuser11/counter/counterDUT1.prj/components/count/count.ip was found in the project. Info: Finished generating IP file(s) in the project. Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/tempuser11/counter/counterDUT1.prj/components/count/count). Info: Skipped generation of synthesis files for the Platform Designer IP file /home/tempuser11/counter/counterDUT1.prj/components/count/count.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Quartus Prime IP Generation Tool was successful. 0 errors, 0 warnings Info: Peak virtual memory: 701 megabytes Info: Processing ended: Mon Jul 23 09:02:04 2018 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 Info: ******************************************************************* Info: Running Quartus Prime Synthesis Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition Info: Processing started: Mon Jul 23 09:02:12 2018 Info: Command: quartus_syn --read_settings_files=off --write_settings_files=off quartus_compile -c quartus_compile Info: Using INI file /home/tempuser11/counter/counterDUT1.prj/quartus/quartus.ini Info: qis_default_flow_script.tcl version: #1 Info: Initializing Synthesis... Info: Project = "quartus_compile" Info: Revision = "quartus_compile" Info: Analyzing source files Error (19286): No license for family Arria 10 Error: Flow failed: ERROR: Current design not found Error: Quartus Prime Synthesis was unsuccessful. 2 errors, 0 warnings Error: Peak virtual memory: 868 megabytes Error: Processing ended: Mon Jul 23 09:02:12 2018 Error: Elapsed time: 00:00:00 Error: Total CPU time (on all processors): 00:00:01 Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 0 warnings Error: Flow compile (for project /home/tempuser11/counter/counterDUT1.prj/quartus/quartus_compile) was not successful Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last. Error (23031): Evaluation of Tcl script /D/intelFPGA_pro/17.1/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 11 errors, 0 warnings Error: Peak virtual memory: 696 megabytes Error: Processing ended: Mon Jul 23 09:02:14 2018 Error: Elapsed time: 00:00:14 Error: Total CPU time (on all processors): 00:00:05