Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity FLASH_CTRL is
    generic(
        ADDR_START            :        unsigned(23 downto 0):= to_unsigned(0,24);
        ADDR_END                :        unsigned(23 downto 0):=to_unsigned(1024,24)
    );
    port(
        i_clk                    : in        std_logic;
        i_rst                    : in         std_logic;
        i_mode                : in        std_logic_vector(2 downto 0);
        i_data                : in        std_logic_vector(31 downto 0);
        i_addr                : in        std_logic_vector(23 downto 0);
        o_data                : out        std_logic_vector(31 downto 0);
        o_newdata            : out        std_logic;      
        QSPI_CLK                : out        std_logic;
        QSPI_IO                : inout    std_logic_vector(3 downto 0);
        QSPI_CSn                : out        std_logic_vector(0 downto 0)    
        );        
        
end FLASH_CTRL;

architecture RTL of FLASH_CTRL is

component QUAD_SPI_n25q_512 is
        port (
            clk_clk                                                        : in    std_logic                     := 'X';             -- clk
            reset_reset_n                                                  : in    std_logic                     := 'X';             -- reset_n
            generic_quad_spi_controller_0_clock_sink_clk                   : in    std_logic                     := 'X';             -- clk
            generic_quad_spi_controller_0_reset_reset_n                    : in    std_logic                     := 'X';             -- reset_n
            generic_quad_spi_controller_0_avl_csr_read                     : in    std_logic                     := 'X';             -- read
            generic_quad_spi_controller_0_avl_csr_waitrequest              : out   std_logic;                                        --  waitrequest
            generic_quad_spi_controller_0_avl_csr_write                    : in    std_logic                     := 'X';             -- write
            generic_quad_spi_controller_0_avl_csr_address                  : in    std_logic_vector(2 downto 0)  := (others => 'X'); -- address
            generic_quad_spi_controller_0_avl_csr_writedata                : in    std_logic_vector(31 downto 0) := (others => 'X'); --  writedata
            generic_quad_spi_controller_0_avl_csr_readdata                 : out   std_logic_vector(31 downto 0);                    -- readdata
            generic_quad_spi_controller_0_avl_csr_readdatavalid            : out   std_logic;                                        --  readdatavalid
            generic_quad_spi_controller_0_avl_mem_write                    : in    std_logic                     := 'X';             -- write
            generic_quad_spi_controller_0_avl_mem_burstcount               : in    std_logic_vector(6 downto 0)  := (others => 'X'); --  burstcount
            generic_quad_spi_controller_0_avl_mem_waitrequest              : out   std_logic;                                        --  waitrequest
            generic_quad_spi_controller_0_avl_mem_read                     : in    std_logic                     := 'X';             -- read
            generic_quad_spi_controller_0_avl_mem_address                  : in    std_logic_vector(23 downto 0) := (others => 'X'); -- address
            generic_quad_spi_controller_0_avl_mem_writedata                : in    std_logic_vector(31 downto 0) := (others => 'X'); --  writedata
            generic_quad_spi_controller_0_avl_mem_readdata                 : out   std_logic_vector(31 downto 0);                    -- readdata
            generic_quad_spi_controller_0_avl_mem_readdatavalid            : out   std_logic;                                        --  readdatavalid
            generic_quad_spi_controller_0_avl_mem_byteenable               : in    std_logic_vector(3 downto 0)  := (others => 'X'); --  byteenable
            generic_quad_spi_controller_0_interrupt_sender_irq             : out   std_logic;                                        -- irq
            generic_quad_spi_controller_0_flash_dataout_conduit_dataout    : inout std_logic_vector(3 downto 0)  := (others => 'X'); --  conduit_dataout
             generic_quad_spi_controller_0_flash_dclk_out_conduit_dclk_out : out    std_logic;                                        -- conduit_dclk_out
            generic_quad_spi_controller_0_flash_ncs_conduit_ncs            : out   std_logic_vector(0 downto 0)                      --  conduit_ncs
        );
end component QUAD_SPI_n25q_512;


type t_state is (IDLE,DATAREAD1,DATAREAD2,DATAWRITE1,DATAWRITE2,CSRREAD,CSRWRITE,HOLD);

signal r_mode            : unsigned(3 downto 0);
signal state            : t_state;
signal r_addr             : unsigned(23 downto 0);
signal r_counter2        : unsigned(31 downto 0);
signal r_datareg        : unsigned(15 downto 0);


--QUAD_SPI_n25q_512_bb interface

--signal clk_clk                                                                : std_logic;
--signal    reset_reset_n                                                        : std_logic;
signal    gqsc_reset_reset_n                : std_logic;
signal    gqsc_csr_read                        : std_logic;
signal    gqsc_csr_waitrequest                : std_logic;
signal    gqsc_csr_write                        : std_logic;
signal    gqsc_csr_address                    : unsigned(2 downto 0);
signal    gqsc_csr_writedata                : std_logic_vector(31 downto 0);
signal    gqsc_csr_readdata                    : std_logic_vector(31 downto 0);
signal    gqsc_csr_readdatavalid            : std_logic;
signal    gqsc_mem_write                        : std_logic;
signal    gqsc_mem_burstcount                : unsigned(6 downto 0);
signal    gqsc_mem_waitrequest                : std_logic;
signal    gqsc_mem_read                        : std_logic;
signal    gqsc_mem_address                    : unsigned(23 downto 0);
signal    gqsc_mem_writedata                : std_logic_vector(31 downto 0);
signal    gqsc_mem_readdata                    : std_logic_vector(31 downto 0);
signal    gqsc_mem_readdatavalid            : std_logic;
signal    gqsc_mem_byteenable                : std_logic_vector(3 downto 0);
signal    gqsc_clock_sink_clk                : std_logic; 
signal    gqsc_interrupt_sender_irq        : std_logic;
signal    gqsc_flash_dataout_conduit_dataout        : std_logic_vector(3 downto 0);
signal    gqsc_flash_dclk_out_conduit_dclk_out    : std_logic;
signal    gqsc_flash_ncs_conduit_ncs                    : std_logic;



begin
QUAD_SPI : QUAD_SPI_n25q_512 port map(i_clk,
i_rst, 
gqsc_clock_sink_clk, 
i_rst, 
gqsc_csr_read, 
gqsc_csr_waitrequest, 
gqsc_csr_write,
std_logic_vector(gqsc_csr_address),
gqsc_csr_writedata,
gqsc_csr_readdata,
gqsc_csr_readdatavalid,
gqsc_mem_write,
std_logic_vector(gqsc_mem_burstcount),
gqsc_mem_waitrequest,gqsc_mem_read,
std_logic_vector(gqsc_mem_address),
gqsc_mem_writedata,gqsc_mem_readdata,
gqsc_mem_readdatavalid,
gqsc_mem_byteenable,
gqsc_interrupt_sender_irq,
QSPI_IO, 
QSPI_CLK, 
QSPI_CSn);

    
end architecture;