Microsoft Windows [Versión 10.0.18363.720]
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C:\Users\Usuario>cd Desktop\design\LL10G_10GBASER\simulation\ed_sim\mentor

C:\Users\Usuario\Desktop\design\LL10G_10GBASER\simulation\ed_sim\mentor>vsim -c -do tb_run.tcl
Reading C:/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl

# 10.5b

# do tb_run.tcl
# C:\intelFPGA_pro\19.1\quartus
# ../setup_scripts
# msim_wave.do
# ./../setup_scripts
# tb_top
# [exec] file_copy
# List Of Command Line Aliases
#
# file_copy                                         -- Copy ROM/RAM files to simulation directory
#
# dev_com                                           -- Compile device library files
#
# com                                               -- Compile the design files in correct order
#
# elab                                              -- Elaborate top level design
#
# elab_debug                                        -- Elaborate the top level design with -voptargs=+acc option
#
# ld                                                -- Compile all the design files and elaborate the top level design
#
# ld_debug                                          -- Compile all the design files and elaborate the top level design with  -voptargs=+acc
#
#
#
# List Of Variables
#
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
#
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
#
# QSYS_SIMDIR                                       -- Qsys base simulation directory.
#
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
#
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
#
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
#
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.
#
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
#
# SILENCE                                           -- Set to true to suppress all informational and/or warning messages in the generated simulation script.
#
# FORCE_MODELSIM_AE_SELECTION                       -- Set to true to force to select Modelsim AE always.
# [exec] dev_com
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:52:59 on Mar 16,2020
# vlog -sv -work work C:\intelFPGA_pro\19.1\quartus/../ip/altera/sopc_builder_ip/verification/lib/verbosity_pkg.sv
# -- Compiling package verbosity_pkg
#
# Top level modules:
#       --none--
# End time: 21:52:59 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:52:59 on Mar 16,2020
# vlog -sv -work work C:\intelFPGA_pro\19.1\quartus/../ip/altera/sopc_builder_ip/verification/lib/avalon_mm_pkg.sv
# -- Compiling package avalon_mm_pkg
# -- Importing package verbosity_pkg
#
# Top level modules:
#       --none--
# End time: 21:52:59 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:00 on Mar 16,2020
# vlog -sv -work work C:\intelFPGA_pro\19.1\quartus/../ip/altera/sopc_builder_ip/verification/lib/avalon_utilities_pkg.sv
# -- Compiling package avalon_utilities_pkg
#
# Top level modules:
#       --none--
# End time: 21:53:00 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:00 on Mar 16,2020
# vlog -sv -work work C:\intelFPGA_pro\19.1\quartus/../ip/altera/sopc_builder_ip/verification/altera_avalon_mm_master_bfm/altera_avalon_mm_master_bfm.sv
# -- Compiling module altera_avalon_mm_master_bfm
# -- Importing package verbosity_pkg
# -- Importing package avalon_mm_pkg
# -- Importing package avalon_utilities_pkg
#
# Top level modules:
#       altera_avalon_mm_master_bfm
# End time: 21:53:00 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:00 on Mar 16,2020
# vlog -sv -work work C:\intelFPGA_pro\19.1\quartus/../ip/altera/sopc_builder_ip/verification/altera_avalon_st_sink_bfm/altera_avalon_st_sink_bfm.sv
# -- Compiling module altera_avalon_st_sink_bfm
# -- Importing package verbosity_pkg
#
# Top level modules:
#       altera_avalon_st_sink_bfm
# End time: 21:53:01 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:01 on Mar 16,2020
# vlog -sv -work work C:\intelFPGA_pro\19.1\quartus/../ip/altera/sopc_builder_ip/verification/altera_avalon_st_source_bfm/altera_avalon_st_source_bfm.sv
# -- Compiling module altera_avalon_st_source_bfm
# -- Importing package verbosity_pkg
# -- Importing package avalon_utilities_pkg
#
# Top level modules:
#       altera_avalon_st_source_bfm
# End time: 21:53:01 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# [exec] com
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:01 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/altera_xcvr_native_a10_functions_h.sv -work altera_common_sv_packages
# -- Compiling package altera_xcvr_native_a10_functions_h
#
# Top level modules:
#       --none--
# End time: 21:53:02 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:02 on Mar 16,2020
# vlog -sv "+incdir+../models" ../models/tb_top.sv
# -- Compiling package eth_register_map_params_pkg
# -- Compiling package avalon_if_params_pkt
# -- Compiling module avalon_bfm_wrapper
# -- Importing package avalon_if_params_pkt
# -- Compiling package tb_top_sv_unit
# -- Compiling module avalon_driver
# -- Importing package avalon_if_params_pkt
# -- Importing package eth_register_map_params_pkg
# -- Importing package avalon_mm_pkg
# -- Importing package verbosity_pkg
# -- Compiling module avalon_st_eth_packet_monitor
# -- Compiling package default_test_params_pkt
# -- Compiling module tb_top
# -- Importing package default_test_params_pkt
#
# Top level modules:
#       tb_top
# End time: 21:53:02 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:02 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/altera_avalon_sc_fifo.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module altera_avalon_sc_fifo
#
# Top level modules:
#       altera_avalon_sc_fifo
# End time: 21:53:03 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Start time: 21:53:03 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/avalon_st_gen.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module avalon_st_gen
# -- Compiling module prbs23
#
# Top level modules:
#       avalon_st_gen
# End time: 21:53:03 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:03 on Mar 16,2020
# vlog -sv ../../../rtl/eth_traffic_controller/avalon_st_loopback.sv
# -- Compiling module avalon_st_loopback
#
# Top level modules:
#       avalon_st_loopback
# End time: 21:53:04 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Start time: 21:53:04 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/avalon_st_loopback_csr.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module avalon_st_loopback_csr
#
# Top level modules:
#       avalon_st_loopback_csr
# End time: 21:53:04 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:04 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/avalon_st_mon.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module avalon_st_mon
#
# Top level modules:
#       avalon_st_mon
# End time: 21:53:04 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:04 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/avalon_st_prtmux.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module avalon_st_prtmux
#
# Top level modules:
#       avalon_st_prtmux
# End time: 21:53:05 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Start time: 21:53:05 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/eth_std_traffic_controller_top.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module eth_std_traffic_controller_top
# -- Compiling module traffic_reset_sync
#
# Top level modules:
#       eth_std_traffic_controller_top
# End time: 21:53:05 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:05 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/shiftreg_ctrl.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module shiftreg_ctrl
#
# Top level modules:
#       shiftreg_ctrl
# End time: 21:53:05 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:05 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/shiftreg_data.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module shiftreg_data
#
# Top level modules:
#       shiftreg_data
# End time: 21:53:06 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Start time: 21:53:06 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/avalon_st_to_crc_if_bridge.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module avalon_st_to_crc_if_bridge
#
# Top level modules:
#       avalon_st_to_crc_if_bridge
# End time: 21:53:06 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:06 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/bit_endian_converter.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module bit_endian_converter
#
# Top level modules:
#       bit_endian_converter
# End time: 21:53:06 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:06 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/byte_endian_converter.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module byte_endian_converter
#
# Top level modules:
#       byte_endian_converter
# End time: 21:53:07 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Start time: 21:53:07 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc_checksum_aligner.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc_checksum_aligner
#
# Top level modules:
#       crc_checksum_aligner
# End time: 21:53:07 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:07 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc_comparator.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc_comparator
#
# Top level modules:
#       crc_comparator
# End time: 21:53:07 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:07 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_calculator.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_calculator
#
# Top level modules:
#       crc32_calculator
# End time: 21:53:08 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Start time: 21:53:08 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_chk.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_chk
#
# Top level modules:
#       crc32_chk
# End time: 21:53:08 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:08 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_gen.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_gen
#
# Top level modules:
#       crc32_gen
# End time: 21:53:08 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:08 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc_ethernet.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc_ethernet
#
# Top level modules:
#       crc_ethernet
# End time: 21:53:09 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Start time: 21:53:09 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc_register.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc_register
#
# Top level modules:
#       crc_register
# End time: 21:53:09 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:09 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat8.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_dat8
# -- Compiling module crc32_dat8_flat
# -- Compiling module crc32_dat8_factor
#
# Top level modules:
#       crc32_dat8
# End time: 21:53:09 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:09 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat16.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_dat16
# -- Compiling module crc32_dat16_flat
# -- Compiling module crc32_dat16_factor
#
# Top level modules:
#       crc32_dat16
# End time: 21:53:10 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Start time: 21:53:10 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat24.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_dat24
# -- Compiling module crc32_dat24_flat
# -- Compiling module crc32_dat24_factor
#
# Top level modules:
#       crc32_dat24
# End time: 21:53:10 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:10 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat32.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_dat32
# -- Compiling module crc32_dat32_flat
# -- Compiling module crc32_dat32_factor
#
# Top level modules:
#       crc32_dat32
# End time: 21:53:11 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Start time: 21:53:11 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat32_any_byte.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_dat32_any_byte
#
# Top level modules:
#       crc32_dat32_any_byte
# End time: 21:53:11 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:11 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat40.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_dat40
# -- Compiling module crc32_dat40_flat
# -- Compiling module crc32_dat40_factor
#
# Top level modules:
#       crc32_dat40
# End time: 21:53:12 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Start time: 21:53:12 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat48.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_dat48
# -- Compiling module crc32_dat48_flat
# -- Compiling module crc32_dat48_factor
#
# Top level modules:
#       crc32_dat48
# End time: 21:53:12 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:12 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat56.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_dat56
# -- Compiling module crc32_dat56_flat
# -- Compiling module crc32_dat56_factor
#
# Top level modules:
#       crc32_dat56
# End time: 21:53:12 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:13 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat64.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_dat64
# -- Compiling module crc32_dat64_flat
# -- Compiling module crc32_dat64_factor
#
# Top level modules:
#       crc32_dat64
# End time: 21:53:13 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:13 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat64_any_byte.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module crc32_dat64_any_byte
#
# Top level modules:
#       crc32_dat64_any_byte
# End time: 21:53:13 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:13 on Mar 16,2020
# vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/xor6.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module xor6
#
# Top level modules:
#       xor6
# End time: 21:53:14 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:14 on Mar 16,2020
# vlog -sv ../../../rtl/altera_eth_10g_mac_base_r.sv
# -- Compiling module altera_eth_10g_mac_base_r
#
# Top level modules:
#       altera_eth_10g_mac_base_r
# End time: 21:53:14 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 21:53:14 on Mar 16,2020
# vlog ../../../rtl/altera_eth_10g_mac_base_r_wrap.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module altera_eth_10g_mac_base_r_wrap
#
# Top level modules:
#       altera_eth_10g_mac_base_r_wrap
# End time: 21:53:14 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:15 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_resync.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module alt_xcvr_resync
# ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_resync" is being recompiled as unprotected.
#
# Top level modules:
#       alt_xcvr_resync
# End time: 21:53:15 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:15 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_arbiter.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module alt_xcvr_arbiter
# ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_arbiter" is being recompiled as unprotected.
#
# Top level modules:
#       alt_xcvr_arbiter
# End time: 21:53:15 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:15 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/mentor/alt_xcvr_resync.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# ** Warning: (vlog-2070) Existing unprotected design unit "alt_xcvr_resync" is being recompiled as protected.
#
# Top level modules:
# End time: 21:53:17 on Mar 16,2020, Elapsed time: 0:00:02
# Errors: 0, Warnings: 2
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:17 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/mentor/alt_xcvr_arbiter.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# ** Warning: (vlog-2070) Existing unprotected design unit "alt_xcvr_arbiter" is being recompiled as protected.
#
# Top level modules:
# End time: 21:53:18 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 2
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:18 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/twentynm_pcs.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module twentynm_pcs_rev_20nm1
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_pcs_rev_20nm1" is being recompiled as unprotected.
# -- Compiling module twentynm_pcs_rev_20nm2
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_pcs_rev_20nm2" is being recompiled as unprotected.
# -- Compiling module twentynm_pcs_rev_20nm3
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_pcs_rev_20nm3" is being recompiled as unprotected.
# -- Compiling module twentynm_pcs_rev_20nm4
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_pcs_rev_20nm4" is being recompiled as unprotected.
# -- Compiling module twentynm_pcs_rev_20nm5
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_pcs_rev_20nm5" is being recompiled as unprotected.
#
# Top level modules:
#       twentynm_pcs_rev_20nm1
#       twentynm_pcs_rev_20nm2
#       twentynm_pcs_rev_20nm3
#       twentynm_pcs_rev_20nm4
#       twentynm_pcs_rev_20nm5
# End time: 21:53:21 on Mar 16,2020, Elapsed time: 0:00:03
# Errors: 0, Warnings: 5
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:21 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/twentynm_pma.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module twentynm_pma_rev_20nm1
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_pma_rev_20nm1" is being recompiled as unprotected.
# -- Compiling module twentynm_pma_rev_20nm2
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_pma_rev_20nm2" is being recompiled as unprotected.
# -- Compiling module twentynm_pma_rev_20nm3
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_pma_rev_20nm3" is being recompiled as unprotected.
# -- Compiling module twentynm_pma_rev_20nm4
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_pma_rev_20nm4" is being recompiled as unprotected.
# -- Compiling module twentynm_pma_rev_20nm5
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_pma_rev_20nm5" is being recompiled as unprotected.
#
# Top level modules:
#       twentynm_pma_rev_20nm1
#       twentynm_pma_rev_20nm2
#       twentynm_pma_rev_20nm3
#       twentynm_pma_rev_20nm4
#       twentynm_pma_rev_20nm5
# End time: 21:53:22 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 5
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:22 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/twentynm_xcvr_avmm.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module twentynm_xcvr_avmm
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_avmm" is being recompiled as unprotected.
#
# Top level modules:
#       twentynm_xcvr_avmm
# End time: 21:53:22 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:22 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/twentynm_xcvr_native.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module twentynm_xcvr_native
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_native" is being recompiled as unprotected.
# -- Compiling module twentynm_xcvr_native_rev_20nm1
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_native_rev_20nm1" is being recompiled as unprotected.
# -- Compiling module twentynm_xcvr_native_rev_20nm2
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_native_rev_20nm2" is being recompiled as unprotected.
# -- Compiling module twentynm_xcvr_native_rev_20nm3
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_native_rev_20nm3" is being recompiled as unprotected.
# -- Compiling module twentynm_xcvr_native_rev_20nm4
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_native_rev_20nm4" is being recompiled as unprotected.
# -- Compiling module twentynm_xcvr_native_rev_20nm5
# ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_native_rev_20nm5" is being recompiled as unprotected.
#
# Top level modules:
#       twentynm_xcvr_native
# End time: 21:53:24 on Mar 16,2020, Elapsed time: 0:00:02
# Errors: 0, Warnings: 6
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:24 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/mentor/twentynm_pcs.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pcs_rev_20nm1" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pcs_rev_20nm2" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pcs_rev_20nm3" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pcs_rev_20nm4" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pcs_rev_20nm5" is being recompiled as protected.
#
# Top level modules:
# End time: 21:53:29 on Mar 16,2020, Elapsed time: 0:00:05
# Errors: 0, Warnings: 10
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:29 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/mentor/twentynm_pma.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pma_rev_20nm1" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pma_rev_20nm2" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pma_rev_20nm3" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pma_rev_20nm4" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pma_rev_20nm5" is being recompiled as protected.
#
# Top level modules:
# End time: 21:53:31 on Mar 16,2020, Elapsed time: 0:00:02
# Errors: 0, Warnings: 10
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:31 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/mentor/twentynm_xcvr_avmm.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_avmm" is being recompiled as protected.
#
# Top level modules:
# End time: 21:53:32 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 2
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:32 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/mentor/twentynm_xcvr_native.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_native" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_native_rev_20nm1" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_native_rev_20nm2" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_native_rev_20nm3" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_native_rev_20nm4" is being recompiled as protected.
# ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_native_rev_20nm5" is being recompiled as protected.
#
# Top level modules:
# End time: 21:53:36 on Mar 16,2020, Elapsed time: 0:00:04
# Errors: 0, Warnings: 12
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:36 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/a10_avmm_h.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling package a10_avmm_h
#
# Top level modules:
#       --none--
# End time: 21:53:36 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:36 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_pipe_retry.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module alt_xcvr_native_pipe_retry
#
# Top level modules:
#       alt_xcvr_native_pipe_retry
# End time: 21:53:37 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:37 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_avmm_csr.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module alt_xcvr_native_avmm_csr
# -- Importing package a10_avmm_h
#
# Top level modules:
#       alt_xcvr_native_avmm_csr
# End time: 21:53:37 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:37 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_prbs_accum.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module alt_xcvr_native_prbs_accum
#
# Top level modules:
#       alt_xcvr_native_prbs_accum
# End time: 21:53:37 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:37 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_odi_accel.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module alt_xcvr_native_odi_accel
#
# Top level modules:
#       alt_xcvr_native_odi_accel
# End time: 21:53:38 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:38 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_arb.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module alt_xcvr_native_rcfg_arb
#
# Top level modules:
#       alt_xcvr_native_rcfg_arb
# End time: 21:53:38 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:38 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/altera_xcvr_native_pcie_dfe_params_h.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling package altera_xcvr_native_pcie_dfe_params_h
#
# Top level modules:
#       --none--
# End time: 21:53:38 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:39 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_commands_h.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling package pcie_mgmt_commands_h
#
# Top level modules:
#       --none--
# End time: 21:53:39 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:39 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_functions_h.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling package pcie_mgmt_functions_h
# -- Importing package pcie_mgmt_commands_h
#
# Top level modules:
#       --none--
# End time: 21:53:39 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:39 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_program.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling package pcie_mgmt_program
# -- Importing package pcie_mgmt_functions_h
# -- Importing package pcie_mgmt_commands_h
# -- Importing package altera_xcvr_native_pcie_dfe_params_h
#
# Top level modules:
#       --none--
# End time: 21:53:40 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:40 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_cpu.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module pcie_mgmt_cpu
# -- Importing package pcie_mgmt_commands_h
#
# Top level modules:
#       pcie_mgmt_cpu
# End time: 21:53:40 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:40 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_master.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module pcie_mgmt_master
# -- Importing package pcie_mgmt_functions_h
# -- Importing package pcie_mgmt_commands_h
# -- Importing package pcie_mgmt_program
# -- Importing package altera_xcvr_native_pcie_dfe_params_h
#
# Top level modules:
#       pcie_mgmt_master
# End time: 21:53:41 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:41 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/altera_xcvr_native_pcie_dfe_ip.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module altera_xcvr_native_pcie_dfe_ip
# -- Importing package altera_xcvr_native_pcie_dfe_params_h
#
# Top level modules:
#       altera_xcvr_native_pcie_dfe_ip
# End time: 21:53:41 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:41 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/altera_eth_10gbaser_phy_altera_xcvr_native_a10_191_6rgg7fy.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module altera_eth_10gbaser_phy_altera_xcvr_native_a10_191_6rgg7fy
# -- Importing package altera_common_sv_packages.altera_xcvr_native_a10_functions_h
#
# Top level modules:
#       altera_eth_10gbaser_phy_altera_xcvr_native_a10_191_6rgg7fy
# End time: 21:53:42 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:42 on Mar 16,2020
# vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_6rgg7fy.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# -- Compiling module alt_xcvr_native_rcfg_opt_logic_6rgg7fy
# -- Importing package altera_common_sv_packages.altera_xcvr_native_a10_functions_h
#
# Top level modules:
#       alt_xcvr_native_rcfg_opt_logic_6rgg7fy
# End time: 21:53:42 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:42 on Mar 16,2020
# vcom ../../../rtl/phy/altera_eth_10gbaser_phy/sim/altera_eth_10gbaser_phy.vhd -work altera_eth_10gbaser_phy
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity altera_eth_10gbaser_phy
# -- Compiling architecture rtl of altera_eth_10gbaser_phy
# -- Loading package vl_types
# -- Loading entity altera_eth_10gbaser_phy_altera_xcvr_native_a10_191_6rgg7fy
# End time: 21:53:43 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:43 on Mar 16,2020
# vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_clk_csr/sim/address_decode_clk_csr.vhd -work address_decode_clk_csr
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity address_decode_clk_csr
# -- Compiling architecture rtl of address_decode_clk_csr
# End time: 21:53:44 on Mar 16,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:53:44 on Mar 16,2020
# vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_0/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_0_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191
# ** Error: (vlog-7) Failed to open design unit file "../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_0/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_0_altera_merlin_slave_translator_191_x56fcki.sv" in read mode.
# No such file or directory. (errno = ENOENT)
# End time: 21:53:44 on Mar 16,2020, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed.
# Error in macro ./tb_run.tcl line 38
# C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed.
#     while executing
# "vlog -sv    "../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_0/altera_merlin_slave_translator_191/sim/address_decode_eth_gen..."
#     ("eval" body line 1)
#     invoked from within
# "eval $file"
#     ("foreach" body line 2)
#     invoked from within
# "foreach file $design_files {
#     eval $file
#   }"
#     ("eval" body line 13)
#     invoked from within
# "com"
ModelSim>