Microsoft Windows [Versión 10.0.18363.720] (c) 2019 Microsoft Corporation. Todos los derechos reservados. C:\Users\Usuario>cd C:\FP\e\simulation\ed_sim\mentor C:\FP\e\simulation\ed_sim\mentor>vsim -c -do tb_run.tcl Reading C:/intelFPGA_pro/19.1/modelsim_ase/tcl/vsim/pref.tcl # 10.6d # do tb_run.tcl # C:\intelFPGA_pro\19.1\quartus # ../setup_scripts # msim_wave.do # ./../setup_scripts # tb_top # [exec] file_copy # List Of Command Line Aliases # # file_copy -- Copy ROM/RAM files to simulation directory # # dev_com -- Compile device library files # # com -- Compile the design files in correct order # # elab -- Elaborate top level design # # elab_debug -- Elaborate the top level design with -voptargs=+acc option # # ld -- Compile all the design files and elaborate the top level design # # ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc # # # # List Of Variables # # TOP_LEVEL_NAME -- Top level module name. # For most designs, this should be overridden # to enable the elab/elab_debug aliases. # # SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module. # # QSYS_SIMDIR -- Qsys base simulation directory. # # QUARTUS_INSTALL_DIR -- Quartus installation directory. # # USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases. # # USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases. # # USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases. # # USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases. # # SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script. # # FORCE_MODELSIM_AE_SELECTION -- Set to true to force to select Modelsim AE always. # [exec] dev_com # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:36 on Mar 19,2020 # vlog -sv -work work C:\intelFPGA_pro\19.1\quartus/../ip/altera/sopc_builder_ip/verification/lib/verbosity_pkg.sv # -- Compiling package verbosity_pkg # # Top level modules: # --none-- # End time: 11:25:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:36 on Mar 19,2020 # vlog -sv -work work C:\intelFPGA_pro\19.1\quartus/../ip/altera/sopc_builder_ip/verification/lib/avalon_mm_pkg.sv # -- Compiling package avalon_mm_pkg # -- Importing package verbosity_pkg # # Top level modules: # --none-- # End time: 11:25:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:36 on Mar 19,2020 # vlog -sv -work work C:\intelFPGA_pro\19.1\quartus/../ip/altera/sopc_builder_ip/verification/lib/avalon_utilities_pkg.sv # -- Compiling package avalon_utilities_pkg # # Top level modules: # --none-- # End time: 11:25:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:36 on Mar 19,2020 # vlog -sv -work work C:\intelFPGA_pro\19.1\quartus/../ip/altera/sopc_builder_ip/verification/altera_avalon_mm_master_bfm/altera_avalon_mm_master_bfm.sv # -- Compiling module altera_avalon_mm_master_bfm # -- Importing package verbosity_pkg # -- Importing package avalon_mm_pkg # -- Importing package avalon_utilities_pkg # # Top level modules: # altera_avalon_mm_master_bfm # End time: 11:25:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:36 on Mar 19,2020 # vlog -sv -work work C:\intelFPGA_pro\19.1\quartus/../ip/altera/sopc_builder_ip/verification/altera_avalon_st_sink_bfm/altera_avalon_st_sink_bfm.sv # -- Compiling module altera_avalon_st_sink_bfm # -- Importing package verbosity_pkg # # Top level modules: # altera_avalon_st_sink_bfm # End time: 11:25:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:36 on Mar 19,2020 # vlog -sv -work work C:\intelFPGA_pro\19.1\quartus/../ip/altera/sopc_builder_ip/verification/altera_avalon_st_source_bfm/altera_avalon_st_source_bfm.sv # -- Compiling module altera_avalon_st_source_bfm # -- Importing package verbosity_pkg # -- Importing package avalon_utilities_pkg # # Top level modules: # altera_avalon_st_source_bfm # End time: 11:25:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # [exec] com # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:36 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/altera_xcvr_native_a10_functions_h.sv -work altera_common_sv_packages # -- Compiling package altera_xcvr_native_a10_functions_h # # Top level modules: # --none-- # End time: 11:25:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:36 on Mar 19,2020 # vlog -sv "+incdir+../models" ../models/tb_top.sv # -- Compiling package eth_register_map_params_pkg # -- Compiling package avalon_if_params_pkt # -- Compiling module avalon_bfm_wrapper # -- Importing package avalon_if_params_pkt # -- Compiling package tb_top_sv_unit # -- Compiling module avalon_driver # -- Importing package avalon_if_params_pkt # -- Importing package eth_register_map_params_pkg # -- Importing package avalon_mm_pkg # -- Importing package verbosity_pkg # -- Compiling module avalon_st_eth_packet_monitor # -- Compiling package default_test_params_pkt # -- Compiling module tb_top # -- Importing package default_test_params_pkt # # Top level modules: # tb_top # End time: 11:25:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:36 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/altera_avalon_sc_fifo.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module altera_avalon_sc_fifo # # Top level modules: # altera_avalon_sc_fifo # End time: 11:25:37 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Start time: 11:25:37 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/avalon_st_gen.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module avalon_st_gen # -- Compiling module prbs23 # # Top level modules: # avalon_st_gen # End time: 11:25:37 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:37 on Mar 19,2020 # vlog -sv ../../../rtl/eth_traffic_controller/avalon_st_loopback.sv # -- Compiling module avalon_st_loopback # # Top level modules: # avalon_st_loopback # End time: 11:25:37 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:37 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/avalon_st_loopback_csr.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module avalon_st_loopback_csr # # Top level modules: # avalon_st_loopback_csr # End time: 11:25:37 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:37 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/avalon_st_mon.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module avalon_st_mon # # Top level modules: # avalon_st_mon # End time: 11:25:37 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:37 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/avalon_st_prtmux.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module avalon_st_prtmux # # Top level modules: # avalon_st_prtmux # End time: 11:25:37 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:37 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/eth_std_traffic_controller_top.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module eth_std_traffic_controller_top # -- Compiling module traffic_reset_sync # # Top level modules: # eth_std_traffic_controller_top # End time: 11:25:37 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:37 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/shiftreg_ctrl.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module shiftreg_ctrl # # Top level modules: # shiftreg_ctrl # End time: 11:25:37 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:37 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/shiftreg_data.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module shiftreg_data # # Top level modules: # shiftreg_data # End time: 11:25:37 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:37 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/avalon_st_to_crc_if_bridge.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module avalon_st_to_crc_if_bridge # # Top level modules: # avalon_st_to_crc_if_bridge # End time: 11:25:37 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:37 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/bit_endian_converter.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module bit_endian_converter # # Top level modules: # bit_endian_converter # End time: 11:25:37 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:37 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/byte_endian_converter.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module byte_endian_converter # # Top level modules: # byte_endian_converter # End time: 11:25:37 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:37 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc_checksum_aligner.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc_checksum_aligner # # Top level modules: # crc_checksum_aligner # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Start time: 11:25:38 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc_comparator.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc_comparator # # Top level modules: # crc_comparator # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:38 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_calculator.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_calculator # # Top level modules: # crc32_calculator # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:38 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_chk.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_chk # # Top level modules: # crc32_chk # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:38 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_gen.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_gen # # Top level modules: # crc32_gen # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:38 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc_ethernet.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc_ethernet # # Top level modules: # crc_ethernet # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:38 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc_register.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc_register # # Top level modules: # crc_register # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:38 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat8.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_dat8 # -- Compiling module crc32_dat8_flat # -- Compiling module crc32_dat8_factor # # Top level modules: # crc32_dat8 # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:38 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat16.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_dat16 # -- Compiling module crc32_dat16_flat # -- Compiling module crc32_dat16_factor # # Top level modules: # crc32_dat16 # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:38 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat24.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_dat24 # -- Compiling module crc32_dat24_flat # -- Compiling module crc32_dat24_factor # # Top level modules: # crc32_dat24 # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:38 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat32.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_dat32 # -- Compiling module crc32_dat32_flat # -- Compiling module crc32_dat32_factor # # Top level modules: # crc32_dat32 # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:38 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat32_any_byte.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_dat32_any_byte # # Top level modules: # crc32_dat32_any_byte # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:38 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat40.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_dat40 # -- Compiling module crc32_dat40_flat # -- Compiling module crc32_dat40_factor # # Top level modules: # crc32_dat40 # End time: 11:25:38 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:39 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat48.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_dat48 # -- Compiling module crc32_dat48_flat # -- Compiling module crc32_dat48_factor # # Top level modules: # crc32_dat48 # End time: 11:25:39 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:39 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat56.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_dat56 # -- Compiling module crc32_dat56_flat # -- Compiling module crc32_dat56_factor # # Top level modules: # crc32_dat56 # End time: 11:25:39 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:39 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat64.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_dat64 # -- Compiling module crc32_dat64_flat # -- Compiling module crc32_dat64_factor # # Top level modules: # crc32_dat64 # End time: 11:25:39 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:39 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/crc32_dat64_any_byte.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module crc32_dat64_any_byte # # Top level modules: # crc32_dat64_any_byte # End time: 11:25:39 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:39 on Mar 19,2020 # vlog ../../../rtl/eth_traffic_controller/crc32/crc32_lib/xor6.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module xor6 # # Top level modules: # xor6 # End time: 11:25:39 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:39 on Mar 19,2020 # vlog -sv ../../../rtl/altera_eth_10g_mac_base_r.sv # -- Compiling module altera_eth_10g_mac_base_r # # Top level modules: # altera_eth_10g_mac_base_r # End time: 11:25:39 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Start time: 11:25:39 on Mar 19,2020 # vlog ../../../rtl/altera_eth_10g_mac_base_r_wrap.v # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # -- Compiling module altera_eth_10g_mac_base_r_wrap # # Top level modules: # altera_eth_10g_mac_base_r_wrap # End time: 11:25:39 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:39 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_resync.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module alt_xcvr_resync # ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_resync" is being recompiled as unprotected. # # Top level modules: # alt_xcvr_resync # End time: 11:25:39 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:39 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_arbiter.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module alt_xcvr_arbiter # ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_arbiter" is being recompiled as unprotected. # # Top level modules: # alt_xcvr_arbiter # End time: 11:25:39 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:39 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/mentor/alt_xcvr_resync.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # ** Warning: (vlog-2070) Existing unprotected design unit "alt_xcvr_resync" is being recompiled as protected. # # Top level modules: # End time: 11:25:40 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:40 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/mentor/alt_xcvr_arbiter.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # ** Warning: (vlog-2070) Existing unprotected design unit "alt_xcvr_arbiter" is being recompiled as protected. # # Top level modules: # End time: 11:25:40 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:40 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/twentynm_pcs.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module twentynm_pcs_rev_20nm1 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_pcs_rev_20nm1" is being recompiled as unprotected. # -- Compiling module twentynm_pcs_rev_20nm2 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_pcs_rev_20nm2" is being recompiled as unprotected. # -- Compiling module twentynm_pcs_rev_20nm3 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_pcs_rev_20nm3" is being recompiled as unprotected. # -- Compiling module twentynm_pcs_rev_20nm4 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_pcs_rev_20nm4" is being recompiled as unprotected. # -- Compiling module twentynm_pcs_rev_20nm5 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_pcs_rev_20nm5" is being recompiled as unprotected. # # Top level modules: # twentynm_pcs_rev_20nm1 # twentynm_pcs_rev_20nm2 # twentynm_pcs_rev_20nm3 # twentynm_pcs_rev_20nm4 # twentynm_pcs_rev_20nm5 # End time: 11:25:40 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 5 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:40 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/twentynm_pma.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module twentynm_pma_rev_20nm1 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_pma_rev_20nm1" is being recompiled as unprotected. # -- Compiling module twentynm_pma_rev_20nm2 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_pma_rev_20nm2" is being recompiled as unprotected. # -- Compiling module twentynm_pma_rev_20nm3 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_pma_rev_20nm3" is being recompiled as unprotected. # -- Compiling module twentynm_pma_rev_20nm4 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_pma_rev_20nm4" is being recompiled as unprotected. # -- Compiling module twentynm_pma_rev_20nm5 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_pma_rev_20nm5" is being recompiled as unprotected. # # Top level modules: # twentynm_pma_rev_20nm1 # twentynm_pma_rev_20nm2 # twentynm_pma_rev_20nm3 # twentynm_pma_rev_20nm4 # twentynm_pma_rev_20nm5 # End time: 11:25:40 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 5 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:40 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/twentynm_xcvr_avmm.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module twentynm_xcvr_avmm # ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_avmm" is being recompiled as unprotected. # # Top level modules: # twentynm_xcvr_avmm # End time: 11:25:41 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:41 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/twentynm_xcvr_native.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module twentynm_xcvr_native # ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_native" is being recompiled as unprotected. # -- Compiling module twentynm_xcvr_native_rev_20nm1 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_native_rev_20nm1" is being recompiled as unprotected. # -- Compiling module twentynm_xcvr_native_rev_20nm2 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_native_rev_20nm2" is being recompiled as unprotected. # -- Compiling module twentynm_xcvr_native_rev_20nm3 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_native_rev_20nm3" is being recompiled as unprotected. # -- Compiling module twentynm_xcvr_native_rev_20nm4 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_native_rev_20nm4" is being recompiled as unprotected. # -- Compiling module twentynm_xcvr_native_rev_20nm5 # ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_native_rev_20nm5" is being recompiled as unprotected. # # Top level modules: # twentynm_xcvr_native # End time: 11:25:41 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 6 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:41 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/mentor/twentynm_pcs.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pcs_rev_20nm1" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pcs_rev_20nm2" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pcs_rev_20nm3" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pcs_rev_20nm4" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pcs_rev_20nm5" is being recompiled as protected. # # Top level modules: # End time: 11:25:42 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 10 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:42 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/mentor/twentynm_pma.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pma_rev_20nm1" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pma_rev_20nm2" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pma_rev_20nm3" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pma_rev_20nm4" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_pma_rev_20nm5" is being recompiled as protected. # # Top level modules: # End time: 11:25:43 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 10 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:43 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/mentor/twentynm_xcvr_avmm.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_avmm" is being recompiled as protected. # # Top level modules: # End time: 11:25:43 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:43 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/mentor/twentynm_xcvr_native.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_native" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_native_rev_20nm1" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_native_rev_20nm2" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_native_rev_20nm3" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_native_rev_20nm4" is being recompiled as protected. # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_native_rev_20nm5" is being recompiled as protected. # # Top level modules: # End time: 11:25:44 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 12 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:44 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/a10_avmm_h.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling package a10_avmm_h # # Top level modules: # --none-- # End time: 11:25:44 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:44 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_pipe_retry.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module alt_xcvr_native_pipe_retry # # Top level modules: # alt_xcvr_native_pipe_retry # End time: 11:25:44 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:44 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_avmm_csr.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module alt_xcvr_native_avmm_csr # -- Importing package a10_avmm_h # # Top level modules: # alt_xcvr_native_avmm_csr # End time: 11:25:44 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:44 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_prbs_accum.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module alt_xcvr_native_prbs_accum # # Top level modules: # alt_xcvr_native_prbs_accum # End time: 11:25:44 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:44 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_odi_accel.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module alt_xcvr_native_odi_accel # # Top level modules: # alt_xcvr_native_odi_accel # End time: 11:25:44 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:44 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_arb.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module alt_xcvr_native_rcfg_arb # # Top level modules: # alt_xcvr_native_rcfg_arb # End time: 11:25:44 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:44 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/altera_xcvr_native_pcie_dfe_params_h.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling package altera_xcvr_native_pcie_dfe_params_h # # Top level modules: # --none-- # End time: 11:25:44 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:44 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_commands_h.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling package pcie_mgmt_commands_h # # Top level modules: # --none-- # End time: 11:25:44 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:44 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_functions_h.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling package pcie_mgmt_functions_h # -- Importing package pcie_mgmt_commands_h # # Top level modules: # --none-- # End time: 11:25:44 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:45 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_program.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling package pcie_mgmt_program # -- Importing package pcie_mgmt_functions_h # -- Importing package pcie_mgmt_commands_h # -- Importing package altera_xcvr_native_pcie_dfe_params_h # # Top level modules: # --none-- # End time: 11:25:45 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:45 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_cpu.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module pcie_mgmt_cpu # -- Importing package pcie_mgmt_commands_h # # Top level modules: # pcie_mgmt_cpu # End time: 11:25:45 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:45 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_master.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module pcie_mgmt_master # -- Importing package pcie_mgmt_functions_h # -- Importing package pcie_mgmt_commands_h # -- Importing package pcie_mgmt_program # -- Importing package altera_xcvr_native_pcie_dfe_params_h # # Top level modules: # pcie_mgmt_master # End time: 11:25:45 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:45 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/altera_xcvr_native_pcie_dfe_ip.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module altera_xcvr_native_pcie_dfe_ip # -- Importing package altera_xcvr_native_pcie_dfe_params_h # # Top level modules: # altera_xcvr_native_pcie_dfe_ip # End time: 11:25:45 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:45 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/altera_eth_10gbaser_phy_altera_xcvr_native_a10_191_6rgg7fy.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module altera_eth_10gbaser_phy_altera_xcvr_native_a10_191_6rgg7fy # -- Importing package altera_common_sv_packages.altera_xcvr_native_a10_functions_h # # Top level modules: # altera_eth_10gbaser_phy_altera_xcvr_native_a10_191_6rgg7fy # End time: 11:25:45 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:45 on Mar 19,2020 # vlog -sv ../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_6rgg7fy.sv -L altera_common_sv_packages -work altera_xcvr_native_a10_191 # -- Compiling module alt_xcvr_native_rcfg_opt_logic_6rgg7fy # -- Importing package altera_common_sv_packages.altera_xcvr_native_a10_functions_h # # Top level modules: # alt_xcvr_native_rcfg_opt_logic_6rgg7fy # End time: 11:25:45 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:45 on Mar 19,2020 # vcom ../../../rtl/phy/altera_eth_10gbaser_phy/sim/altera_eth_10gbaser_phy.vhd -work altera_eth_10gbaser_phy # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity altera_eth_10gbaser_phy # -- Compiling architecture rtl of altera_eth_10gbaser_phy # -- Loading package vl_types # -- Loading entity altera_eth_10gbaser_phy_altera_xcvr_native_a10_191_6rgg7fy # End time: 11:25:45 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:45 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_clk_csr/sim/address_decode_clk_csr.vhd -work address_decode_clk_csr # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_clk_csr # -- Compiling architecture rtl of address_decode_clk_csr # End time: 11:25:45 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:46 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_0/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_0_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_eth_gen_mon_0_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_eth_gen_mon_0_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:46 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:46 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_0/sim/address_decode_eth_gen_mon_0.vhd -work address_decode_eth_gen_mon_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_eth_gen_mon_0 # -- Compiling architecture rtl of address_decode_eth_gen_mon_0 # -- Loading package vl_types # -- Loading entity address_decode_eth_gen_mon_0_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:46 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:46 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_1/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_1_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_eth_gen_mon_1_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_eth_gen_mon_1_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:46 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:46 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_1/sim/address_decode_eth_gen_mon_1.vhd -work address_decode_eth_gen_mon_1 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_eth_gen_mon_1 # -- Compiling architecture rtl of address_decode_eth_gen_mon_1 # -- Loading package vl_types # -- Loading entity address_decode_eth_gen_mon_1_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:46 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:46 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_10/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_10_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_eth_gen_mon_10_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_eth_gen_mon_10_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:46 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:46 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_10/sim/address_decode_eth_gen_mon_10.vhd -work address_decode_eth_gen_mon_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_eth_gen_mon_10 # -- Compiling architecture rtl of address_decode_eth_gen_mon_10 # -- Loading package vl_types # -- Loading entity address_decode_eth_gen_mon_10_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:46 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:46 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_11/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_11_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_eth_gen_mon_11_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_eth_gen_mon_11_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:46 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:46 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_11/sim/address_decode_eth_gen_mon_11.vhd -work address_decode_eth_gen_mon_11 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_eth_gen_mon_11 # -- Compiling architecture rtl of address_decode_eth_gen_mon_11 # -- Loading package vl_types # -- Loading entity address_decode_eth_gen_mon_11_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:47 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:47 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_2/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_2_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_eth_gen_mon_2_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_eth_gen_mon_2_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:47 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:47 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_2/sim/address_decode_eth_gen_mon_2.vhd -work address_decode_eth_gen_mon_2 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_eth_gen_mon_2 # -- Compiling architecture rtl of address_decode_eth_gen_mon_2 # -- Loading package vl_types # -- Loading entity address_decode_eth_gen_mon_2_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:47 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:47 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_3/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_3_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_eth_gen_mon_3_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_eth_gen_mon_3_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:47 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:47 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_3/sim/address_decode_eth_gen_mon_3.vhd -work address_decode_eth_gen_mon_3 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_eth_gen_mon_3 # -- Compiling architecture rtl of address_decode_eth_gen_mon_3 # -- Loading package vl_types # -- Loading entity address_decode_eth_gen_mon_3_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:47 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:47 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_4/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_4_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_eth_gen_mon_4_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_eth_gen_mon_4_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:47 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:47 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_4/sim/address_decode_eth_gen_mon_4.vhd -work address_decode_eth_gen_mon_4 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_eth_gen_mon_4 # -- Compiling architecture rtl of address_decode_eth_gen_mon_4 # -- Loading package vl_types # -- Loading entity address_decode_eth_gen_mon_4_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:47 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:47 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_5/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_5_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_eth_gen_mon_5_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_eth_gen_mon_5_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:47 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:47 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_5/sim/address_decode_eth_gen_mon_5.vhd -work address_decode_eth_gen_mon_5 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_eth_gen_mon_5 # -- Compiling architecture rtl of address_decode_eth_gen_mon_5 # -- Loading package vl_types # -- Loading entity address_decode_eth_gen_mon_5_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:48 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:48 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_6/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_6_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_eth_gen_mon_6_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_eth_gen_mon_6_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:48 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:48 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_6/sim/address_decode_eth_gen_mon_6.vhd -work address_decode_eth_gen_mon_6 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_eth_gen_mon_6 # -- Compiling architecture rtl of address_decode_eth_gen_mon_6 # -- Loading package vl_types # -- Loading entity address_decode_eth_gen_mon_6_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:48 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:48 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_7/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_7_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_eth_gen_mon_7_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_eth_gen_mon_7_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:48 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:48 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_7/sim/address_decode_eth_gen_mon_7.vhd -work address_decode_eth_gen_mon_7 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_eth_gen_mon_7 # -- Compiling architecture rtl of address_decode_eth_gen_mon_7 # -- Loading package vl_types # -- Loading entity address_decode_eth_gen_mon_7_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:48 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:48 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_8/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_8_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_eth_gen_mon_8_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_eth_gen_mon_8_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:48 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:48 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_8/sim/address_decode_eth_gen_mon_8.vhd -work address_decode_eth_gen_mon_8 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_eth_gen_mon_8 # -- Compiling architecture rtl of address_decode_eth_gen_mon_8 # -- Loading package vl_types # -- Loading entity address_decode_eth_gen_mon_8_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:48 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:48 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_9/altera_merlin_slave_translator_191/sim/address_decode_eth_gen_mon_9_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_eth_gen_mon_9_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_eth_gen_mon_9_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:48 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:48 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_eth_gen_mon_9/sim/address_decode_eth_gen_mon_9.vhd -work address_decode_eth_gen_mon_9 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_eth_gen_mon_9 # -- Compiling architecture rtl of address_decode_eth_gen_mon_9 # -- Loading package vl_types # -- Loading entity address_decode_eth_gen_mon_9_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:49 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:49 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.v -work altera_jtag_dc_streaming_191 # -- Compiling module altera_avalon_st_jtag_interface # # Top level modules: # altera_avalon_st_jtag_interface # End time: 11:25:49 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:49 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_jtag_dc_streaming.v -work altera_jtag_dc_streaming_191 # -- Compiling module altera_jtag_control_signal_crosser # -- Compiling module altera_jtag_src_crosser # -- Compiling module altera_jtag_dc_streaming # # Top level modules: # altera_jtag_dc_streaming # End time: 11:25:49 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:49 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_jtag_sld_node.v -work altera_jtag_dc_streaming_191 # -- Compiling module altera_jtag_sld_node # # Top level modules: # altera_jtag_sld_node # End time: 11:25:49 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:49 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_jtag_streaming.v -work altera_jtag_dc_streaming_191 # -- Compiling module altera_jtag_streaming # # Top level modules: # altera_jtag_streaming # End time: 11:25:49 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:49 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_avalon_st_clock_crosser.v -work altera_jtag_dc_streaming_191 # -- Compiling module altera_avalon_st_clock_crosser # # Top level modules: # altera_avalon_st_clock_crosser # End time: 11:25:49 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:49 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_std_synchronizer_nocut.v -work altera_jtag_dc_streaming_191 # -- Compiling module altera_std_synchronizer_nocut # # Top level modules: # altera_std_synchronizer_nocut # End time: 11:25:49 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:49 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_base.v -work altera_jtag_dc_streaming_191 # -- Compiling module altera_avalon_st_pipeline_base # # Top level modules: # altera_avalon_st_pipeline_base # End time: 11:25:49 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:49 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_remover.v -work altera_jtag_dc_streaming_191 # -- Compiling module altera_avalon_st_idle_remover # # Top level modules: # altera_avalon_st_idle_remover # End time: 11:25:49 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:49 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_inserter.v -work altera_jtag_dc_streaming_191 # -- Compiling module altera_avalon_st_idle_inserter # # Top level modules: # altera_avalon_st_idle_inserter # End time: 11:25:49 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:49 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_stage.sv -work altera_jtag_dc_streaming_191 # -- Compiling module altera_avalon_st_pipeline_stage # # Top level modules: # altera_avalon_st_pipeline_stage # End time: 11:25:49 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:49 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/timing_adapter_191/sim/address_decode_master_0_timing_adapter_191_rrgemwi.sv -work timing_adapter_191 # -- Compiling module address_decode_master_0_timing_adapter_191_rrgemwi # # Top level modules: # address_decode_master_0_timing_adapter_191_rrgemwi # End time: 11:25:49 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:50 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_avalon_sc_fifo_191/sim/address_decode_master_0_altera_avalon_sc_fifo_191_e5eqkcq.v -work altera_avalon_sc_fifo_191 # -- Compiling module address_decode_master_0_altera_avalon_sc_fifo_191_e5eqkcq # # Top level modules: # address_decode_master_0_altera_avalon_sc_fifo_191_e5eqkcq # End time: 11:25:50 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:50 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_avalon_st_bytes_to_packets_191/sim/altera_avalon_st_bytes_to_packets.v -work altera_avalon_st_bytes_to_packets_191 # -- Compiling module altera_avalon_st_bytes_to_packets # # Top level modules: # altera_avalon_st_bytes_to_packets # End time: 11:25:50 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:50 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_avalon_st_packets_to_bytes_191/sim/altera_avalon_st_packets_to_bytes.v -work altera_avalon_st_packets_to_bytes_191 # -- Compiling module altera_avalon_st_packets_to_bytes # # Top level modules: # altera_avalon_st_packets_to_bytes # End time: 11:25:50 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:50 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_avalon_packets_to_master_191/sim/altera_avalon_packets_to_master.v -work altera_avalon_packets_to_master_191 # -- Compiling module altera_avalon_packets_to_master # -- Compiling module packets_to_fifo # -- Compiling module fifo_buffer_single_clock_fifo # -- Compiling module fifo_buffer_scfifo_with_controls # -- Compiling module fifo_buffer # -- Compiling module fifo_to_packet # -- Compiling module packets_to_master # # Top level modules: # altera_avalon_packets_to_master # End time: 11:25:50 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:50 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/channel_adapter_191/sim/address_decode_master_0_channel_adapter_191_uc27kqq.sv -work channel_adapter_191 # -- Compiling module address_decode_master_0_channel_adapter_191_uc27kqq # # Top level modules: # address_decode_master_0_channel_adapter_191_uc27kqq # End time: 11:25:50 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:50 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/channel_adapter_191/sim/address_decode_master_0_channel_adapter_191_cco4x3a.sv -work channel_adapter_191 # -- Compiling module address_decode_master_0_channel_adapter_191_cco4x3a # # Top level modules: # address_decode_master_0_channel_adapter_191_cco4x3a # End time: 11:25:50 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:50 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_reset_controller_191/sim/mentor/altera_reset_controller.v -work altera_reset_controller_191 # # Top level modules: # End time: 11:25:50 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:50 on Mar 19,2020 # vlog ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_reset_controller_191/sim/mentor/altera_reset_synchronizer.v -work altera_reset_controller_191 # # Top level modules: # End time: 11:25:50 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:50 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_avalon_master_191/sim/address_decode_master_0_altera_jtag_avalon_master_191_3zppvky.vhd -work altera_jtag_avalon_master_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_master_0_altera_jtag_avalon_master_191_3zppvky # -- Compiling architecture rtl of address_decode_master_0_altera_jtag_avalon_master_191_3zppvky # -- Loading package vl_types # -- Loading entity altera_avalon_st_jtag_interface # -- Loading entity address_decode_master_0_timing_adapter_191_rrgemwi # -- Loading entity address_decode_master_0_altera_avalon_sc_fifo_191_e5eqkcq # -- Loading entity altera_avalon_st_bytes_to_packets # -- Loading entity altera_avalon_st_packets_to_bytes # -- Loading entity altera_avalon_packets_to_master # -- Loading entity address_decode_master_0_channel_adapter_191_uc27kqq # -- Loading entity address_decode_master_0_channel_adapter_191_cco4x3a # End time: 11:25:51 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:51 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/sim/address_decode_master_0.vhd -work address_decode_master_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_master_0 # -- Compiling architecture rtl of address_decode_master_0 # -- Loading entity address_decode_master_0_altera_jtag_avalon_master_191_3zppvky # End time: 11:25:51 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:51 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_merlin_master_translator_0/altera_merlin_master_translator_191/sim/address_decode_merlin_master_translator_0_altera_merlin_master_translator_191_g7h47bq.sv -work altera_merlin_master_translator_191 # -- Compiling module address_decode_merlin_master_translator_0_altera_merlin_master_translator_191_g7h47bq # # Top level modules: # address_decode_merlin_master_translator_0_altera_merlin_master_translator_191_g7h47bq # End time: 11:25:51 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:51 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_merlin_master_translator_0/sim/address_decode_merlin_master_translator_0.vhd -work address_decode_merlin_master_translator_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_merlin_master_translator_0 # -- Compiling architecture rtl of address_decode_merlin_master_translator_0 # -- Loading package vl_types # -- Loading entity address_decode_merlin_master_translator_0_altera_merlin_master_translator_191_g7h47bq # End time: 11:25:51 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:51 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_0/altera_merlin_slave_translator_191/sim/address_decode_mm_to_mac_0_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_mac_0_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_mac_0_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:51 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:52 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_0/sim/address_decode_mm_to_mac_0.vhd -work address_decode_mm_to_mac_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_mac_0 # -- Compiling architecture rtl of address_decode_mm_to_mac_0 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_mac_0_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:52 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:52 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_1/altera_merlin_slave_translator_191/sim/address_decode_mm_to_mac_1_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_mac_1_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_mac_1_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:52 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:52 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_1/sim/address_decode_mm_to_mac_1.vhd -work address_decode_mm_to_mac_1 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_mac_1 # -- Compiling architecture rtl of address_decode_mm_to_mac_1 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_mac_1_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:52 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:52 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_10/altera_merlin_slave_translator_191/sim/address_decode_mm_to_mac_10_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_mac_10_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_mac_10_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:52 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:52 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_10/sim/address_decode_mm_to_mac_10.vhd -work address_decode_mm_to_mac_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_mac_10 # -- Compiling architecture rtl of address_decode_mm_to_mac_10 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_mac_10_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:52 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:52 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_11/altera_merlin_slave_translator_191/sim/address_decode_mm_to_mac_11_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_mac_11_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_mac_11_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:52 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:52 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_11/sim/address_decode_mm_to_mac_11.vhd -work address_decode_mm_to_mac_11 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_mac_11 # -- Compiling architecture rtl of address_decode_mm_to_mac_11 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_mac_11_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:52 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:52 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_2/altera_merlin_slave_translator_191/sim/address_decode_mm_to_mac_2_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_mac_2_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_mac_2_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:53 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:53 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_2/sim/address_decode_mm_to_mac_2.vhd -work address_decode_mm_to_mac_2 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_mac_2 # -- Compiling architecture rtl of address_decode_mm_to_mac_2 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_mac_2_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:53 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:53 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_3/altera_merlin_slave_translator_191/sim/address_decode_mm_to_mac_3_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_mac_3_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_mac_3_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:53 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:53 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_3/sim/address_decode_mm_to_mac_3.vhd -work address_decode_mm_to_mac_3 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_mac_3 # -- Compiling architecture rtl of address_decode_mm_to_mac_3 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_mac_3_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:53 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:53 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_4/altera_merlin_slave_translator_191/sim/address_decode_mm_to_mac_4_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_mac_4_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_mac_4_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:53 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:53 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_4/sim/address_decode_mm_to_mac_4.vhd -work address_decode_mm_to_mac_4 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_mac_4 # -- Compiling architecture rtl of address_decode_mm_to_mac_4 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_mac_4_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:53 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:53 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_5/altera_merlin_slave_translator_191/sim/address_decode_mm_to_mac_5_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_mac_5_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_mac_5_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:53 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:53 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_5/sim/address_decode_mm_to_mac_5.vhd -work address_decode_mm_to_mac_5 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_mac_5 # -- Compiling architecture rtl of address_decode_mm_to_mac_5 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_mac_5_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:53 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:53 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_6/altera_merlin_slave_translator_191/sim/address_decode_mm_to_mac_6_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_mac_6_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_mac_6_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:54 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:54 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_6/sim/address_decode_mm_to_mac_6.vhd -work address_decode_mm_to_mac_6 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_mac_6 # -- Compiling architecture rtl of address_decode_mm_to_mac_6 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_mac_6_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:54 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:54 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_7/altera_merlin_slave_translator_191/sim/address_decode_mm_to_mac_7_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_mac_7_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_mac_7_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:54 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:54 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_7/sim/address_decode_mm_to_mac_7.vhd -work address_decode_mm_to_mac_7 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_mac_7 # -- Compiling architecture rtl of address_decode_mm_to_mac_7 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_mac_7_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:54 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:54 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_8/altera_merlin_slave_translator_191/sim/address_decode_mm_to_mac_8_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_mac_8_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_mac_8_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:54 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:54 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_8/sim/address_decode_mm_to_mac_8.vhd -work address_decode_mm_to_mac_8 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_mac_8 # -- Compiling architecture rtl of address_decode_mm_to_mac_8 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_mac_8_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:54 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:54 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_9/altera_merlin_slave_translator_191/sim/address_decode_mm_to_mac_9_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_mac_9_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_mac_9_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:54 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:54 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_mac_9/sim/address_decode_mm_to_mac_9.vhd -work address_decode_mm_to_mac_9 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_mac_9 # -- Compiling architecture rtl of address_decode_mm_to_mac_9 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_mac_9_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:54 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:55 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_0/altera_merlin_slave_translator_191/sim/address_decode_mm_to_phy_0_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_phy_0_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_phy_0_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:55 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:55 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_0/sim/address_decode_mm_to_phy_0.vhd -work address_decode_mm_to_phy_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_phy_0 # -- Compiling architecture rtl of address_decode_mm_to_phy_0 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_phy_0_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:55 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:55 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_1/altera_merlin_slave_translator_191/sim/address_decode_mm_to_phy_1_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_phy_1_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_phy_1_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:55 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:55 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_1/sim/address_decode_mm_to_phy_1.vhd -work address_decode_mm_to_phy_1 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_phy_1 # -- Compiling architecture rtl of address_decode_mm_to_phy_1 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_phy_1_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:55 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:55 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_10/altera_merlin_slave_translator_191/sim/address_decode_mm_to_phy_10_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_phy_10_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_phy_10_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:55 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:55 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_10/sim/address_decode_mm_to_phy_10.vhd -work address_decode_mm_to_phy_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_phy_10 # -- Compiling architecture rtl of address_decode_mm_to_phy_10 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_phy_10_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:55 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:55 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_11/altera_merlin_slave_translator_191/sim/address_decode_mm_to_phy_11_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_phy_11_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_phy_11_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:55 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:55 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_11/sim/address_decode_mm_to_phy_11.vhd -work address_decode_mm_to_phy_11 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_phy_11 # -- Compiling architecture rtl of address_decode_mm_to_phy_11 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_phy_11_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:56 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:56 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_2/altera_merlin_slave_translator_191/sim/address_decode_mm_to_phy_2_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_phy_2_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_phy_2_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:56 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:56 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_2/sim/address_decode_mm_to_phy_2.vhd -work address_decode_mm_to_phy_2 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_phy_2 # -- Compiling architecture rtl of address_decode_mm_to_phy_2 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_phy_2_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:56 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:56 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_3/altera_merlin_slave_translator_191/sim/address_decode_mm_to_phy_3_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_phy_3_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_phy_3_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:56 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:56 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_3/sim/address_decode_mm_to_phy_3.vhd -work address_decode_mm_to_phy_3 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_phy_3 # -- Compiling architecture rtl of address_decode_mm_to_phy_3 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_phy_3_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:56 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:56 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_4/altera_merlin_slave_translator_191/sim/address_decode_mm_to_phy_4_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_phy_4_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_phy_4_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:56 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:56 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_4/sim/address_decode_mm_to_phy_4.vhd -work address_decode_mm_to_phy_4 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_phy_4 # -- Compiling architecture rtl of address_decode_mm_to_phy_4 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_phy_4_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:56 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:56 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_5/altera_merlin_slave_translator_191/sim/address_decode_mm_to_phy_5_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_phy_5_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_phy_5_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:56 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:56 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_5/sim/address_decode_mm_to_phy_5.vhd -work address_decode_mm_to_phy_5 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_phy_5 # -- Compiling architecture rtl of address_decode_mm_to_phy_5 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_phy_5_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:57 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:57 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_6/altera_merlin_slave_translator_191/sim/address_decode_mm_to_phy_6_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_phy_6_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_phy_6_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:57 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:57 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_6/sim/address_decode_mm_to_phy_6.vhd -work address_decode_mm_to_phy_6 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_phy_6 # -- Compiling architecture rtl of address_decode_mm_to_phy_6 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_phy_6_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:57 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:57 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_7/altera_merlin_slave_translator_191/sim/address_decode_mm_to_phy_7_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_phy_7_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_phy_7_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:57 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:57 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_7/sim/address_decode_mm_to_phy_7.vhd -work address_decode_mm_to_phy_7 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_phy_7 # -- Compiling architecture rtl of address_decode_mm_to_phy_7 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_phy_7_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:57 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:57 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_8/altera_merlin_slave_translator_191/sim/address_decode_mm_to_phy_8_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_phy_8_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_phy_8_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:57 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:57 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_8/sim/address_decode_mm_to_phy_8.vhd -work address_decode_mm_to_phy_8 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_phy_8 # -- Compiling architecture rtl of address_decode_mm_to_phy_8 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_phy_8_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:57 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:57 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_9/altera_merlin_slave_translator_191/sim/address_decode_mm_to_phy_9_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_mm_to_phy_9_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_mm_to_phy_9_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:58 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:58 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_mm_to_phy_9/sim/address_decode_mm_to_phy_9.vhd -work address_decode_mm_to_phy_9 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_mm_to_phy_9 # -- Compiling architecture rtl of address_decode_mm_to_phy_9 # -- Loading package vl_types # -- Loading entity address_decode_mm_to_phy_9_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:58 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:58 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_0/altera_merlin_slave_translator_191/sim/address_decode_rx_sc_fifo_0_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_rx_sc_fifo_0_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_rx_sc_fifo_0_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:58 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:58 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_0/sim/address_decode_rx_sc_fifo_0.vhd -work address_decode_rx_sc_fifo_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_sc_fifo_0 # -- Compiling architecture rtl of address_decode_rx_sc_fifo_0 # -- Loading package vl_types # -- Loading entity address_decode_rx_sc_fifo_0_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:58 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:58 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_1/altera_merlin_slave_translator_191/sim/address_decode_rx_sc_fifo_1_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_rx_sc_fifo_1_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_rx_sc_fifo_1_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:58 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:58 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_1/sim/address_decode_rx_sc_fifo_1.vhd -work address_decode_rx_sc_fifo_1 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_sc_fifo_1 # -- Compiling architecture rtl of address_decode_rx_sc_fifo_1 # -- Loading package vl_types # -- Loading entity address_decode_rx_sc_fifo_1_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:58 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:58 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_10/altera_merlin_slave_translator_191/sim/address_decode_rx_sc_fifo_10_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_rx_sc_fifo_10_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_rx_sc_fifo_10_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:58 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:58 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_10/sim/address_decode_rx_sc_fifo_10.vhd -work address_decode_rx_sc_fifo_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_sc_fifo_10 # -- Compiling architecture rtl of address_decode_rx_sc_fifo_10 # -- Loading package vl_types # -- Loading entity address_decode_rx_sc_fifo_10_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:58 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:58 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_11/altera_merlin_slave_translator_191/sim/address_decode_rx_sc_fifo_11_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_rx_sc_fifo_11_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_rx_sc_fifo_11_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:59 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:59 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_11/sim/address_decode_rx_sc_fifo_11.vhd -work address_decode_rx_sc_fifo_11 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_sc_fifo_11 # -- Compiling architecture rtl of address_decode_rx_sc_fifo_11 # -- Loading package vl_types # -- Loading entity address_decode_rx_sc_fifo_11_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:59 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:59 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_2/altera_merlin_slave_translator_191/sim/address_decode_rx_sc_fifo_2_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_rx_sc_fifo_2_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_rx_sc_fifo_2_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:59 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:59 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_2/sim/address_decode_rx_sc_fifo_2.vhd -work address_decode_rx_sc_fifo_2 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_sc_fifo_2 # -- Compiling architecture rtl of address_decode_rx_sc_fifo_2 # -- Loading package vl_types # -- Loading entity address_decode_rx_sc_fifo_2_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:59 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:59 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_3/altera_merlin_slave_translator_191/sim/address_decode_rx_sc_fifo_3_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_rx_sc_fifo_3_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_rx_sc_fifo_3_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:59 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:59 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_3/sim/address_decode_rx_sc_fifo_3.vhd -work address_decode_rx_sc_fifo_3 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_sc_fifo_3 # -- Compiling architecture rtl of address_decode_rx_sc_fifo_3 # -- Loading package vl_types # -- Loading entity address_decode_rx_sc_fifo_3_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:59 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:59 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_4/altera_merlin_slave_translator_191/sim/address_decode_rx_sc_fifo_4_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_rx_sc_fifo_4_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_rx_sc_fifo_4_altera_merlin_slave_translator_191_x56fcki # End time: 11:25:59 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:25:59 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_4/sim/address_decode_rx_sc_fifo_4.vhd -work address_decode_rx_sc_fifo_4 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_sc_fifo_4 # -- Compiling architecture rtl of address_decode_rx_sc_fifo_4 # -- Loading package vl_types # -- Loading entity address_decode_rx_sc_fifo_4_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:00 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:00 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_5/altera_merlin_slave_translator_191/sim/address_decode_rx_sc_fifo_5_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_rx_sc_fifo_5_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_rx_sc_fifo_5_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:00 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:00 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_5/sim/address_decode_rx_sc_fifo_5.vhd -work address_decode_rx_sc_fifo_5 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_sc_fifo_5 # -- Compiling architecture rtl of address_decode_rx_sc_fifo_5 # -- Loading package vl_types # -- Loading entity address_decode_rx_sc_fifo_5_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:00 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:00 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_6/altera_merlin_slave_translator_191/sim/address_decode_rx_sc_fifo_6_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_rx_sc_fifo_6_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_rx_sc_fifo_6_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:00 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:00 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_6/sim/address_decode_rx_sc_fifo_6.vhd -work address_decode_rx_sc_fifo_6 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_sc_fifo_6 # -- Compiling architecture rtl of address_decode_rx_sc_fifo_6 # -- Loading package vl_types # -- Loading entity address_decode_rx_sc_fifo_6_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:00 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:00 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_7/altera_merlin_slave_translator_191/sim/address_decode_rx_sc_fifo_7_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_rx_sc_fifo_7_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_rx_sc_fifo_7_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:00 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:00 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_7/sim/address_decode_rx_sc_fifo_7.vhd -work address_decode_rx_sc_fifo_7 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_sc_fifo_7 # -- Compiling architecture rtl of address_decode_rx_sc_fifo_7 # -- Loading package vl_types # -- Loading entity address_decode_rx_sc_fifo_7_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:00 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:00 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_8/altera_merlin_slave_translator_191/sim/address_decode_rx_sc_fifo_8_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_rx_sc_fifo_8_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_rx_sc_fifo_8_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:00 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:01 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_8/sim/address_decode_rx_sc_fifo_8.vhd -work address_decode_rx_sc_fifo_8 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_sc_fifo_8 # -- Compiling architecture rtl of address_decode_rx_sc_fifo_8 # -- Loading package vl_types # -- Loading entity address_decode_rx_sc_fifo_8_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:01 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:01 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_9/altera_merlin_slave_translator_191/sim/address_decode_rx_sc_fifo_9_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_rx_sc_fifo_9_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_rx_sc_fifo_9_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:01 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:01 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_sc_fifo_9/sim/address_decode_rx_sc_fifo_9.vhd -work address_decode_rx_sc_fifo_9 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_sc_fifo_9 # -- Compiling architecture rtl of address_decode_rx_sc_fifo_9 # -- Loading package vl_types # -- Loading entity address_decode_rx_sc_fifo_9_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:01 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:01 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_rx_xcvr_clk/sim/address_decode_rx_xcvr_clk.vhd -work address_decode_rx_xcvr_clk # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_rx_xcvr_clk # -- Compiling architecture rtl of address_decode_rx_xcvr_clk # End time: 11:26:01 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:01 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_0/altera_merlin_slave_translator_191/sim/address_decode_tx_sc_fifo_0_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_tx_sc_fifo_0_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_tx_sc_fifo_0_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:01 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:01 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_0/sim/address_decode_tx_sc_fifo_0.vhd -work address_decode_tx_sc_fifo_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_sc_fifo_0 # -- Compiling architecture rtl of address_decode_tx_sc_fifo_0 # -- Loading package vl_types # -- Loading entity address_decode_tx_sc_fifo_0_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:01 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:01 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_1/altera_merlin_slave_translator_191/sim/address_decode_tx_sc_fifo_1_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_tx_sc_fifo_1_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_tx_sc_fifo_1_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:01 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:01 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_1/sim/address_decode_tx_sc_fifo_1.vhd -work address_decode_tx_sc_fifo_1 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_sc_fifo_1 # -- Compiling architecture rtl of address_decode_tx_sc_fifo_1 # -- Loading package vl_types # -- Loading entity address_decode_tx_sc_fifo_1_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:02 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:02 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_10/altera_merlin_slave_translator_191/sim/address_decode_tx_sc_fifo_10_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_tx_sc_fifo_10_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_tx_sc_fifo_10_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:02 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:02 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_10/sim/address_decode_tx_sc_fifo_10.vhd -work address_decode_tx_sc_fifo_10 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_sc_fifo_10 # -- Compiling architecture rtl of address_decode_tx_sc_fifo_10 # -- Loading package vl_types # -- Loading entity address_decode_tx_sc_fifo_10_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:02 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:02 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_11/altera_merlin_slave_translator_191/sim/address_decode_tx_sc_fifo_11_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_tx_sc_fifo_11_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_tx_sc_fifo_11_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:02 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:02 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_11/sim/address_decode_tx_sc_fifo_11.vhd -work address_decode_tx_sc_fifo_11 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_sc_fifo_11 # -- Compiling architecture rtl of address_decode_tx_sc_fifo_11 # -- Loading package vl_types # -- Loading entity address_decode_tx_sc_fifo_11_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:02 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:02 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_2/altera_merlin_slave_translator_191/sim/address_decode_tx_sc_fifo_2_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_tx_sc_fifo_2_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_tx_sc_fifo_2_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:02 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:02 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_2/sim/address_decode_tx_sc_fifo_2.vhd -work address_decode_tx_sc_fifo_2 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_sc_fifo_2 # -- Compiling architecture rtl of address_decode_tx_sc_fifo_2 # -- Loading package vl_types # -- Loading entity address_decode_tx_sc_fifo_2_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:02 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:02 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_3/altera_merlin_slave_translator_191/sim/address_decode_tx_sc_fifo_3_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_tx_sc_fifo_3_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_tx_sc_fifo_3_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:02 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:02 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_3/sim/address_decode_tx_sc_fifo_3.vhd -work address_decode_tx_sc_fifo_3 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_sc_fifo_3 # -- Compiling architecture rtl of address_decode_tx_sc_fifo_3 # -- Loading package vl_types # -- Loading entity address_decode_tx_sc_fifo_3_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:03 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:03 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_4/altera_merlin_slave_translator_191/sim/address_decode_tx_sc_fifo_4_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_tx_sc_fifo_4_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_tx_sc_fifo_4_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:03 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:03 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_4/sim/address_decode_tx_sc_fifo_4.vhd -work address_decode_tx_sc_fifo_4 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_sc_fifo_4 # -- Compiling architecture rtl of address_decode_tx_sc_fifo_4 # -- Loading package vl_types # -- Loading entity address_decode_tx_sc_fifo_4_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:03 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:03 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_5/altera_merlin_slave_translator_191/sim/address_decode_tx_sc_fifo_5_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_tx_sc_fifo_5_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_tx_sc_fifo_5_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:03 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:03 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_5/sim/address_decode_tx_sc_fifo_5.vhd -work address_decode_tx_sc_fifo_5 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_sc_fifo_5 # -- Compiling architecture rtl of address_decode_tx_sc_fifo_5 # -- Loading package vl_types # -- Loading entity address_decode_tx_sc_fifo_5_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:03 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:03 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_6/altera_merlin_slave_translator_191/sim/address_decode_tx_sc_fifo_6_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_tx_sc_fifo_6_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_tx_sc_fifo_6_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:03 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:03 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_6/sim/address_decode_tx_sc_fifo_6.vhd -work address_decode_tx_sc_fifo_6 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_sc_fifo_6 # -- Compiling architecture rtl of address_decode_tx_sc_fifo_6 # -- Loading package vl_types # -- Loading entity address_decode_tx_sc_fifo_6_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:03 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:03 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_7/altera_merlin_slave_translator_191/sim/address_decode_tx_sc_fifo_7_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_tx_sc_fifo_7_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_tx_sc_fifo_7_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:03 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:03 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_7/sim/address_decode_tx_sc_fifo_7.vhd -work address_decode_tx_sc_fifo_7 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_sc_fifo_7 # -- Compiling architecture rtl of address_decode_tx_sc_fifo_7 # -- Loading package vl_types # -- Loading entity address_decode_tx_sc_fifo_7_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:04 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:04 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_8/altera_merlin_slave_translator_191/sim/address_decode_tx_sc_fifo_8_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_tx_sc_fifo_8_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_tx_sc_fifo_8_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:04 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:04 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_8/sim/address_decode_tx_sc_fifo_8.vhd -work address_decode_tx_sc_fifo_8 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_sc_fifo_8 # -- Compiling architecture rtl of address_decode_tx_sc_fifo_8 # -- Loading package vl_types # -- Loading entity address_decode_tx_sc_fifo_8_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:04 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:04 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_9/altera_merlin_slave_translator_191/sim/address_decode_tx_sc_fifo_9_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_tx_sc_fifo_9_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_tx_sc_fifo_9_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:04 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:04 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_sc_fifo_9/sim/address_decode_tx_sc_fifo_9.vhd -work address_decode_tx_sc_fifo_9 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_sc_fifo_9 # -- Compiling architecture rtl of address_decode_tx_sc_fifo_9 # -- Loading package vl_types # -- Loading entity address_decode_tx_sc_fifo_9_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:04 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:04 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_xcvr_clk/sim/address_decode_tx_xcvr_clk.vhd -work address_decode_tx_xcvr_clk # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_xcvr_clk # -- Compiling architecture rtl of address_decode_tx_xcvr_clk # End time: 11:26:04 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:04 on Mar 19,2020 # vcom ../../../rtl/address_decoder/ip/address_decode/address_decode_tx_xcvr_half_clk/sim/address_decode_tx_xcvr_half_clk.vhd -work address_decode_tx_xcvr_half_clk # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_tx_xcvr_half_clk # -- Compiling architecture rtl of address_decode_tx_xcvr_half_clk # End time: 11:26:04 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:04 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_master_translator_191/sim/address_decode_altera_merlin_master_translator_191_g7h47bq.sv -work altera_merlin_master_translator_191 # -- Compiling module address_decode_altera_merlin_master_translator_191_g7h47bq # # Top level modules: # address_decode_altera_merlin_master_translator_191_g7h47bq # End time: 11:26:04 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:04 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_slave_translator_191/sim/address_decode_altera_merlin_slave_translator_191_x56fcki.sv -work altera_merlin_slave_translator_191 # -- Compiling module address_decode_altera_merlin_slave_translator_191_x56fcki # # Top level modules: # address_decode_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:04 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:04 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_master_agent_191/sim/address_decode_altera_merlin_master_agent_191_mpbm6tq.sv -work altera_merlin_master_agent_191 # -- Compiling module address_decode_altera_merlin_master_agent_191_mpbm6tq # # Top level modules: # address_decode_altera_merlin_master_agent_191_mpbm6tq # End time: 11:26:05 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:05 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_slave_agent_191/sim/address_decode_altera_merlin_slave_agent_191_ncfkfri.sv -work altera_merlin_slave_agent_191 # -- Compiling module address_decode_altera_merlin_slave_agent_191_ncfkfri # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_slave_agent_191/sim/address_decode_altera_merlin_slave_agent_191_ncfkfri.sv(659): (vlog-2186) SystemVerilog testbench feature # (randomization, coverage or assertion) detected in the design. # These features are only supported in Questasim. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_slave_agent_191/sim/address_decode_altera_merlin_slave_agent_191_ncfkfri.sv(510): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_slave_agent_191/sim/address_decode_altera_merlin_slave_agent_191_ncfkfri.sv(511): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_slave_agent_191/sim/address_decode_altera_merlin_slave_agent_191_ncfkfri.sv(512): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_slave_agent_191/sim/address_decode_altera_merlin_slave_agent_191_ncfkfri.sv(513): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_slave_agent_191/sim/address_decode_altera_merlin_slave_agent_191_ncfkfri.sv(28): (vlog-2186) SystemVerilog testbench feature # (randomization, coverage or assertion) detected in the design. # These features are only supported in Questasim. # # Top level modules: # address_decode_altera_merlin_slave_agent_191_ncfkfri # End time: 11:26:05 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 6 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:05 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_slave_agent_191/sim/altera_merlin_burst_uncompressor.sv -work altera_merlin_slave_agent_191 # -- Compiling module altera_merlin_burst_uncompressor # # Top level modules: # altera_merlin_burst_uncompressor # End time: 11:26:05 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:05 on Mar 19,2020 # vlog ../../../rtl/address_decoder/address_decode/altera_avalon_sc_fifo_191/sim/address_decode_altera_avalon_sc_fifo_191_e5eqkcq.v -work altera_avalon_sc_fifo_191 # -- Compiling module address_decode_altera_avalon_sc_fifo_191_e5eqkcq # # Top level modules: # address_decode_altera_avalon_sc_fifo_191_e5eqkcq # End time: 11:26:05 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:05 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_router_191/sim/address_decode_altera_merlin_router_191_prlkaiy.sv -work altera_merlin_router_191 # -- Compiling module address_decode_altera_merlin_router_191_prlkaiy_default_decode # -- Compiling module address_decode_altera_merlin_router_191_prlkaiy # # Top level modules: # address_decode_altera_merlin_router_191_prlkaiy # End time: 11:26:05 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:05 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_router_191/sim/address_decode_altera_merlin_router_191_anzw7xi.sv -work altera_merlin_router_191 # -- Compiling module address_decode_altera_merlin_router_191_anzw7xi_default_decode # -- Compiling module address_decode_altera_merlin_router_191_anzw7xi # # Top level modules: # address_decode_altera_merlin_router_191_anzw7xi # End time: 11:26:05 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:05 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_5qlhcyq.vhd -work altera_merlin_traffic_limiter_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_altera_merlin_traffic_limiter_191_5qlhcyq # -- Compiling architecture rtl of address_decode_altera_merlin_traffic_limiter_191_5qlhcyq # -- Loading package vl_types # -- Loading entity address_decode_altera_avalon_sc_fifo_191_e5eqkcq # End time: 11:26:05 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:05 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/alt_hiconnect_sc_fifo_191/sim/address_decode_alt_hiconnect_sc_fifo_191_7qtmpqq.sv -work alt_hiconnect_sc_fifo_191 # -- Compiling module address_decode_alt_hiconnect_sc_fifo_191_7qtmpqq # # Top level modules: # address_decode_alt_hiconnect_sc_fifo_191_7qtmpqq # End time: 11:26:05 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:05 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/alt_hiconnect_sc_fifo_191/sim/alt_st_infer_scfifo.sv -work alt_hiconnect_sc_fifo_191 # -- Compiling module alt_st_infer_scfifo # # Top level modules: # alt_st_infer_scfifo # End time: 11:26:05 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:05 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo.sv -work alt_hiconnect_sc_fifo_191 # -- Compiling module alt_st_mlab_scfifo # # Top level modules: # alt_st_mlab_scfifo # End time: 11:26:05 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:05 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/alt_hiconnect_sc_fifo_191/sim/alt_st_fifo_empty.sv -work alt_hiconnect_sc_fifo_191 # -- Compiling module alt_st_fifo_empty # # Top level modules: # alt_st_fifo_empty # End time: 11:26:05 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:05 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo_a6.sv -work alt_hiconnect_sc_fifo_191 # -- Compiling module alt_st_mlab_scfifo_a6 # # Top level modules: # alt_st_mlab_scfifo_a6 # End time: 11:26:06 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:06 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo_a7.sv -work alt_hiconnect_sc_fifo_191 # -- Compiling module alt_st_mlab_scfifo_a7 # # Top level modules: # alt_st_mlab_scfifo_a7 # End time: 11:26:06 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:06 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/alt_hiconnect_sc_fifo_191/sim/alt_st_reg_scfifo.sv -work alt_hiconnect_sc_fifo_191 # -- Compiling module alt_st_reg_scfifo # # Top level modules: # alt_st_reg_scfifo # End time: 11:26:06 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:06 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_qib4nvi.vhd -work altera_merlin_traffic_limiter_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_altera_merlin_traffic_limiter_191_qib4nvi # -- Compiling architecture rtl of address_decode_altera_merlin_traffic_limiter_191_qib4nvi # -- Loading package vl_types # -- Loading entity address_decode_alt_hiconnect_sc_fifo_191_7qtmpqq # End time: 11:26:06 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:06 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/altera_merlin_reorder_memory.sv -work altera_merlin_traffic_limiter_191 # -- Compiling module altera_merlin_reorder_memory # -- Compiling module memory_pointer_controller # # Top level modules: # altera_merlin_reorder_memory # End time: 11:26:06 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:06 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/altera_avalon_st_pipeline_base.v -work altera_merlin_traffic_limiter_191 # -- Compiling module altera_avalon_st_pipeline_base # # Top level modules: # altera_avalon_st_pipeline_base # End time: 11:26:06 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:06 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv -work altera_merlin_traffic_limiter_191 # -- Compiling module address_decode_altera_merlin_traffic_limiter_191_kcba44q # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(611): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(702): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(703): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(704): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(705): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(706): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(707): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(712): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(714): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(717): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(718): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(744): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(746): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(747): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(748): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(749): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(750): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(755): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(757): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(760): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_traffic_limiter_191/sim/address_decode_altera_merlin_traffic_limiter_191_kcba44q.sv(761): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # # Top level modules: # address_decode_altera_merlin_traffic_limiter_191_kcba44q # End time: 11:26:06 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 21 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:06 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/address_decode_altera_merlin_burst_adapter_191_j2f5cla.sv -work altera_merlin_burst_adapter_191 # -- Compiling module address_decode_altera_merlin_burst_adapter_191_j2f5cla # # Top level modules: # address_decode_altera_merlin_burst_adapter_191_j2f5cla # End time: 11:26:06 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:06 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_uncmpr.sv -work altera_merlin_burst_adapter_191 # -- Compiling module altera_merlin_burst_adapter_uncompressed_only # # Top level modules: # altera_merlin_burst_adapter_uncompressed_only # End time: 11:26:06 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:06 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_13_1.sv -work altera_merlin_burst_adapter_191 # -- Compiling module altera_merlin_burst_adapter_burstwrap_increment # -- Compiling module altera_merlin_burst_adapter_adder # -- Compiling module altera_merlin_burst_adapter_subtractor # -- Compiling module altera_merlin_burst_adapter_min # -- Compiling module altera_merlin_burst_adapter_13_1 # # Top level modules: # altera_merlin_burst_adapter_13_1 # End time: 11:26:06 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:06 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv -work altera_merlin_burst_adapter_191 # -- Compiling module altera_merlin_burst_adapter_new # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(549): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(550): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(551): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(552): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(553): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(554): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(555): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(556): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(557): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(558): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(560): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(561): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(562): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(563): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(564): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(565): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(566): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(567): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(568): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(569): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(570): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(571): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(572): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(575): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(576): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(702): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(703): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(704): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(705): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(706): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(707): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(708): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(709): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(710): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(711): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(712): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(713): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(850): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(864): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(982): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(983): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(984): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(985): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(986): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(987): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(988): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(989): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1056): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1057): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1058): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1059): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1096): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1098): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1101): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1103): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1216): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1217): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1218): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1219): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1220): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1221): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1222): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1223): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1224): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1225): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1295): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1296): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1297): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1298): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1299): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1300): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1315): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1317): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1440): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1441): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1442): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1443): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1444): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1445): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1446): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1447): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1448): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1449): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1450): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1533): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1534): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1535): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1536): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1537): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1538): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1568): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_burst_adapter_new.sv(1571): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # # Top level modules: # altera_merlin_burst_adapter_new # End time: 11:26:07 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 92 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:07 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_incr_burst_converter.sv -work altera_merlin_burst_adapter_191 # -- Compiling module altera_incr_burst_converter # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_incr_burst_converter.sv(453): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_incr_burst_converter.sv(455): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_incr_burst_converter.sv(490): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_incr_burst_converter.sv(492): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # # Top level modules: # altera_incr_burst_converter # End time: 11:26:07 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 4 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:07 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_wrap_burst_converter.sv -work altera_merlin_burst_adapter_191 # -- Compiling module altera_wrap_burst_converter # # Top level modules: # altera_wrap_burst_converter # End time: 11:26:07 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:07 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_default_burst_converter.sv -work altera_merlin_burst_adapter_191 # -- Compiling module altera_default_burst_converter # ** Warning: ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_default_burst_converter.sv(130): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks. # # Top level modules: # altera_default_burst_converter # End time: 11:26:07 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:07 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_merlin_address_alignment.sv -work altera_merlin_burst_adapter_191 # -- Compiling module altera_merlin_address_alignment # # Top level modules: # altera_merlin_address_alignment # End time: 11:26:07 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:07 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_avalon_st_pipeline_stage.sv -work altera_merlin_burst_adapter_191 # -- Compiling module altera_avalon_st_pipeline_stage # # Top level modules: # altera_avalon_st_pipeline_stage # End time: 11:26:07 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:07 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_burst_adapter_191/sim/altera_avalon_st_pipeline_base.v -work altera_merlin_burst_adapter_191 # -- Compiling module altera_avalon_st_pipeline_base # # Top level modules: # altera_avalon_st_pipeline_base # End time: 11:26:07 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:07 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_demultiplexer_191/sim/address_decode_altera_merlin_demultiplexer_191_qlmvu7a.sv -work altera_merlin_demultiplexer_191 # -- Compiling module address_decode_altera_merlin_demultiplexer_191_qlmvu7a # # Top level modules: # address_decode_altera_merlin_demultiplexer_191_qlmvu7a # End time: 11:26:07 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:07 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_multiplexer_191/sim/address_decode_altera_merlin_multiplexer_191_6qc733q.sv -work altera_merlin_multiplexer_191 # -- Compiling module address_decode_altera_merlin_multiplexer_191_6qc733q # # Top level modules: # address_decode_altera_merlin_multiplexer_191_6qc733q # End time: 11:26:07 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:07 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv -work altera_merlin_multiplexer_191 # -- Compiling module altera_merlin_arbitrator # -- Compiling module altera_merlin_arb_adder # # Top level modules: # altera_merlin_arbitrator # End time: 11:26:07 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:07 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_demultiplexer_191/sim/address_decode_altera_merlin_demultiplexer_191_tqe34ei.sv -work altera_merlin_demultiplexer_191 # -- Compiling module address_decode_altera_merlin_demultiplexer_191_tqe34ei # # Top level modules: # address_decode_altera_merlin_demultiplexer_191_tqe34ei # End time: 11:26:07 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:07 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_multiplexer_191/sim/address_decode_altera_merlin_multiplexer_191_uq6phiq.sv -work altera_merlin_multiplexer_191 # -- Compiling module address_decode_altera_merlin_multiplexer_191_uq6phiq # # Top level modules: # address_decode_altera_merlin_multiplexer_191_uq6phiq # End time: 11:26:07 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:07 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv -work altera_merlin_multiplexer_191 # -- Compiling module altera_merlin_arbitrator # -- Compiling module altera_merlin_arb_adder # # Top level modules: # altera_merlin_arbitrator # End time: 11:26:08 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:08 on Mar 19,2020 # vlog ../../../rtl/address_decoder/address_decode/altera_avalon_st_handshake_clock_crosser_191/sim/address_decode_altera_avalon_st_handshake_clock_crosser_191_3vi6gwa.v -work altera_avalon_st_handshake_clock_crosser_191 # -- Compiling module address_decode_altera_avalon_st_handshake_clock_crosser_191_3vi6gwa # # Top level modules: # address_decode_altera_avalon_st_handshake_clock_crosser_191_3vi6gwa # End time: 11:26:08 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:08 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_avalon_st_handshake_clock_crosser_191/sim/altera_avalon_st_clock_crosser.v -work altera_avalon_st_handshake_clock_crosser_191 # -- Compiling module altera_avalon_st_clock_crosser # # Top level modules: # altera_avalon_st_clock_crosser # End time: 11:26:08 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:08 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_avalon_st_handshake_clock_crosser_191/sim/altera_avalon_st_pipeline_base.v -work altera_avalon_st_handshake_clock_crosser_191 # -- Compiling module altera_avalon_st_pipeline_base # # Top level modules: # altera_avalon_st_pipeline_base # End time: 11:26:08 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:08 on Mar 19,2020 # vlog -sv ../../../rtl/address_decoder/address_decode/altera_avalon_st_handshake_clock_crosser_191/sim/altera_std_synchronizer_nocut.v -work altera_avalon_st_handshake_clock_crosser_191 # -- Compiling module altera_std_synchronizer_nocut # # Top level modules: # altera_std_synchronizer_nocut # End time: 11:26:08 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:08 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_mm_interconnect_191/sim/address_decode_altera_mm_interconnect_191_xb26wyy_merlin_master_translator_0_avalon_universal_master_0_agent.vhd -work altera_mm_interconnect_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_altera_mm_interconnect_191_xb26wyy_merlin_master_translator_0_avalon_universal_master_0_agent # -- Compiling architecture rtl of address_decode_altera_mm_interconnect_191_xb26wyy_merlin_master_translator_0_avalon_universal_master_0_agent # -- Loading package vl_types # -- Loading entity address_decode_altera_merlin_master_agent_191_mpbm6tq # End time: 11:26:08 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:08 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_mm_interconnect_191/sim/address_decode_altera_mm_interconnect_191_xb26wyy_master_0_master_agent.vhd -work altera_mm_interconnect_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_altera_mm_interconnect_191_xb26wyy_master_0_master_agent # -- Compiling architecture rtl of address_decode_altera_mm_interconnect_191_xb26wyy_master_0_master_agent # -- Loading package vl_types # -- Loading entity address_decode_altera_merlin_master_agent_191_mpbm6tq # End time: 11:26:08 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:08 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_mm_interconnect_191/sim/address_decode_altera_mm_interconnect_191_xb26wyy_merlin_master_translator_0_avalon_universal_master_0_translator.vhd -work altera_mm_interconnect_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_altera_mm_interconnect_191_xb26wyy_merlin_master_translator_0_avalon_universal_master_0_translator # -- Compiling architecture rtl of address_decode_altera_mm_interconnect_191_xb26wyy_merlin_master_translator_0_avalon_universal_master_0_translator # -- Loading package vl_types # -- Loading entity address_decode_altera_merlin_master_translator_191_g7h47bq # End time: 11:26:08 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:08 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_mm_interconnect_191/sim/address_decode_altera_mm_interconnect_191_xb26wyy_master_0_master_translator.vhd -work altera_mm_interconnect_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_altera_mm_interconnect_191_xb26wyy_master_0_master_translator # -- Compiling architecture rtl of address_decode_altera_mm_interconnect_191_xb26wyy_master_0_master_translator # -- Loading package vl_types # -- Loading entity address_decode_altera_merlin_master_translator_191_g7h47bq # End time: 11:26:08 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:08 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_mm_interconnect_191/sim/address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_mac_0_avalon_universal_slave_0_agent_rsp_fifo.vhd -work altera_mm_interconnect_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_mac_0_avalon_universal_slave_0_agent_rsp_fifo # -- Compiling architecture rtl of address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_mac_0_avalon_universal_slave_0_agent_rsp_fifo # -- Loading package vl_types # -- Loading entity address_decode_altera_avalon_sc_fifo_191_e5eqkcq # End time: 11:26:09 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:09 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_mm_interconnect_191/sim/address_decode_altera_mm_interconnect_191_xb26wyy_tx_sc_fifo_0_avalon_universal_slave_0_agent_rdata_fifo.vhd -work altera_mm_interconnect_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_altera_mm_interconnect_191_xb26wyy_tx_sc_fifo_0_avalon_universal_slave_0_agent_rdata_fifo # -- Compiling architecture rtl of address_decode_altera_mm_interconnect_191_xb26wyy_tx_sc_fifo_0_avalon_universal_slave_0_agent_rdata_fifo # -- Loading package vl_types # -- Loading entity address_decode_altera_avalon_sc_fifo_191_e5eqkcq # End time: 11:26:09 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:09 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_mm_interconnect_191/sim/address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_mac_0_avalon_universal_slave_0_translator.vhd -work altera_mm_interconnect_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_mac_0_avalon_universal_slave_0_translator # -- Compiling architecture rtl of address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_mac_0_avalon_universal_slave_0_translator # -- Loading package vl_types # -- Loading entity address_decode_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:09 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:09 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_mm_interconnect_191/sim/address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_phy_0_avalon_universal_slave_0_translator.vhd -work altera_mm_interconnect_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_phy_0_avalon_universal_slave_0_translator # -- Compiling architecture rtl of address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_phy_0_avalon_universal_slave_0_translator # -- Loading package vl_types # -- Loading entity address_decode_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:09 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:09 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_mm_interconnect_191/sim/address_decode_altera_mm_interconnect_191_xb26wyy_tx_sc_fifo_0_avalon_universal_slave_0_translator.vhd -work altera_mm_interconnect_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_altera_mm_interconnect_191_xb26wyy_tx_sc_fifo_0_avalon_universal_slave_0_translator # -- Compiling architecture rtl of address_decode_altera_mm_interconnect_191_xb26wyy_tx_sc_fifo_0_avalon_universal_slave_0_translator # -- Loading package vl_types # -- Loading entity address_decode_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:09 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:09 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_mm_interconnect_191/sim/address_decode_altera_mm_interconnect_191_xb26wyy_eth_gen_mon_0_avalon_universal_slave_0_translator.vhd -work altera_mm_interconnect_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode_altera_mm_interconnect_191_xb26wyy_eth_gen_mon_0_avalon_universal_slave_0_translator # -- Compiling architecture rtl of address_decode_altera_mm_interconnect_191_xb26wyy_eth_gen_mon_0_avalon_universal_slave_0_translator # -- Loading package vl_types # -- Loading entity address_decode_altera_merlin_slave_translator_191_x56fcki # End time: 11:26:09 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:09 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/altera_mm_interconnect_191/sim/address_decode_altera_mm_interconnect_191_xb26wyy.vhd -work altera_mm_interconnect_191 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_merlin_master_translator_0_avalon_universal_master_0_agent # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_master_0_master_agent # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_merlin_master_translator_0_avalon_universal_master_0_translator # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_master_0_master_translator # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_mac_0_avalon_universal_slave_0_agent_rsp_fifo # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_tx_sc_fifo_0_avalon_universal_slave_0_agent_rdata_fifo # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_mac_0_avalon_universal_slave_0_translator # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_phy_0_avalon_universal_slave_0_translator # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_tx_sc_fifo_0_avalon_universal_slave_0_translator # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_eth_gen_mon_0_avalon_universal_slave_0_translator # -- Compiling entity address_decode_altera_mm_interconnect_191_xb26wyy # -- Compiling architecture rtl of address_decode_altera_mm_interconnect_191_xb26wyy # -- Loading package vl_types # -- Loading entity address_decode_altera_merlin_slave_agent_191_ncfkfri # -- Loading entity address_decode_altera_merlin_router_191_prlkaiy # -- Loading entity address_decode_altera_merlin_router_191_anzw7xi # -- Loading entity address_decode_altera_merlin_traffic_limiter_191_kcba44q # -- Loading entity address_decode_altera_merlin_burst_adapter_191_j2f5cla # -- Loading entity address_decode_altera_merlin_demultiplexer_191_qlmvu7a # -- Loading entity address_decode_altera_merlin_multiplexer_191_6qc733q # -- Loading entity address_decode_altera_merlin_demultiplexer_191_tqe34ei # -- Loading entity address_decode_altera_merlin_multiplexer_191_uq6phiq # -- Loading entity address_decode_altera_avalon_st_handshake_clock_crosser_191_3vi6gwa # End time: 11:26:10 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:10 on Mar 19,2020 # vlog ../../../rtl/address_decoder/address_decode/altera_reset_controller_191/sim/mentor/altera_reset_controller.v -work altera_reset_controller_191 # # Top level modules: # End time: 11:26:11 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:11 on Mar 19,2020 # vlog ../../../rtl/address_decoder/address_decode/altera_reset_controller_191/sim/mentor/altera_reset_synchronizer.v -work altera_reset_controller_191 # # Top level modules: # End time: 11:26:11 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:11 on Mar 19,2020 # vcom ../../../rtl/address_decoder/address_decode/sim/address_decode.vhd -work address_decode # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity address_decode # -- Compiling architecture rtl of address_decode # -- Loading entity address_decode_clk_csr # -- Loading entity address_decode_eth_gen_mon_0 # -- Loading entity address_decode_eth_gen_mon_1 # -- Loading entity address_decode_eth_gen_mon_10 # -- Loading entity address_decode_eth_gen_mon_11 # -- Loading entity address_decode_eth_gen_mon_2 # -- Loading entity address_decode_eth_gen_mon_3 # -- Loading entity address_decode_eth_gen_mon_4 # -- Loading entity address_decode_eth_gen_mon_5 # -- Loading entity address_decode_eth_gen_mon_6 # -- Loading entity address_decode_eth_gen_mon_7 # -- Loading entity address_decode_eth_gen_mon_8 # -- Loading entity address_decode_eth_gen_mon_9 # -- Loading entity address_decode_master_0 # -- Loading entity address_decode_merlin_master_translator_0 # -- Loading entity address_decode_mm_to_mac_0 # -- Loading entity address_decode_mm_to_mac_1 # -- Loading entity address_decode_mm_to_mac_10 # -- Loading entity address_decode_mm_to_mac_11 # -- Loading entity address_decode_mm_to_mac_2 # -- Loading entity address_decode_mm_to_mac_3 # -- Loading entity address_decode_mm_to_mac_4 # -- Loading entity address_decode_mm_to_mac_5 # -- Loading entity address_decode_mm_to_mac_6 # -- Loading entity address_decode_mm_to_mac_7 # -- Loading entity address_decode_mm_to_mac_8 # -- Loading entity address_decode_mm_to_mac_9 # -- Loading entity address_decode_mm_to_phy_0 # -- Loading entity address_decode_mm_to_phy_1 # -- Loading entity address_decode_mm_to_phy_10 # -- Loading entity address_decode_mm_to_phy_11 # -- Loading entity address_decode_mm_to_phy_2 # -- Loading entity address_decode_mm_to_phy_3 # -- Loading entity address_decode_mm_to_phy_4 # -- Loading entity address_decode_mm_to_phy_5 # -- Loading entity address_decode_mm_to_phy_6 # -- Loading entity address_decode_mm_to_phy_7 # -- Loading entity address_decode_mm_to_phy_8 # -- Loading entity address_decode_mm_to_phy_9 # -- Loading entity address_decode_rx_sc_fifo_0 # -- Loading entity address_decode_rx_sc_fifo_1 # -- Loading entity address_decode_rx_sc_fifo_10 # -- Loading entity address_decode_rx_sc_fifo_11 # -- Loading entity address_decode_rx_sc_fifo_2 # -- Loading entity address_decode_rx_sc_fifo_3 # -- Loading entity address_decode_rx_sc_fifo_4 # -- Loading entity address_decode_rx_sc_fifo_5 # -- Loading entity address_decode_rx_sc_fifo_6 # -- Loading entity address_decode_rx_sc_fifo_7 # -- Loading entity address_decode_rx_sc_fifo_8 # -- Loading entity address_decode_rx_sc_fifo_9 # -- Loading entity address_decode_rx_xcvr_clk # -- Loading entity address_decode_tx_sc_fifo_0 # -- Loading entity address_decode_tx_sc_fifo_1 # -- Loading entity address_decode_tx_sc_fifo_10 # -- Loading entity address_decode_tx_sc_fifo_11 # -- Loading entity address_decode_tx_sc_fifo_2 # -- Loading entity address_decode_tx_sc_fifo_3 # -- Loading entity address_decode_tx_sc_fifo_4 # -- Loading entity address_decode_tx_sc_fifo_5 # -- Loading entity address_decode_tx_sc_fifo_6 # -- Loading entity address_decode_tx_sc_fifo_7 # -- Loading entity address_decode_tx_sc_fifo_8 # -- Loading entity address_decode_tx_sc_fifo_9 # -- Loading entity address_decode_tx_xcvr_clk # -- Loading entity address_decode_tx_xcvr_half_clk # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_merlin_master_translator_0_avalon_universal_master_0_agent # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_master_0_master_agent # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_merlin_master_translator_0_avalon_universal_master_0_translator # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_master_0_master_translator # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_mac_0_avalon_universal_slave_0_agent_rsp_fifo # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_tx_sc_fifo_0_avalon_universal_slave_0_agent_rdata_fifo # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_mac_0_avalon_universal_slave_0_translator # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_phy_0_avalon_universal_slave_0_translator # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_tx_sc_fifo_0_avalon_universal_slave_0_translator # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy_eth_gen_mon_0_avalon_universal_slave_0_translator # -- Loading entity address_decode_altera_mm_interconnect_191_xb26wyy # End time: 11:26:11 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:11 on Mar 19,2020 # vlog ../../../rtl/fifo_dcfifo/ip/dc_fifo/dc_fifo_0/altera_avalon_dc_fifo_191/sim/dc_fifo_0_altera_avalon_dc_fifo_191_27jzy3q.v -work altera_avalon_dc_fifo_191 # -- Compiling module dc_fifo_0_altera_avalon_dc_fifo_191_27jzy3q # # Top level modules: # dc_fifo_0_altera_avalon_dc_fifo_191_27jzy3q # End time: 11:26:11 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:11 on Mar 19,2020 # vlog ../../../rtl/fifo_dcfifo/ip/dc_fifo/dc_fifo_0/altera_avalon_dc_fifo_191/sim/altera_dcfifo_synchronizer_bundle.v -work altera_avalon_dc_fifo_191 # -- Compiling module altera_dcfifo_synchronizer_bundle # # Top level modules: # altera_dcfifo_synchronizer_bundle # End time: 11:26:11 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:11 on Mar 19,2020 # vlog ../../../rtl/fifo_dcfifo/ip/dc_fifo/dc_fifo_0/altera_avalon_dc_fifo_191/sim/altera_std_synchronizer_nocut.v -work altera_avalon_dc_fifo_191 # -- Compiling module altera_std_synchronizer_nocut # # Top level modules: # altera_std_synchronizer_nocut # End time: 11:26:11 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:11 on Mar 19,2020 # vcom ../../../rtl/fifo_dcfifo/ip/dc_fifo/dc_fifo_0/sim/dc_fifo_0.vhd -work dc_fifo_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity dc_fifo_0 # -- Compiling architecture rtl of dc_fifo_0 # -- Loading package vl_types # -- Loading entity dc_fifo_0_altera_avalon_dc_fifo_191_27jzy3q # End time: 11:26:12 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:12 on Mar 19,2020 # vcom ../../../rtl/fifo_dcfifo/dc_fifo/sim/dc_fifo.vhd -work dc_fifo # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity dc_fifo # -- Compiling architecture rtl of dc_fifo # -- Loading entity dc_fifo_0 # End time: 11:26:12 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:12 on Mar 19,2020 # vlog ../../../rtl/fifo_scfifo/ip/sc_fifo/sc_fifo_rx_sc_fifo/altera_avalon_sc_fifo_191/sim/sc_fifo_rx_sc_fifo_altera_avalon_sc_fifo_191_cf2wdji.v -work altera_avalon_sc_fifo_191 # -- Compiling module sc_fifo_rx_sc_fifo_altera_avalon_sc_fifo_191_cf2wdji # # Top level modules: # sc_fifo_rx_sc_fifo_altera_avalon_sc_fifo_191_cf2wdji # End time: 11:26:12 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:12 on Mar 19,2020 # vcom ../../../rtl/fifo_scfifo/ip/sc_fifo/sc_fifo_rx_sc_fifo/sim/sc_fifo_rx_sc_fifo.vhd -work sc_fifo_rx_sc_fifo # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity sc_fifo_rx_sc_fifo # -- Compiling architecture rtl of sc_fifo_rx_sc_fifo # -- Loading package vl_types # -- Loading entity sc_fifo_rx_sc_fifo_altera_avalon_sc_fifo_191_cf2wdji # End time: 11:26:13 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:13 on Mar 19,2020 # vlog ../../../rtl/fifo_scfifo/ip/sc_fifo/sc_fifo_tx_sc_fifo/altera_avalon_sc_fifo_191/sim/sc_fifo_tx_sc_fifo_altera_avalon_sc_fifo_191_cf2wdji.v -work altera_avalon_sc_fifo_191 # -- Compiling module sc_fifo_tx_sc_fifo_altera_avalon_sc_fifo_191_cf2wdji # # Top level modules: # sc_fifo_tx_sc_fifo_altera_avalon_sc_fifo_191_cf2wdji # End time: 11:26:13 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:13 on Mar 19,2020 # vcom ../../../rtl/fifo_scfifo/ip/sc_fifo/sc_fifo_tx_sc_fifo/sim/sc_fifo_tx_sc_fifo.vhd -work sc_fifo_tx_sc_fifo # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity sc_fifo_tx_sc_fifo # -- Compiling architecture rtl of sc_fifo_tx_sc_fifo # -- Loading package vl_types # -- Loading entity sc_fifo_tx_sc_fifo_altera_avalon_sc_fifo_191_cf2wdji # End time: 11:26:13 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:13 on Mar 19,2020 # vcom ../../../rtl/fifo_scfifo/sc_fifo/sim/sc_fifo.vhd -work sc_fifo # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity sc_fifo # -- Compiling architecture rtl of sc_fifo # -- Loading entity sc_fifo_rx_sc_fifo # -- Loading entity sc_fifo_tx_sc_fifo # End time: 11:26:13 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:13 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/twentynm_xcvr_avmm.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # -- Compiling module twentynm_xcvr_avmm # ** Warning: (vlog-2070) Existing protected design unit "twentynm_xcvr_avmm" is being recompiled as unprotected. # # Top level modules: # twentynm_xcvr_avmm # End time: 11:26:13 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:13 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/mentor/twentynm_xcvr_avmm.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # ** Warning: (vlog-2070) Existing unprotected design unit "twentynm_xcvr_avmm" is being recompiled as protected. # # Top level modules: # End time: 11:26:13 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:13 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_resync.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # -- Compiling module alt_xcvr_resync # ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_resync" is being recompiled as unprotected. # # Top level modules: # alt_xcvr_resync # End time: 11:26:13 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:13 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_arbiter.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # -- Compiling module alt_xcvr_arbiter # ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_arbiter" is being recompiled as unprotected. # # Top level modules: # alt_xcvr_arbiter # End time: 11:26:13 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:13 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_resync.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # ** Warning: (vlog-2070) Existing unprotected design unit "alt_xcvr_resync" is being recompiled as protected. # # Top level modules: # End time: 11:26:13 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:13 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_arbiter.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # ** Warning: (vlog-2070) Existing unprotected design unit "alt_xcvr_arbiter" is being recompiled as protected. # # Top level modules: # End time: 11:26:14 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:14 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/a10_avmm_h.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # -- Compiling package a10_avmm_h # # Top level modules: # --none-- # End time: 11:26:14 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:14 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_atx_pll_rcfg_arb.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # -- Compiling module alt_xcvr_atx_pll_rcfg_arb # ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_atx_pll_rcfg_arb" is being recompiled as unprotected. # # Top level modules: # alt_xcvr_atx_pll_rcfg_arb # End time: 11:26:14 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:14 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/a10_xcvr_atx_pll.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # -- Compiling module a10_xcvr_atx_pll # ** Warning: (vlog-2070) Existing protected design unit "a10_xcvr_atx_pll" is being recompiled as unprotected. # # Top level modules: # a10_xcvr_atx_pll # End time: 11:26:14 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:14 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_pll_embedded_debug.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # -- Compiling module alt_xcvr_pll_embedded_debug # ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_pll_embedded_debug" is being recompiled as unprotected. # # Top level modules: # alt_xcvr_pll_embedded_debug # End time: 11:26:14 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:14 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_pll_avmm_csr.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # -- Compiling module alt_xcvr_pll_avmm_csr # -- Importing package a10_avmm_h # ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_pll_avmm_csr" is being recompiled as unprotected. # # Top level modules: # alt_xcvr_pll_avmm_csr # End time: 11:26:14 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:14 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_atx_pll_rcfg_arb.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # ** Warning: (vlog-2070) Existing unprotected design unit "alt_xcvr_atx_pll_rcfg_arb" is being recompiled as protected. # # Top level modules: # End time: 11:26:14 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:14 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/mentor/a10_xcvr_atx_pll.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # ** Warning: (vlog-2070) Existing unprotected design unit "a10_xcvr_atx_pll" is being recompiled as protected. # # Top level modules: # End time: 11:26:14 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:14 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_pll_embedded_debug.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # ** Warning: (vlog-2070) Existing unprotected design unit "alt_xcvr_pll_embedded_debug" is being recompiled as protected. # # Top level modules: # End time: 11:26:15 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:15 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_pll_avmm_csr.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # -- Importing package a10_avmm_h # ** Warning: (vlog-2070) Existing unprotected design unit "alt_xcvr_pll_avmm_csr" is being recompiled as protected. # # Top level modules: # End time: 11:26:15 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:15 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/altera_xcvr_atx_pll_ip_altera_xcvr_atx_pll_a10_191_cmegwma.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # -- Compiling module altera_xcvr_atx_pll_ip_altera_xcvr_atx_pll_a10_191_cmegwma # # Top level modules: # altera_xcvr_atx_pll_ip_altera_xcvr_atx_pll_a10_191_cmegwma # End time: 11:26:15 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:15 on Mar 19,2020 # vlog -sv ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_atx_pll_rcfg_opt_logic_cmegwma.sv -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191 # -- Compiling module alt_xcvr_atx_pll_rcfg_opt_logic_cmegwma # -- Importing package altera_common_sv_packages.altera_xcvr_native_a10_functions_h # # Top level modules: # alt_xcvr_atx_pll_rcfg_opt_logic_cmegwma # End time: 11:26:15 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:15 on Mar 19,2020 # vcom ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/sim/altera_xcvr_atx_pll_ip.vhd -work altera_xcvr_atx_pll_ip # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity altera_xcvr_atx_pll_ip # -- Compiling architecture rtl of altera_xcvr_atx_pll_ip # -- Loading package vl_types # -- Loading entity altera_xcvr_atx_pll_ip_altera_xcvr_atx_pll_a10_191_cmegwma # End time: 11:26:15 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:15 on Mar 19,2020 # vlog ../../../rtl/pll_mpll/pll/altera_iopll_191/sim/pll_altera_iopll_191_gucrrmi.vo -work altera_iopll_191 # -- Compiling module pll_altera_iopll_191_gucrrmi # # Top level modules: # pll_altera_iopll_191_gucrrmi # End time: 11:26:15 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:15 on Mar 19,2020 # vcom ../../../rtl/pll_mpll/pll/sim/pll.vhd -work pll # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity pll # -- Compiling architecture rtl of pll # -- Loading package vl_types # -- Loading entity pll_altera_iopll_191_gucrrmi # End time: 11:26:15 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:15 on Mar 19,2020 # vlog -sv ../../../rtl/xcvr_reset_controller/reset_control/altera_xcvr_reset_control_191/sim/altera_xcvr_functions.sv -work altera_xcvr_reset_control_191 # -- Compiling package altera_xcvr_functions # ** Warning: (vlog-2070) Existing protected design unit "altera_xcvr_functions" is being recompiled as unprotected. # # Top level modules: # --none-- # End time: 11:26:15 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:15 on Mar 19,2020 # vlog -sv ../../../rtl/xcvr_reset_controller/reset_control/altera_xcvr_reset_control_191/sim/mentor/altera_xcvr_functions.sv -work altera_xcvr_reset_control_191 # ** Warning: (vlog-2070) Existing unprotected design unit "altera_xcvr_functions" is being recompiled as protected. # # Top level modules: # --none-- # End time: 11:26:16 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:16 on Mar 19,2020 # vlog -sv ../../../rtl/xcvr_reset_controller/reset_control/altera_xcvr_reset_control_191/sim/alt_xcvr_resync.sv -work altera_xcvr_reset_control_191 # -- Compiling module alt_xcvr_resync # ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_resync" is being recompiled as unprotected. # # Top level modules: # alt_xcvr_resync # End time: 11:26:16 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:16 on Mar 19,2020 # vlog -sv ../../../rtl/xcvr_reset_controller/reset_control/altera_xcvr_reset_control_191/sim/mentor/alt_xcvr_resync.sv -work altera_xcvr_reset_control_191 # ** Warning: (vlog-2070) Existing unprotected design unit "alt_xcvr_resync" is being recompiled as protected. # # Top level modules: # End time: 11:26:16 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:16 on Mar 19,2020 # vlog -sv ../../../rtl/xcvr_reset_controller/reset_control/altera_xcvr_reset_control_191/sim/altera_xcvr_reset_control.sv -work altera_xcvr_reset_control_191 # -- Compiling module altera_xcvr_reset_control # ** Warning: (vlog-2070) Existing protected design unit "altera_xcvr_reset_control" is being recompiled as unprotected. # # Top level modules: # altera_xcvr_reset_control # End time: 11:26:16 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:16 on Mar 19,2020 # vlog -sv ../../../rtl/xcvr_reset_controller/reset_control/altera_xcvr_reset_control_191/sim/alt_xcvr_reset_counter.sv -work altera_xcvr_reset_control_191 # -- Compiling module alt_xcvr_reset_counter # ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_reset_counter" is being recompiled as unprotected. # # Top level modules: # alt_xcvr_reset_counter # End time: 11:26:16 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 1 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:16 on Mar 19,2020 # vlog -sv ../../../rtl/xcvr_reset_controller/reset_control/altera_xcvr_reset_control_191/sim/mentor/altera_xcvr_reset_control.sv -work altera_xcvr_reset_control_191 # ** Warning: (vlog-2070) Existing unprotected design unit "altera_xcvr_reset_control" is being recompiled as protected. # # Top level modules: # End time: 11:26:16 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:16 on Mar 19,2020 # vlog -sv ../../../rtl/xcvr_reset_controller/reset_control/altera_xcvr_reset_control_191/sim/mentor/alt_xcvr_reset_counter.sv -work altera_xcvr_reset_control_191 # ** Warning: (vlog-2070) Existing unprotected design unit "alt_xcvr_reset_counter" is being recompiled as protected. # # Top level modules: # End time: 11:26:16 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 2 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:16 on Mar 19,2020 # vcom ../../../rtl/xcvr_reset_controller/reset_control/sim/reset_control.vhd -work reset_control # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity reset_control # -- Compiling architecture rtl of reset_control # End time: 11:26:17 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:17 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/alt_em10g32.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:17 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:17 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/alt_em10g32unit.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:17 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:17 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_clk_rst.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:17 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:17 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_clock_crosser.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:17 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:17 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_crc32.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:17 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:17 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:18 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:18 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_creg_map.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:18 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:18 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_creg_top.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:18 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:18 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_frm_decoder.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:18 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:18 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:18 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:19 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_pipeline_base.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:19 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:19 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:19 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:19 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:19 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:19 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rst_cnt.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:19 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:19 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:19 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:19 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:20 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:20 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:20 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:20 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_frm_control.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:20 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:20 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:20 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:20 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:20 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:20 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:20 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:20 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:21 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:21 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b_top.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:21 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:21 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:21 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:21 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:21 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:21 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:21 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:21 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:21 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:21 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_top.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:22 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:22 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_stat_mem.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:22 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:22 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_stat_reg.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:22 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:22 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:22 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:22 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:22 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:22 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:22 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:22 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_flow_control.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:23 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:23 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:23 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:23 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:23 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:23 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:23 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:23 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:23 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:23 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_pause_req.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:23 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:23 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:24 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:24 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rr_buffer.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:24 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:24 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:24 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:24 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b_top.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:24 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:24 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:24 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:24 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:24 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:25 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_sc_fifo.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:25 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:25 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_top.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:25 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:25 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:25 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:25 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:25 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:25 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:25 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:25 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:26 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:26 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:26 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:26 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:26 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:26 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:26 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:26 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:26 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:26 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:26 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:26 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:27 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:27 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:27 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:27 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_st_adapter/alt_em10g32_vldpkt_rddly.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:27 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:27 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:27 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:27 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:27 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:27 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:27 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:27 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:28 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:28 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser_sync.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:28 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:28 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:28 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:28 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:28 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:28 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:28 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:28 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_32_to_64_xgmii_conversion.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:28 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:28 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_64_to_32_xgmii_conversion.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:29 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:29 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_32_to_64_adapter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:29 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:29 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_64_to_32_adapter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:29 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:29 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_data_format_adapter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:29 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:29 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:29 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:29 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_altsyncram.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:29 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:29 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_lat_calc.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:29 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:29 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:30 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:30 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:30 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:30 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:30 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:30 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:30 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:30 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:30 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:30 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:30 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:31 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:31 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:31 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:31 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:31 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:31 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:31 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer_ultra.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:31 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:31 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii_ultra.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:31 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:31 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:32 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:32 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:32 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:32 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_gmii_tsu.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:32 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:32 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_gmii16b_tsu.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:32 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:32 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_lpm_mult.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:32 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:32 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:32 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:32 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:33 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:33 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:33 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:33 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:33 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:33 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_gmii16b_crc_inserter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:33 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:33 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:33 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:33 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:33 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:33 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter_1g2p5g10g.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:34 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:34 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_ptp_processor.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:34 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:34 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:34 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:34 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:34 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:34 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:34 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:34 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:35 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:35 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_crc328generator.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:35 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:35 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_crc32ctl8.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:35 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:35 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_crc32galois8.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:35 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:35 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:35 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:35 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_gmii16b_crc_inserter.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:36 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:36 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/rtl/alt_em10g32_gmii16b_crc32.v -work alt_em10g32_191 # # Top level modules: # End time: 11:26:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:36 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/alt_em10g32_avalon_dc_fifo.v -work alt_em10g32_191 # -- Compiling module alt_em10g32_avalon_dc_fifo # # Top level modules: # alt_em10g32_avalon_dc_fifo # End time: 11:26:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:36 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/alt_em10g32_dcfifo_synchronizer_bundle.v -work alt_em10g32_191 # -- Compiling module alt_em10g32_dcfifo_synchronizer_bundle # # Top level modules: # alt_em10g32_dcfifo_synchronizer_bundle # End time: 11:26:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:36 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/alt_em10g32_std_synchronizer.v -work alt_em10g32_191 # -- Compiling module alt_em10g32_std_synchronizer # # Top level modules: # alt_em10g32_std_synchronizer # End time: 11:26:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:36 on Mar 19,2020 # vlog ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/altera_std_synchronizer_nocut.v -work alt_em10g32_191 # -- Compiling module altera_std_synchronizer_nocut # # Top level modules: # altera_std_synchronizer_nocut # End time: 11:26:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:36 on Mar 19,2020 # vcom ../../../rtl/mac/altera_eth_10g_mac/sim/altera_eth_10g_mac.vhd -work altera_eth_10g_mac # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity altera_eth_10g_mac # -- Compiling architecture rtl of altera_eth_10g_mac # End time: 11:26:36 on Mar 19,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Start time: 11:26:36 on Mar 19,2020 # vlog -work work -refresh -force_refresh # -- Refreshing module altera_avalon_mm_master_bfm # -- Importing package verbosity_pkg # -- Importing package avalon_mm_pkg # -- Importing package avalon_utilities_pkg # -- Refreshing module altera_avalon_sc_fifo # -- Refreshing module altera_avalon_st_sink_bfm # -- Refreshing module altera_avalon_st_source_bfm # -- Refreshing module altera_eth_10g_mac_base_r # -- Refreshing module altera_eth_10g_mac_base_r_wrap # -- Refreshing module avalon_bfm_wrapper # -- Importing package avalon_if_params_pkt # -- Refreshing module avalon_driver # -- Importing package eth_register_map_params_pkg # -- Refreshing package avalon_if_params_pkt # -- Refreshing package avalon_mm_pkg # -- Refreshing module avalon_st_eth_packet_monitor # -- Refreshing module avalon_st_gen # -- Refreshing module avalon_st_loopback # -- Refreshing module avalon_st_loopback_csr # -- Refreshing module avalon_st_mon # -- Refreshing module avalon_st_prtmux # -- Refreshing module avalon_st_to_crc_if_bridge # -- Refreshing package avalon_utilities_pkg # -- Refreshing module bit_endian_converter # -- Refreshing module byte_endian_converter # -- Refreshing module crc32_calculator # -- Refreshing module crc32_chk # -- Refreshing module crc32_dat16 # -- Refreshing module crc32_dat16_factor # -- Refreshing module crc32_dat16_flat # -- Refreshing module crc32_dat24 # -- Refreshing module crc32_dat24_factor # -- Refreshing module crc32_dat24_flat # -- Refreshing module crc32_dat32 # -- Refreshing module crc32_dat32_any_byte # -- Refreshing module crc32_dat32_factor # -- Refreshing module crc32_dat32_flat # -- Refreshing module crc32_dat40 # -- Refreshing module crc32_dat40_factor # -- Refreshing module crc32_dat40_flat # -- Refreshing module crc32_dat48 # -- Refreshing module crc32_dat48_factor # -- Refreshing module crc32_dat48_flat # -- Refreshing module crc32_dat56 # -- Refreshing module crc32_dat56_factor # -- Refreshing module crc32_dat56_flat # -- Refreshing module crc32_dat64 # -- Refreshing module crc32_dat64_any_byte # -- Refreshing module crc32_dat64_factor # -- Refreshing module crc32_dat64_flat # -- Refreshing module crc32_dat8 # -- Refreshing module crc32_dat8_factor # -- Refreshing module crc32_dat8_flat # -- Refreshing module crc32_gen # -- Refreshing module crc_checksum_aligner # -- Refreshing module crc_comparator # -- Refreshing module crc_ethernet # -- Refreshing module crc_register # -- Refreshing package default_test_params_pkt # -- Refreshing package eth_register_map_params_pkg # -- Refreshing module eth_std_traffic_controller_top # -- Refreshing module prbs23 # -- Refreshing module shiftreg_ctrl # -- Refreshing module shiftreg_data # -- Refreshing module tb_top # -- Importing package default_test_params_pkt # -- Refreshing package tb_top_sv_unit # -- Refreshing module traffic_reset_sync # -- Refreshing package verbosity_pkg # -- Refreshing module xor6 # End time: 11:26:37 on Mar 19,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # [exec] elab_debug # vsim -voptargs="+acc" -t fs -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10gx_ver -L cyclone10gx_hssi_ver -L cyclone10gx_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclone10gx -L cyclone10gx_hssi -L cyclone10gx_hip -L altera_common_sv_packages -L altera_xcvr_native_a10_191 -L altera_eth_10gbaser_phy -L address_decode_clk_csr -L altera_merlin_slave_translator_191 -L address_decode_eth_gen_mon_0 -L address_decode_eth_gen_mon_1 -L address_decode_eth_gen_mon_10 -L address_decode_eth_gen_mon_11 -L address_decode_eth_gen_mon_2 -L address_decode_eth_gen_mon_3 -L address_decode_eth_gen_mon_4 -L address_decode_eth_gen_mon_5 -L address_decode_eth_gen_mon_6 -L address_decode_eth_gen_mon_7 -L address_decode_eth_gen_mon_8 -L address_decode_eth_gen_mon_9 -L altera_jtag_dc_streaming_191 -L timing_adapter_191 -L altera_avalon_sc_fifo_191 -L altera_avalon_st_bytes_to_packets_191 -L altera_avalon_st_packets_to_bytes_191 -L altera_avalon_packets_to_master_191 -L channel_adapter_191 -L altera_reset_controller_191 -L altera_jtag_avalon_master_191 -L address_decode_master_0 -L altera_merlin_master_translator_191 -L address_decode_merlin_master_translator_0 -L address_decode_mm_to_mac_0 -L address_decode_mm_to_mac_1 -L address_decode_mm_to_mac_10 -L address_decode_mm_to_mac_11 -L address_decode_mm_to_mac_2 -L address_decode_mm_to_mac_3 -L address_decode_mm_to_mac_4 -L address_decode_mm_to_mac_5 -L address_decode_mm_to_mac_6 -L address_decode_mm_to_mac_7 -L address_decode_mm_to_mac_8 -L address_decode_mm_to_mac_9 -L address_decode_mm_to_phy_0 -L address_decode_mm_to_phy_1 -L address_decode_mm_to_phy_10 -L address_decode_mm_to_phy_11 -L address_decode_mm_to_phy_2 -L address_decode_mm_to_phy_3 -L address_decode_mm_to_phy_4 -L address_decode_mm_to_phy_5 -L address_decode_mm_to_phy_6 -L address_decode_mm_to_phy_7 -L address_decode_mm_to_phy_8 -L address_decode_mm_to_phy_9 -L address_decode_rx_sc_fifo_0 -L address_decode_rx_sc_fifo_1 -L address_decode_rx_sc_fifo_10 -L address_decode_rx_sc_fifo_11 -L address_decode_rx_sc_fifo_2 -L address_decode_rx_sc_fifo_3 -L address_decode_rx_sc_fifo_4 -L address_decode_rx_sc_fifo_5 -L address_decode_rx_sc_fifo_6 -L address_decode_rx_sc_fifo_7 -L address_decode_rx_sc_fifo_8 -L address_decode_rx_sc_fifo_9 -L address_decode_rx_xcvr_clk -L address_decode_tx_sc_fifo_0 -L address_decode_tx_sc_fifo_1 -L address_decode_tx_sc_fifo_10 -L address_decode_tx_sc_fifo_11 -L address_decode_tx_sc_fifo_2 -L address_decode_tx_sc_fifo_3 -L address_decode_tx_sc_fifo_4 -L address_decode_tx_sc_fifo_5 -L address_decode_tx_sc_fifo_6 -L address_decode_tx_sc_fifo_7 -L address_decode_tx_sc_fifo_8 -L address_decode_tx_sc_fifo_9 -L address_decode_tx_xcvr_clk -L address_decode_tx_xcvr_half_clk -L altera_merlin_master_agent_191 -L altera_merlin_slave_agent_191 -L altera_merlin_router_191 -L altera_merlin_traffic_limiter_191 -L alt_hiconnect_sc_fifo_191 -L altera_merlin_burst_adapter_191 -L altera_merlin_demultiplexer_191 -L altera_merlin_multiplexer_191 -L altera_avalon_st_handshake_clock_crosser_191 -L altera_mm_interconnect_191 -L address_decode -L altera_avalon_dc_fifo_191 -L dc_fifo_0 -L dc_fifo -L sc_fifo_rx_sc_fifo -L sc_fifo_tx_sc_fifo -L sc_fifo -L altera_xcvr_atx_pll_a10_191 -L altera_xcvr_atx_pll_ip -L altera_iopll_191 -L pll -L altera_xcvr_reset_control_191 -L reset_control -L alt_em10g32_191 -L altera_eth_10g_mac tb_top # Start time: 11:26:37 on Mar 19,2020 # Loading sv_std.std # Loading work.default_test_params_pkt # Loading work.eth_register_map_params_pkg # Loading work.avalon_if_params_pkt # Loading work.tb_top_sv_unit # Loading work.tb_top # Loading work.altera_eth_10g_mac_base_r # Loading work.verbosity_pkg # Loading work.avalon_mm_pkg # Loading work.avalon_driver # Loading work.avalon_bfm_wrapper # Loading work.avalon_utilities_pkg # Loading work.altera_avalon_mm_master_bfm # Loading work.altera_avalon_st_sink_bfm # Loading work.altera_avalon_st_source_bfm # Loading work.avalon_st_eth_packet_monitor # Loading work.altera_eth_10g_mac_base_r_wrap # Loading work.eth_std_traffic_controller_top # Loading work.traffic_reset_sync # Loading work.avalon_st_gen # Loading work.prbs23 # Loading work.crc32_gen # Loading work.crc32_calculator # Loading work.avalon_st_to_crc_if_bridge # Loading work.byte_endian_converter # Loading work.crc_ethernet # Loading work.crc_register # Loading work.crc_checksum_aligner # Loading work.shiftreg_data # Loading altera_mf_ver.altshift_taps # Loading work.shiftreg_ctrl # Loading work.avalon_st_mon # Loading work.crc32_chk # Loading work.crc_comparator # Loading work.avalon_st_loopback # Loading work.avalon_st_loopback_csr # Loading work.altera_avalon_sc_fifo # Loading altera_mf_ver.altera_std_synchronizer # Loading work.crc32_dat64_any_byte # Loading work.crc32_dat8 # Loading work.crc32_dat16 # Loading work.crc32_dat24 # Loading work.crc32_dat32 # Loading work.crc32_dat40 # Loading work.crc32_dat48 # Loading work.crc32_dat56 # Loading work.crc32_dat64 # Loading alt_em10g32_191.alt_em10g32_avalon_dc_fifo # Loading alt_em10g32_191.alt_em10g32_dcfifo_synchronizer_bundle # Loading alt_em10g32_191.altera_std_synchronizer_nocut # Loading work.crc32_dat8_factor # Loading work.xor6 # Loading work.crc32_dat16_factor # Loading work.crc32_dat24_factor # Loading work.crc32_dat32_factor # Loading work.crc32_dat40_factor # Loading work.crc32_dat48_factor # Loading work.crc32_dat56_factor # Loading work.crc32_dat64_factor # Loading alt_em10g32_191.alt_em10g32_std_synchronizer # Loading altera_mf_ver.altsyncram # Loading altera_mf_ver.altera_syncram_derived # Loading altera_mf_ver.ALTERA_MF_MEMORY_INITIALIZATION # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading verilog.vl_types(body) # Loading pll.pll(rtl) # Loading altera_iopll_191.pll_altera_iopll_191_gucrrmi # Loading altera_lnsim_ver.altera_iopll # Loading altera_lnsim_ver.cyclone10gx_iopll_ip # Loading cyclone10gx_ver.cyclone10gx_iopll # Loading altera_xcvr_atx_pll_ip.altera_xcvr_atx_pll_ip(rtl) # Loading altera_xcvr_atx_pll_a10_191.altera_xcvr_atx_pll_ip_altera_xcvr_atx_pll_a10_191_cmegwma # Loading altera_common_sv_packages.altera_xcvr_native_a10_functions_h # Loading altera_xcvr_atx_pll_a10_191.alt_xcvr_atx_pll_rcfg_opt_logic_cmegwma # Loading cyclone10gx_hssi_ver.twentynm_hssi_pma_lc_refclk_select_mux # Loading cyclone10gx_hssi_ver.twentynm_atx_pll # Loading cyclone10gx_hssi_ver.twentynm_hssi_avmm_if # Loading altera_eth_10g_mac.altera_eth_10g_mac(rtl) # Loading lpm_ver.lpm_mult # Loading lpm_ver.LPM_HINT_EVALUATION # Loading altera_eth_10gbaser_phy.altera_eth_10gbaser_phy(rtl) # Loading altera_xcvr_native_a10_191.altera_eth_10gbaser_phy_altera_xcvr_native_a10_191_6rgg7fy # Loading altera_xcvr_native_a10_191.alt_xcvr_native_rcfg_opt_logic_6rgg7fy # Loading cyclone10gx_hssi_ver.twentynm_hssi_pma_adaptation # Loading cyclone10gx_hssi_ver.twentynm_hssi_pma_cdr_refclk_select_mux # Loading cyclone10gx_hssi_ver.twentynm_hssi_pma_channel_pll # Loading cyclone10gx_hssi_ver.twentynm_hssi_pma_rx_buf # Loading cyclone10gx_hssi_ver.twentynm_hssi_pma_rx_deser # Loading cyclone10gx_hssi_ver.twentynm_hssi_pma_rx_dfe # Loading cyclone10gx_hssi_ver.twentynm_hssi_pma_rx_odi # Loading cyclone10gx_hssi_ver.twentynm_hssi_pma_rx_sd # Loading cyclone10gx_hssi_ver.twentynm_hssi_pma_tx_buf # Loading cyclone10gx_hssi_ver.twentynm_hssi_pma_tx_cgb # Loading cyclone10gx_hssi_ver.twentynm_hssi_pma_tx_ser # Loading cyclone10gx_hssi_ver.twentynm_hssi_10g_rx_pcs # Loading cyclone10gx_hssi_ver.twentynm_hssi_10g_tx_pcs # Loading cyclone10gx_hssi_ver.twentynm_hssi_8g_rx_pcs # Loading cyclone10gx_hssi_ver.twentynm_hssi_8g_tx_pcs # Loading cyclone10gx_hssi_ver.twentynm_hssi_common_pcs_pma_interface # Loading cyclone10gx_hssi_ver.twentynm_hssi_common_pld_pcs_interface # Loading cyclone10gx_hssi_ver.twentynm_hssi_fifo_rx_pcs # Loading cyclone10gx_hssi_ver.twentynm_hssi_fifo_tx_pcs # Loading cyclone10gx_hssi_ver.twentynm_hssi_gen3_rx_pcs # Loading cyclone10gx_hssi_ver.twentynm_hssi_gen3_tx_pcs # Loading cyclone10gx_hssi_ver.twentynm_hssi_krfec_rx_pcs # Loading cyclone10gx_hssi_ver.twentynm_hssi_krfec_tx_pcs # Loading cyclone10gx_hssi_ver.twentynm_hssi_pipe_gen1_2 # Loading cyclone10gx_hssi_ver.twentynm_hssi_pipe_gen3 # Loading cyclone10gx_hssi_ver.twentynm_hssi_rx_pcs_pma_interface # Loading cyclone10gx_hssi_ver.twentynm_hssi_rx_pld_pcs_interface # Loading cyclone10gx_hssi_ver.twentynm_hssi_tx_pcs_pma_interface # Loading cyclone10gx_hssi_ver.twentynm_hssi_tx_pld_pcs_interface # Loading reset_control.reset_control(rtl) # Loading sc_fifo.sc_fifo(rtl) # Loading sc_fifo_rx_sc_fifo.sc_fifo_rx_sc_fifo(rtl) # Loading altera_avalon_sc_fifo_191.sc_fifo_rx_sc_fifo_altera_avalon_sc_fifo_191_cf2wdji # Loading sc_fifo_tx_sc_fifo.sc_fifo_tx_sc_fifo(rtl) # Loading altera_avalon_sc_fifo_191.sc_fifo_tx_sc_fifo_altera_avalon_sc_fifo_191_cf2wdji # Loading address_decode.address_decode(rtl) # Loading address_decode_clk_csr.address_decode_clk_csr(rtl) # Loading address_decode_eth_gen_mon_0.address_decode_eth_gen_mon_0(rtl) # Loading altera_merlin_slave_translator_191.address_decode_eth_gen_mon_0_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_eth_gen_mon_1.address_decode_eth_gen_mon_1(rtl) # Loading altera_merlin_slave_translator_191.address_decode_eth_gen_mon_1_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_eth_gen_mon_10.address_decode_eth_gen_mon_10(rtl) # Loading altera_merlin_slave_translator_191.address_decode_eth_gen_mon_10_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_eth_gen_mon_11.address_decode_eth_gen_mon_11(rtl) # Loading altera_merlin_slave_translator_191.address_decode_eth_gen_mon_11_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_eth_gen_mon_2.address_decode_eth_gen_mon_2(rtl) # Loading altera_merlin_slave_translator_191.address_decode_eth_gen_mon_2_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_eth_gen_mon_3.address_decode_eth_gen_mon_3(rtl) # Loading altera_merlin_slave_translator_191.address_decode_eth_gen_mon_3_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_eth_gen_mon_4.address_decode_eth_gen_mon_4(rtl) # Loading altera_merlin_slave_translator_191.address_decode_eth_gen_mon_4_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_eth_gen_mon_5.address_decode_eth_gen_mon_5(rtl) # Loading altera_merlin_slave_translator_191.address_decode_eth_gen_mon_5_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_eth_gen_mon_6.address_decode_eth_gen_mon_6(rtl) # Loading altera_merlin_slave_translator_191.address_decode_eth_gen_mon_6_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_eth_gen_mon_7.address_decode_eth_gen_mon_7(rtl) # Loading altera_merlin_slave_translator_191.address_decode_eth_gen_mon_7_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_eth_gen_mon_8.address_decode_eth_gen_mon_8(rtl) # Loading altera_merlin_slave_translator_191.address_decode_eth_gen_mon_8_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_eth_gen_mon_9.address_decode_eth_gen_mon_9(rtl) # Loading altera_merlin_slave_translator_191.address_decode_eth_gen_mon_9_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_master_0.address_decode_master_0(rtl) # Loading altera_jtag_avalon_master_191.address_decode_master_0_altera_jtag_avalon_master_191_3zppvky(rtl) # Loading altera_jtag_dc_streaming_191.altera_avalon_st_jtag_interface # Loading altera_jtag_dc_streaming_191.altera_jtag_sld_node # Loading altera_jtag_dc_streaming_191.altera_jtag_dc_streaming # Loading altera_jtag_dc_streaming_191.altera_jtag_streaming # Loading altera_jtag_dc_streaming_191.altera_avalon_st_idle_remover # Loading altera_jtag_dc_streaming_191.altera_avalon_st_idle_inserter # Loading altera_jtag_dc_streaming_191.altera_avalon_st_clock_crosser # Loading altera_jtag_dc_streaming_191.altera_std_synchronizer_nocut # Loading altera_jtag_dc_streaming_191.altera_jtag_src_crosser # Loading altera_jtag_dc_streaming_191.altera_jtag_control_signal_crosser # Loading altera_jtag_dc_streaming_191.altera_avalon_st_pipeline_base # Loading timing_adapter_191.address_decode_master_0_timing_adapter_191_rrgemwi # Loading altera_avalon_sc_fifo_191.address_decode_master_0_altera_avalon_sc_fifo_191_e5eqkcq # Loading altera_avalon_st_bytes_to_packets_191.altera_avalon_st_bytes_to_packets # Loading altera_avalon_st_packets_to_bytes_191.altera_avalon_st_packets_to_bytes # Loading altera_avalon_packets_to_master_191.altera_avalon_packets_to_master # Loading altera_avalon_packets_to_master_191.packets_to_master # Loading channel_adapter_191.address_decode_master_0_channel_adapter_191_uc27kqq # Loading channel_adapter_191.address_decode_master_0_channel_adapter_191_cco4x3a # Loading address_decode_merlin_master_translator_0.address_decode_merlin_master_translator_0(rtl) # Loading altera_merlin_master_translator_191.address_decode_merlin_master_translator_0_altera_merlin_master_translator_191_g7h47bq # Loading address_decode_mm_to_mac_0.address_decode_mm_to_mac_0(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_mac_0_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_mac_1.address_decode_mm_to_mac_1(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_mac_1_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_mac_10.address_decode_mm_to_mac_10(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_mac_10_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_mac_11.address_decode_mm_to_mac_11(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_mac_11_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_mac_2.address_decode_mm_to_mac_2(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_mac_2_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_mac_3.address_decode_mm_to_mac_3(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_mac_3_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_mac_4.address_decode_mm_to_mac_4(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_mac_4_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_mac_5.address_decode_mm_to_mac_5(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_mac_5_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_mac_6.address_decode_mm_to_mac_6(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_mac_6_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_mac_7.address_decode_mm_to_mac_7(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_mac_7_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_mac_8.address_decode_mm_to_mac_8(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_mac_8_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_mac_9.address_decode_mm_to_mac_9(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_mac_9_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_phy_0.address_decode_mm_to_phy_0(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_phy_0_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_phy_1.address_decode_mm_to_phy_1(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_phy_1_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_phy_10.address_decode_mm_to_phy_10(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_phy_10_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_phy_11.address_decode_mm_to_phy_11(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_phy_11_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_phy_2.address_decode_mm_to_phy_2(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_phy_2_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_phy_3.address_decode_mm_to_phy_3(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_phy_3_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_phy_4.address_decode_mm_to_phy_4(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_phy_4_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_phy_5.address_decode_mm_to_phy_5(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_phy_5_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_phy_6.address_decode_mm_to_phy_6(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_phy_6_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_phy_7.address_decode_mm_to_phy_7(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_phy_7_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_phy_8.address_decode_mm_to_phy_8(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_phy_8_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_mm_to_phy_9.address_decode_mm_to_phy_9(rtl) # Loading altera_merlin_slave_translator_191.address_decode_mm_to_phy_9_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_sc_fifo_0.address_decode_rx_sc_fifo_0(rtl) # Loading altera_merlin_slave_translator_191.address_decode_rx_sc_fifo_0_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_sc_fifo_1.address_decode_rx_sc_fifo_1(rtl) # Loading altera_merlin_slave_translator_191.address_decode_rx_sc_fifo_1_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_sc_fifo_10.address_decode_rx_sc_fifo_10(rtl) # Loading altera_merlin_slave_translator_191.address_decode_rx_sc_fifo_10_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_sc_fifo_11.address_decode_rx_sc_fifo_11(rtl) # Loading altera_merlin_slave_translator_191.address_decode_rx_sc_fifo_11_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_sc_fifo_2.address_decode_rx_sc_fifo_2(rtl) # Loading altera_merlin_slave_translator_191.address_decode_rx_sc_fifo_2_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_sc_fifo_3.address_decode_rx_sc_fifo_3(rtl) # Loading altera_merlin_slave_translator_191.address_decode_rx_sc_fifo_3_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_sc_fifo_4.address_decode_rx_sc_fifo_4(rtl) # Loading altera_merlin_slave_translator_191.address_decode_rx_sc_fifo_4_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_sc_fifo_5.address_decode_rx_sc_fifo_5(rtl) # Loading altera_merlin_slave_translator_191.address_decode_rx_sc_fifo_5_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_sc_fifo_6.address_decode_rx_sc_fifo_6(rtl) # Loading altera_merlin_slave_translator_191.address_decode_rx_sc_fifo_6_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_sc_fifo_7.address_decode_rx_sc_fifo_7(rtl) # Loading altera_merlin_slave_translator_191.address_decode_rx_sc_fifo_7_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_sc_fifo_8.address_decode_rx_sc_fifo_8(rtl) # Loading altera_merlin_slave_translator_191.address_decode_rx_sc_fifo_8_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_sc_fifo_9.address_decode_rx_sc_fifo_9(rtl) # Loading altera_merlin_slave_translator_191.address_decode_rx_sc_fifo_9_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_rx_xcvr_clk.address_decode_rx_xcvr_clk(rtl) # Loading address_decode_tx_sc_fifo_0.address_decode_tx_sc_fifo_0(rtl) # Loading altera_merlin_slave_translator_191.address_decode_tx_sc_fifo_0_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_tx_sc_fifo_1.address_decode_tx_sc_fifo_1(rtl) # Loading altera_merlin_slave_translator_191.address_decode_tx_sc_fifo_1_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_tx_sc_fifo_10.address_decode_tx_sc_fifo_10(rtl) # Loading altera_merlin_slave_translator_191.address_decode_tx_sc_fifo_10_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_tx_sc_fifo_11.address_decode_tx_sc_fifo_11(rtl) # Loading altera_merlin_slave_translator_191.address_decode_tx_sc_fifo_11_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_tx_sc_fifo_2.address_decode_tx_sc_fifo_2(rtl) # Loading altera_merlin_slave_translator_191.address_decode_tx_sc_fifo_2_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_tx_sc_fifo_3.address_decode_tx_sc_fifo_3(rtl) # Loading altera_merlin_slave_translator_191.address_decode_tx_sc_fifo_3_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_tx_sc_fifo_4.address_decode_tx_sc_fifo_4(rtl) # Loading altera_merlin_slave_translator_191.address_decode_tx_sc_fifo_4_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_tx_sc_fifo_5.address_decode_tx_sc_fifo_5(rtl) # Loading altera_merlin_slave_translator_191.address_decode_tx_sc_fifo_5_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_tx_sc_fifo_6.address_decode_tx_sc_fifo_6(rtl) # Loading altera_merlin_slave_translator_191.address_decode_tx_sc_fifo_6_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_tx_sc_fifo_7.address_decode_tx_sc_fifo_7(rtl) # Loading altera_merlin_slave_translator_191.address_decode_tx_sc_fifo_7_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_tx_sc_fifo_8.address_decode_tx_sc_fifo_8(rtl) # Loading altera_merlin_slave_translator_191.address_decode_tx_sc_fifo_8_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_tx_sc_fifo_9.address_decode_tx_sc_fifo_9(rtl) # Loading altera_merlin_slave_translator_191.address_decode_tx_sc_fifo_9_altera_merlin_slave_translator_191_x56fcki # Loading address_decode_tx_xcvr_clk.address_decode_tx_xcvr_clk(rtl) # Loading address_decode_tx_xcvr_half_clk.address_decode_tx_xcvr_half_clk(rtl) # Loading altera_mm_interconnect_191.address_decode_altera_mm_interconnect_191_xb26wyy(rtl) # Loading altera_mm_interconnect_191.address_decode_altera_mm_interconnect_191_xb26wyy_merlin_master_translator_0_avalon_universal_master_0_translator(rtl) # Loading altera_merlin_master_translator_191.address_decode_altera_merlin_master_translator_191_g7h47bq # Loading altera_mm_interconnect_191.address_decode_altera_mm_interconnect_191_xb26wyy_master_0_master_translator(rtl) # Loading altera_mm_interconnect_191.address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_mac_0_avalon_universal_slave_0_translator(rtl) # Loading altera_merlin_slave_translator_191.address_decode_altera_merlin_slave_translator_191_x56fcki # Loading altera_mm_interconnect_191.address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_phy_0_avalon_universal_slave_0_translator(rtl) # Loading altera_mm_interconnect_191.address_decode_altera_mm_interconnect_191_xb26wyy_tx_sc_fifo_0_avalon_universal_slave_0_translator(rtl) # Loading altera_mm_interconnect_191.address_decode_altera_mm_interconnect_191_xb26wyy_eth_gen_mon_0_avalon_universal_slave_0_translator(rtl) # Loading altera_mm_interconnect_191.address_decode_altera_mm_interconnect_191_xb26wyy_merlin_master_translator_0_avalon_universal_master_0_agent(rtl) # Loading altera_merlin_master_agent_191.address_decode_altera_merlin_master_agent_191_mpbm6tq # Loading altera_mm_interconnect_191.address_decode_altera_mm_interconnect_191_xb26wyy_master_0_master_agent(rtl) # Loading altera_merlin_slave_agent_191.address_decode_altera_merlin_slave_agent_191_ncfkfri # Loading altera_merlin_slave_agent_191.altera_merlin_burst_uncompressor # ** Warning: (vsim-8311) System Verilog assertions are supported only in Questasim. # Loading altera_mm_interconnect_191.address_decode_altera_mm_interconnect_191_xb26wyy_mm_to_mac_0_avalon_universal_slave_0_agent_rsp_fifo(rtl) # Loading altera_avalon_sc_fifo_191.address_decode_altera_avalon_sc_fifo_191_e5eqkcq # Loading altera_mm_interconnect_191.address_decode_altera_mm_interconnect_191_xb26wyy_tx_sc_fifo_0_avalon_universal_slave_0_agent_rdata_fifo(rtl) # Loading altera_merlin_router_191.address_decode_altera_merlin_router_191_prlkaiy # Loading altera_merlin_router_191.address_decode_altera_merlin_router_191_prlkaiy_default_decode # Loading altera_merlin_router_191.address_decode_altera_merlin_router_191_anzw7xi # Loading altera_merlin_router_191.address_decode_altera_merlin_router_191_anzw7xi_default_decode # Loading altera_merlin_traffic_limiter_191.address_decode_altera_merlin_traffic_limiter_191_kcba44q # Loading altera_merlin_burst_adapter_191.address_decode_altera_merlin_burst_adapter_191_j2f5cla # Loading altera_merlin_burst_adapter_191.altera_merlin_burst_adapter_13_1 # Loading altera_merlin_burst_adapter_191.altera_merlin_address_alignment # Loading altera_merlin_burst_adapter_191.altera_merlin_burst_adapter_burstwrap_increment # Loading altera_merlin_burst_adapter_191.altera_merlin_burst_adapter_min # Loading altera_merlin_burst_adapter_191.altera_merlin_burst_adapter_subtractor # Loading altera_merlin_burst_adapter_191.altera_merlin_burst_adapter_adder # Loading altera_merlin_demultiplexer_191.address_decode_altera_merlin_demultiplexer_191_qlmvu7a # Loading altera_merlin_multiplexer_191.address_decode_altera_merlin_multiplexer_191_6qc733q # Loading altera_merlin_multiplexer_191.altera_merlin_arbitrator # Loading altera_merlin_multiplexer_191.altera_merlin_arb_adder # Loading altera_merlin_demultiplexer_191.address_decode_altera_merlin_demultiplexer_191_tqe34ei # Loading altera_merlin_multiplexer_191.address_decode_altera_merlin_multiplexer_191_uq6phiq # Loading altera_avalon_st_handshake_clock_crosser_191.address_decode_altera_avalon_st_handshake_clock_crosser_191_3vi6gwa # Loading altera_avalon_st_handshake_clock_crosser_191.altera_avalon_st_clock_crosser # Loading altera_avalon_st_handshake_clock_crosser_191.altera_std_synchronizer_nocut # ** Warning: (vsim-3017) ../models/tb_top.sv(196): [TFMPC] - Too few port connections. Expected 23, found 19. # Time: 0 fs Iteration: 0 Instance: /tb_top/dut File: ../../../rtl/altera_eth_10g_mac_base_r.sv # ** Warning: (vsim-3722) ../models/tb_top.sv(196): [TFMPC] - Missing connection for port 'core_clk_156'. # ** Warning: (vsim-3722) ../models/tb_top.sv(196): [TFMPC] - Missing connection for port 'avalon_st_rxstatus_valid_156'. # ** Warning: (vsim-3722) ../models/tb_top.sv(196): [TFMPC] - Missing connection for port 'avalon_st_rxstatus_data_156'. # ** Warning: (vsim-3722) ../models/tb_top.sv(196): [TFMPC] - Missing connection for port 'avalon_st_rxstatus_error_156'. # ** Warning: (vsim-3017) $MODEL_TECH/../altera/verilog/src/altera_lnsim.sv(35897): [TFMPC] - Too few port connections. Expected 51, found 50. # Time: 0 fs Iteration: 0 Instance: /tb_top/dut/pll_inst/iopll_0/altera_iopll_i/genblk1/c10gx_pll/iopll_inst File: $MODEL_TECH/../altera/verilog/src/cyclone10gx_atoms.v # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/altera_lnsim.sv(35897): [TFMPC] - Missing connection for port 'pipeline_global_en_n'. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/pll_inst/iopll_0/altera_iopll_i/genblk1/c10gx_pll/iopll_inst/inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/cyclone10gx_atoms_ncrypt.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-8822) ../../../rtl/altera_eth_10g_mac_base_r.sv(262): [TFMPC] - Missing Verilog connection for formal VHDL port 'pll_powerdown'. # Time: 0 fs Iteration: 0 Instance: /tb_top/dut/atx_pll_inst File: ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/sim/altera_xcvr_atx_pll_ip.vhd # ** Warning: (vsim-8822) ../../../rtl/altera_eth_10g_mac_base_r.sv(262): [TFMPC] - Missing Verilog connection for formal VHDL port 'pll_cal_busy'. # Time: 0 fs Iteration: 0 Instance: /tb_top/dut/atx_pll_inst File: ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/sim/altera_xcvr_atx_pll_ip.vhd # ** Warning: (vsim-8822) ../../../rtl/altera_eth_10g_mac_base_r.sv(262): [TFMPC] - Missing Verilog connection for formal VHDL port 'mcgb_cal_busy'. # Time: 0 fs Iteration: 0 Instance: /tb_top/dut/atx_pll_inst File: ../../../rtl/pll_atxpll/altera_xcvr_atx_pll_ip/sim/altera_xcvr_atx_pll_ip.vhd # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/atx_pll_inst/altera_xcvr_atx_pll_ip_inst/a10_xcvr_atx_pll_inst/ File: $MODEL_TECH/../altera/verilog/src/cyclone10gx_hssi_atoms.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[0]/wrapper_inst/mac_inst/alt_em10g32_0/////////// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3016) (): Port type is incompatible with connection (). # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[0]/wrapper_inst/mac_inst/alt_em10g32_0/////////// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3016) $MODEL_TECH/../altera/verilog/src/altera_mf.v(48044): Port type is incompatible with connection (port 'clock0'). # Time: 0 fs Iteration: 0 Instance: /tb_top/dut/CHANNEL[0]/wrapper_inst/mac_inst/alt_em10g32_0////////////m_arria10/altera_syncram_inst File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[0]/wrapper_inst/mac_inst/alt_em10g32_0/////////// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3016) (): Port type is incompatible with connection (). # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[0]/wrapper_inst/mac_inst/alt_em10g32_0/////////// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3016) $MODEL_TECH/../altera/verilog/src/altera_mf.v(48044): Port type is incompatible with connection (port 'clock0'). # Time: 0 fs Iteration: 0 Instance: /tb_top/dut/CHANNEL[0]/wrapper_inst/mac_inst/alt_em10g32_0////////////m_arria10/altera_syncram_inst File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[0]/wrapper_inst/mac_inst/alt_em10g32_0/////////// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[0]/wrapper_inst/mac_inst/alt_em10g32_0/////////// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[0]/wrapper_inst/baser_inst/xcvr_native_a10_0/g_xcvr_native_insts[0]/twentynm_xcvr_native_inst//////twentynm_hssi_pma_channel_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/cyclone10gx_hssi_atoms_ncrypt.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Too few port connections. Expected 131, found 121. # Time: 0 fs Iteration: 0 Instance: /tb_top/dut/CHANNEL[0]/dc_fifo_adapter_inst File: ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'tx_egress_p2p_update_156'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'tx_egress_p2p_val_156'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'tx_egress_asymmetry_update_156'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'tx_egress_p2p_update_312'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'tx_egress_p2p_val_312'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'tx_egress_asymmetry_update_312'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'rx_ingress_p2p_val_valid_312'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'rx_ingress_p2p_val_312'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'rx_ingress_p2p_val_valid_156'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'rx_ingress_p2p_val_156'. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[0]/dc_fifo_adapter_inst///fifo_mem//// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[0]/dc_fifo_adapter_inst///fifo_mem//// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[0]/dc_fifo_adapter_inst///fifo_mem//// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[1]/wrapper_inst/mac_inst/alt_em10g32_0/////////// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3016) (): Port type is incompatible with connection (). # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[1]/wrapper_inst/mac_inst/alt_em10g32_0/////////// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3016) $MODEL_TECH/../altera/verilog/src/altera_mf.v(48044): Port type is incompatible with connection (port 'clock0'). # Time: 0 fs Iteration: 0 Instance: /tb_top/dut/CHANNEL[1]/wrapper_inst/mac_inst/alt_em10g32_0////////////m_arria10/altera_syncram_inst File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[1]/wrapper_inst/mac_inst/alt_em10g32_0/////////// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3016) (): Port type is incompatible with connection (). # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[1]/wrapper_inst/mac_inst/alt_em10g32_0/////////// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3016) $MODEL_TECH/../altera/verilog/src/altera_mf.v(48044): Port type is incompatible with connection (port 'clock0'). # Time: 0 fs Iteration: 0 Instance: /tb_top/dut/CHANNEL[1]/wrapper_inst/mac_inst/alt_em10g32_0////////////m_arria10/altera_syncram_inst File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[1]/wrapper_inst/mac_inst/alt_em10g32_0/////////// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[1]/wrapper_inst/mac_inst/alt_em10g32_0/////////// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[1]/wrapper_inst/baser_inst/xcvr_native_a10_0/g_xcvr_native_insts[0]/twentynm_xcvr_native_inst//////twentynm_hssi_pma_channel_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/cyclone10gx_hssi_atoms_ncrypt.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Too few port connections. Expected 131, found 121. # Time: 0 fs Iteration: 0 Instance: /tb_top/dut/CHANNEL[1]/dc_fifo_adapter_inst File: ../../../rtl/mac/altera_eth_10g_mac/alt_em10g32_191/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'tx_egress_p2p_update_156'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'tx_egress_p2p_val_156'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'tx_egress_asymmetry_update_156'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'tx_egress_p2p_update_312'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'tx_egress_p2p_val_312'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'tx_egress_asymmetry_update_312'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'rx_ingress_p2p_val_valid_312'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'rx_ingress_p2p_val_312'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'rx_ingress_p2p_val_valid_156'. # ** Warning: (vsim-3722) ../../../rtl/altera_eth_10g_mac_base_r.sv(466): [TFMPC] - Missing connection for port 'rx_ingress_p2p_val_156'. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[1]/dc_fifo_adapter_inst///fifo_mem//// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[1]/dc_fifo_adapter_inst///fifo_mem//// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 fs Iteration: 0 Protected: /tb_top/dut/CHANNEL[1]/dc_fifo_adapter_inst///fifo_mem//// File: $MODEL_TECH/../altera/verilog/src/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3015) ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.v(89): [PCDPC] - Port size (3) does not match connection size (1) for port 'ir_out'. The port definition is at: ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_jtag_sld_node.v(18). # Time: 0 fs Iteration: 0 Instance: /tb_top/dut/address_decoder_inst/master_0/master_0/jtag_phy_embedded_in_jtag_master/genblk1/node File: ../../../rtl/address_decoder/ip/address_decode/address_decode_master_0/altera_jtag_dc_streaming_191/sim/altera_jtag_sld_node.v # ** Warning: Design size of 187312 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity. # Expect performance to be adversely affected. # wave activecursor not supported in batch mode # configure wave not supported in batch mode # configure wave not supported in batch mode # configure wave not supported in batch mode # configure wave not supported in batch mode # configure wave not supported in batch mode # configure wave not supported in batch mode # configure wave not supported in batch mode # configure wave not supported in batch mode # configure wave not supported in batch mode # configure wave not supported in batch mode # configure wave not supported in batch mode # configure wave not supported in batch mode # configure wave not supported in batch mode # # Warning: por to CB BFM is not connected, internal por is used. # # # ================================================ # Module twentynm_hssi_pma_lc_refclk_select_mux # ================================================ # inclk0_logical_to_physical_mapping = ref_iqclk0 # inclk1_logical_to_physical_mapping = power_down # inclk2_logical_to_physical_mapping = power_down # inclk3_logical_to_physical_mapping = power_down # inclk4_logical_to_physical_mapping = power_down # powerdown_mode = powerup # refclk_select = ref_iqclk0 # silicon_rev = 20nm1 # local_xmux_lc_scratch0_src = scratch0_src_iqclk # local_xmux_lc_scratch1_src = scratch1_src_iqclk # local_xmux_lc_scratch2_src = scratch2_src_iqclk # local_xmux_lc_scratch3_src = scratch3_src_iqclk # local_xmux_lc_scratch4_src = scratch4_src_iqclk # local_xmux_refclk_src = src_iqclk # local_xpm_iqref_mux_iqclk_sel = ref_iqclk0 # local_xpm_iqref_mux_scratch0_src = scratch0_ref_iqclk0 # local_xpm_iqref_mux_scratch1_src = scratch1_power_down # local_xpm_iqref_mux_scratch2_src = scratch2_power_down # local_xpm_iqref_mux_scratch3_src = scratch3_power_down # local_xpm_iqref_mux_scratch4_src = scratch4_power_down # # # ================================================ # Module twentynm_atx_pll # ================================================ # analog_mode = user_custom # bandwidth_range_high = 0 hz # bandwidth_range_low = 0 hz # bonding = cpri_bonding # bw_sel = low # cal_status = cal_done # calibration_mode = cal_off # cascadeclk_test = cascadetest_off # cgb_div = 1 # clk_high_perf_voltage = 000 # clk_low_power_voltage = 000 # clk_mid_power_voltage = 000 # cp_compensation_enable = true # cp_current_setting = cp_current_setting23 # cp_lf_3rd_pole_freq = lf_3rd_pole_setting2 # cp_lf_order = lf_3rd_order # cp_testmode = cp_normal # d2a_voltage = d2a_setting_4 # datarate = 10312500000 bps # device_variant = device1 # dprio_clk_vreg_boost_expected_voltage = 000 # dprio_clk_vreg_boost_scratch = 0 # dprio_clk_vreg_boost_step_size = 00 # dprio_lc_vreg1_boost_expected_voltage = 000 # dprio_lc_vreg1_boost_scratch = 0 # dprio_lc_vreg_boost_expected_voltage = 000 # dprio_lc_vreg_boost_scratch = 0 # dprio_mcgb_vreg_boost_expected_voltage = 000 # dprio_mcgb_vreg_boost_scratch = 0 # dprio_mcgb_vreg_boost_step_size = 00 # dprio_vreg1_boost_step_size = 00 # dprio_vreg_boost_step_size = 00 # dsm_ecn_bypass = false # dsm_ecn_test_en = false # dsm_fractional_division_bin = 00000000000000000000000000000001 # dsm_fractional_value_ready = pll_k_ready # dsm_mode = dsm_mode_integer # dsm_out_sel = pll_dsm_disable # enable_hclk = hclk_disabled # enable_idle_atx_pll_support = idle_none # enable_lc_calibration = false # enable_lc_vreg_calibration = false # expected_lc_boost_voltage = 000 # f_max_lcnt_fpll_cascading_bin = 00000000000000000000000000000001 # f_max_pfd = 0 hz # f_max_pfd_fractional = 0 hz # f_max_ref = 0 hz # f_max_tank_0 = 0 hz # f_max_tank_1 = 0 hz # f_max_tank_2 = 0 hz # f_max_vco = 0 hz # f_max_vco_fractional = 0 hz # f_max_x1 = 0 hz # f_min_pfd = 0 hz # f_min_ref = 0 hz # f_min_tank_0 = 0 hz # f_min_tank_1 = 0 hz # f_min_tank_2 = 0 hz # f_min_vco = 0 hz # fb_select = direct_fb # fpll_refclk_selection = select_vco_output # hclk_divide = 1 # initial_settings = true # iqclk_mux_sel = iqtxrxclk0 # is_cascaded_pll = false # is_otn = false # is_sdi = false # l_counter_scratch = 1 # l_counter_enable = true # l_counter_scratch = 01 # lc_atb = atb_selectdisable # lc_mode = lccmu_normal # lc_to_fpll_l_counter = lcounter_setting0 # lc_to_fpll_l_counter_scratch = 01 # lf_cbig_size = lf_cbig_setting4 # lf_resistance = lf_setting1 # lf_ripplecap = lf_ripple_cap_0 # m_counter = 64 # max_fractional_percentage = 00 # min_fractional_percentage = 00 # n_counter_scratch = 1 # output_clock_frequency = 5156250000 Hz # output_regulator_supply = vreg1v_setting0 # overrange_voltage = over_setting0 # pfd_delay_compensation = normal_delay # pfd_pulse_width = pulse_width_setting0 # pm_speed_grade = e2 # pma_width = 64 # power_mode = low_power # power_rail_et = 0 # powerdown_mode = powerup # primary_use = hssi_x1 # prot_mode = basic_tx # ref_clk_div = 4 # reference_clock_frequency = 322265625 Hz # regulator_bypass = reg_enable # side = side_unknown # silicon_rev = 20nm1 # sup_mode = user_mode # tank_band = lc_band4 # tank_sel = lctank1 # tank_voltage_coarse = vreg_setting_coarse0 # tank_voltage_fine = vreg_setting5 # top_or_bottom = tb_unknown # underrange_voltage = under_setting4 # vccdreg_clk = vreg_clk0 # vccdreg_fb = vreg_fb0 # vccdreg_fw = vreg_fw0 # vco_bypass_enable = false # vco_freq = 10312500000 Hz # xcpvco_xchgpmplf_cp_current_boost = normal_setting # # # ================================================ # Module twentynm_hssi_pma_adaptation # ================================================ # adapt_dfe_control_sel = r_adapt_dfe_control_sel_0 # adapt_dfe_sel = r_adapt_dfe_sel_0 # adapt_mode = manual # adapt_vga_sel = r_adapt_vga_sel_0 # adapt_vref_sel = r_adapt_vref_sel_0 # adp_1s_ctle_bypass = radp_1s_ctle_bypass_1 # adp_4s_ctle_bypass = radp_4s_ctle_bypass_1 # adp_adapt_control_sel = radp_adapt_control_sel_0 # adp_adapt_rstn = radp_adapt_rstn_1 # adp_adapt_start = radp_adapt_start_0 # adp_bist_auxpath_en = radp_bist_auxpath_disable # adp_bist_count_rstn = radp_bist_count_rstn_0 # adp_bist_datapath_en = radp_bist_datapath_disable # adp_bist_mode = radp_bist_mode_0 # adp_bist_odi_dfe_sel = radp_bist_odi_dfe_sel_0 # adp_bist_spec_en = radp_bist_spec_en_0 # adp_control_mux_bypass = radp_control_mux_bypass_0 # adp_ctle_acgain_4s = radp_ctle_acgain_4s_0 # adp_ctle_adapt_bw = radp_ctle_adapt_bw_3 # adp_ctle_adapt_cycle_window = radp_ctle_adapt_cycle_window_7 # adp_ctle_adapt_oneshot = radp_ctle_adapt_oneshot_1 # adp_ctle_en = radp_ctle_disable # adp_ctle_eqz_1s_sel = radp_ctle_eqz_1s_sel_0 # adp_ctle_force_spec_sign = radp_ctle_force_spec_sign_0 # adp_ctle_hold_en = radp_ctle_not_held # adp_ctle_load = radp_ctle_load_0 # adp_ctle_load_value = radp_ctle_load_value_0 # adp_ctle_scale = radp_ctle_scale_0 # adp_ctle_scale_en = radp_ctle_scale_en_0 # adp_ctle_spec_sign = radp_ctle_spec_sign_0 # adp_ctle_sweep_direction = radp_ctle_sweep_direction_1 # adp_ctle_threshold = radp_ctle_threshold_0 # adp_ctle_threshold_en = radp_ctle_threshold_en_0 # adp_ctle_vref_polarity = radp_ctle_vref_polarity_0 # adp_ctle_window = radp_ctle_window_0 # adp_dfe_bw = radp_dfe_bw_3 # adp_dfe_clkout_div_sel = radp_dfe_clkout_div_sel_0 # adp_dfe_cycle = radp_dfe_cycle_6 # adp_dfe_fltap_bypass = radp_dfe_fltap_bypass_1 # adp_dfe_fltap_en = radp_dfe_fltap_disable # adp_dfe_fltap_hold_en = radp_dfe_fltap_not_held # adp_dfe_fltap_load = radp_dfe_fltap_load_0 # adp_dfe_fltap_position = radp_dfe_fltap_position_0 # adp_dfe_force_spec_sign = radp_dfe_force_spec_sign_0 # adp_dfe_fxtap1 = radp_dfe_fxtap1_0 # adp_dfe_fxtap10 = radp_dfe_fxtap10_0 # adp_dfe_fxtap10_sgn = radp_dfe_fxtap10_sgn_0 # adp_dfe_fxtap11 = radp_dfe_fxtap11_0 # adp_dfe_fxtap11_sgn = radp_dfe_fxtap11_sgn_0 # adp_dfe_fxtap2 = radp_dfe_fxtap2_0 # adp_dfe_fxtap2_sgn = radp_dfe_fxtap2_sgn_0 # adp_dfe_fxtap3 = radp_dfe_fxtap3_0 # adp_dfe_fxtap3_sgn = radp_dfe_fxtap3_sgn_0 # adp_dfe_fxtap4 = radp_dfe_fxtap4_0 # adp_dfe_fxtap4_sgn = radp_dfe_fxtap4_sgn_0 # adp_dfe_fxtap5 = radp_dfe_fxtap5_0 # adp_dfe_fxtap5_sgn = radp_dfe_fxtap5_sgn_0 # adp_dfe_fxtap6 = radp_dfe_fxtap6_0 # adp_dfe_fxtap6_sgn = radp_dfe_fxtap6_sgn_0 # adp_dfe_fxtap7 = radp_dfe_fxtap7_0 # adp_dfe_fxtap7_sgn = radp_dfe_fxtap7_sgn_0 # adp_dfe_fxtap8 = radp_dfe_fxtap8_0 # adp_dfe_fxtap8_sgn = radp_dfe_fxtap8_sgn_0 # adp_dfe_fxtap9 = radp_dfe_fxtap9_0 # adp_dfe_fxtap9_sgn = radp_dfe_fxtap9_sgn_0 # adp_dfe_fxtap_bypass = radp_dfe_fxtap_bypass_1 # adp_dfe_fxtap_en = radp_dfe_fxtap_disable # adp_dfe_fxtap_hold_en = radp_dfe_fxtap_not_held # adp_dfe_fxtap_load = radp_dfe_fxtap_load_0 # adp_dfe_mode = radp_dfe_mode_4 # adp_dfe_spec_sign = radp_dfe_spec_sign_0 # adp_dfe_vref_polarity = radp_dfe_vref_polarity_0 # adp_force_freqlock = radp_force_freqlock_off # adp_frame_capture = radp_frame_capture_0 # adp_frame_en = radp_frame_en_0 # adp_frame_odi_sel = radp_frame_odi_sel_0 # adp_frame_out_sel = radp_frame_out_sel_0 # adp_lfeq_fb_sel = radp_lfeq_fb_sel_0 # adp_mode = radp_mode_8 # adp_odi_control_sel = radp_odi_control_sel_0 # adp_onetime_dfe = radp_onetime_dfe_0 # adp_spec_avg_window = radp_spec_avg_window_4 # adp_spec_trans_filter = radp_spec_trans_filter_2 # adp_status_sel = radp_status_sel_0 # adp_vga_bypass = radp_vga_bypass_1 # adp_vga_en = radp_vga_disable # adp_vga_load = radp_vga_load_0 # adp_vga_polarity = radp_vga_polarity_0 # adp_vga_sel = radp_vga_sel_0 # adp_vga_sweep_direction = radp_vga_sweep_direction_1 # adp_vga_threshold = radp_vga_threshold_4 # adp_vref_bw = radp_vref_bw_1 # adp_vref_bypass = radp_vref_bypass_1 # adp_vref_cycle = radp_vref_cycle_6 # adp_vref_dfe_spec_en = radp_vref_dfe_spec_en_0 # adp_vref_en = radp_vref_disable # adp_vref_hold_en = radp_vref_not_held # adp_vref_load = radp_vref_load_0 # adp_vref_polarity = radp_vref_polarity_0 # adp_vref_sel = radp_vref_sel_21 # adp_vref_vga_level = radp_vref_vga_level_13 # datarate = 10312500000 bps # initial_settings = true # odi_count_threshold = rodi_count_threshold_0 # odi_dfe_spec_en = rodi_dfe_spec_en_0 # odi_en = rodi_en_0 # odi_mode = rodi_mode_0 # odi_rstn = rodi_rstn_0 # odi_spec_sel = rodi_spec_sel_0 # odi_start = rodi_start_0 # odi_vref_sel = rodi_vref_sel_0 # optimal = false # prot_mode = basic_rx # rrx_pcie_eqz = rrx_pcie_eqz_0 # silicon_rev = 20nm1 # sup_mode = user_mode # # # ================================================ # Module twentynm_hssi_pma_cdr_refclk_select_mux # ================================================ # local_cdr_clkin_scratch0_src = cdr_clkin_scratch0_src_refclk_iqclk # local_cdr_clkin_scratch1_src = cdr_clkin_scratch1_src_refclk_iqclk # local_cdr_clkin_scratch2_src = cdr_clkin_scratch2_src_refclk_iqclk # local_cdr_clkin_scratch3_src = cdr_clkin_scratch3_src_refclk_iqclk # local_cdr_clkin_scratch4_src = cdr_clkin_scratch4_src_refclk_iqclk # inclk0_logical_to_physical_mapping = ref_iqclk0 # inclk1_logical_to_physical_mapping = power_down # inclk2_logical_to_physical_mapping = power_down # inclk3_logical_to_physical_mapping = power_down # inclk4_logical_to_physical_mapping = power_down # powerdown_mode = powerup # receiver_detect_src = iqclk_src # refclk_select = ref_iqclk0 # silicon_rev = 20nm1 # local_xmux_refclk_src = refclk_iqclk # local_xpm_iqref_mux_iqclk_sel = ref_iqclk0 # local_xpm_iqref_mux_scratch0_src = scratch0_ref_iqclk0 # local_xpm_iqref_mux_scratch1_src = scratch1_power_down # local_xpm_iqref_mux_scratch2_src = scratch2_power_down # local_xpm_iqref_mux_scratch3_src = scratch3_power_down # local_xpm_iqref_mux_scratch4_src = scratch4_power_down # # # ================================================ # Module twentynm_hssi_pma_channel_pll # ================================================ # analog_mode = user_custom # atb_select_control = atb_off # auto_reset_on = auto_reset_off # bandwidth_range_high = 0 hz # bandwidth_range_low = 0 hz # bbpd_data_pattern_filter_select = bbpd_data_pat_off # bw_sel = medium # cal_vco_count_length = sel_8b_count # cdr_odi_select = sel_cdr # cdr_phaselock_mode = no_ignore_lock # cdr_powerdown_mode = power_up # cgb_div = 1 # chgpmp_current_dn_pd = cp_current_pd_dn_setting3 # chgpmp_current_dn_trim = cp_current_trimming_dn_setting0 # chgpmp_current_pfd = cp_current_pfd_setting2 # chgpmp_current_up_pd = cp_current_pd_up_setting3 # chgpmp_current_up_trim = cp_current_trimming_up_setting0 # chgpmp_dn_pd_trim_double = normal_dn_trim_current # chgpmp_replicate = false # chgpmp_testmode = cp_test_disable # chgpmp_up_pd_trim_double = normal_up_trim_current # chgpmp_vccreg = vreg_fw0 # clklow_mux_select = clklow_mux_cdr_fbclk # datarate = 10312500000 bps # diag_loopback_enable = false # disable_up_dn = true # enable_idle_rx_channel_support = false # f_max_cmu_out_freq_bin = 00000000000000000000000000000001 # f_max_m_counter_bin = 00000000000000000000000000000001 # f_max_pfd = 0 hz # f_max_ref = 0 hz # f_max_vco = 0 hz # f_min_gt_channel = 0 hz # f_min_pfd = 0 hz # f_min_ref = 0 hz # f_min_vco = 0 hz # fb_select = direct_fb # fref_clklow_div = 1 # fref_mux_select = fref_mux_cdr_refclk # gpon_lck2ref_control = gpon_lck2ref_off # initial_settings = true # iqclk_mux_sel = power_down # is_cascaded_pll = false # lck2ref_delay_control = lck2ref_delay_2 # lf_resistor_pd = lf_pd_setting2 # lf_resistor_pfd = lf_pfd_setting2 # lf_ripple_cap = lf_no_ripple # loop_filter_bias_select = lpflt_bias_7 # loopback_mode = loopback_disabled # lpd_counter = 01 # lpfd_counter = 01 # ltd_ltr_micro_controller_select = ltd_ltr_pcs # m_counter = 16 # n_counter_scratch = 1 # n_counter_scratch = 01 # optimal = false # output_clock_frequency = 5156250000 Hz # pcie_gen = non_pcie # pd_fastlock_mode = false # pd_l_counter = 1 # pfd_l_counter = 1 # pm_speed_grade = e2 # pma_width = 32 # position = position_unknown # power_mode = low_power # primary_use = cdr # prot_mode = basic_rx # reference_clock_frequency = 322265625 hz # requires_gt_capable_channel = false # reverse_serial_loopback = no_loopback # set_cdr_input_freq_range = 00 # set_cdr_v2i_enable = true # set_cdr_vco_reset = false # set_cdr_vco_speed = 03 # set_cdr_vco_speed_fix = 3c # set_cdr_vco_speed_pciegen3 = cdr_vco_max_speedbin_pciegen3 # side = side_unknown # silicon_rev = 20nm1 # sup_mode = user_mode # top_or_bottom = tb_unknown # tx_pll_prot_mode = txpll_unused # txpll_hclk_driver_enable = false # uc_cru_rstb = cdr_lf_reset_off # uc_ro_cal = uc_ro_cal_on # uc_ro_cal_status = uc_ro_cal_notdone # vco_freq = 5156250000 Hz # vco_overrange_voltage = vco_overrange_off # vco_underrange_voltage = vco_underange_off # # # ================================================ # Module twentynm_hssi_pma_rx_buf # ================================================ # act_isource_disable = isrc_en # bodybias_enable = bodybias_en # bodybias_select = bodybias_sel1 # bypass_eqz_stages_234 = bypass_off # cdrclk_to_cgb = cdrclk_2cgb_dis # cgm_bias_disable = cgmbias_en # datarate = 10312500000 bps # diag_lp_en = dlp_off # eq_bw_sel = eq_bw_1 # eq_dc_gain_trim = no_dc_gain # xrx_path_initial_settings = true # input_vcm_sel = high_vcm # iostandard = hssi_diffio # lfeq_enable = non_lfeq_mode # lfeq_zero_control = lfeq_setting_2 # link_rx = sr # link_rx = sr # loopback_modes = lpbk_disable # offset_cal_pd = eqz1_en # offset_cancellation_coarse = coarse_setting_00 # offset_cancellation_ctrl = volt_0mv # offset_cancellation_fine = fine_setting_00 # offset_pd = oc_en # one_stage_enable = non_s1_mode # xrx_path_optimal = false # pdb_rx = normal_rx_on # pm_speed_grade = e2 # pm_tx_rx_cvp_mode = cvp_off # pm_tx_rx_pcie_gen = non_pcie # pm_tx_rx_pcie_gen_bitwidth = pcie_gen3_32b # pm_tx_rx_testmux_select = setting0 # power_mode_rx = low_power # power_mode_rx = low_power # power_rail_eht = 0 # power_rail_er = 0 # xrx_path_prot_mode = basic_rx # qpi_enable = non_qpi_mode # refclk_en = disable # rx_atb_select = atb_disable # rx_refclk_divider = bypass_divider # rx_sel_bias_source = bias_vcmdrv # rx_vga_oc_en = vga_cal_off # silicon_rev = 20nm1 # xrx_path_sup_mode = user_mode # term_sel = r_r1 # term_tri_enable = disable_tri # vccela_supply_voltage = vccela_1p1v # vcm_current_add = vcm_current_default # vcm_sel = vcm_setting_10 # vga_bandwidth_select = vga_bw_1 # xrx_path_analog_mode = user_custom # xrx_path_datarate = 10312500000 bps # xrx_path_datawidth = 20 # xrx_path_gt_enabled = disable # xrx_path_initial_settings = true # xrx_path_jtag_hys = hys_increase_disable # xrx_path_jtag_lp = lp_off # xrx_path_optimal = false # xrx_path_pma_rx_divclk_hz_bin = 00000000000000000000000013356219 # xrx_path_prot_mode = basic_rx # xrx_path_sup_mode = user_mode # xrx_path_uc_cal_enable = rx_cal_off # xrx_path_uc_cru_rstb = cdr_lf_reset_off # xrx_path_uc_pcie_sw = uc_pcie_gen1 # xrx_path_uc_rx_rstb = rx_reset_on # # # ================================================ # Module twentynm_hssi_pma_rx_deser # ================================================ # bitslip_bypass = bs_bypass_yes # clkdiv_source = vco_bypass_normal # clkdivrx_user_mode = clkdivrx_user_clkdiv_div2 # datarate = 10312500000 bps # deser_factor = 32 # deser_powerdown = deser_power_up # force_adaptation_outputs = normal_outputs # force_clkdiv_for_testing = normal_clkdiv # optimal = false # pcie_gen = non_pcie # pcie_gen_bitwidth = pcie_gen3_32b # prot_mode = basic_rx # rst_n_adapt_odi = no_rst_adapt_odi # sdclk_enable = false # silicon_rev = 20nm1 # sup_mode = user_mode # tdr_mode = select_bbpd_data # # # ================================================ # Module twentynm_hssi_pma_rx_dfe # ================================================ # atb_select = atb_disable # datarate = 10312500000 bps # dft_en = dft_disable # initial_settings = true # oc_sa_adp1 = 00 # oc_sa_adp2 = 00 # oc_sa_c270 = 00 # oc_sa_c90 = 00 # oc_sa_d0c0 = 00 # oc_sa_d0c180 = 00 # oc_sa_d1c0 = 00 # oc_sa_d1c180 = 00 # optimal = false # pdb = 6466655f656e61626c65 # pdb_fixedtap = fixtap_dfe_powerdown # pdb_floattap = floattap_dfe_powerdown # pdb_fxtap4t7 = fxtap4t7_powerdown # power_mode = low_power # prot_mode = basic_rx # sel_fltapstep_dec = fltap_step_no_dec # sel_fltapstep_inc = fltap_step_no_inc # sel_fxtapstep_dec = fxtap_step_no_dec # sel_fxtapstep_inc = fxtap_step_no_inc # sel_oc_en = off_canc_disable # sel_probe_tstmx = probe_tstmx_none # silicon_rev = 20nm1 # sup_mode = user_mode # uc_rx_dfe_cal = uc_rx_dfe_cal_off # uc_rx_dfe_cal_status = uc_rx_dfe_cal_notdone # # # ================================================ # Module twentynm_hssi_pma_rx_odi # ================================================ # clk_dcd_bypass = no_bypass # datarate = 10312500000 bps # enable_odi = power_down_eye # initial_settings = true # invert_dfe_vref = no_inversion # monitor_bw_sel = bw_1 # oc_sa_c0 = 00 # oc_sa_c180 = 00 # optimal = false # phase_steps_64_vs_128 = phase_steps_64 # phase_steps_sel = step40 # power_mode = low_power # prot_mode = basic_rx # sel_oc_en = off_canc_disable # silicon_rev = 20nm1 # step_ctrl_sel = dprio_mode # sup_mode = user_mode # v_vert_sel = plus # v_vert_threshold_scaling = scale_3 # vert_threshold = vert_0 # # # ================================================ # Module twentynm_hssi_pma_rx_sd # ================================================ # link = sr # optimal = false # power_mode = low_power # prot_mode = basic_rx # sd_output_off = 1 # sd_output_on = 15 # sd_pdb = sd_off # sd_threshold = sdlv_3 # silicon_rev = 20nm1 # sup_mode = user_mode # # # ================================================ # Module twentynm_hssi_pma_tx_buf # ================================================ # xtx_path_calibration_en = false # calibration_resistor_value = res_setting0 # cdr_cp_calibration_en = cdr_cp_cal_disable # chgpmp_current_dn_trim = cp_current_trimming_dn_setting0 # chgpmp_current_up_trim = cp_current_trimming_up_setting0 # chgpmp_dn_trim_double = normal_dn_trim_current # chgpmp_up_trim_double = normal_up_trim_current # compensation_driver_en = disable # compensation_en = enable # cpen_ctrl = cp_l0 # datarate = 10312500000 bps # dcd_clk_div_ctrl = dcd_ck_div128 # dcd_detection_en = enable # dft_sel = dft_disabled # duty_cycle_correction_bandwidth = dcc_bw_12 # duty_cycle_correction_bandwidth_dn = dcd_bw_dn_0 # duty_cycle_correction_mode_ctrl = dcc_disable # duty_cycle_correction_reference1 = dcc_ref1_3 # duty_cycle_correction_reference2 = dcc_ref2_3 # duty_cycle_correction_reset_n = reset_n # duty_cycle_cp_comp_en = cp_comp_off # duty_cycle_detector_cp_cal = dcd_cp_cal_disable # duty_cycle_detector_sa_cal = dcd_sa_cal_disable # duty_cycle_input_polarity = dcc_input_pos # duty_cycle_setting = dcc_t32 # duty_cycle_setting_aux = dcc2_t32 # enable_idle_tx_channel_support = false # xtx_path_initial_settings = true # jtag_drv_sel = drv1 # jtag_lp = lp_off # link_tx = sr # link_tx = sr # low_power_en = disable # lst = 6174625f64697361626c6564 # mcgb_location_for_pcie = 0 # xtx_path_optimal = false # pm_speed_grade = e2 # power_mode = low_power # power_rail_eht = 0 # power_rail_et = 0 # pre_emp_sign_1st_post_tap = fir_post_1t_neg # pre_emp_sign_2nd_post_tap = fir_post_2t_neg # pre_emp_sign_pre_tap_1t = fir_pre_1t_neg # pre_emp_sign_pre_tap_2t = fir_pre_2t_neg # pre_emp_switching_ctrl_1st_post_tap = 00 # pre_emp_switching_ctrl_2nd_post_tap = 0 # pre_emp_switching_ctrl_pre_tap_1t = 00 # pre_emp_switching_ctrl_pre_tap_2t = 0 # xtx_path_prot_mode = basic_tx # res_cal_local = non_local # rx_det = mode_0 # rx_det_output_sel = rx_det_pcie_out # rx_det_pdb = rx_det_off # sense_amp_offset_cal_curr_n = sa_os_cal_in_0 # sense_amp_offset_cal_curr_p = 00 # ser_powerdown = normal_ser_on # silicon_rev = 20nm1 # slew_rate_ctrl = slew_r7 # xtx_path_sup_mode = user_mode # xtx_path_swing_level = lv # term_code = rterm_code7 # term_n_tune = rterm_n0 # term_p_tune = rterm_p0 # term_sel = r_r1 # tri_driver = tri_driver_disable # tx_powerdown = normal_tx_on # uc_dcd_cal = uc_dcd_cal_off # uc_dcd_cal_status = uc_dcd_cal_notdone # uc_gen3 = gen3_off # uc_gen4 = gen4_off # uc_skew_cal = uc_skew_cal_off # uc_skew_cal_status = uc_skew_cal_notdone # uc_txvod_cal = uc_tx_vod_cal_off # uc_txvod_cal_cont = uc_tx_vod_cal_cont_off # uc_txvod_cal_status = uc_tx_vod_cal_notdone # uc_vcc_setting = vcc_setting0 # user_fir_coeff_ctrl_sel = ram_ctl # vod_output_swing_ctrl = 00 # vreg_output = vccdreg_nominal # xtx_path_analog_mode = user_custom # xtx_path_bonding_mode = x1_non_bonded # xtx_path_calibration_en = false # xtx_path_clock_divider_ratio = 1 # xtx_path_datarate = 10312500000 bps # xtx_path_datawidth = 20 # xtx_path_gt_enabled = disable # xtx_path_initial_settings = true # xtx_path_optimal = false # xtx_path_pma_tx_divclk_hz_bin = 00000000000000000000000013356219 # xtx_path_prot_mode = basic_tx # xtx_path_sup_mode = user_mode # xtx_path_swing_level = lv # xtx_path_tx_pll_clk_hz = 5156250000 # # ================ INPUT ================= # prot_mode = basic_tx # input_select_x1 = fpll_bot # input_select_xn = unused # input_select_gen3 = unused # ================ OUTPUT ================ # x1_clock_source_sel = fpll_bot # xn_clock_source_sel = sel_cgb_loc # ================ END =================== # # # # ================================================ # Module twentynm_hssi_pma_tx_cgb # ================================================ # bitslip_enable = disable_bitslip # bonding_mode = x1_non_bonded # bonding_reset_enable = disallow_bonding_reset # cgb_power_down = normal_cgb # datarate = 10312500000 bps # dprio_cgb_vreg_boost = no_voltage_boost # initial_settings = true # input_select_gen3 = unused # input_select_x1 = fpll_bot # input_select_xn = unused # observe_cgb_clocks = observe_nothing # pcie_gen3_bitwidth = pciegen3_wide # prot_mode = basic_tx # scratch0_x1_clock_src = fpll_bot # scratch1_x1_clock_src = unused # scratch2_x1_clock_src = unused # scratch3_x1_clock_src = unused # select_done_master_or_slave = choose_slave_pcie_sw_done # ser_mode = thirty_two_bit # ser_powerdown = normal_poweron_ser # silicon_rev = 20nm1 # sup_mode = user_mode # tx_ucontrol_en = disable # tx_ucontrol_pcie = gen1 # tx_ucontrol_reset = disable # vccdreg_output = vccdreg_nominal # local_x1_clock_source_sel = fpll_bot # x1_div_m_sel = divbypass # local_xn_clock_source_sel = sel_cgb_loc # # # ================================================ # Module twentynm_hssi_pma_tx_ser # ================================================ # bonding_mode = x1_non_bonded # clk_divtx_deskew = deskew_delay8 # control_clk_divtx = no_dft_control_clkdivtx # duty_cycle_correction_mode_ctrl = dcc_disable # initial_settings = true # prot_mode = basic_tx # ser_clk_divtx_user_sel = divtx_user_2 # ser_clk_mon = disable_clk_mon # ser_powerdown = normal_poweron_ser # silicon_rev = 20nm1 # sup_mode = user_mode # # # ================================================ # Module twentynm_hssi_10g_rx_pcs # ================================================ # advanced_user_mode = disable # align_del = align_del_dis # ber_bit_err_total_cnt = bit_err_total_cnt_10g # ber_clken = ber_clk_en # ber_xus_timer_window = 004c4a # bitslip_mode = bitslip_dis # blksync_bitslip_type = bitslip_comb # blksync_bitslip_wait_cnt = 1 # blksync_bitslip_wait_type = bitslip_cnt # blksync_bypass = blksync_bypass_dis # blksync_clken = blksync_clk_en # blksync_enum_invalid_sh_cnt = enum_invalid_sh_cnt_10g # blksync_knum_sh_cnt_postlock = knum_sh_cnt_postlock_10g # blksync_knum_sh_cnt_prelock = knum_sh_cnt_prelock_10g # blksync_pipeln = blksync_pipeln_dis # clr_errblk_cnt_en = enable # control_del = control_del_none # crcchk_bypass = crcchk_bypass_en # crcchk_clken = crcchk_clk_dis # crcchk_inv = crcchk_inv_en # crcchk_pipeln = crcchk_pipeln_en # crcflag_pipeln = crcflag_pipeln_en # ctrl_bit_reverse = ctrl_bit_reverse_en # data_bit_reverse = data_bit_reverse_dis # dec64b66b_clken = dec64b66b_clk_en # dec_64b66b_rxsm_bypass = dec_64b66b_rxsm_bypass_dis # descrm_bypass = descrm_bypass_dis # descrm_clken = descrm_clk_en # descrm_mode = async # descrm_pipeln = enable # dft_clk_out_sel = rx_master_clk # dis_signal_ok = dis_signal_ok_en # dispchk_bypass = dispchk_bypass_en # empty_flag_type = empty_rd_side # fast_path = fast_path_dis # fec_clken = fec_clk_dis # fec_enable = fec_dis # fifo_double_read = fifo_double_read_dis # fifo_stop_rd = n_rd_empty # fifo_stop_wr = n_wr_full # force_align = force_align_dis # frmsync_bypass = frmsync_bypass_en # frmsync_clken = frmsync_clk_dis # frmsync_enum_scrm = enum_scrm_default # frmsync_enum_sync = enum_sync_default # frmsync_flag_type = location_only # frmsync_knum_sync = knum_sync_default # frmsync_mfrm_length = 0800 # frmsync_pipeln = frmsync_pipeln_en # full_flag_type = full_wr_side # gb_rx_idwidth = width_32 # gb_rx_odwidth = width_66 # gbexp_clken = gbexp_clk_en # low_latency_en = disable # lpbk_mode = lpbk_dis # master_clk_sel = master_rx_pma_clk # pempty_flag_type = pempty_rd_side # pfull_flag_type = pfull_wr_side # phcomp_rd_del = phcomp_rd_del2 # pld_if_type = fifo # prot_mode = teng_baser_mode # rand_clken = rand_clk_en # rd_clk_sel = rd_rx_pld_clk # rdfifo_clken = rdfifo_clk_en # reconfig_settings = {} # rx_fifo_write_ctrl = blklock_stops # rx_scrm_width = bit64 # rx_sh_location = lsb # rx_signal_ok_sel = synchronized_ver # rx_sm_bypass = rx_sm_bypass_dis # rx_sm_hiber = rx_sm_hiber_en # rx_sm_pipeln = rx_sm_pipeln_en # rx_testbus_sel = rx_fifo_testbus1 # rx_true_b2b = b2b # rxfifo_empty = empty_default # rxfifo_full = full_default # rxfifo_mode = clk_comp_10g # rxfifo_pempty = 02 # rxfifo_pfull = 17 # silicon_rev = 20nm1 # stretch_num_stages = two_stage # sup_mode = user_mode # test_mode = test_off # wrfifo_clken = wrfifo_clk_en # # # ================================================ # Module twentynm_hssi_10g_tx_pcs # ================================================ # advanced_user_mode = disable # bitslip_en = bitslip_dis # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # comp_cnt = 00 # compin_sel = compin_master # crcgen_bypass = crcgen_bypass_en # crcgen_clken = crcgen_clk_dis # crcgen_err = crcgen_err_dis # crcgen_inv = crcgen_inv_en # ctrl_bit_reverse = ctrl_bit_reverse_en # ctrl_plane_bonding = individual # data_bit_reverse = data_bit_reverse_dis # dft_clk_out_sel = tx_master_clk # dispgen_bypass = dispgen_bypass_en # dispgen_clken = dispgen_clk_dis # dispgen_err = dispgen_err_dis # dispgen_pipeln = dispgen_pipeln_dis # distdwn_bypass_pipeln = distdwn_bypass_pipeln_dis # distdwn_master = distdwn_master_en # distup_bypass_pipeln = distup_bypass_pipeln_dis # distup_master = distup_master_en # dv_bond = dv_bond_dis # empty_flag_type = empty_rd_side # enc64b66b_txsm_clken = enc64b66b_txsm_clk_en # enc_64b66b_txsm_bypass = enc_64b66b_txsm_bypass_dis # fastpath = fastpath_dis # fec_clken = fec_clk_dis # fec_enable = fec_dis # fifo_double_write = fifo_double_write_dis # fifo_reg_fast = fifo_reg_fast_dis # fifo_stop_rd = rd_empty # fifo_stop_wr = n_wr_full # frmgen_burst = frmgen_burst_dis # frmgen_bypass = frmgen_bypass_en # frmgen_clken = frmgen_clk_dis # frmgen_mfrm_length = 0800 # frmgen_pipeln = frmgen_pipeln_en # frmgen_pyld_ins = frmgen_pyld_ins_dis # frmgen_wordslip = frmgen_wordslip_dis # full_flag_type = full_wr_side # gb_pipeln_bypass = disable # gb_tx_idwidth = width_66 # gb_tx_odwidth = width_32 # gbred_clken = gbred_clk_en # indv = indv_en # low_latency_en = disable # master_clk_sel = master_tx_pma_clk # pempty_flag_type = pempty_rd_side # pfull_flag_type = pfull_wr_side # phcomp_rd_del = phcomp_rd_del4 # pld_if_type = fifo # prot_mode = teng_baser_mode # pseudo_random = all_0 # pseudo_seed_a_bin = 000000000000000003ffffffffffffff # pseudo_seed_b_bin = 000000000000000003ffffffffffffff # random_disp = disable # rdfifo_clken = rdfifo_clk_en # reconfig_settings = {} # scrm_bypass = scrm_bypass_dis # scrm_clken = scrm_clk_en # scrm_mode = async # scrm_pipeln = enable # sh_err = sh_err_dis # silicon_rev = 20nm1 # sop_mark = sop_mark_dis # stretch_num_stages = two_stage # sup_mode = user_mode # test_mode = test_off # tx_scrm_err = scrm_err_dis # tx_scrm_width = bit64 # tx_sh_location = lsb # tx_sm_bypass = tx_sm_bypass_dis # tx_sm_pipeln = tx_sm_pipeln_en # tx_testbus_sel = tx_fifo_testbus1 # txfifo_empty = empty_default # txfifo_full = full_default # txfifo_mode = phase_comp # txfifo_pempty = 2 # txfifo_pfull = b # wr_clk_sel = wr_tx_pld_clk # wrfifo_clken = wrfifo_clk_en # # # ================================================ # Module twentynm_hssi_8g_rx_pcs # ================================================ # auto_error_replacement = dis_err_replace # auto_speed_nego = dis_asn # bit_reversal = dis_bit_reversal # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # bypass_pipeline_reg = dis_bypass_pipeline # byte_deserializer = dis_bds # cdr_ctrl_rxvalid_mask = dis_rxvalid_mask # clkcmp_pattern_n = 00000 # clkcmp_pattern_p = 00000 # clock_gate_bds_dec_asn = en_bds_dec_asn_clk_gating # clock_gate_cdr_eidle = en_cdr_eidle_clk_gating # clock_gate_dw_pc_wrclk = en_dw_pc_wrclk_gating # clock_gate_dw_rm_rd = en_dw_rm_rdclk_gating # clock_gate_dw_rm_wr = en_dw_rm_wrclk_gating # clock_gate_dw_wa = en_dw_wa_clk_gating # clock_gate_pc_rdclk = en_pc_rdclk_gating # clock_gate_sw_pc_wrclk = en_sw_pc_wrclk_gating # clock_gate_sw_rm_rd = en_sw_rm_rdclk_gating # clock_gate_sw_rm_wr = en_sw_rm_wrclk_gating # clock_gate_sw_wa = en_sw_wa_clk_gating # clock_observation_in_pld_core = internal_sw_wa_clk # ctrl_plane_bonding_compensation = dis_compensation # ctrl_plane_bonding_consumption = individual # ctrl_plane_bonding_distribution = not_master_chnl_distr # eidle_entry_eios = dis_eidle_eios # eidle_entry_iei = dis_eidle_iei # eidle_entry_sd = dis_eidle_sd # eightb_tenb_decoder = en_8b10b_ibm # err_flags_sel = err_flags_wa # fixed_pat_det = dis_fixed_patdet # fixed_pat_num = 0 # force_signal_detect = en_force_signal_detect # gen3_clk_en = disable_clk # gen3_rx_clk_sel = rcvd_clk # gen3_tx_clk_sel = tx_pma_clk # hip_mode = dis_hip # ibm_invalid_code = dis_ibm_invalid_code # invalid_code_flag_only = dis_invalid_code_only # pad_or_edb_error_replace = replace_edb # pcs_bypass = dis_pcs_bypass # phase_comp_rdptr = disable_rdptr # phase_compensation_fifo = low_latency # pipe_if_enable = dis_pipe_rx # pma_dw = ten_bit # polinv_8b10b_dec = dis_polinv_8b10b_dec # prot_mode = disabled_prot_mode # rate_match = dis_rm # rate_match_del_thres = dis_rm_del_thres # rate_match_empty_thres = dis_rm_empty_thres # rate_match_full_thres = dis_rm_full_thres # rate_match_ins_thres = dis_rm_ins_thres # rate_match_start_thres = dis_rm_start_thres # reconfig_settings = {} # rx_clk2 = rcvd_clk_clk2 # rx_clk_free_running = en_rx_clk_free_run # rx_pcs_urst = en_rx_pcs_urst # rx_rcvd_clk = rcvd_clk_rcvd_clk # rx_rd_clk = pld_rx_clk # rx_refclk = dis_refclk_sel # rx_wr_clk = rx_clk2_div_1_2_4 # silicon_rev = 20nm1 # sup_mode = user_mode # symbol_swap = dis_symbol_swap # sync_sm_idle_eios = dis_syncsm_idle # test_bus_sel = tx_testbus # tx_rx_parallel_loopback = dis_plpbk # wa_boundary_lock_ctrl = sync_sm # wa_clk_slip_spacing = 010 # wa_det_latency_sync_status_beh = dont_care_assert_sync # wa_disp_err_flag = en_disp_err_flag # wa_kchar = dis_kchar # wa_pd = wa_pd_10 # wa_pd_data_bin = 00000000000000000000000000000000 # wa_pd_polarity = dont_care_both_pol # wa_pld_controlled = dis_pld_ctrl # wa_renumber_data = 03 # wa_rgnumber_data = 03 # wa_rknumber_data = 03 # wa_rosnumber_data = 1 # wa_rvnumber_data = 0000 # wa_sync_sm_ctrl = gige_sync_sm # wait_cnt = 000 # # # ================================================ # Module twentynm_hssi_8g_tx_pcs # ================================================ # auto_speed_nego_gen2 = dis_asn_g2 # bit_reversal = dis_bit_reversal # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # bypass_pipeline_reg = dis_bypass_pipeline # byte_serializer = dis_bs # clock_gate_bs_enc = en_bs_enc_clk_gating # clock_gate_dw_fifowr = en_dw_fifowr_clk_gating # clock_gate_fiford = en_fiford_clk_gating # clock_gate_sw_fifowr = en_sw_fifowr_clk_gating # clock_observation_in_pld_core = internal_refclk_b # ctrl_plane_bonding_compensation = dis_compensation # ctrl_plane_bonding_consumption = individual # ctrl_plane_bonding_distribution = not_master_chnl_distr # data_selection_8b10b_encoder_input = normal_data_path # dynamic_clk_switch = dis_dyn_clk_switch # eightb_tenb_disp_ctrl = dis_disp_ctrl # eightb_tenb_encoder = en_8b10b_ibm # force_echar = dis_force_echar # force_kchar = dis_force_kchar # gen3_tx_clk_sel = dis_tx_clk # gen3_tx_pipe_clk_sel = dis_tx_pipe_clk # hip_mode = dis_hip # pcs_bypass = dis_pcs_bypass # phase_comp_rdptr = disable_rdptr # phase_compensation_fifo = low_latency # phfifo_write_clk_sel = pld_tx_clk # pma_dw = ten_bit # prot_mode = disabled_prot_mode # reconfig_settings = {} # refclk_b_clk_sel = tx_pma_clock # revloop_back_rm = dis_rev_loopback_rx_rm # silicon_rev = 20nm1 # sup_mode = user_mode # symbol_swap = dis_symbol_swap # tx_bitslip = dis_tx_bitslip # tx_compliance_controlled_disparity = dis_txcompliance # tx_fast_pld_reg = dis_tx_fast_pld_reg # txclk_freerun = en_freerun_tx # txpcs_urst = en_txpcs_urst # # # ================================================ # Module twentynm_hssi_common_pcs_pma_interface # ================================================ # asn_clk_enable = false # asn_enable = dis_asn # block_sel = eight_g_pcs # bypass_early_eios = true # bypass_pcie_switch = true # bypass_pma_ltr = true # bypass_pma_sw_done = false # bypass_ppm_lock = false # bypass_send_syncp_fbkp = true # bypass_txdetectrx = true # cdr_control = dis_cdr_ctrl # cid_enable = dis_cid_mode # cp_cons_sel = cp_cons_master # cp_dwn_mstr = true # cp_up_mstr = true # ctrl_plane_bonding = individual # data_mask_count = 0000 # data_mask_count_multi = 0 # dft_observation_clock_selection = dft_clk_obsrv_tx0 # early_eios_counter = 00 # force_freqdet = force_freqdet_dis # free_run_clk_enable = false # ignore_sigdet_g23 = false # pc_en_counter = 00 # pc_rst_counter = 00 # pcie_hip_mode = hip_disable # ph_fifo_reg_mode = phfifo_reg_mode_dis # phfifo_flush_wait = 00 # pipe_if_g3pcs = pipe_if_8gpcs # pma_done_counter = 00000 # pma_if_dft_en = dft_dis # pma_if_dft_val = dft_0 # ppm_cnt_rst = ppm_cnt_rst_dis # ppm_deassert_early = deassert_early_dis # ppm_det_buckets = ppm_100_bucket # ppm_gen1_2_cnt = cnt_32k # ppm_post_eidle_delay = cnt_200_cycles # ppmsel = ppmsel_1000 # prot_mode = other_protocols # reconfig_settings = {} # rxvalid_mask = rxvalid_mask_dis # sigdet_wait_counter = 000 # sigdet_wait_counter_multi = 0 # silicon_rev = 20nm1 # sim_mode = disable # spd_chg_rst_wait_cnt_en = false # sup_mode = user_mode # testout_sel = asn_test # wait_clk_on_off_timer = 0 # wait_pipe_synchronizing = 00 # wait_send_syncp_fbkp = 000 # # # ================================================ # Module twentynm_hssi_common_pld_pcs_interface # ================================================ # dft_clk_out_en = dft_clk_out_disable # dft_clk_out_sel = teng_rx_dft_clk # hrdrstctrl_en = hrst_dis # pcs_testbus_block_sel = pma_if # reconfig_settings = {} # silicon_rev = 20nm1 # # # ================================================ # Module twentynm_hssi_fifo_rx_pcs # ================================================ # double_read_mode = double_read_dis # prot_mode = teng_mode # silicon_rev = 20nm1 # # # ================================================ # Module twentynm_hssi_fifo_tx_pcs # ================================================ # double_write_mode = double_write_dis # prot_mode = teng_mode # silicon_rev = 20nm1 # # # ================================================ # Module twentynm_hssi_gen3_rx_pcs # ================================================ # block_sync = bypass_block_sync # block_sync_sm = disable_blk_sync_sm # cdr_ctrl_force_unalgn = disable # lpbk_force = lpbk_frce_dis # mode = disable_pcs # rate_match_fifo = bypass_rm_fifo # rate_match_fifo_latency = low_latency # reconfig_settings = {} # reverse_lpbk = rev_lpbk_dis # rx_b4gb_par_lpbk = b4gb_par_lpbk_dis # rx_force_balign = dis_force_balign # rx_ins_del_one_skip = ins_del_one_skip_dis # rx_num_fixed_pat = 0 # rx_test_out_sel = rx_test_out0 # silicon_rev = 20nm1 # sup_mode = user_mode # # # ================================================ # Module twentynm_hssi_gen3_tx_pcs # ================================================ # mode = disable_pcs # reverse_lpbk = rev_lpbk_dis # silicon_rev = 20nm1 # sup_mode = user_mode # tx_bitslip = 00 # tx_gbox_byp = bypass_gbox # # # ================================================ # Module twentynm_hssi_krfec_rx_pcs # ================================================ # blksync_cor_en = detect # bypass_gb = bypass_dis # clr_ctrl = both_enabled # ctrl_bit_reverse = ctrl_bit_reverse_en # data_bit_reverse = data_bit_reverse_dis # dv_start = with_blklock # err_mark_type = err_mark_10g # error_marking_en = err_mark_dis # low_latency_en = disable # lpbk_mode = lpbk_dis # parity_invalid_enum = 08 # parity_valid_num = 4 # pipeln_blksync = enable # pipeln_descrm = disable # pipeln_errcorrect = disable # pipeln_errtrap_ind = enable # pipeln_errtrap_lfsr = disable # pipeln_errtrap_loc = disable # pipeln_errtrap_pat = disable # pipeln_gearbox = enable # pipeln_syndrm = enable # pipeln_trans_dec = disable # prot_mode = disable_mode # receive_order = receive_lsb # reconfig_settings = {} # rx_testbus_sel = overall # signal_ok_en = sig_ok_en # silicon_rev = 20nm1 # sup_mode = user_mode # # # ================================================ # Module twentynm_hssi_krfec_tx_pcs # ================================================ # burst_err = burst_err_dis # burst_err_len = burst_err_len1 # ctrl_bit_reverse = ctrl_bit_reverse_en # data_bit_reverse = data_bit_reverse_dis # enc_frame_query = enc_query_dis # low_latency_en = disable # pipeln_encoder = enable # pipeln_scrambler = enable # prot_mode = disable_mode # silicon_rev = 20nm1 # sup_mode = user_mode # transcode_err = trans_err_dis # transmit_order = transmit_lsb # tx_testbus_sel = overall # # # ================================================ # Module twentynm_hssi_pipe_gen1_2 # ================================================ # elec_idle_delay_val = 0 # error_replace_pad = replace_edb # hip_mode = dis_hip # ind_error_reporting = dis_ind_error_reporting # phystatus_delay_val = 0 # phystatus_rst_toggle = dis_phystatus_rst_toggle # pipe_byte_de_serializer_en = dont_care_bds # prot_mode = disabled_prot_mode # reconfig_settings = {} # rpre_emph_a_val = 00 # rpre_emph_b_val = 00 # rpre_emph_c_val = 00 # rpre_emph_d_val = 00 # rpre_emph_e_val = 00 # rvod_sel_a_val = 00 # rvod_sel_b_val = 00 # rvod_sel_c_val = 00 # rvod_sel_d_val = 00 # rvod_sel_e_val = 00 # rx_pipe_enable = dis_pipe_rx # rxdetect_bypass = dis_rxdetect_bypass # silicon_rev = 20nm1 # sup_mode = user_mode # tx_pipe_enable = dis_pipe_tx # txswing = dis_txswing # # # ================================================ # Module twentynm_hssi_pipe_gen3 # ================================================ # bypass_rx_detection_enable = false # bypass_rx_preset = 0 # bypass_rx_preset_enable = false # bypass_tx_coefficent = 00000 # bypass_tx_coefficent_enable = false # elecidle_delay_g3 = 0 # ind_error_reporting = dis_ind_error_reporting # mode = disable_pcs # phy_status_delay_g12 = 0 # phy_status_delay_g3 = 0 # phystatus_rst_toggle_g12 = dis_phystatus_rst_toggle # phystatus_rst_toggle_g3 = dis_phystatus_rst_toggle_g3 # rate_match_pad_insertion = dis_rm_fifo_pad_ins # silicon_rev = 20nm1 # sup_mode = user_mode # test_out_sel = disable_test_out # # # ================================================ # Module twentynm_hssi_rx_pcs_pma_interface # ================================================ # block_sel = ten_g_pcs # channel_operation_mode = tx_rx_pair_enabled # clkslip_sel = pld # lpbk_en = disable # master_clk_sel = master_rx_pma_clk # pldif_datawidth_mode = pldif_data_10bit # pma_dw_rx = pma_32b_rx # pma_if_dft_en = dft_dis # pma_if_dft_val = dft_0 # prbs9_dwidth = prbs9_64b # prbs_clken = prbs_clk_dis # prbs_ver = prbs_off # prot_mode_rx = teng_krfec_mode_rx # reconfig_settings = {} # rx_dyn_polarity_inversion = rx_dyn_polinv_dis # rx_lpbk_en = lpbk_dis # rx_prbs_force_signal_ok = force_sig_ok # rx_prbs_mask = prbsmask128 # rx_prbs_mode = teng_mode # rx_signalok_signaldet_sel = sel_sig_det # rx_static_polarity_inversion = rx_stat_polinv_dis # rx_uhsif_lpbk_en = uhsif_lpbk_dis # silicon_rev = 20nm1 # sup_mode = user_mode # # Note - If you are performing a post-fit simulation, you must add the 'altera_a10_xcvr_clock_module' to your top-level design. Please refer to the 'Arria 10 Transceiver PHY User Guide' for details. # # ================================================ # Module twentynm_hssi_rx_pld_pcs_interface # ================================================ # hd_10g_advanced_user_mode_rx = disable # hd_10g_channel_operation_mode = tx_rx_pair_enabled # hd_10g_ctrl_plane_bonding_rx = individual_rx # hd_10g_fifo_mode_rx = fifo_rx # hd_10g_low_latency_en_rx = disable # hd_10g_lpbk_en = disable # hd_10g_pma_dw_rx = pma_32b_rx # hd_10g_prot_mode_rx = teng_baser_mode_rx # hd_10g_shared_fifo_width_rx = single_rx # hd_10g_sup_mode = user_mode # hd_10g_test_bus_mode = rx # hd_8g_channel_operation_mode = tx_rx_pair_enabled # hd_8g_ctrl_plane_bonding_rx = individual_rx # hd_8g_fifo_mode_rx = fifo_rx # hd_8g_hip_mode = disable # hd_8g_lpbk_en = disable # hd_8g_pma_dw_rx = pma_10b_rx # hd_8g_prot_mode_rx = disabled_prot_mode_rx # hd_8g_sup_mode = user_mode # hd_chnl_channel_operation_mode = tx_rx_pair_enabled # hd_chnl_clklow_clk_hz = 13356219 # hd_chnl_ctrl_plane_bonding_rx = individual_rx # hd_chnl_fref_clk_hz = 13356219 # hd_chnl_frequency_rules_en = enable # hd_chnl_func_mode = enable # hd_chnl_hclk_clk_hz = 00000000 # hd_chnl_hip_en = disable # hd_chnl_hrdrstctl_en = disable # hd_chnl_low_latency_en_rx = disable # hd_chnl_lpbk_en = disable # hd_chnl_operating_voltage = standard # hd_chnl_pcs_ac_pwr_rules_en = disable # hd_chnl_pcs_pair_ac_pwr_uw_per_mhz = 00000 # hd_chnl_pcs_rx_ac_pwr_uw_per_mhz = 00000 # hd_chnl_pcs_rx_pwr_scaling_clk = pma_rx_clk # hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz = 00000000 # hd_chnl_pld_fifo_mode_rx = fifo_rx # hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz = 00000000 # hd_chnl_pld_rx_clk_hz = 09502f90 # hd_chnl_pma_dw_rx = pma_32b_rx # hd_chnl_pma_rx_clk_hz = 13356219 # hd_chnl_prot_mode_rx = teng_baser_rx # hd_chnl_shared_fifo_width_rx = single_rx # hd_chnl_speed_grade = e2 # hd_chnl_sup_mode = user_mode # hd_chnl_transparent_pcs_rx = disable # hd_fifo_channel_operation_mode = tx_rx_pair_enabled # hd_fifo_prot_mode_rx = teng_mode_rx # hd_fifo_shared_fifo_width_rx = single_rx # hd_fifo_sup_mode = user_mode # hd_g3_prot_mode = disabled_prot_mode # hd_g3_sup_mode = user_mode # hd_krfec_channel_operation_mode = tx_rx_pair_enabled # hd_krfec_low_latency_en_rx = disable # hd_krfec_lpbk_en = disable # hd_krfec_prot_mode_rx = disabled_prot_mode_rx # hd_krfec_sup_mode = user_mode # hd_krfec_test_bus_mode = tx # hd_pldif_hrdrstctl_en = disable # hd_pldif_prot_mode_rx = teng_pld_fifo_mode_rx # hd_pldif_sup_mode = user_mode # hd_pmaif_channel_operation_mode = tx_rx_pair_enabled # hd_pmaif_lpbk_en = disable # hd_pmaif_pma_dw_rx = pma_32b_rx # hd_pmaif_prot_mode_rx = teng_krfec_mode_rx # hd_pmaif_sim_mode = disable # hd_pmaif_sup_mode = user_mode # pcs_rx_block_sel = teng # pcs_rx_clk_out_sel = teng_clk_out # pcs_rx_clk_sel = pld_rx_clk # pcs_rx_hip_clk_en = hip_rx_disable # pcs_rx_output_sel = teng_output # reconfig_settings = {} # silicon_rev = 20nm1 # # # ================================================ # Module twentynm_hssi_tx_pcs_pma_interface # ================================================ # bypass_pma_txelecidle = true # channel_operation_mode = tx_rx_pair_enabled # lpbk_en = disable # master_clk_sel = master_tx_pma_clk # pcie_sub_prot_mode_tx = other_prot_mode # pldif_datawidth_mode = pldif_data_10bit # pma_dw_tx = pma_32b_tx # pma_if_dft_en = dft_dis # pmagate_en = pmagate_dis # prbs9_dwidth = prbs9_64b # prbs_clken = prbs_clk_dis # prbs_gen_pat = prbs_gen_dis # prot_mode_tx = teng_krfec_mode_tx # reconfig_settings = {} # silicon_rev = 20nm1 # sq_wave_num = sq_wave_default # sqwgen_clken = sqwgen_clk_dis # sup_mode = user_mode # tx_dyn_polarity_inversion = tx_dyn_polinv_dis # tx_pma_data_sel = ten_g_pcs # tx_static_polarity_inversion = tx_stat_polinv_dis # uhsif_cnt_step_filt_before_lock = uhsif_filt_stepsz_b4lock_2 # uhsif_cnt_thresh_filt_after_lock_value = 0 # uhsif_cnt_thresh_filt_before_lock = uhsif_filt_cntthr_b4lock_8 # uhsif_dcn_test_update_period = uhsif_dcn_test_period_4 # uhsif_dcn_testmode_enable = uhsif_dcn_test_mode_disable # uhsif_dead_zone_count_thresh = uhsif_dzt_cnt_thr_2 # uhsif_dead_zone_detection_enable = uhsif_dzt_disable # uhsif_dead_zone_obser_window = uhsif_dzt_obr_win_16 # uhsif_dead_zone_skip_size = uhsif_dzt_skipsz_4 # uhsif_delay_cell_index_sel = uhsif_index_cram # uhsif_delay_cell_margin = uhsif_dcn_margin_2 # uhsif_delay_cell_static_index_value = 00 # uhsif_dft_dead_zone_control = uhsif_dft_dz_det_val_0 # uhsif_dft_up_filt_control = uhsif_dft_up_val_0 # uhsif_enable = uhsif_disable # uhsif_lock_det_segsz_after_lock = uhsif_lkd_segsz_aflock_512 # uhsif_lock_det_segsz_before_lock = uhsif_lkd_segsz_b4lock_16 # uhsif_lock_det_thresh_cnt_after_lock_value = 0 # uhsif_lock_det_thresh_cnt_before_lock_value = 0 # uhsif_lock_det_thresh_diff_after_lock_value = 0 # uhsif_lock_det_thresh_diff_before_lock_value = 0 # # Note - If you are performing a post-fit simulation, you must add the 'altera_a10_xcvr_clock_module' to your top-level design. Please refer to the 'Arria 10 Transceiver PHY User Guide' for details. # # ================================================ # Module twentynm_hssi_tx_pld_pcs_interface # ================================================ # hd_10g_advanced_user_mode_tx = disable # hd_10g_channel_operation_mode = tx_rx_pair_enabled # hd_10g_ctrl_plane_bonding_tx = individual_tx # hd_10g_fifo_mode_tx = fifo_tx # hd_10g_low_latency_en_tx = disable # hd_10g_lpbk_en = disable # hd_10g_pma_dw_tx = pma_32b_tx # hd_10g_prot_mode_tx = teng_baser_mode_tx # hd_10g_shared_fifo_width_tx = single_tx # hd_10g_sup_mode = user_mode # hd_8g_channel_operation_mode = tx_rx_pair_enabled # hd_8g_ctrl_plane_bonding_tx = individual_tx # hd_8g_fifo_mode_tx = fifo_tx # hd_8g_hip_mode = disable # hd_8g_lpbk_en = disable # hd_8g_pma_dw_tx = pma_10b_tx # hd_8g_prot_mode_tx = disabled_prot_mode_tx # hd_8g_sup_mode = user_mode # hd_chnl_channel_operation_mode = tx_rx_pair_enabled # hd_chnl_ctrl_plane_bonding_tx = individual_tx # hd_chnl_frequency_rules_en = enable # hd_chnl_func_mode = enable # hd_chnl_hclk_clk_hz = 00000000 # hd_chnl_hip_en = disable # hd_chnl_hrdrstctl_en = disable # hd_chnl_low_latency_en_tx = disable # hd_chnl_lpbk_en = disable # hd_chnl_pcs_tx_ac_pwr_uw_per_mhz = 00000 # hd_chnl_pcs_tx_pwr_scaling_clk = pma_tx_clk # hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz = 00000000 # hd_chnl_pld_fifo_mode_tx = fifo_tx # hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz = 00000000 # hd_chnl_pld_tx_clk_hz = 09502f90 # hd_chnl_pld_uhsif_tx_clk_hz = 00000000 # hd_chnl_pma_dw_tx = pma_32b_tx # hd_chnl_pma_tx_clk_hz = 13356219 # hd_chnl_prot_mode_tx = teng_baser_tx # hd_chnl_shared_fifo_width_tx = single_tx # hd_chnl_speed_grade = e2 # hd_chnl_sup_mode = user_mode # hd_fifo_channel_operation_mode = tx_rx_pair_enabled # hd_fifo_prot_mode_tx = teng_mode_tx # hd_fifo_shared_fifo_width_tx = single_tx # hd_fifo_sup_mode = user_mode # hd_g3_prot_mode = disabled_prot_mode # hd_g3_sup_mode = user_mode # hd_krfec_channel_operation_mode = tx_rx_pair_enabled # hd_krfec_low_latency_en_tx = disable # hd_krfec_lpbk_en = disable # hd_krfec_prot_mode_tx = disabled_prot_mode_tx # hd_krfec_sup_mode = user_mode # hd_pldif_hrdrstctl_en = disable # hd_pldif_prot_mode_tx = teng_pld_fifo_mode_tx # hd_pldif_sup_mode = user_mode # hd_pmaif_channel_operation_mode = tx_rx_pair_enabled # hd_pmaif_ctrl_plane_bonding = individual # hd_pmaif_lpbk_en = disable # hd_pmaif_pma_dw_tx = pma_32b_tx # hd_pmaif_prot_mode_tx = teng_krfec_mode_tx # hd_pmaif_sim_mode = disable # hd_pmaif_sup_mode = user_mode # pcs_tx_clk_out_sel = teng_clk_out # pcs_tx_clk_source = teng # pcs_tx_data_source = hip_disable # pcs_tx_delay1_clk_en = delay1_clk_disable # pcs_tx_delay1_clk_sel = pcs_tx_clk # pcs_tx_delay1_ctrl = delay1_path0 # pcs_tx_delay1_data_sel = one_ff_delay # pcs_tx_delay2_clk_en = delay2_clk_disable # pcs_tx_delay2_ctrl = delay2_path0 # pcs_tx_output_sel = teng_output # reconfig_settings = {} # silicon_rev = 20nm1 # # # ================================================ # Module twentynm_hssi_pma_adaptation # ================================================ # adapt_dfe_control_sel = r_adapt_dfe_control_sel_0 # adapt_dfe_sel = r_adapt_dfe_sel_0 # adapt_mode = manual # adapt_vga_sel = r_adapt_vga_sel_0 # adapt_vref_sel = r_adapt_vref_sel_0 # adp_1s_ctle_bypass = radp_1s_ctle_bypass_1 # adp_4s_ctle_bypass = radp_4s_ctle_bypass_1 # adp_adapt_control_sel = radp_adapt_control_sel_0 # adp_adapt_rstn = radp_adapt_rstn_1 # adp_adapt_start = radp_adapt_start_0 # adp_bist_auxpath_en = radp_bist_auxpath_disable # adp_bist_count_rstn = radp_bist_count_rstn_0 # adp_bist_datapath_en = radp_bist_datapath_disable # adp_bist_mode = radp_bist_mode_0 # adp_bist_odi_dfe_sel = radp_bist_odi_dfe_sel_0 # adp_bist_spec_en = radp_bist_spec_en_0 # adp_control_mux_bypass = radp_control_mux_bypass_0 # adp_ctle_acgain_4s = radp_ctle_acgain_4s_0 # adp_ctle_adapt_bw = radp_ctle_adapt_bw_3 # adp_ctle_adapt_cycle_window = radp_ctle_adapt_cycle_window_7 # adp_ctle_adapt_oneshot = radp_ctle_adapt_oneshot_1 # adp_ctle_en = radp_ctle_disable # adp_ctle_eqz_1s_sel = radp_ctle_eqz_1s_sel_0 # adp_ctle_force_spec_sign = radp_ctle_force_spec_sign_0 # adp_ctle_hold_en = radp_ctle_not_held # adp_ctle_load = radp_ctle_load_0 # adp_ctle_load_value = radp_ctle_load_value_0 # adp_ctle_scale = radp_ctle_scale_0 # adp_ctle_scale_en = radp_ctle_scale_en_0 # adp_ctle_spec_sign = radp_ctle_spec_sign_0 # adp_ctle_sweep_direction = radp_ctle_sweep_direction_1 # adp_ctle_threshold = radp_ctle_threshold_0 # adp_ctle_threshold_en = radp_ctle_threshold_en_0 # adp_ctle_vref_polarity = radp_ctle_vref_polarity_0 # adp_ctle_window = radp_ctle_window_0 # adp_dfe_bw = radp_dfe_bw_3 # adp_dfe_clkout_div_sel = radp_dfe_clkout_div_sel_0 # adp_dfe_cycle = radp_dfe_cycle_6 # adp_dfe_fltap_bypass = radp_dfe_fltap_bypass_1 # adp_dfe_fltap_en = radp_dfe_fltap_disable # adp_dfe_fltap_hold_en = radp_dfe_fltap_not_held # adp_dfe_fltap_load = radp_dfe_fltap_load_0 # adp_dfe_fltap_position = radp_dfe_fltap_position_0 # adp_dfe_force_spec_sign = radp_dfe_force_spec_sign_0 # adp_dfe_fxtap1 = radp_dfe_fxtap1_0 # adp_dfe_fxtap10 = radp_dfe_fxtap10_0 # adp_dfe_fxtap10_sgn = radp_dfe_fxtap10_sgn_0 # adp_dfe_fxtap11 = radp_dfe_fxtap11_0 # adp_dfe_fxtap11_sgn = radp_dfe_fxtap11_sgn_0 # adp_dfe_fxtap2 = radp_dfe_fxtap2_0 # adp_dfe_fxtap2_sgn = radp_dfe_fxtap2_sgn_0 # adp_dfe_fxtap3 = radp_dfe_fxtap3_0 # adp_dfe_fxtap3_sgn = radp_dfe_fxtap3_sgn_0 # adp_dfe_fxtap4 = radp_dfe_fxtap4_0 # adp_dfe_fxtap4_sgn = radp_dfe_fxtap4_sgn_0 # adp_dfe_fxtap5 = radp_dfe_fxtap5_0 # adp_dfe_fxtap5_sgn = radp_dfe_fxtap5_sgn_0 # adp_dfe_fxtap6 = radp_dfe_fxtap6_0 # adp_dfe_fxtap6_sgn = radp_dfe_fxtap6_sgn_0 # adp_dfe_fxtap7 = radp_dfe_fxtap7_0 # adp_dfe_fxtap7_sgn = radp_dfe_fxtap7_sgn_0 # adp_dfe_fxtap8 = radp_dfe_fxtap8_0 # adp_dfe_fxtap8_sgn = radp_dfe_fxtap8_sgn_0 # adp_dfe_fxtap9 = radp_dfe_fxtap9_0 # adp_dfe_fxtap9_sgn = radp_dfe_fxtap9_sgn_0 # adp_dfe_fxtap_bypass = radp_dfe_fxtap_bypass_1 # adp_dfe_fxtap_en = radp_dfe_fxtap_disable # adp_dfe_fxtap_hold_en = radp_dfe_fxtap_not_held # adp_dfe_fxtap_load = radp_dfe_fxtap_load_0 # adp_dfe_mode = radp_dfe_mode_4 # adp_dfe_spec_sign = radp_dfe_spec_sign_0 # adp_dfe_vref_polarity = radp_dfe_vref_polarity_0 # adp_force_freqlock = radp_force_freqlock_off # adp_frame_capture = radp_frame_capture_0 # adp_frame_en = radp_frame_en_0 # adp_frame_odi_sel = radp_frame_odi_sel_0 # adp_frame_out_sel = radp_frame_out_sel_0 # adp_lfeq_fb_sel = radp_lfeq_fb_sel_0 # adp_mode = radp_mode_8 # adp_odi_control_sel = radp_odi_control_sel_0 # adp_onetime_dfe = radp_onetime_dfe_0 # adp_spec_avg_window = radp_spec_avg_window_4 # adp_spec_trans_filter = radp_spec_trans_filter_2 # adp_status_sel = radp_status_sel_0 # adp_vga_bypass = radp_vga_bypass_1 # adp_vga_en = radp_vga_disable # adp_vga_load = radp_vga_load_0 # adp_vga_polarity = radp_vga_polarity_0 # adp_vga_sel = radp_vga_sel_0 # adp_vga_sweep_direction = radp_vga_sweep_direction_1 # adp_vga_threshold = radp_vga_threshold_4 # adp_vref_bw = radp_vref_bw_1 # adp_vref_bypass = radp_vref_bypass_1 # adp_vref_cycle = radp_vref_cycle_6 # adp_vref_dfe_spec_en = radp_vref_dfe_spec_en_0 # adp_vref_en = radp_vref_disable # adp_vref_hold_en = radp_vref_not_held # adp_vref_load = radp_vref_load_0 # adp_vref_polarity = radp_vref_polarity_0 # adp_vref_sel = radp_vref_sel_21 # adp_vref_vga_level = radp_vref_vga_level_13 # datarate = 10312500000 bps # initial_settings = true # odi_count_threshold = rodi_count_threshold_0 # odi_dfe_spec_en = rodi_dfe_spec_en_0 # odi_en = rodi_en_0 # odi_mode = rodi_mode_0 # odi_rstn = rodi_rstn_0 # odi_spec_sel = rodi_spec_sel_0 # odi_start = rodi_start_0 # odi_vref_sel = rodi_vref_sel_0 # optimal = false # prot_mode = basic_rx # rrx_pcie_eqz = rrx_pcie_eqz_0 # silicon_rev = 20nm1 # sup_mode = user_mode # # # ================================================ # Module twentynm_hssi_pma_cdr_refclk_select_mux # ================================================ # local_cdr_clkin_scratch0_src = cdr_clkin_scratch0_src_refclk_iqclk # local_cdr_clkin_scratch1_src = cdr_clkin_scratch1_src_refclk_iqclk # local_cdr_clkin_scratch2_src = cdr_clkin_scratch2_src_refclk_iqclk # local_cdr_clkin_scratch3_src = cdr_clkin_scratch3_src_refclk_iqclk # local_cdr_clkin_scratch4_src = cdr_clkin_scratch4_src_refclk_iqclk # inclk0_logical_to_physical_mapping = ref_iqclk0 # inclk1_logical_to_physical_mapping = power_down # inclk2_logical_to_physical_mapping = power_down # inclk3_logical_to_physical_mapping = power_down # inclk4_logical_to_physical_mapping = power_down # powerdown_mode = powerup # receiver_detect_src = iqclk_src # refclk_select = ref_iqclk0 # silicon_rev = 20nm1 # local_xmux_refclk_src = refclk_iqclk # local_xpm_iqref_mux_iqclk_sel = ref_iqclk0 # local_xpm_iqref_mux_scratch0_src = scratch0_ref_iqclk0 # local_xpm_iqref_mux_scratch1_src = scratch1_power_down # local_xpm_iqref_mux_scratch2_src = scratch2_power_down # local_xpm_iqref_mux_scratch3_src = scratch3_power_down # local_xpm_iqref_mux_scratch4_src = scratch4_power_down # # # ================================================ # Module twentynm_hssi_pma_channel_pll # ================================================ # analog_mode = user_custom # atb_select_control = atb_off # auto_reset_on = auto_reset_off # bandwidth_range_high = 0 hz # bandwidth_range_low = 0 hz # bbpd_data_pattern_filter_select = bbpd_data_pat_off # bw_sel = medium # cal_vco_count_length = sel_8b_count # cdr_odi_select = sel_cdr # cdr_phaselock_mode = no_ignore_lock # cdr_powerdown_mode = power_up # cgb_div = 1 # chgpmp_current_dn_pd = cp_current_pd_dn_setting3 # chgpmp_current_dn_trim = cp_current_trimming_dn_setting0 # chgpmp_current_pfd = cp_current_pfd_setting2 # chgpmp_current_up_pd = cp_current_pd_up_setting3 # chgpmp_current_up_trim = cp_current_trimming_up_setting0 # chgpmp_dn_pd_trim_double = normal_dn_trim_current # chgpmp_replicate = false # chgpmp_testmode = cp_test_disable # chgpmp_up_pd_trim_double = normal_up_trim_current # chgpmp_vccreg = vreg_fw0 # clklow_mux_select = clklow_mux_cdr_fbclk # datarate = 10312500000 bps # diag_loopback_enable = false # disable_up_dn = true # enable_idle_rx_channel_support = false # f_max_cmu_out_freq_bin = 00000000000000000000000000000001 # f_max_m_counter_bin = 00000000000000000000000000000001 # f_max_pfd = 0 hz # f_max_ref = 0 hz # f_max_vco = 0 hz # f_min_gt_channel = 0 hz # f_min_pfd = 0 hz # f_min_ref = 0 hz # f_min_vco = 0 hz # fb_select = direct_fb # fref_clklow_div = 1 # fref_mux_select = fref_mux_cdr_refclk # gpon_lck2ref_control = gpon_lck2ref_off # initial_settings = true # iqclk_mux_sel = power_down # is_cascaded_pll = false # lck2ref_delay_control = lck2ref_delay_2 # lf_resistor_pd = lf_pd_setting2 # lf_resistor_pfd = lf_pfd_setting2 # lf_ripple_cap = lf_no_ripple # loop_filter_bias_select = lpflt_bias_7 # loopback_mode = loopback_disabled # lpd_counter = 01 # lpfd_counter = 01 # ltd_ltr_micro_controller_select = ltd_ltr_pcs # m_counter = 16 # n_counter_scratch = 1 # n_counter_scratch = 01 # optimal = false # output_clock_frequency = 5156250000 Hz # pcie_gen = non_pcie # pd_fastlock_mode = false # pd_l_counter = 1 # pfd_l_counter = 1 # pm_speed_grade = e2 # pma_width = 32 # position = position_unknown # power_mode = low_power # primary_use = cdr # prot_mode = basic_rx # reference_clock_frequency = 322265625 hz # requires_gt_capable_channel = false # reverse_serial_loopback = no_loopback # set_cdr_input_freq_range = 00 # set_cdr_v2i_enable = true # set_cdr_vco_reset = false # set_cdr_vco_speed = 03 # set_cdr_vco_speed_fix = 3c # set_cdr_vco_speed_pciegen3 = cdr_vco_max_speedbin_pciegen3 # side = side_unknown # silicon_rev = 20nm1 # sup_mode = user_mode # top_or_bottom = tb_unknown # tx_pll_prot_mode = txpll_unused # txpll_hclk_driver_enable = false # uc_cru_rstb = cdr_lf_reset_off # uc_ro_cal = uc_ro_cal_on # uc_ro_cal_status = uc_ro_cal_notdone # vco_freq = 5156250000 Hz # vco_overrange_voltage = vco_overrange_off # vco_underrange_voltage = vco_underange_off # # # ================================================ # Module twentynm_hssi_pma_rx_buf # ================================================ # act_isource_disable = isrc_en # bodybias_enable = bodybias_en # bodybias_select = bodybias_sel1 # bypass_eqz_stages_234 = bypass_off # cdrclk_to_cgb = cdrclk_2cgb_dis # cgm_bias_disable = cgmbias_en # datarate = 10312500000 bps # diag_lp_en = dlp_off # eq_bw_sel = eq_bw_1 # eq_dc_gain_trim = no_dc_gain # xrx_path_initial_settings = true # input_vcm_sel = high_vcm # iostandard = hssi_diffio # lfeq_enable = non_lfeq_mode # lfeq_zero_control = lfeq_setting_2 # link_rx = sr # link_rx = sr # loopback_modes = lpbk_disable # offset_cal_pd = eqz1_en # offset_cancellation_coarse = coarse_setting_00 # offset_cancellation_ctrl = volt_0mv # offset_cancellation_fine = fine_setting_00 # offset_pd = oc_en # one_stage_enable = non_s1_mode # xrx_path_optimal = false # pdb_rx = normal_rx_on # pm_speed_grade = e2 # pm_tx_rx_cvp_mode = cvp_off # pm_tx_rx_pcie_gen = non_pcie # pm_tx_rx_pcie_gen_bitwidth = pcie_gen3_32b # pm_tx_rx_testmux_select = setting0 # power_mode_rx = low_power # power_mode_rx = low_power # power_rail_eht = 0 # power_rail_er = 0 # xrx_path_prot_mode = basic_rx # qpi_enable = non_qpi_mode # refclk_en = disable # rx_atb_select = atb_disable # rx_refclk_divider = bypass_divider # rx_sel_bias_source = bias_vcmdrv # rx_vga_oc_en = vga_cal_off # silicon_rev = 20nm1 # xrx_path_sup_mode = user_mode # term_sel = r_r1 # term_tri_enable = disable_tri # vccela_supply_voltage = vccela_1p1v # vcm_current_add = vcm_current_default # vcm_sel = vcm_setting_10 # vga_bandwidth_select = vga_bw_1 # xrx_path_analog_mode = user_custom # xrx_path_datarate = 10312500000 bps # xrx_path_datawidth = 20 # xrx_path_gt_enabled = disable # xrx_path_initial_settings = true # xrx_path_jtag_hys = hys_increase_disable # xrx_path_jtag_lp = lp_off # xrx_path_optimal = false # xrx_path_pma_rx_divclk_hz_bin = 00000000000000000000000013356219 # xrx_path_prot_mode = basic_rx # xrx_path_sup_mode = user_mode # xrx_path_uc_cal_enable = rx_cal_off # xrx_path_uc_cru_rstb = cdr_lf_reset_off # xrx_path_uc_pcie_sw = uc_pcie_gen1 # xrx_path_uc_rx_rstb = rx_reset_on # # # ================================================ # Module twentynm_hssi_pma_rx_deser # ================================================ # bitslip_bypass = bs_bypass_yes # clkdiv_source = vco_bypass_normal # clkdivrx_user_mode = clkdivrx_user_clkdiv_div2 # datarate = 10312500000 bps # deser_factor = 32 # deser_powerdown = deser_power_up # force_adaptation_outputs = normal_outputs # force_clkdiv_for_testing = normal_clkdiv # optimal = false # pcie_gen = non_pcie # pcie_gen_bitwidth = pcie_gen3_32b # prot_mode = basic_rx # rst_n_adapt_odi = no_rst_adapt_odi # sdclk_enable = false # silicon_rev = 20nm1 # sup_mode = user_mode # tdr_mode = select_bbpd_data # # # ================================================ # Module twentynm_hssi_pma_rx_dfe # ================================================ # atb_select = atb_disable # datarate = 10312500000 bps # dft_en = dft_disable # initial_settings = true # oc_sa_adp1 = 00 # oc_sa_adp2 = 00 # oc_sa_c270 = 00 # oc_sa_c90 = 00 # oc_sa_d0c0 = 00 # oc_sa_d0c180 = 00 # oc_sa_d1c0 = 00 # oc_sa_d1c180 = 00 # optimal = false # pdb = 6466655f656e61626c65 # pdb_fixedtap = fixtap_dfe_powerdown # pdb_floattap = floattap_dfe_powerdown # pdb_fxtap4t7 = fxtap4t7_powerdown # power_mode = low_power # prot_mode = basic_rx # sel_fltapstep_dec = fltap_step_no_dec # sel_fltapstep_inc = fltap_step_no_inc # sel_fxtapstep_dec = fxtap_step_no_dec # sel_fxtapstep_inc = fxtap_step_no_inc # sel_oc_en = off_canc_disable # sel_probe_tstmx = probe_tstmx_none # silicon_rev = 20nm1 # sup_mode = user_mode # uc_rx_dfe_cal = uc_rx_dfe_cal_off # uc_rx_dfe_cal_status = uc_rx_dfe_cal_notdone # # # ================================================ # Module twentynm_hssi_pma_rx_odi # ================================================ # clk_dcd_bypass = no_bypass # datarate = 10312500000 bps # enable_odi = power_down_eye # initial_settings = true # invert_dfe_vref = no_inversion # monitor_bw_sel = bw_1 # oc_sa_c0 = 00 # oc_sa_c180 = 00 # optimal = false # phase_steps_64_vs_128 = phase_steps_64 # phase_steps_sel = step40 # power_mode = low_power # prot_mode = basic_rx # sel_oc_en = off_canc_disable # silicon_rev = 20nm1 # step_ctrl_sel = dprio_mode # sup_mode = user_mode # v_vert_sel = plus # v_vert_threshold_scaling = scale_3 # vert_threshold = vert_0 # # # ================================================ # Module twentynm_hssi_pma_rx_sd # ================================================ # link = sr # optimal = false # power_mode = low_power # prot_mode = basic_rx # sd_output_off = 1 # sd_output_on = 15 # sd_pdb = sd_off # sd_threshold = sdlv_3 # silicon_rev = 20nm1 # sup_mode = user_mode # # # ================================================ # Module twentynm_hssi_pma_tx_buf # ================================================ # xtx_path_calibration_en = false # calibration_resistor_value = res_setting0 # cdr_cp_calibration_en = cdr_cp_cal_disable # chgpmp_current_dn_trim = cp_current_trimming_dn_setting0 # chgpmp_current_up_trim = cp_current_trimming_up_setting0 # chgpmp_dn_trim_double = normal_dn_trim_current # chgpmp_up_trim_double = normal_up_trim_current # compensation_driver_en = disable # compensation_en = enable # cpen_ctrl = cp_l0 # datarate = 10312500000 bps # dcd_clk_div_ctrl = dcd_ck_div128 # dcd_detection_en = enable # dft_sel = dft_disabled # duty_cycle_correction_bandwidth = dcc_bw_12 # duty_cycle_correction_bandwidth_dn = dcd_bw_dn_0 # duty_cycle_correction_mode_ctrl = dcc_disable # duty_cycle_correction_reference1 = dcc_ref1_3 # duty_cycle_correction_reference2 = dcc_ref2_3 # duty_cycle_correction_reset_n = reset_n # duty_cycle_cp_comp_en = cp_comp_off # duty_cycle_detector_cp_cal = dcd_cp_cal_disable # duty_cycle_detector_sa_cal = dcd_sa_cal_disable # duty_cycle_input_polarity = dcc_input_pos # duty_cycle_setting = dcc_t32 # duty_cycle_setting_aux = dcc2_t32 # enable_idle_tx_channel_support = false # xtx_path_initial_settings = true # jtag_drv_sel = drv1 # jtag_lp = lp_off # link_tx = sr # link_tx = sr # low_power_en = disable # lst = 6174625f64697361626c6564 # mcgb_location_for_pcie = 0 # xtx_path_optimal = false # pm_speed_grade = e2 # power_mode = low_power # power_rail_eht = 0 # power_rail_et = 0 # pre_emp_sign_1st_post_tap = fir_post_1t_neg # pre_emp_sign_2nd_post_tap = fir_post_2t_neg # pre_emp_sign_pre_tap_1t = fir_pre_1t_neg # pre_emp_sign_pre_tap_2t = fir_pre_2t_neg # pre_emp_switching_ctrl_1st_post_tap = 00 # pre_emp_switching_ctrl_2nd_post_tap = 0 # pre_emp_switching_ctrl_pre_tap_1t = 00 # pre_emp_switching_ctrl_pre_tap_2t = 0 # xtx_path_prot_mode = basic_tx # res_cal_local = non_local # rx_det = mode_0 # rx_det_output_sel = rx_det_pcie_out # rx_det_pdb = rx_det_off # sense_amp_offset_cal_curr_n = sa_os_cal_in_0 # sense_amp_offset_cal_curr_p = 00 # ser_powerdown = normal_ser_on # silicon_rev = 20nm1 # slew_rate_ctrl = slew_r7 # xtx_path_sup_mode = user_mode # xtx_path_swing_level = lv # term_code = rterm_code7 # term_n_tune = rterm_n0 # term_p_tune = rterm_p0 # term_sel = r_r1 # tri_driver = tri_driver_disable # tx_powerdown = normal_tx_on # uc_dcd_cal = uc_dcd_cal_off # uc_dcd_cal_status = uc_dcd_cal_notdone # uc_gen3 = gen3_off # uc_gen4 = gen4_off # uc_skew_cal = uc_skew_cal_off # uc_skew_cal_status = uc_skew_cal_notdone # uc_txvod_cal = uc_tx_vod_cal_off # uc_txvod_cal_cont = uc_tx_vod_cal_cont_off # uc_txvod_cal_status = uc_tx_vod_cal_notdone # uc_vcc_setting = vcc_setting0 # user_fir_coeff_ctrl_sel = ram_ctl # vod_output_swing_ctrl = 00 # vreg_output = vccdreg_nominal # xtx_path_analog_mode = user_custom # xtx_path_bonding_mode = x1_non_bonded # xtx_path_calibration_en = false # xtx_path_clock_divider_ratio = 1 # xtx_path_datarate = 10312500000 bps # xtx_path_datawidth = 20 # xtx_path_gt_enabled = disable # xtx_path_initial_settings = true # xtx_path_optimal = false # xtx_path_pma_tx_divclk_hz_bin = 00000000000000000000000013356219 # xtx_path_prot_mode = basic_tx # xtx_path_sup_mode = user_mode # xtx_path_swing_level = lv # xtx_path_tx_pll_clk_hz = 5156250000 # # ================ INPUT ================= # prot_mode = basic_tx # input_select_x1 = fpll_bot # input_select_xn = unused # input_select_gen3 = unused # ================ OUTPUT ================ # x1_clock_source_sel = fpll_bot # xn_clock_source_sel = sel_cgb_loc # ================ END =================== # # # # ================================================ # Module twentynm_hssi_pma_tx_cgb # ================================================ # bitslip_enable = disable_bitslip # bonding_mode = x1_non_bonded # bonding_reset_enable = disallow_bonding_reset # cgb_power_down = normal_cgb # datarate = 10312500000 bps # dprio_cgb_vreg_boost = no_voltage_boost # initial_settings = true # input_select_gen3 = unused # input_select_x1 = fpll_bot # input_select_xn = unused # observe_cgb_clocks = observe_nothing # pcie_gen3_bitwidth = pciegen3_wide # prot_mode = basic_tx # scratch0_x1_clock_src = fpll_bot # scratch1_x1_clock_src = unused # scratch2_x1_clock_src = unused # scratch3_x1_clock_src = unused # select_done_master_or_slave = choose_slave_pcie_sw_done # ser_mode = thirty_two_bit # ser_powerdown = normal_poweron_ser # silicon_rev = 20nm1 # sup_mode = user_mode # tx_ucontrol_en = disable # tx_ucontrol_pcie = gen1 # tx_ucontrol_reset = disable # vccdreg_output = vccdreg_nominal # local_x1_clock_source_sel = fpll_bot # x1_div_m_sel = divbypass # local_xn_clock_source_sel = sel_cgb_loc # # # ================================================ # Module twentynm_hssi_pma_tx_ser # ================================================ # bonding_mode = x1_non_bonded # clk_divtx_deskew = deskew_delay8 # control_clk_divtx = no_dft_control_clkdivtx # duty_cycle_correction_mode_ctrl = dcc_disable # initial_settings = true # prot_mode = basic_tx # ser_clk_divtx_user_sel = divtx_user_2 # ser_clk_mon = disable_clk_mon # ser_powerdown = normal_poweron_ser # silicon_rev = 20nm1 # sup_mode = user_mode # # # ================================================ # Module twentynm_hssi_10g_rx_pcs # ================================================ # advanced_user_mode = disable # align_del = align_del_dis # ber_bit_err_total_cnt = bit_err_total_cnt_10g # ber_clken = ber_clk_en # ber_xus_timer_window = 004c4a # bitslip_mode = bitslip_dis # blksync_bitslip_type = bitslip_comb # blksync_bitslip_wait_cnt = 1 # blksync_bitslip_wait_type = bitslip_cnt # blksync_bypass = blksync_bypass_dis # blksync_clken = blksync_clk_en # blksync_enum_invalid_sh_cnt = enum_invalid_sh_cnt_10g # blksync_knum_sh_cnt_postlock = knum_sh_cnt_postlock_10g # blksync_knum_sh_cnt_prelock = knum_sh_cnt_prelock_10g # blksync_pipeln = blksync_pipeln_dis # clr_errblk_cnt_en = enable # control_del = control_del_none # crcchk_bypass = crcchk_bypass_en # crcchk_clken = crcchk_clk_dis # crcchk_inv = crcchk_inv_en # crcchk_pipeln = crcchk_pipeln_en # crcflag_pipeln = crcflag_pipeln_en # ctrl_bit_reverse = ctrl_bit_reverse_en # data_bit_reverse = data_bit_reverse_dis # dec64b66b_clken = dec64b66b_clk_en # dec_64b66b_rxsm_bypass = dec_64b66b_rxsm_bypass_dis # descrm_bypass = descrm_bypass_dis # descrm_clken = descrm_clk_en # descrm_mode = async # descrm_pipeln = enable # dft_clk_out_sel = rx_master_clk # dis_signal_ok = dis_signal_ok_en # dispchk_bypass = dispchk_bypass_en # empty_flag_type = empty_rd_side # fast_path = fast_path_dis # fec_clken = fec_clk_dis # fec_enable = fec_dis # fifo_double_read = fifo_double_read_dis # fifo_stop_rd = n_rd_empty # fifo_stop_wr = n_wr_full # force_align = force_align_dis # frmsync_bypass = frmsync_bypass_en # frmsync_clken = frmsync_clk_dis # frmsync_enum_scrm = enum_scrm_default # frmsync_enum_sync = enum_sync_default # frmsync_flag_type = location_only # frmsync_knum_sync = knum_sync_default # frmsync_mfrm_length = 0800 # frmsync_pipeln = frmsync_pipeln_en # full_flag_type = full_wr_side # gb_rx_idwidth = width_32 # gb_rx_odwidth = width_66 # gbexp_clken = gbexp_clk_en # low_latency_en = disable # lpbk_mode = lpbk_dis # master_clk_sel = master_rx_pma_clk # pempty_flag_type = pempty_rd_side # pfull_flag_type = pfull_wr_side # phcomp_rd_del = phcomp_rd_del2 # pld_if_type = fifo # prot_mode = teng_baser_mode # rand_clken = rand_clk_en # rd_clk_sel = rd_rx_pld_clk # rdfifo_clken = rdfifo_clk_en # reconfig_settings = {} # rx_fifo_write_ctrl = blklock_stops # rx_scrm_width = bit64 # rx_sh_location = lsb # rx_signal_ok_sel = synchronized_ver # rx_sm_bypass = rx_sm_bypass_dis # rx_sm_hiber = rx_sm_hiber_en # rx_sm_pipeln = rx_sm_pipeln_en # rx_testbus_sel = rx_fifo_testbus1 # rx_true_b2b = b2b # rxfifo_empty = empty_default # rxfifo_full = full_default # rxfifo_mode = clk_comp_10g # rxfifo_pempty = 02 # rxfifo_pfull = 17 # silicon_rev = 20nm1 # stretch_num_stages = two_stage # sup_mode = user_mode # test_mode = test_off # wrfifo_clken = wrfifo_clk_en # # # ================================================ # Module twentynm_hssi_10g_tx_pcs # ================================================ # advanced_user_mode = disable # bitslip_en = bitslip_dis # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # comp_cnt = 00 # compin_sel = compin_master # crcgen_bypass = crcgen_bypass_en # crcgen_clken = crcgen_clk_dis # crcgen_err = crcgen_err_dis # crcgen_inv = crcgen_inv_en # ctrl_bit_reverse = ctrl_bit_reverse_en # ctrl_plane_bonding = individual # data_bit_reverse = data_bit_reverse_dis # dft_clk_out_sel = tx_master_clk # dispgen_bypass = dispgen_bypass_en # dispgen_clken = dispgen_clk_dis # dispgen_err = dispgen_err_dis # dispgen_pipeln = dispgen_pipeln_dis # distdwn_bypass_pipeln = distdwn_bypass_pipeln_dis # distdwn_master = distdwn_master_en # distup_bypass_pipeln = distup_bypass_pipeln_dis # distup_master = distup_master_en # dv_bond = dv_bond_dis # empty_flag_type = empty_rd_side # enc64b66b_txsm_clken = enc64b66b_txsm_clk_en # enc_64b66b_txsm_bypass = enc_64b66b_txsm_bypass_dis # fastpath = fastpath_dis # fec_clken = fec_clk_dis # fec_enable = fec_dis # fifo_double_write = fifo_double_write_dis # fifo_reg_fast = fifo_reg_fast_dis # fifo_stop_rd = rd_empty # fifo_stop_wr = n_wr_full # frmgen_burst = frmgen_burst_dis # frmgen_bypass = frmgen_bypass_en # frmgen_clken = frmgen_clk_dis # frmgen_mfrm_length = 0800 # frmgen_pipeln = frmgen_pipeln_en # frmgen_pyld_ins = frmgen_pyld_ins_dis # frmgen_wordslip = frmgen_wordslip_dis # full_flag_type = full_wr_side # gb_pipeln_bypass = disable # gb_tx_idwidth = width_66 # gb_tx_odwidth = width_32 # gbred_clken = gbred_clk_en # indv = indv_en # low_latency_en = disable # master_clk_sel = master_tx_pma_clk # pempty_flag_type = pempty_rd_side # pfull_flag_type = pfull_wr_side # phcomp_rd_del = phcomp_rd_del4 # pld_if_type = fifo # prot_mode = teng_baser_mode # pseudo_random = all_0 # pseudo_seed_a_bin = 000000000000000003ffffffffffffff # pseudo_seed_b_bin = 000000000000000003ffffffffffffff # random_disp = disable # rdfifo_clken = rdfifo_clk_en # reconfig_settings = {} # scrm_bypass = scrm_bypass_dis # scrm_clken = scrm_clk_en # scrm_mode = async # scrm_pipeln = enable # sh_err = sh_err_dis # silicon_rev = 20nm1 # sop_mark = sop_mark_dis # stretch_num_stages = two_stage # sup_mode = user_mode # test_mode = test_off # tx_scrm_err = scrm_err_dis # tx_scrm_width = bit64 # tx_sh_location = lsb # tx_sm_bypass = tx_sm_bypass_dis # tx_sm_pipeln = tx_sm_pipeln_en # tx_testbus_sel = tx_fifo_testbus1 # txfifo_empty = empty_default # txfifo_full = full_default # txfifo_mode = phase_comp # txfifo_pempty = 2 # txfifo_pfull = b # wr_clk_sel = wr_tx_pld_clk # wrfifo_clken = wrfifo_clk_en # # # ================================================ # Module twentynm_hssi_8g_rx_pcs # ================================================ # auto_error_replacement = dis_err_replace # auto_speed_nego = dis_asn # bit_reversal = dis_bit_reversal # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # bypass_pipeline_reg = dis_bypass_pipeline # byte_deserializer = dis_bds # cdr_ctrl_rxvalid_mask = dis_rxvalid_mask # clkcmp_pattern_n = 00000 # clkcmp_pattern_p = 00000 # clock_gate_bds_dec_asn = en_bds_dec_asn_clk_gating # clock_gate_cdr_eidle = en_cdr_eidle_clk_gating # clock_gate_dw_pc_wrclk = en_dw_pc_wrclk_gating # clock_gate_dw_rm_rd = en_dw_rm_rdclk_gating # clock_gate_dw_rm_wr = en_dw_rm_wrclk_gating # clock_gate_dw_wa = en_dw_wa_clk_gating # clock_gate_pc_rdclk = en_pc_rdclk_gating # clock_gate_sw_pc_wrclk = en_sw_pc_wrclk_gating # clock_gate_sw_rm_rd = en_sw_rm_rdclk_gating # clock_gate_sw_rm_wr = en_sw_rm_wrclk_gating # clock_gate_sw_wa = en_sw_wa_clk_gating # clock_observation_in_pld_core = internal_sw_wa_clk # ctrl_plane_bonding_compensation = dis_compensation # ctrl_plane_bonding_consumption = individual # ctrl_plane_bonding_distribution = not_master_chnl_distr # eidle_entry_eios = dis_eidle_eios # eidle_entry_iei = dis_eidle_iei # eidle_entry_sd = dis_eidle_sd # eightb_tenb_decoder = en_8b10b_ibm # err_flags_sel = err_flags_wa # fixed_pat_det = dis_fixed_patdet # fixed_pat_num = 0 # force_signal_detect = en_force_signal_detect # gen3_clk_en = disable_clk # gen3_rx_clk_sel = rcvd_clk # gen3_tx_clk_sel = tx_pma_clk # hip_mode = dis_hip # ibm_invalid_code = dis_ibm_invalid_code # invalid_code_flag_only = dis_invalid_code_only # pad_or_edb_error_replace = replace_edb # pcs_bypass = dis_pcs_bypass # phase_comp_rdptr = disable_rdptr # phase_compensation_fifo = low_latency # pipe_if_enable = dis_pipe_rx # pma_dw = ten_bit # polinv_8b10b_dec = dis_polinv_8b10b_dec # prot_mode = disabled_prot_mode # rate_match = dis_rm # rate_match_del_thres = dis_rm_del_thres # rate_match_empty_thres = dis_rm_empty_thres # rate_match_full_thres = dis_rm_full_thres # rate_match_ins_thres = dis_rm_ins_thres # rate_match_start_thres = dis_rm_start_thres # reconfig_settings = {} # rx_clk2 = rcvd_clk_clk2 # rx_clk_free_running = en_rx_clk_free_run # rx_pcs_urst = en_rx_pcs_urst # rx_rcvd_clk = rcvd_clk_rcvd_clk # rx_rd_clk = pld_rx_clk # rx_refclk = dis_refclk_sel # rx_wr_clk = rx_clk2_div_1_2_4 # silicon_rev = 20nm1 # sup_mode = user_mode # symbol_swap = dis_symbol_swap # sync_sm_idle_eios = dis_syncsm_idle # test_bus_sel = tx_testbus # tx_rx_parallel_loopback = dis_plpbk # wa_boundary_lock_ctrl = sync_sm # wa_clk_slip_spacing = 010 # wa_det_latency_sync_status_beh = dont_care_assert_sync # wa_disp_err_flag = en_disp_err_flag # wa_kchar = dis_kchar # wa_pd = wa_pd_10 # wa_pd_data_bin = 00000000000000000000000000000000 # wa_pd_polarity = dont_care_both_pol # wa_pld_controlled = dis_pld_ctrl # wa_renumber_data = 03 # wa_rgnumber_data = 03 # wa_rknumber_data = 03 # wa_rosnumber_data = 1 # wa_rvnumber_data = 0000 # wa_sync_sm_ctrl = gige_sync_sm # wait_cnt = 000 # # # ================================================ # Module twentynm_hssi_8g_tx_pcs # ================================================ # auto_speed_nego_gen2 = dis_asn_g2 # bit_reversal = dis_bit_reversal # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # bypass_pipeline_reg = dis_bypass_pipeline # byte_serializer = dis_bs # clock_gate_bs_enc = en_bs_enc_clk_gating # clock_gate_dw_fifowr = en_dw_fifowr_clk_gating # clock_gate_fiford = en_fiford_clk_gating # clock_gate_sw_fifowr = en_sw_fifowr_clk_gating # clock_observation_in_pld_core = internal_refclk_b # ctrl_plane_bonding_compensation = dis_compensation # ctrl_plane_bonding_consumption = individual # ctrl_plane_bonding_distribution = not_master_chnl_distr # data_selection_8b10b_encoder_input = normal_data_path # dynamic_clk_switch = dis_dyn_clk_switch # eightb_tenb_disp_ctrl = dis_disp_ctrl # eightb_tenb_encoder = en_8b10b_ibm # force_echar = dis_force_echar # force_kchar = dis_force_kchar # gen3_tx_clk_sel = dis_tx_clk # gen3_tx_pipe_clk_sel = dis_tx_pipe_clk # hip_mode = dis_hip # pcs_bypass = dis_pcs_bypass # phase_comp_rdptr = disable_rdptr # phase_compensation_fifo = low_latency # phfifo_write_clk_sel = pld_tx_clk # pma_dw = ten_bit # prot_mode = disabled_prot_mode # reconfig_settings = {} # refclk_b_clk_sel = tx_pma_clock # revloop_back_rm = dis_rev_loopback_rx_rm # silicon_rev = 20nm1 # sup_mode = user_mode # symbol_swap = dis_symbol_swap # tx_bitslip = dis_tx_bitslip # tx_compliance_controlled_disparity = dis_txcompliance # tx_fast_pld_reg = dis_tx_fast_pld_reg # txclk_freerun = en_freerun_tx # txpcs_urst = en_txpcs_urst # # # ================================================ # Module twentynm_hssi_common_pcs_pma_interface # ================================================ # asn_clk_enable = false # asn_enable = dis_asn # block_sel = eight_g_pcs # bypass_early_eios = true # bypass_pcie_switch = true # bypass_pma_ltr = true # bypass_pma_sw_done = false # bypass_ppm_lock = false # bypass_send_syncp_fbkp = true # bypass_txdetectrx = true # cdr_control = dis_cdr_ctrl # cid_enable = dis_cid_mode # cp_cons_sel = cp_cons_master # cp_dwn_mstr = true # cp_up_mstr = true # ctrl_plane_bonding = individual # data_mask_count = 0000 # data_mask_count_multi = 0 # dft_observation_clock_selection = dft_clk_obsrv_tx0 # early_eios_counter = 00 # force_freqdet = force_freqdet_dis # free_run_clk_enable = false # ignore_sigdet_g23 = false # pc_en_counter = 00 # pc_rst_counter = 00 # pcie_hip_mode = hip_disable # ph_fifo_reg_mode = phfifo_reg_mode_dis # phfifo_flush_wait = 00 # pipe_if_g3pcs = pipe_if_8gpcs # pma_done_counter = 00000 # pma_if_dft_en = dft_dis # pma_if_dft_val = dft_0 # ppm_cnt_rst = ppm_cnt_rst_dis # ppm_deassert_early = deassert_early_dis # ppm_det_buckets = ppm_100_bucket # ppm_gen1_2_cnt = cnt_32k # ppm_post_eidle_delay = cnt_200_cycles # ppmsel = ppmsel_1000 # prot_mode = other_protocols # reconfig_settings = {} # rxvalid_mask = rxvalid_mask_dis # sigdet_wait_counter = 000 # sigdet_wait_counter_multi = 0 # silicon_rev = 20nm1 # sim_mode = disable # spd_chg_rst_wait_cnt_en = false # sup_mode = user_mode # testout_sel = asn_test # wait_clk_on_off_timer = 0 # wait_pipe_synchronizing = 00 # wait_send_syncp_fbkp = 000 # # # ================================================ # Module twentynm_hssi_common_pld_pcs_interface # ================================================ # dft_clk_out_en = dft_clk_out_disable # dft_clk_out_sel = teng_rx_dft_clk # hrdrstctrl_en = hrst_dis # pcs_testbus_block_sel = pma_if # reconfig_settings = {} # silicon_rev = 20nm1 # # # ================================================ # Module twentynm_hssi_fifo_rx_pcs # ================================================ # double_read_mode = double_read_dis # prot_mode = teng_mode # silicon_rev = 20nm1 # # # ================================================ # Module twentynm_hssi_fifo_tx_pcs # ================================================ # double_write_mode = double_write_dis # prot_mode = teng_mode # silicon_rev = 20nm1 # # # ================================================ # Module twentynm_hssi_gen3_rx_pcs # ================================================ # block_sync = bypass_block_sync # block_sync_sm = disable_blk_sync_sm # cdr_ctrl_force_unalgn = disable # lpbk_force = lpbk_frce_dis # mode = disable_pcs # rate_match_fifo = bypass_rm_fifo # rate_match_fifo_latency = low_latency # reconfig_settings = {} # reverse_lpbk = rev_lpbk_dis # rx_b4gb_par_lpbk = b4gb_par_lpbk_dis # rx_force_balign = dis_force_balign # rx_ins_del_one_skip = ins_del_one_skip_dis # rx_num_fixed_pat = 0 # rx_test_out_sel = rx_test_out0 # silicon_rev = 20nm1 # sup_mode = user_mode # # # ================================================ # Module twentynm_hssi_gen3_tx_pcs # ================================================ # mode = disable_pcs # reverse_lpbk = rev_lpbk_dis # silicon_rev = 20nm1 # sup_mode = user_mode # tx_bitslip = 00 # tx_gbox_byp = bypass_gbox # # # ================================================ # Module twentynm_hssi_krfec_rx_pcs # ================================================ # blksync_cor_en = detect # bypass_gb = bypass_dis # clr_ctrl = both_enabled # ctrl_bit_reverse = ctrl_bit_reverse_en # data_bit_reverse = data_bit_reverse_dis # dv_start = with_blklock # err_mark_type = err_mark_10g # error_marking_en = err_mark_dis # low_latency_en = disable # lpbk_mode = lpbk_dis # parity_invalid_enum = 08 # parity_valid_num = 4 # pipeln_blksync = enable # pipeln_descrm = disable # pipeln_errcorrect = disable # pipeln_errtrap_ind = enable # pipeln_errtrap_lfsr = disable # pipeln_errtrap_loc = disable # pipeln_errtrap_pat = disable # pipeln_gearbox = enable # pipeln_syndrm = enable # pipeln_trans_dec = disable # prot_mode = disable_mode # receive_order = receive_lsb # reconfig_settings = {} # rx_testbus_sel = overall # signal_ok_en = sig_ok_en # silicon_rev = 20nm1 # sup_mode = user_mode # # # ================================================ # Module twentynm_hssi_krfec_tx_pcs # ================================================ # burst_err = burst_err_dis # burst_err_len = burst_err_len1 # ctrl_bit_reverse = ctrl_bit_reverse_en # data_bit_reverse = data_bit_reverse_dis # enc_frame_query = enc_query_dis # low_latency_en = disable # pipeln_encoder = enable # pipeln_scrambler = enable # prot_mode = disable_mode # silicon_rev = 20nm1 # sup_mode = user_mode # transcode_err = trans_err_dis # transmit_order = transmit_lsb # tx_testbus_sel = overall # # # ================================================ # Module twentynm_hssi_pipe_gen1_2 # ================================================ # elec_idle_delay_val = 0 # error_replace_pad = replace_edb # hip_mode = dis_hip # ind_error_reporting = dis_ind_error_reporting # phystatus_delay_val = 0 # phystatus_rst_toggle = dis_phystatus_rst_toggle # pipe_byte_de_serializer_en = dont_care_bds # prot_mode = disabled_prot_mode # reconfig_settings = {} # rpre_emph_a_val = 00 # rpre_emph_b_val = 00 # rpre_emph_c_val = 00 # rpre_emph_d_val = 00 # rpre_emph_e_val = 00 # rvod_sel_a_val = 00 # rvod_sel_b_val = 00 # rvod_sel_c_val = 00 # rvod_sel_d_val = 00 # rvod_sel_e_val = 00 # rx_pipe_enable = dis_pipe_rx # rxdetect_bypass = dis_rxdetect_bypass # silicon_rev = 20nm1 # sup_mode = user_mode # tx_pipe_enable = dis_pipe_tx # txswing = dis_txswing # # # ================================================ # Module twentynm_hssi_pipe_gen3 # ================================================ # bypass_rx_detection_enable = false # bypass_rx_preset = 0 # bypass_rx_preset_enable = false # bypass_tx_coefficent = 00000 # bypass_tx_coefficent_enable = false # elecidle_delay_g3 = 0 # ind_error_reporting = dis_ind_error_reporting # mode = disable_pcs # phy_status_delay_g12 = 0 # phy_status_delay_g3 = 0 # phystatus_rst_toggle_g12 = dis_phystatus_rst_toggle # phystatus_rst_toggle_g3 = dis_phystatus_rst_toggle_g3 # rate_match_pad_insertion = dis_rm_fifo_pad_ins # silicon_rev = 20nm1 # sup_mode = user_mode # test_out_sel = disable_test_out # # # ================================================ # Module twentynm_hssi_rx_pcs_pma_interface # ================================================ # block_sel = ten_g_pcs # channel_operation_mode = tx_rx_pair_enabled # clkslip_sel = pld # lpbk_en = disable # master_clk_sel = master_rx_pma_clk # pldif_datawidth_mode = pldif_data_10bit # pma_dw_rx = pma_32b_rx # pma_if_dft_en = dft_dis # pma_if_dft_val = dft_0 # prbs9_dwidth = prbs9_64b # prbs_clken = prbs_clk_dis # prbs_ver = prbs_off # prot_mode_rx = teng_krfec_mode_rx # reconfig_settings = {} # rx_dyn_polarity_inversion = rx_dyn_polinv_dis # rx_lpbk_en = lpbk_dis # rx_prbs_force_signal_ok = force_sig_ok # rx_prbs_mask = prbsmask128 # rx_prbs_mode = teng_mode # rx_signalok_signaldet_sel = sel_sig_det # rx_static_polarity_inversion = rx_stat_polinv_dis # rx_uhsif_lpbk_en = uhsif_lpbk_dis # silicon_rev = 20nm1 # sup_mode = user_mode # # Note - If you are performing a post-fit simulation, you must add the 'altera_a10_xcvr_clock_module' to your top-level design. Please refer to the 'Arria 10 Transceiver PHY User Guide' for details. # # ================================================ # Module twentynm_hssi_rx_pld_pcs_interface # ================================================ # hd_10g_advanced_user_mode_rx = disable # hd_10g_channel_operation_mode = tx_rx_pair_enabled # hd_10g_ctrl_plane_bonding_rx = individual_rx # hd_10g_fifo_mode_rx = fifo_rx # hd_10g_low_latency_en_rx = disable # hd_10g_lpbk_en = disable # hd_10g_pma_dw_rx = pma_32b_rx # hd_10g_prot_mode_rx = teng_baser_mode_rx # hd_10g_shared_fifo_width_rx = single_rx # hd_10g_sup_mode = user_mode # hd_10g_test_bus_mode = rx # hd_8g_channel_operation_mode = tx_rx_pair_enabled # hd_8g_ctrl_plane_bonding_rx = individual_rx # hd_8g_fifo_mode_rx = fifo_rx # hd_8g_hip_mode = disable # hd_8g_lpbk_en = disable # hd_8g_pma_dw_rx = pma_10b_rx # hd_8g_prot_mode_rx = disabled_prot_mode_rx # hd_8g_sup_mode = user_mode # hd_chnl_channel_operation_mode = tx_rx_pair_enabled # hd_chnl_clklow_clk_hz = 13356219 # hd_chnl_ctrl_plane_bonding_rx = individual_rx # hd_chnl_fref_clk_hz = 13356219 # hd_chnl_frequency_rules_en = enable # hd_chnl_func_mode = enable # hd_chnl_hclk_clk_hz = 00000000 # hd_chnl_hip_en = disable # hd_chnl_hrdrstctl_en = disable # hd_chnl_low_latency_en_rx = disable # hd_chnl_lpbk_en = disable # hd_chnl_operating_voltage = standard # hd_chnl_pcs_ac_pwr_rules_en = disable # hd_chnl_pcs_pair_ac_pwr_uw_per_mhz = 00000 # hd_chnl_pcs_rx_ac_pwr_uw_per_mhz = 00000 # hd_chnl_pcs_rx_pwr_scaling_clk = pma_rx_clk # hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz = 00000000 # hd_chnl_pld_fifo_mode_rx = fifo_rx # hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz = 00000000 # hd_chnl_pld_rx_clk_hz = 09502f90 # hd_chnl_pma_dw_rx = pma_32b_rx # hd_chnl_pma_rx_clk_hz = 13356219 # hd_chnl_prot_mode_rx = teng_baser_rx # hd_chnl_shared_fifo_width_rx = single_rx # hd_chnl_speed_grade = e2 # hd_chnl_sup_mode = user_mode # hd_chnl_transparent_pcs_rx = disable # hd_fifo_channel_operation_mode = tx_rx_pair_enabled # hd_fifo_prot_mode_rx = teng_mode_rx # hd_fifo_shared_fifo_width_rx = single_rx # hd_fifo_sup_mode = user_mode # hd_g3_prot_mode = disabled_prot_mode # hd_g3_sup_mode = user_mode # hd_krfec_channel_operation_mode = tx_rx_pair_enabled # hd_krfec_low_latency_en_rx = disable # hd_krfec_lpbk_en = disable # hd_krfec_prot_mode_rx = disabled_prot_mode_rx # hd_krfec_sup_mode = user_mode # hd_krfec_test_bus_mode = tx # hd_pldif_hrdrstctl_en = disable # hd_pldif_prot_mode_rx = teng_pld_fifo_mode_rx # hd_pldif_sup_mode = user_mode # hd_pmaif_channel_operation_mode = tx_rx_pair_enabled # hd_pmaif_lpbk_en = disable # hd_pmaif_pma_dw_rx = pma_32b_rx # hd_pmaif_prot_mode_rx = teng_krfec_mode_rx # hd_pmaif_sim_mode = disable # hd_pmaif_sup_mode = user_mode # pcs_rx_block_sel = teng # pcs_rx_clk_out_sel = teng_clk_out # pcs_rx_clk_sel = pld_rx_clk # pcs_rx_hip_clk_en = hip_rx_disable # pcs_rx_output_sel = teng_output # reconfig_settings = {} # silicon_rev = 20nm1 # # # ================================================ # Module twentynm_hssi_tx_pcs_pma_interface # ================================================ # bypass_pma_txelecidle = true # channel_operation_mode = tx_rx_pair_enabled # lpbk_en = disable # master_clk_sel = master_tx_pma_clk # pcie_sub_prot_mode_tx = other_prot_mode # pldif_datawidth_mode = pldif_data_10bit # pma_dw_tx = pma_32b_tx # pma_if_dft_en = dft_dis # pmagate_en = pmagate_dis # prbs9_dwidth = prbs9_64b # prbs_clken = prbs_clk_dis # prbs_gen_pat = prbs_gen_dis # prot_mode_tx = teng_krfec_mode_tx # reconfig_settings = {} # silicon_rev = 20nm1 # sq_wave_num = sq_wave_default # sqwgen_clken = sqwgen_clk_dis # sup_mode = user_mode # tx_dyn_polarity_inversion = tx_dyn_polinv_dis # tx_pma_data_sel = ten_g_pcs # tx_static_polarity_inversion = tx_stat_polinv_dis # uhsif_cnt_step_filt_before_lock = uhsif_filt_stepsz_b4lock_2 # uhsif_cnt_thresh_filt_after_lock_value = 0 # uhsif_cnt_thresh_filt_before_lock = uhsif_filt_cntthr_b4lock_8 # uhsif_dcn_test_update_period = uhsif_dcn_test_period_4 # uhsif_dcn_testmode_enable = uhsif_dcn_test_mode_disable # uhsif_dead_zone_count_thresh = uhsif_dzt_cnt_thr_2 # uhsif_dead_zone_detection_enable = uhsif_dzt_disable # uhsif_dead_zone_obser_window = uhsif_dzt_obr_win_16 # uhsif_dead_zone_skip_size = uhsif_dzt_skipsz_4 # uhsif_delay_cell_index_sel = uhsif_index_cram # uhsif_delay_cell_margin = uhsif_dcn_margin_2 # uhsif_delay_cell_static_index_value = 00 # uhsif_dft_dead_zone_control = uhsif_dft_dz_det_val_0 # uhsif_dft_up_filt_control = uhsif_dft_up_val_0 # uhsif_enable = uhsif_disable # uhsif_lock_det_segsz_after_lock = uhsif_lkd_segsz_aflock_512 # uhsif_lock_det_segsz_before_lock = uhsif_lkd_segsz_b4lock_16 # uhsif_lock_det_thresh_cnt_after_lock_value = 0 # uhsif_lock_det_thresh_cnt_before_lock_value = 0 # uhsif_lock_det_thresh_diff_after_lock_value = 0 # uhsif_lock_det_thresh_diff_before_lock_value = 0 # # Note - If you are performing a post-fit simulation, you must add the 'altera_a10_xcvr_clock_module' to your top-level design. Please refer to the 'Arria 10 Transceiver PHY User Guide' for details. # # ================================================ # Module twentynm_hssi_tx_pld_pcs_interface # ================================================ # hd_10g_advanced_user_mode_tx = disable # hd_10g_channel_operation_mode = tx_rx_pair_enabled # hd_10g_ctrl_plane_bonding_tx = individual_tx # hd_10g_fifo_mode_tx = fifo_tx # hd_10g_low_latency_en_tx = disable # hd_10g_lpbk_en = disable # hd_10g_pma_dw_tx = pma_32b_tx # hd_10g_prot_mode_tx = teng_baser_mode_tx # hd_10g_shared_fifo_width_tx = single_tx # hd_10g_sup_mode = user_mode # hd_8g_channel_operation_mode = tx_rx_pair_enabled # hd_8g_ctrl_plane_bonding_tx = individual_tx # hd_8g_fifo_mode_tx = fifo_tx # hd_8g_hip_mode = disable # hd_8g_lpbk_en = disable # hd_8g_pma_dw_tx = pma_10b_tx # hd_8g_prot_mode_tx = disabled_prot_mode_tx # hd_8g_sup_mode = user_mode # hd_chnl_channel_operation_mode = tx_rx_pair_enabled # hd_chnl_ctrl_plane_bonding_tx = individual_tx # hd_chnl_frequency_rules_en = enable # hd_chnl_func_mode = enable # hd_chnl_hclk_clk_hz = 00000000 # hd_chnl_hip_en = disable # hd_chnl_hrdrstctl_en = disable # hd_chnl_low_latency_en_tx = disable # hd_chnl_lpbk_en = disable # hd_chnl_pcs_tx_ac_pwr_uw_per_mhz = 00000 # hd_chnl_pcs_tx_pwr_scaling_clk = pma_tx_clk # hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz = 00000000 # hd_chnl_pld_fifo_mode_tx = fifo_tx # hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz = 00000000 # hd_chnl_pld_tx_clk_hz = 09502f90 # hd_chnl_pld_uhsif_tx_clk_hz = 00000000 # hd_chnl_pma_dw_tx = pma_32b_tx # hd_chnl_pma_tx_clk_hz = 13356219 # hd_chnl_prot_mode_tx = teng_baser_tx # hd_chnl_shared_fifo_width_tx = single_tx # hd_chnl_speed_grade = e2 # hd_chnl_sup_mode = user_mode # hd_fifo_channel_operation_mode = tx_rx_pair_enabled # hd_fifo_prot_mode_tx = teng_mode_tx # hd_fifo_shared_fifo_width_tx = single_tx # hd_fifo_sup_mode = user_mode # hd_g3_prot_mode = disabled_prot_mode # hd_g3_sup_mode = user_mode # hd_krfec_channel_operation_mode = tx_rx_pair_enabled # hd_krfec_low_latency_en_tx = disable # hd_krfec_lpbk_en = disable # hd_krfec_prot_mode_tx = disabled_prot_mode_tx # hd_krfec_sup_mode = user_mode # hd_pldif_hrdrstctl_en = disable # hd_pldif_prot_mode_tx = teng_pld_fifo_mode_tx # hd_pldif_sup_mode = user_mode # hd_pmaif_channel_operation_mode = tx_rx_pair_enabled # hd_pmaif_ctrl_plane_bonding = individual # hd_pmaif_lpbk_en = disable # hd_pmaif_pma_dw_tx = pma_32b_tx # hd_pmaif_prot_mode_tx = teng_krfec_mode_tx # hd_pmaif_sim_mode = disable # hd_pmaif_sup_mode = user_mode # pcs_tx_clk_out_sel = teng_clk_out # pcs_tx_clk_source = teng # pcs_tx_data_source = hip_disable # pcs_tx_delay1_clk_en = delay1_clk_disable # pcs_tx_delay1_clk_sel = pcs_tx_clk # pcs_tx_delay1_ctrl = delay1_path0 # pcs_tx_delay1_data_sel = one_ff_delay # pcs_tx_delay2_clk_en = delay2_clk_disable # pcs_tx_delay2_ctrl = delay2_path0 # pcs_tx_output_sel = teng_output # reconfig_settings = {} # silicon_rev = 20nm1 # # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - Hello from altera_avalon_mm_master_bfm # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - $Revision: #1 $ # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - $Date: 2019/02/14 $ # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - AV_ADDRESS_W = 19 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - AV_SYMBOL_W = 8 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - AV_NUMSYMBOLS = 4 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - AV_BURSTCOUNT_W = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - REGISTER_WAITREQUEST = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - AV_FIX_READ_LATENCY = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - AV_MAX_PENDING_READS = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - AV_MAX_PENDING_WRITES = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_READ = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_WRITE = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_ADDRESS = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_BYTE_ENABLE = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_BURSTCOUNT = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_READ_DATA = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_READ_DATA_VALID = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_WRITE_DATA = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_BEGIN_TRANSFER = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_BEGIN_BURST_TRANSFER = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_WAIT_REQUEST = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_LOCK = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_DEBUGACCESS = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_TRANSACTIONID = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_WRITERESPONSE = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_READRESPONSE = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_mm_csr_bfm.__hello: - USE_CLKEN = 0 # 0: INFO: ------------------------------------------------------------ # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - Hello from altera_avalon_st_sink_bfm. # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - $Revision: #1 $ # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - $Date: 2019/02/14 $ # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - ST_SYMBOL_W = 8 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - ST_NUMSYMBOLS = 4 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - ST_CHANNEL_W = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - ST_ERROR_W = 6 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - ST_EMPTY_W = 2 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - ST_READY_LATENCY = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - ST_MAX_CHANNELS = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - ST_BEATSPERCYCLE = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - USE_PACKET = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - USE_CHANNEL = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - USE_ERROR = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - USE_READY = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - USE_VALID = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_rx_bfm.__hello: - USE_EMPTY = 1 # 0: INFO: ------------------------------------------------------------ # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - Hello from altera_avalon_st_source_bfm. # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - $Revision: #1 $ # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - $Date: 2019/02/14 $ # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - ST_SYMBOL_W = 8 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - ST_NUMSYMBOLS = 4 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - ST_CHANNEL_W = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - ST_ERROR_W = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - ST_EMPTY_W = 2 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - ST_READY_LATENCY = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - ST_MAX_CHANNELS = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - ST_BEATSPERCYCLE = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - USE_PACKET = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - USE_CHANNEL = 0 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - USE_ERROR = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - USE_READY = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - USE_VALID = 1 # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.__hello: - USE_EMPTY = 1 # 0: INFO: ------------------------------------------------------------ # 0: INFO: tb_top.U_AVALON_DRIVER.U_BFM_WRAPPER.avalon_st_tx_bfm.set_response_timeout: Response timeout set to 1000000 cycles # _ERROR_: CRC Error Found 0 # _INFO_: Received Packet 0 # _ERROR_: CRC Error Found 0 # _INFO_: Received Packet 0