# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
# Date created = 09:11:12  February 15, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		multi_5_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSXFC6C6U23C7
set_global_assignment -name TOP_LEVEL_ENTITY multi_5
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:11:12  FEBRUARY 15, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS 3
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_Y13 -to clk_clk
set_instance_assignment -name IO_STANDARD "SSTL-135" -to clk_clk
set_instance_assignment -name IO_STANDARD HCSL -to clk_pll[0]
set_location_assignment PIN_V5 -to clk_pll[0]
set_location_assignment PIN_V4 -to "clk_pll[0](n)"
set_location_assignment PIN_AA11 -to rst
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to tx_serial_data[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_serial_data[4]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_serial_data[3]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_serial_data[2]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_serial_data[1]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_serial_data[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to tx_serial_data[4]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to tx_serial_data[3]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to tx_serial_data[2]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to tx_serial_data[1]
set_location_assignment PIN_AF2 -to rx_serial_data[0]
set_location_assignment PIN_AF1 -to "rx_serial_data[0](n)"
set_location_assignment PIN_AB2 -to rx_serial_data[1]
set_location_assignment PIN_AB1 -to "rx_serial_data[1](n)"
set_location_assignment PIN_V2 -to rx_serial_data[2]
set_location_assignment PIN_V1 -to "rx_serial_data[2](n)"
set_location_assignment PIN_P2 -to rx_serial_data[3]
set_location_assignment PIN_P1 -to "rx_serial_data[3](n)"
set_location_assignment PIN_K2 -to rx_serial_data[4]
set_location_assignment PIN_K1 -to "rx_serial_data[4](n)"
set_location_assignment PIN_AD2 -to tx_serial_data[0]
set_location_assignment PIN_AD1 -to "tx_serial_data[0](n)"
set_location_assignment PIN_Y2 -to tx_serial_data[1]
set_location_assignment PIN_Y1 -to "tx_serial_data[1](n)"
set_location_assignment PIN_T2 -to tx_serial_data[2]
set_location_assignment PIN_T1 -to "tx_serial_data[2](n)"
set_location_assignment PIN_M2 -to tx_serial_data[3]
set_location_assignment PIN_M1 -to "tx_serial_data[3](n)"
set_location_assignment PIN_H2 -to tx_serial_data[4]
set_location_assignment PIN_H1 -to "tx_serial_data[4](n)"
set_global_assignment -name SDC_FILE multi_5.out.sdc
set_global_assignment -name QIP_FILE nPhyCV.qip
set_global_assignment -name SIP_FILE nPhyCV.sip
set_global_assignment -name QIP_FILE nPhyReconf.qip
set_global_assignment -name SIP_FILE nPhyReconf.sip
set_global_assignment -name QIP_FILE nPhyRstCtrl.qip
set_global_assignment -name SIP_FILE nPhyRstCtrl.sip
set_global_assignment -name VHDL_FILE multi_5.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top