library ieee;
use ieee.std_logic_1164. all;
entity MAIN is
port(
    reset	           :	IN  STD_LOGIC;
    clock	           :	IN  STD_LOGIC;
    reconfig	        :	IN  STD_LOGIC ;
    read_param	      :	IN  STD_LOGIC ;
    write_param	     :	IN  STD_LOGIC ;
   --- pll_scandataout	 :	IN  STD_LOGIC ;
    counter_param	   :	IN  STD_LOGIC_VECTOR (2 DOWNTO 0) ;
		counter_type	    :	IN  STD_LOGIC_VECTOR (3 DOWNTO 0) ;
    data_in	         :	IN  STD_LOGIC_VECTOR (8 DOWNTO 0) ; 
    ---------------------------------------------------------------
    busy             : OUT STD_LOGIC ;
    data_out	        :	OUT  STD_LOGIC_VECTOR (8 DOWNTO 0);
  		c0		             : OUT STD_LOGIC ;
		locked		         : OUT STD_LOGIC 

    
  );
end entity;
architecture BEH of MAIN is
  ---------------------------------------------------------
------------////ALTPLL_RECONFIG Component///-------------

component ALTPLL_RECONFIG_50MHz_pllrcfg_9k51 IS 
	 PORT 
	 ( 
		 busy	:	OUT  STD_LOGIC;
		 clock	:	IN  STD_LOGIC;
		 counter_param	:	IN  STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0');
		 counter_type	:	IN  STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
		 data_in	:	IN  STD_LOGIC_VECTOR (8 DOWNTO 0) := (OTHERS => '0');
		 data_out	:	OUT  STD_LOGIC_VECTOR (8 DOWNTO 0);
		 pll_areset	:	OUT  STD_LOGIC;
		 pll_areset_in	:	IN  STD_LOGIC := '0';
		 pll_configupdate	:	OUT  STD_LOGIC;
		 pll_scanclk	:	OUT  STD_LOGIC;
		 pll_scanclkena	:	OUT  STD_LOGIC;
		 pll_scandata	:	OUT  STD_LOGIC;
		 pll_scandataout	:	IN  STD_LOGIC := '0';
		 pll_scandone	:	IN  STD_LOGIC := '0';
		 read_param	:	IN  STD_LOGIC := '0';
		 reconfig	:	IN  STD_LOGIC := '0';
		 reset	:	IN  STD_LOGIC;
		 write_param	:	IN  STD_LOGIC := '0'
	 ); 
 END component;
-------------------------------------------------------
-------------///ALT_PLL Component////------------------
component ALTPLL_50MHz IS
	PORT
	(
		areset		: IN STD_LOGIC  := '0';
		configupdate		: IN STD_LOGIC  := '0';
		inclk0		: IN STD_LOGIC  := '0';
		scanclk		: IN STD_LOGIC  := '1';
		scanclkena		: IN STD_LOGIC  := '0';
		scandata		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC ;
		locked		: OUT STD_LOGIC ;
		scandataout		: OUT STD_LOGIC ;
		scandone		: OUT STD_LOGIC 
	);
END component;
------------------------------------------------------------
---------------/////Intermediate signals///-----------------
signal scandataout		   : STD_LOGIC :='0';
signal scandone		      : STD_LOGIC ;
signal areset		        : STD_LOGIC ;
signal configupdate		  : STD_LOGIC  ;
signal scanclk		       : STD_LOGIC  := '1';
signal scanclkena		    : STD_LOGIC  := '0';
signal scandata	      	: STD_LOGIC  := '0';
signal pll_areset_in   : STD_LOGIC  := '0';
-------------------------------------------------------------
begin
U2:  ALTPLL_RECONFIG_50MHz_pllrcfg_9k51 
	 PORT MAP
	 ( 
	 -----///Input ports///-------------------
		 write_param	=> write_param,
		 clock	=> clock,
		 counter_param	=> counter_param,
		 counter_type	=>counter_type,
		 data_in	=> data_in	,
		 pll_areset_in	=> pll_areset_in, -----------'0',---------------------always work
		 pll_scandataout	=>scandataout	,
		 pll_scandone	=>scandone	,
		 read_param	=> read_param,
		 reconfig	=> reconfig,
		 reset	=>reset, 
 ---------///Output ports///---------------
		 busy	=> busy,
		 data_out	=> data_out, 
		 pll_areset	=>areset	,
		 pll_configupdate	=>configupdate	,
		 pll_scanclk	=>scanclk	,
		 pll_scanclkena	=>scanclkena,
		 pll_scandata	=>scandata	
	 );  
  
 U1: ALTPLL_50MHz  
	PORT map
	(
	-------------/////Input ports///------------------
		areset		=>areset	,
		configupdate		=>configupdate	,
		inclk0		=> CLOCK,
		scanclk		=>scanclk	,
		scanclkena		=>scanclkena,
		scandata		=>scandata	,
-----------------////output ports///---------------
		c0		=> C0,
		locked		=> locked,
		scandataout		=>scandataout	,
		scandone		=>scandone	
	);
  
end architecture;
  
