# Reading C:/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl
# do testfpga_run_msim_rtl_verilog.do
# if ![file isdirectory testfpga_iputf_libs] {
# 	file mkdir testfpga_iputf_libs
# }
# 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work rtl_work 
# Modifying C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/modelsim.ini
# 
###### Libraries for IPUTF cores 
# vlib testfpga_iputf_libs/dual_boot_0
# vmap dual_boot_0 ./testfpga_iputf_libs/dual_boot_0
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap dual_boot_0 ./testfpga_iputf_libs/dual_boot_0 
# Modifying C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/modelsim.ini
# vlib testfpga_iputf_libs/onchip_flash_0
# vmap onchip_flash_0 ./testfpga_iputf_libs/onchip_flash_0
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap onchip_flash_0 ./testfpga_iputf_libs/onchip_flash_0 
# Modifying C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/modelsim.ini
###### End libraries for IPUTF cores 
###### MIF file copy and HDL compilation commands for IPUTF cores 
# 
# 
# vlog "C:/Users/anandr1x/Downloads/testfpga/dual_cfg_ip/simulation/submodules/mentor/altera_dual_boot.v"               -work dual_boot_0   
# ** Note: (vlog-1901) OptionFile "C:/Users/anandr1x/Desktop/testsim/vlog.opt" not found. Ignored.
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:08:09 on Jan 08,2020
# vlog -reportprogress 300 C:/Users/anandr1x/Downloads/testfpga/dual_cfg_ip/simulation/submodules/mentor/altera_dual_boot.v -work dual_boot_0 
# 
# Top level modules:
# End time: 09:08:10 on Jan 08,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog "C:/Users/anandr1x/Downloads/testfpga/dual_cfg_ip/simulation/submodules/mentor/alt_dual_boot_avmm.v"             -work dual_boot_0   
# ** Note: (vlog-1901) OptionFile "C:/Users/anandr1x/Desktop/testsim/vlog.opt" not found. Ignored.
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:08:10 on Jan 08,2020
# vlog -reportprogress 300 C:/Users/anandr1x/Downloads/testfpga/dual_cfg_ip/simulation/submodules/mentor/alt_dual_boot_avmm.v -work dual_boot_0 
# 
# Top level modules:
# End time: 09:08:11 on Jan 08,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog "C:/Users/anandr1x/Downloads/testfpga/dual_cfg_ip/simulation/submodules/mentor/alt_dual_boot.v"                  -work dual_boot_0   
# ** Note: (vlog-1901) OptionFile "C:/Users/anandr1x/Desktop/testsim/vlog.opt" not found. Ignored.
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:08:11 on Jan 08,2020
# vlog -reportprogress 300 C:/Users/anandr1x/Downloads/testfpga/dual_cfg_ip/simulation/submodules/mentor/alt_dual_boot.v -work dual_boot_0 
# 
# Top level modules:
# End time: 09:08:12 on Jan 08,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog "C:/Users/anandr1x/Downloads/testfpga/dual_cfg_ip/simulation/dual_cfg_ip.v"                                                          
# ** Note: (vlog-1901) OptionFile "C:/Users/anandr1x/Desktop/testsim/vlog.opt" not found. Ignored.
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:08:13 on Jan 08,2020
# vlog -reportprogress 300 C:/Users/anandr1x/Downloads/testfpga/dual_cfg_ip/simulation/dual_cfg_ip.v 
# -- Compiling module dual_cfg_ip
# 
# Top level modules:
# 	dual_cfg_ip
# End time: 09:08:13 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog "C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash_util.v"                 -work onchip_flash_0
# ** Note: (vlog-1901) OptionFile "C:/Users/anandr1x/Desktop/testsim/vlog.opt" not found. Ignored.
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:08:13 on Jan 08,2020
# vlog -reportprogress 300 C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash_util.v -work onchip_flash_0 
# -- Compiling module altera_onchip_flash_address_range_check
# -- Compiling module altera_onchip_flash_address_write_protection_check
# -- Compiling module altera_onchip_flash_s_address_write_protection_check
# -- Compiling module altera_onchip_flash_a_address_write_protection_check
# -- Compiling module altera_onchip_flash_convert_address
# -- Compiling module altera_onchip_flash_convert_sector
# -- Compiling module altera_onchip_flash_counter
# 
# Top level modules:
# 	altera_onchip_flash_address_range_check
# 	altera_onchip_flash_address_write_protection_check
# 	altera_onchip_flash_s_address_write_protection_check
# 	altera_onchip_flash_a_address_write_protection_check
# 	altera_onchip_flash_convert_address
# 	altera_onchip_flash_convert_sector
# 	altera_onchip_flash_counter
# End time: 09:08:13 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog "C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash.v"                      -work onchip_flash_0
# ** Note: (vlog-1901) OptionFile "C:/Users/anandr1x/Desktop/testsim/vlog.opt" not found. Ignored.
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:08:14 on Jan 08,2020
# vlog -reportprogress 300 C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash.v -work onchip_flash_0 
# -- Compiling module altera_onchip_flash
# 
# Top level modules:
# 	altera_onchip_flash
# End time: 09:08:14 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog "C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash_avmm_data_controller.v" -work onchip_flash_0
# ** Note: (vlog-1901) OptionFile "C:/Users/anandr1x/Desktop/testsim/vlog.opt" not found. Ignored.
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:08:14 on Jan 08,2020
# vlog -reportprogress 300 C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash_avmm_data_controller.v -work onchip_flash_0 
# -- Compiling module altera_onchip_flash_avmm_data_controller
# 
# Top level modules:
# 	altera_onchip_flash_avmm_data_controller
# End time: 09:08:15 on Jan 08,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog "C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash_avmm_csr_controller.v"  -work onchip_flash_0
# ** Note: (vlog-1901) OptionFile "C:/Users/anandr1x/Desktop/testsim/vlog.opt" not found. Ignored.
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:08:16 on Jan 08,2020
# vlog -reportprogress 300 C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash_avmm_csr_controller.v -work onchip_flash_0 
# -- Compiling module altera_onchip_flash_avmm_csr_controller
# 
# Top level modules:
# 	altera_onchip_flash_avmm_csr_controller
# End time: 09:08:16 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog "C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/flash_ip.v"                                                                
# ** Note: (vlog-1901) OptionFile "C:/Users/anandr1x/Desktop/testsim/vlog.opt" not found. Ignored.
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:08:16 on Jan 08,2020
# vlog -reportprogress 300 C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/flash_ip.v 
# -- Compiling module flash_ip
# 
# Top level modules:
# 	flash_ip
# End time: 09:08:17 on Jan 08,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+C:/Users/anandr1x/Downloads/testfpga {C:/Users/anandr1x/Downloads/testfpga/testfpga.v}
# ** Note: (vlog-1901) OptionFile "C:/Users/anandr1x/Desktop/testsim/vlog.opt" not found. Ignored.
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:08:17 on Jan 08,2020
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/anandr1x/Downloads/testfpga" C:/Users/anandr1x/Downloads/testfpga/testfpga.v 
# -- Compiling module testfpga
# 
# Top level modules:
# 	testfpga
# End time: 09:08:17 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+C:/Users/anandr1x/Downloads/testfpga {C:/Users/anandr1x/Downloads/testfpga/testbench.v}
# ** Note: (vlog-1901) OptionFile "C:/Users/anandr1x/Desktop/testsim/vlog.opt" not found. Ignored.
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:08:17 on Jan 08,2020
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/anandr1x/Downloads/testfpga" C:/Users/anandr1x/Downloads/testfpga/testbench.v 
# -- Compiling module testbench
# 
# Top level modules:
# 	testbench
# End time: 09:08:17 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L rtl_work -L work -L dual_boot_0 -L onchip_flash_0 -voptargs="+acc"  testbench
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L rtl_work -L work -L dual_boot_0 -L onchip_flash_0 -voptargs=""+acc"" testbench 
# Start time: 09:08:18 on Jan 08,2020
# Loading work.testbench
# Loading work.testfpga
# Loading work.flash_ip
# Loading onchip_flash_0.altera_onchip_flash
# Loading onchip_flash_0.altera_onchip_flash_avmm_data_controller
# Loading onchip_flash_0.altera_onchip_flash_address_range_check
# Loading onchip_flash_0.altera_onchip_flash_convert_address
# Loading fiftyfivenm_ver.fiftyfivenm_unvm
# Loading work.dual_cfg_ip
# Loading lpm_ver.lpm_shiftreg
# Loading lpm_ver.lpm_counter
# Loading fiftyfivenm_ver.fiftyfivenm_rublock
# Loading altera_mf_ver.altera_std_synchronizer
# Loading onchip_flash_0.altera_onchip_flash_a_address_write_protection_check
# Loading onchip_flash_0.altera_onchip_flash_s_address_write_protection_check
# Loading onchip_flash_0.altera_onchip_flash_convert_sector
# Loading onchip_flash_0.altera_onchip_flash_avmm_csr_controller
# ** Warning: (vsim-3017) C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash_avmm_data_controller.v(1167): [TFMPC] - Too few port connections. Expected 11, found 6.
#    Time: 0 ps  Iteration: 0  Instance: /testbench/testfpga/flash_ip/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/220model.v
# ** Warning: (vsim-3722) C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash_avmm_data_controller.v(1167): [TFMPC] - Missing connection for port 'shiftin'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash_avmm_data_controller.v(1167): [TFMPC] - Missing connection for port 'aset'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash_avmm_data_controller.v(1167): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash_avmm_data_controller.v(1167): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash_avmm_data_controller.v(1167): [TFMPC] - Missing connection for port 'q'.
# ** Warning: (vsim-3017) C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash.v(302): [TFMPC] - Too few port connections. Expected 18, found 17.
#    Time: 0 ps  Iteration: 0  Instance: /testbench/testfpga/flash_ip/onchip_flash_0/altera_onchip_flash_block File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/fiftyfivenm_atoms.v
# ** Warning: (vsim-3722) C:/Users/anandr1x/Downloads/testfpga/flash_ip/simulation/submodules/altera_onchip_flash.v(302): [TFMPC] - Missing connection for port 'bgpbusy'.
# ** Warning: (vsim-3017) <protected>(<protected>): [TFMPC] - Too few port connections. Expected <protected>, found <protected>.
#    Time: 0 ps  Iteration: 0  Protected: /testbench/testfpga/flash_ip/onchip_flash_0/altera_onchip_flash_block/inst/<protected>/<protected>/<protected>/<protected>/<protected> File: nofile
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3017) <protected>(<protected>): [TFMPC] - Too few port connections. Expected <protected>, found <protected>.
#    Time: 0 ps  Iteration: 0  Protected: /testbench/testfpga/dual_cfg_ip/dual_boot_0/<protected>/<protected>/<protected> File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/220model.v
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3017) <protected>(<protected>): [TFMPC] - Too few port connections. Expected <protected>, found <protected>.
#    Time: 0 ps  Iteration: 0  Protected: /testbench/testfpga/dual_cfg_ip/dual_boot_0/<protected>/<protected>/<protected> File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/220model.v
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3017) <protected>(<protected>): [TFMPC] - Too few port connections. Expected <protected>, found <protected>.
#    Time: 0 ps  Iteration: 0  Protected: /testbench/testfpga/dual_cfg_ip/dual_boot_0/<protected>/<protected>/<protected> File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/220model.v
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run 1000 us
# FLASH_READY detected