# Reading C:/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl
cd C:/testfpga/simulation/modelsim
# reading modelsim.ini
source C:/testfpga/dual_cfg_ip/simulation/mentor/msim_setup.tcl
# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                                         -- Copy ROM/RAM files to simulation directory
# 
# dev_com                                           -- Compile device library files
# 
# com                                               -- Compile the design files in correct order
# 
# elab                                              -- Elaborate top level design
# 
# elab_debug                                        -- Elaborate the top level design with novopt option
# 
# ld                                                -- Compile all the design files and elaborate the top level design
# 
# ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                                       -- Platform Designer base simulation directory.
# 
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
# 
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.

source C:/testfpga/flash_ip/simulation/mentor/msim_setup.tcl
# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                                         -- Copy ROM/RAM files to simulation directory
# 
# dev_com                                           -- Compile device library files
# 
# com                                               -- Compile the design files in correct order
# 
# elab                                              -- Elaborate top level design
# 
# elab_debug                                        -- Elaborate the top level design with novopt option
# 
# ld                                                -- Compile all the design files and elaborate the top level design
# 
# ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                                       -- Platform Designer base simulation directory.
# 
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
# 
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.

vlog C:/testfpga/testbench.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 17:29:05 on Jan 08,2020
# vlog -reportprogress 300 C:/testfpga/testbench.v 
# -- Compiling module testbench
# 
# Top level modules:
# 	testbench
# End time: 17:29:05 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

vlog C:/testfpga/testfpga.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 17:29:17 on Jan 08,2020
# vlog -reportprogress 300 C:/testfpga/testfpga.v 
# -- Compiling module testfpga
# 
# Top level modules:
# 	testfpga
# End time: 17:29:17 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

set TOP_LEVEL_NAME testbench
# testbench

com
# [exec] com
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 17:29:30 on Jan 08,2020
# vlog -reportprogress 300 c:/testfpga/flash_ip/synthesis/submodules/altera_onchip_flash_util.v -work onchip_flash_0 
# -- Compiling module altera_onchip_flash_address_range_check
# -- Compiling module altera_onchip_flash_address_write_protection_check
# -- Compiling module altera_onchip_flash_s_address_write_protection_check
# -- Compiling module altera_onchip_flash_a_address_write_protection_check
# -- Compiling module altera_onchip_flash_convert_address
# -- Compiling module altera_onchip_flash_convert_sector
# -- Compiling module altera_onchip_flash_counter
# 
# Top level modules:
# 	altera_onchip_flash_address_range_check
# 	altera_onchip_flash_address_write_protection_check
# 	altera_onchip_flash_s_address_write_protection_check
# 	altera_onchip_flash_a_address_write_protection_check
# 	altera_onchip_flash_convert_address
# 	altera_onchip_flash_convert_sector
# 	altera_onchip_flash_counter
# End time: 17:29:30 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 17:29:30 on Jan 08,2020
# vlog -reportprogress 300 c:/testfpga/flash_ip/synthesis/submodules/altera_onchip_flash.v -work onchip_flash_0 
# -- Compiling module altera_onchip_flash
# 
# Top level modules:
# 	altera_onchip_flash
# End time: 17:29:30 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 17:29:30 on Jan 08,2020
# vlog -reportprogress 300 c:/testfpga/flash_ip/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v -work onchip_flash_0 
# -- Compiling module altera_onchip_flash_avmm_data_controller
# 
# Top level modules:
# 	altera_onchip_flash_avmm_data_controller
# End time: 17:29:30 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 17:29:30 on Jan 08,2020
# vlog -reportprogress 300 c:/testfpga/flash_ip/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v -work onchip_flash_0 
# -- Compiling module altera_onchip_flash_avmm_csr_controller
# 
# Top level modules:
# 	altera_onchip_flash_avmm_csr_controller
# End time: 17:29:30 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 17:29:30 on Jan 08,2020
# vlog -reportprogress 300 c:/testfpga/flash_ip/synthesis/flash_ip.v 
# -- Compiling module flash_ip
# 
# Top level modules:
# 	flash_ip
# End time: 17:29:30 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
elab
# [exec] elab
# vsim -t ps -L work -L work_lib -L dual_boot_0 -L onchip_flash_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver testbench 
# Start time: 17:29:40 on Jan 08,2020
# Loading work.testbench
# Loading work.testfpga
# Loading work.flash_ip
# Loading onchip_flash_0.altera_onchip_flash
# Loading onchip_flash_0.altera_onchip_flash_avmm_data_controller
# Loading onchip_flash_0.altera_onchip_flash_address_range_check
# Loading onchip_flash_0.altera_onchip_flash_convert_address
# ** Error: (vsim-3033) c:/testfpga/flash_ip/synthesis/submodules/altera_onchip_flash.v(309): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.
#    Time: 0 ps  Iteration: 0  Instance: /testbench/testfpga/flash_ip/onchip_flash_0 File: c:/testfpga/flash_ip/synthesis/submodules/altera_onchip_flash.v
#         Searched libraries:
#             C:/testfpga/simulation/modelsim/libraries/onchip_flash_0
#             C:/testfpga/simulation/modelsim/libraries/work
#             C:/testfpga/simulation/modelsim/libraries/dual_boot_0
#             C:/testfpga/simulation/modelsim/libraries/onchip_flash_0
#             C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera
#             C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model
#             C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate
#             C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf
#             C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim
#             C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/fiftyfivenm
# ** Error: (vsim-3033) C:/testfpga/testfpga.v(220): Instantiation of 'dual_cfg_ip' failed. The design unit was not found.
#    Time: 0 ps  Iteration: 0  Instance: /testbench/testfpga File: C:/testfpga/testfpga.v
#         Searched libraries:
#             C:/testfpga/simulation/modelsim/libraries/work
#             C:/testfpga/simulation/modelsim/libraries/work
#             C:/testfpga/simulation/modelsim/libraries/dual_boot_0
#             C:/testfpga/simulation/modelsim/libraries/onchip_flash_0
#             C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera
#             C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model
#             C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate
#             C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf
#             C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim
#             C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/fiftyfivenm
# Error loading design
# End time: 17:29:40 on Jan 08,2020, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0