create_clock -name ClkExt16MHz -period 62.5 [get_ports {ClkExt16MHz}]

derive_pll_clocks
derive_clock_uncertainty


create_generated_clock -divide_by 2 -source {inst8|altpll_component|auto_generated|pll1|clk[0]} -name {MemLin:inst3|clk} {MemLin:inst3|clk}

create_generated_clock -divide_by 2 -source {inst8|altpll_component|auto_generated|pll1|clk[2]} -name {SPI_6xAD7249:inst11|clk} {SPI_6xAD7249:inst11|clk}

create_generated_clock -divide_by 2 -source {inst8|altpll_component|auto_generated|pll1|clk[2]} -name {SPI_LAN:inst10|clk} {SPI_LAN:inst10|clk}

create_generated_clock -divide_by 2 -source {inst8|altpll_component|auto_generated|pll1|clk[2]} -name {SPI_BAT:inst12|clk} {SPI_BAT:inst12|clk}