# Copyright (C) 2018 Intel Corporation. All rights reserved. # Your use of Intel Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Intel Program License # Subscription Agreement, the Intel Quartus Prime License Agreement, # the Intel FPGA IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by # Intel and sold by Intel or its authorized distributors. Please # refer to the applicable agreement for further details. # Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition # File: C:\Users\user\Pictures\Fitting Error\GE04_DDR3.csv # Generated on: Sun Jul 12 11:56:44 2020 # Note: The column header names should not be changed if you wish to import this .csv file into the Quartus Prime software. To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Strict Preservation DDR1_addr[12],Output,PIN_E13,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_addr[11],Output,PIN_D4,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_addr[10],Output,PIN_A5,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_addr[9],Output,PIN_A12,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_addr[8],Output,PIN_B3,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_addr[7],Output,PIN_A13,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_addr[6],Output,PIN_A3,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_addr[5],Output,PIN_D6,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_addr[4],Output,PIN_A4,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_addr[3],Output,PIN_A14,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_addr[2],Output,PIN_A8,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_addr[1],Output,PIN_A15,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_addr[0],Output,PIN_A7,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_ba[2],Output,PIN_F14,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_ba[1],Output,PIN_C4,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_ba[0],Output,PIN_C9,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_cas_n,Output,PIN_B6,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_cke[0],Output,PIN_D5,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_clk[0],Bidir,PIN_B12,7A,B7A_N0,Differential 1.5-V SSTL Class I,,,,DDR1_clk_n[0], DDR1_clk_n[0],Bidir,PIN_A11,7A,B7A_N0,Differential 1.5-V SSTL Class I,,,,DDR1_clk[0], DDR1_cs_n[0],Output,PIN_A6,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_dm[1],Output,PIN_J12,7A,B7A_N0,1.5 V,,,,, DDR1_dm[0],Output,PIN_K13,7A,B7A_N0,1.5 V,,,,, DDR1_dq[15],Bidir,PIN_E12,7A,B7A_N0,1.5 V,,,,, DDR1_dq[14],Bidir,PIN_F11,7A,B7A_N0,1.5 V,,,,, DDR1_dq[13],Bidir,PIN_F13,7A,B7A_N0,1.5 V,,,,, DDR1_dq[12],Bidir,PIN_C10,7A,B7A_N0,1.5 V,,,,, DDR1_dq[11],Bidir,PIN_C8,7A,B7A_N0,1.5 V,,,,, DDR1_dq[10],Bidir,PIN_E7,7A,B7A_N0,1.5 V,,,,, DDR1_dq[9],Bidir,PIN_D10,7A,B7A_N0,1.5 V,,,,, DDR1_dq[8],Bidir,PIN_D7,7A,B7A_N0,1.5 V,,,,, DDR1_dq[7],Bidir,PIN_C12,7A,B7A_N0,1.5 V,,,,, DDR1_dq[6],Bidir,PIN_D12,7A,B7A_N0,1.5 V,,,,, DDR1_dq[5],Bidir,PIN_C5,7A,B7A_N0,1.5 V,,,,, DDR1_dq[4],Bidir,PIN_K12,7A,B7A_N0,1.5 V,,,,, DDR1_dq[3],Bidir,PIN_C6,7A,B7A_N0,1.5 V,,,,, DDR1_dq[2],Bidir,PIN_F12,7A,B7A_N0,1.5 V,,,,, DDR1_dq[1],Bidir,PIN_D13,7A,B7A_N0,1.5 V,,,,, DDR1_dq[0],Bidir,PIN_C13,7A,B7A_N0,1.5 V,,,,, DDR1_dqs[1],Bidir,PIN_E9,7A,B7A_N0,Differential 1.5-V SSTL Class I,,,,DDR1_dqsn[1], DDR1_dqs[0],Bidir,PIN_D11,7A,B7A_N0,Differential 1.5-V SSTL Class I,,,,DDR1_dqsn[0], DDR1_dqsn[1],Bidir,PIN_D9,7A,B7A_N0,Differential 1.5-V SSTL Class I,,,,DDR1_dqs[1], DDR1_dqsn[0],Bidir,PIN_C11,7A,B7A_N0,Differential 1.5-V SSTL Class I,,,,DDR1_dqs[0], DDR1_odt[0],Output,PIN_D8,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_ras_n,Output,PIN_C7,7A,B7A_N0,1.5 V,,maximum current,,, DDR1_reset_n,Output,PIN_B9,7A,B7A_N0,1.5 V,,,,, DDR1_we_n,Output,PIN_A9,7A,B7A_N0,1.5 V,,maximum current,,,