Text file sample without Time information: (Simulation starts with no error) 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 Text file sample with Time information: (error in improper reading of data) 200 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 206.3 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 209.8 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 210.2 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 210.7 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 210.9 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 211.4 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 211.5 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 211.8 0 1 0 0 0 0 0 1 0 0 1 1110 010 1010111111111110 1 1 1 0000000000000000 1 00000001 Test bench: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use STD.textio.all; use ieee.std_logic_textio.all; entity PROC_tb is end PROC_tb; architecture testbench of PROC_tb is component PROC is port ( CTEST : IN STD_LOGIC; EXTCLR : IN STD_LOGIC; TOUT : IN STD_LOGIC; MEXT : IN STD_LOGIC; Q41 : IN STD_LOGIC; Q31 : IN STD_LOGIC; Q21 : IN STD_LOGIC; Q11 : IN STD_LOGIC; TEST : IN STD_LOGIC; WRN : IN STD_LOGIC; RDN : IN STD_LOGIC; ALE : IN STD_LOGIC; CONTCLK_IN : IN STD_LOGIC; QCLK_IN : IN STD_LOGIC; CLEARN : IN STD_LOGIC; A_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0); AD : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); CM : IN STD_LOGIC_VECTOR(3 DOWNTO 1); DISCR_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0); FLASH : IN STD_LOGIC_VECTOR(7 DOWNTO 0); WRSPCL : OUT STD_LOGIC; N_DGATE_MUX : OUT STD_LOGIC; DGATE : OUT STD_LOGIC; DGATE_MUX : OUT STD_LOGIC; DMHZ : OUT STD_LOGIC; N_DGATE : OUT STD_LOGIC; AX1_MGATE : OUT STD_LOGIC; AX2_MGATE : OUT STD_LOGIC; AX3_MGATE : OUT STD_LOGIC; RDSPCL : OUT STD_LOGIC; CEPROM : OUT STD_LOGIC; CLROUT : OUT STD_LOGIC; MCLK : OUT STD_LOGIC; NOGO : OUT STD_LOGIC; TWH : OUT STD_LOGIC; Q32 : OUT STD_LOGIC; Q42 : OUT STD_LOGIC; CONTCLK_OUT : OUT STD_LOGIC; DSYN : OUT STD_LOGIC; INTP : OUT STD_LOGIC; QCLK_OUT : OUT STD_LOGIC; Q12 : OUT STD_LOGIC; Q22 : OUT STD_LOGIC; ABT : OUT STD_LOGIC; o_2PIWRN : OUT STD_LOGIC; A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); IOPORT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); o_2PI : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); RAMPE : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); STS_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 1) ); end component PROC; ----------------------------------------------------------------------------- -- Testbench Internal Signals ----------------------------------------------------------------------------- file file_VECTORS : text; file file_RESULTS : text; signal s_CTEST : STD_ULOGIC; signal s_EXTCLR : STD_ULOGIC; signal s_TOUT : STD_ULOGIC; signal s_MEXT : STD_ULOGIC; signal s_Q41 : STD_ULOGIC; signal s_Q31 : STD_ULOGIC; signal s_Q21 : STD_ULOGIC; signal s_Q11 : STD_ULOGIC; signal s_TEST : STD_ULOGIC; signal s_WRN : STD_ULOGIC; signal s_RDN : STD_ULOGIC; signal s_ALE : STD_ULOGIC; signal s_CONTCLK_IN : STD_ULOGIC; signal s_QCLK_IN : STD_ULOGIC; signal s_CLEARN : STD_ULOGIC; signal s_A_i : STD_ULOGIC_VECTOR(3 DOWNTO 0); signal s_AD : STD_LOGIC_VECTOR(15 DOWNTO 0); signal s_CM : STD_ULOGIC_VECTOR(3 DOWNTO 1); signal s_DISCR_IN : STD_ULOGIC_VECTOR(15 DOWNTO 0); signal s_FLASH : STD_ULOGIC_VECTOR(7 DOWNTO 0); signal s_WRSPCL : STD_LOGIC; signal s_N_DGATE_MUX : STD_LOGIC; signal s_DGATE : STD_LOGIC; signal s_DGATE_MUX : STD_LOGIC; signal s_DMHZ : STD_LOGIC; signal s_N_DGATE : STD_LOGIC; signal s_AX1_MGATE : STD_LOGIC; signal s_AX2_MGATE : STD_LOGIC; signal s_AX3_MGATE : STD_LOGIC; signal s_RDSPCL : STD_LOGIC; signal s_CEPROM : STD_LOGIC; signal s_CLROUT : STD_LOGIC; signal s_MCLK : STD_LOGIC; signal s_NOGO : STD_LOGIC; signal s_TWH : STD_LOGIC; signal s_Q32 : STD_LOGIC; signal s_Q42 : STD_LOGIC; signal s_CONTCLK_OUT : STD_LOGIC; signal s_DSYN : STD_LOGIC; signal s_INTP : STD_LOGIC; signal s_QCLK_OUT : STD_LOGIC; signal s_Q12 : STD_LOGIC; signal s_Q22 : STD_LOGIC; signal s_ABT : STD_LOGIC; signal s_o_2PIWRN : STD_LOGIC; signal s_A : STD_LOGIC_VECTOR(15 DOWNTO 0); signal s_IOPORT : STD_LOGIC_VECTOR(3 DOWNTO 0); signal s_o_2PI : STD_LOGIC_VECTOR(11 DOWNTO 0); signal s_RAMPE : STD_LOGIC_VECTOR(11 DOWNTO 0); signal s_STS_o : STD_LOGIC_VECTOR(3 DOWNTO 1); signal s_AD_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); signal s_E : STD_LOGIC; begin s_AD <= s_AD_temp when s_E = '1' else (others => 'Z'); ----------------------------------------------------------------------------- -- Instantiate and Map UUT ----------------------------------------------------------------------------- PROC_INST : PROC port map ( A => s_A, A_i => To_StdLogicVector(s_A_i), ABT => s_ABT, AD => s_AD, ALE => Std_Logic(s_ALE), AX1_MGATE => s_AX1_MGATE, AX2_MGATE => s_AX2_MGATE, AX3_MGATE => s_AX3_MGATE, CEPROM => s_CEPROM, CLEARN => Std_Logic(s_CLEARN), CLROUT => s_CLROUT, CM => To_StdLogicVector(s_CM), CONTCLK_IN => Std_Logic(s_CONTCLK_IN), CONTCLK_OUT => s_CONTCLK_OUT, CTEST => Std_Logic(s_CTEST), DGATE => s_DGATE, DGATE_MUX => s_DGATE_MUX, DISCR_IN => To_StdLogicVector(s_DISCR_IN), DMHZ => s_DMHZ, DSYN => s_DSYN, EXTCLR => Std_Logic(s_EXTCLR), FLASH => To_StdLogicVector(s_FLASH), INTP => s_INTP, IOPORT => s_IOPORT, MCLK => s_MCLK, MEXT => Std_Logic(s_MEXT), N_DGATE => s_N_DGATE, N_DGATE_MUX => s_N_DGATE_MUX, NOGO => s_NOGO, o_2PI => s_o_2PI, o_2PIWRN => s_o_2PIWRN, Q11 => Std_Logic(s_Q11), Q12 => s_Q12, Q21 => Std_Logic(s_Q21), Q22 => s_Q22, Q31 => Std_Logic(s_Q31), Q32 => s_Q32, Q41 => Std_Logic(s_Q41), Q42 => s_Q42, QCLK_IN => Std_Logic(s_QCLK_IN), QCLK_OUT => s_QCLK_OUT, RAMPE => s_RAMPE, RDN => Std_Logic(s_RDN), RDSPCL => s_RDSPCL, STS_o => s_STS_o, TEST => Std_Logic(s_TEST), TOUT => s_TOUT, TWH => s_TWH, WRN => Std_Logic(s_WRN), WRSPCL => s_WRSPCL ); --------------------------------------------------------------------------- -- This procedure reads the file input_vectors.txt which is located in the -- simulation project area. -- It will read the data in and send it to the ripple-adder component -- to perform the operations. The result is written to the -- output_results.txt file, located in the same directory. --------------------------------------------------------------------------- process variable v_ILINE : line; variable v_OLINE : line; variable v_SPACE : character; variable v_FLASH : std_ulogic_vector(7 downto 0) := x"00"; variable v_AD : std_logic_vector(15 downto 0) := x"0000"; variable v_DISCR_IN : std_ulogic_vector(15 downto 0) := x"0000"; variable v_CM : std_ulogic_vector(2 downto 0) := "000"; variable v_A_i : std_ulogic_vector(3 downto 0) := x"0"; variable v_CLEARN : std_ulogic := '0'; variable v_EXTCLR : std_ulogic := '0'; variable v_CTEST : std_ulogic := '0'; variable v_Q11 : std_ulogic := '0'; variable v_Q21 : std_ulogic := '0'; variable v_Q31 : std_ulogic := '0'; variable v_Q41 : std_ulogic := '0'; variable v_CONTCLK_IN : std_ulogic := '0'; variable v_ALE : std_ulogic := '0'; variable v_WRN : std_ulogic := '0'; variable v_RDN : std_ulogic := '0'; variable v_TOUT : std_ulogic := '0'; variable v_MEXT : std_ulogic := '0'; variable v_TEST : std_ulogic := '0'; variable v_Qclk_IN : std_ulogic := '0'; variable v_sim_time : time := 0 ns; variable v_sim_time_d : time := 0 ns ; variable v_E : std_ulogic; begin file_open(file_VECTORS, "input_vectors.txt", read_mode); while not endfile(file_VECTORS) loop readline(file_VECTORS, v_ILINE); -- read(v_ILINE, v_sim_time); -- read(v_ILINE, v_SPACE); -- read in the space character read(v_ILINE, v_CLEARN); read(v_ILINE, v_SPACE); read(v_ILINE, v_EXTCLR); read(v_ILINE, v_SPACE); read(v_ILINE, v_CTEST); read(v_ILINE, v_SPACE); read(v_ILINE, v_Q11); read(v_ILINE, v_SPACE); read(v_ILINE, v_Q21); read(v_ILINE, v_SPACE); read(v_ILINE, v_Q31); read(v_ILINE, v_SPACE); read(v_ILINE, v_Q41); read(v_ILINE, v_SPACE); read(v_ILINE, v_CONTCLK_IN); read(v_ILINE, v_SPACE); read(v_ILINE, v_ALE); read(v_ILINE, v_SPACE); read(v_ILINE, v_RDN); read(v_ILINE, v_SPACE); read(v_ILINE, v_WRN); read(v_ILINE, v_SPACE); read(v_ILINE, v_A_i); read(v_ILINE, v_SPACE); read(v_ILINE, v_CM); read(v_ILINE, v_SPACE); read(v_ILINE, v_DISCR_IN); read(v_ILINE, v_SPACE); read(v_ILINE, v_TOUT); read(v_ILINE, v_SPACE); read(v_ILINE, v_MEXT); read(v_ILINE, v_SPACE); read(v_ILINE, v_TEST); read(v_ILINE, v_SPACE); v_E := '0'; read(v_ILINE, v_AD); v_E := '1'; read(v_ILINE, v_SPACE); v_E := '0'; read(v_ILINE, v_Qclk_IN); read(v_ILINE, v_SPACE); read(v_ILINE, v_FLASH); s_E <= Std_Logic(v_E); s_A_i <= v_A_i; s_AD_temp <= v_AD; s_ALE <= v_ALE; s_CLEARN <= v_CLEARN; s_CM <= v_CM; s_CONTCLK_IN <= v_CONTCLK_IN; s_CTEST <= v_CTEST; s_DISCR_IN <= v_DISCR_IN; s_EXTCLR <= v_EXTCLR; s_FLASH <= v_FLASH; s_MEXT <= v_MEXT; s_Q11 <= v_Q11; s_Q21 <= v_Q21; s_Q31 <= v_Q31; s_Q41 <= v_Q41; s_QCLK_IN <= v_QCLK_IN; s_RDN <= v_RDN; s_TEST <= v_TEST; s_TOUT <= v_TOUT; s_WRN <= v_WRN; wait for 10 ns; end loop; file_close(file_VECTORS); wait; end process; end testbench;