Parameters
DATA_INTERFACE |
Parallel |
READ_BURST_MODE |
Incrementing |
READ_BURST_COUNT |
2 |
CLOCK_FREQUENCY |
1.0 |
CONFIGURATION_SCHEME |
Internal Configuration |
CONFIGURATION_MODE |
Single Compressed Image |
SECTOR_ID |
NA,1,2,3,4 |
SECTOR_ACCESS_MODE |
Hidden,Read and write,Read and write,Read and write,Read and write |
SECTOR_ADDRESS_MAPPING |
NA,0x00000 - 0x03fff,0x04000 - 0x187ff,0x18800 - 0x26fff,0x27000 - 0x49fff |
SECTOR_STORAGE_TYPE |
NA,UFM,UFM,UFM,CFM |
initFlashContent |
false |
useNonDefaultInitFile |
false |
initializationFileName |
altera_onchip_flash.hex |
initializationFileNameForSim |
altera_onchip_flash.dat |
autoInitializationFileName |
int_flash_ctl_10M04_onchip_flash_0 |
INIT_FILENAME |
|
INIT_FILENAME_SIM |
|
DEVICE_FAMILY |
MAX10FPGA |
PART_NAME |
10M04SAU169I7G |
AUTO_CLOCK_RATE |
0 |
DEVICE_ID |
04 |
SECTOR1_START_ADDR |
0 |
SECTOR1_END_ADDR |
4095 |
SECTOR2_START_ADDR |
4096 |
SECTOR2_END_ADDR |
25087 |
SECTOR3_START_ADDR |
25088 |
SECTOR3_END_ADDR |
39935 |
SECTOR4_START_ADDR |
39936 |
SECTOR4_END_ADDR |
75775 |
SECTOR5_START_ADDR |
0 |
SECTOR5_END_ADDR |
0 |
MIN_VALID_ADDR |
0 |
MAX_VALID_ADDR |
75775 |
MIN_UFM_VALID_ADDR |
0 |
MAX_UFM_VALID_ADDR |
39935 |
SECTOR1_MAP |
2 |
SECTOR2_MAP |
3 |
SECTOR3_MAP |
4 |
SECTOR4_MAP |
5 |
SECTOR5_MAP |
0 |
ADDR_RANGE1_END_ADDR |
75775 |
ADDR_RANGE2_END_ADDR |
75775 |
ADDR_RANGE1_OFFSET |
4608 |
ADDR_RANGE2_OFFSET |
0 |
ADDR_RANGE3_OFFSET |
0 |
AVMM_DATA_ADDR_WIDTH |
17 |
AVMM_DATA_DATA_WIDTH |
32 |
AVMM_DATA_BURSTCOUNT_WIDTH |
2 |
SECTOR_READ_PROTECTION_MODE |
16 |
FLASH_SEQ_READ_DATA_COUNT |
2 |
FLASH_ADDR_ALIGNMENT_BITS |
1 |
FLASH_READ_CYCLE_MAX_INDEX |
4 |
FLASH_RESET_CYCLE_MAX_INDEX |
1 |
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX |
1 |
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX |
350000 |
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX |
305 |
PARALLEL_MODE |
true |
READ_AND_WRITE_MODE |
true |
WRAPPING_BURST_MODE |
false |
IS_DUAL_BOOT |
False |
IS_ERAM_SKIP |
True |
IS_COMPRESSED_IMAGE |
True |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|