## Generated SDC file "Mk1_Safety_Unit_CPLD.out.sdc" ## Copyright (C) 2020 Intel Corporation. All rights reserved. ## Your use of Intel Corporation's design tools, logic functions ## and other software and tools, and any partner logic ## functions, and any output files from any of the foregoing ## (including device programming or simulation files), and any ## associated documentation or information are expressly subject ## to the terms and conditions of the Intel Program License ## Subscription Agreement, the Intel Quartus Prime License Agreement, ## the Intel FPGA IP License Agreement, or other applicable license ## agreement, including, without limitation, that your use is for ## the sole purpose of programming logic devices manufactured by ## Intel and sold by Intel or its authorized distributors. Please ## refer to the applicable agreement for further details, at ## https://fpgasoftware.intel.com/eula. ## VENDOR "Altera" ## PROGRAM "Quartus Prime" ## VERSION "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" ## DATE "Fri Dec 11 13:56:09 2020" ## ## DEVICE "EPM570T100I5" ## #************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {clock_in_3p6864mhz} -period 271.000 -waveform { 0.000 135.000 } [get_ports {clock_in_3p6864mhz}] create_clock -name {cpld_master_clock} -period 542.000 -waveform { 0.000 271.000 } [get_nets {cpld_master_clock}] #************************************************************** # Create Generated Clock #************************************************************** create_generated_clock -name {uart_rx_clock} -source [get_nets {cpld_master_clock}] -divide_by 2 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV2|clk_out}] create_generated_clock -name {uart_tx_clock} -source [get_nets {cpld_master_clock}] -divide_by 32 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV3|clk_out}] create_generated_clock -name {millisec_clock} -source [get_nets {cpld_master_clock}] -divide_by 1920 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV4|clk_out}] create_generated_clock -name {heartbeat_clock} -source [get_nets {cpld_master_clock}] -divide_by 3840 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV5|clk_out}] #************************************************************** # Set Clock Latency #************************************************************** #************************************************************** # Set Clock Uncertainty #************************************************************** #************************************************************** # Set Input Delay #************************************************************** #************************************************************** # Set Output Delay #************************************************************** #************************************************************** # Set Clock Groups #************************************************************** #************************************************************** # Set False Path #************************************************************** #************************************************************** # Set Multicycle Path #************************************************************** #************************************************************** # Set Maximum Delay #************************************************************** #************************************************************** # Set Minimum Delay #************************************************************** #************************************************************** # Set Input Transition #**************************************************************