module backdata_deal(
CLOCK,
RESET_X,

READ_RAM_ADDR,
READ_RAM_DATA,
READ_RAM_ENABLE,

FPGA_REG_ADDR,
FPGA_REG_DATA,
FPGA_REG_SET_EN,

set_fpgareg,
send_inicode,
save_code2flm,
program_flm,

OUT_ENABLE,
READ_REG_ADDR,
READ_REG_DATA 

);

input CLOCK;
input RESET_X;
output [9:0]READ_RAM_ADDR;
input [15:0]READ_RAM_DATA;
output READ_RAM_ENABLE;
output [3:0]FPGA_REG_ADDR;
output [31:0]FPGA_REG_DATA;
output FPGA_REG_SET_EN;
input set_fpgareg;
input send_inicode;
input save_code2flm;
input program_flm;
output OUT_ENABLE;
input [3:0]READ_REG_ADDR;
output [31:0]READ_REG_DATA;
reg READ_RAM_ENABLE;
reg [9:0]READ_RAM_ADDR;
reg [3:0]FPGA_REG_ADDR;
reg [31:0]FPGA_REG_DATA;
reg FPGA_REG_SET_EN;
reg [5:0]clkcnt; //50 fen pin
reg [15:0]data1;
reg [15:0]data2;
reg [15:0]data3;
//reg [15:0]data4;
// FF delay
parameter P_DLY = 1;
///////////////////////////////////
reg_config ureg_config(
.CLOCK(CLOCK), 
.RESET_X(RESET_X),
.SET_REG_ADDR(FPGA_REG_ADDR),
.SET_REG_DATA(FPGA_REG_DATA),
.SET_REG_EN(FPGA_REG_SET_EN),

.OUT_ENABLE(OUT_ENABLE),
.READ_REG_ADDR(READ_REG_ADDR),
.READ_REG_DATA(READ_REG_DATA) 
);

always@(negedge CLOCK or negedge RESET_X)
begin
if(!RESET_X)
begin
READ_RAM_ENABLE <= #P_DLY 1'b0;
end
else if(set_fpgareg == 1'b1 || send_inicode == 1'b1 || save_code2flm == 1'b1)
READ_RAM_ENABLE <= #P_DLY 1'b1;
else 
READ_RAM_ENABLE <= #P_DLY 1'b0;
end
//clkcnt
always@(negedge CLOCK or negedge RESET_X)
begin
if(!RESET_X)
begin
clkcnt <= #P_DLY 6'd0;
end
else if(READ_RAM_ENABLE == 1'b1) begin
if(clkcnt == 6'd40)
clkcnt <= #P_DLY clkcnt + 6'd1;
else
clkcnt <= #P_DLY clkcnt;
end
else
clkcnt <= #P_DLY 1'b0;

end
//ram address
always@(negedge CLOCK or negedge RESET_X)
begin
if(!RESET_X)
begin
READ_RAM_ADDR <= #P_DLY 10'b0;
end
else if(READ_RAM_ADDR == 1'b1) begin
if(clkcnt == 6'd10)
READ_RAM_ADDR <= #P_DLY 10'd1;
if(clkcnt == 6'd20)
READ_RAM_ADDR <= #P_DLY 10'd2;
if(clkcnt == 6'd30)
READ_RAM_ADDR <= #P_DLY 10'd3;
else
READ_RAM_ADDR <= #P_DLY READ_RAM_ADDR;
end 
else 
READ_RAM_ADDR <= #P_DLY 6'd0;
end
//ram data
always@(negedge CLOCK or negedge RESET_X)
begin
if(!RESET_X)
begin
data1 <= 16'd0;
data2 <= 16'd0;
data3 <= 16'd0;
end
else if(READ_RAM_ADDR == 1'b1) begin
if(clkcnt == 6'd6)
data1 <= #P_DLY READ_RAM_DATA;
if(clkcnt == 6'd16)
data2 <= #P_DLY READ_RAM_DATA;
if(clkcnt == 6'd26)
data3 <= #P_DLY READ_RAM_DATA;
else begin
data1 <= #P_DLY data1;
data2 <= #P_DLY data2;
data3 <= #P_DLY data3;
end
end 
end
//set fpga reg addr
always@(negedge CLOCK or negedge RESET_X)
begin
if(!RESET_X)
begin
FPGA_REG_ADDR <= #P_DLY 4'h0;
end
else if(set_fpgareg == 1'b1 && clkcnt == 6'd40) begin
FPGA_REG_ADDR <= #P_DLY data1[3:0];
end
else
FPGA_REG_ADDR <= #P_DLY 4'h0; 
end
//set fpga reg data
always@(negedge CLOCK or negedge RESET_X)
begin
if(!RESET_X)
begin
FPGA_REG_DATA <= #P_DLY 32'd0;
end
else if(set_fpgareg == 1'b1 && clkcnt == 6'd40) begin
FPGA_REG_DATA <= #P_DLY {data2,data3};
end
else
FPGA_REG_DATA <= #P_DLY 32'h0; 
end
//set fpga reg data
always@(negedge CLOCK or negedge RESET_X)
begin
if(!RESET_X)
begin
FPGA_REG_SET_EN <= #P_DLY 1'b0;
end
else if(set_fpgareg == 1'b1 && clkcnt == 6'd40) begin
FPGA_REG_SET_EN <= #P_DLY 1'b1;
end
else
FPGA_REG_SET_EN <= #P_DLY 1'b0; 
end
endmodule