#clock switchover SDC

#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3

#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {MCLK40M} -period 25.000 -waveform { 0.000 12.500 } [get_ports {MCLK40M}]
create_clock -name {clk_in} -period 25.000 -waveform { 0.000 12.500 } [get_ports {clk_in}]


#**************************************************************
# Create Generated Clock
#**************************************************************

#####EXTERNAL CLOCKS
create_generated_clock -name {clock_32_ext} -source [get_ports {clk_in}] -divide_by 10 -multiply_by 8 -duty_cycle 50.00 { pll_inst|asec_pll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk } -add

#DAC_SCLK
create_generated_clock -add -name dac_sclk_ext -master_clock clock_32_ext -source [get_pins {pll_inst|asec_pll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -divide_by 1 -multiply_by 1 -duty_cycle 50/1 [get_ports {dac_ld_sclk}]

#####INTERNAL CLOCKS
create_generated_clock -name {clock_32_int} -source [get_ports {MCLK40M}] -divide_by 10 -multiply_by 8 -duty_cycle 50.00 { pll_inst|asec_pll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk } -add

#DAC_SCLK
create_generated_clock -add -name dac_sclk_int -master_clock clock_32_int -source [get_pins {pll_inst|asec_pll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -divide_by 1 -multiply_by 1 -duty_cycle 50/1 [get_ports {dac_ld_sclk}]


#**************************************************************
# Set Clock Uncertainty
#**************************************************************

derive_clock_uncertainty

#**************************************************************
# Set Clock Groups
#**************************************************************

set_clock_groups -exclusive -group [get_clocks {clk_in clk_out clock_32_ext dac_sclk_ext}] -group [get_clocks {MCLK40M dac_sclk_int}]

#**************************************************************
# Set Input Delay
#**************************************************************

#**************************************************************
# Set Output Delay
#**************************************************************

#DAC CS
set_output_delay -clock { dac__sclk_ext } -add_delay 10.000 [get_ports {dac_cs}]
set_output_delay -clock { dac_sclk_ext } -clock_fall -add_delay 0  [get_ports {dac_cs}]

set_output_delay -clock { dac_sclk_int } -add_delay 10.000 [get_ports {dac_cs}]
set_output_delay -clock { dac_ld_sclk_int } -clock_fall -add_delay 0  [get_ports {dac_cs}]

#DAC DIN
set_output_delay -clock { dac_sclk_ext } -add_delay 5 [get_ports {dac_din}] 
#max and min are the same at 5 V
set_output_delay -clock { dac_sclk_int } -add_delay 5 [get_ports {dac_din}] 
#max and min are the same at 5 V


#**************************************************************
# Set False Path
#**************************************************************