Started by upstream project "MCD4_UVM_Simulation" build number 31 originally caused by: Started by user Greg Beaton (Greg.Beaton) Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on tao-2 in workspace /tmp/workspace/MCD4_UVM_Simulation/default/tao-2 [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... The recommended git tool is: NONE using credential efedb983-6b76-42ee-ad7f-ed211b08657a Cloning the remote Git repository Cloning repository git@gitlab.asatnet.net:MCD4/PL/FPGA.git > git init /tmp/workspace/MCD4_UVM_Simulation/default/tao-2 # timeout=10 Fetching upstream changes from git@gitlab.asatnet.net:MCD4/PL/FPGA.git > git --version # timeout=10 > git --version # 'git version 2.30.1' using GIT_SSH to set credentials git readonly user for Jenkins > git fetch --tags --force --progress -- git@gitlab.asatnet.net:MCD4/PL/FPGA.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@gitlab.asatnet.net:MCD4/PL/FPGA.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch Checking out Revision d91fb1c69a1fcedfc1e2822d0f7f41491b51e929 (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f d91fb1c69a1fcedfc1e2822d0f7f41491b51e929 # timeout=10 Commit message: "remove stale ip that is no longer used." > git rev-list --no-walk d91fb1c69a1fcedfc1e2822d0f7f41491b51e929 # timeout=10 No GitLab connection configured [tao-2] $ /bin/sh -xe /tmp/jenkins15459391867327168052.sh + echo stage 1 stage 1 + cd /tmp/workspace/MCD4_UVM_Simulation/default/tao-2 + scripts/create_target_project.sh mcd4 Warning (292006): Can't contact license server "1717@192.168.22.11" -- this server will be ignored. Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 21.2.0 Build 72 06/14/2021 SC Pro Edition Info: Copyright (C) 2021 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Jul 6 16:25:01 2022 Info: System process ID: 10719 Info: Command: quartus_sh -t /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/scripts/create_target_project.tcl mcd4 Info: Quartus(args): mcd4 The default device is the eval board device AGFB014R24A2E2VR0 If you wish to use another device, add it's option to the argument list Working in Vendor Project Directory = /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Adding project settings... Info (125061): Changed top-level design entity name to "mcd4_top" Adding project sources... Entering add_sources... ../scripts/proj_src.tcl .. Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/common/scripts/proj_src.tcl ../../modules/common ...........Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/emif_core_SIM_x3/scripts/proj_src.tcl ../../modules/emif_core_SIM_x3 Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/emif_core_SIM_x3/../common/scripts/proj_src.tcl ../../modules/emif_core_SIM_x3/../common ......................Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../common ...........Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../fir_decimator/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../fir_decimator Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../fir_decimator/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../fir_decimator/../common .....................Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../demux/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../demux Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../demux/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../demux/../common ...........Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../demux/../demux_64k/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../demux/../demux_64k ..................................................................................................................................................................................................................................Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../demux/../demux_4k/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../demux/../demux_4k ..............................................................................................................................................................................Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../demux_emif/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../demux_emif Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../demux_emif/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../demux_emif/../common ...........Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../demux_emif/../mem_conn/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../demux_emif/../mem_conn .Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture/../common .............................................................Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/../common ...........Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/../rate_converter/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/../rate_converter Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/../rate_converter/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/../rate_converter/../common ..........................................................................Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/../tsync/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/../tsync Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/../tsync/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/../tsync/../common ....................................................................................................................................Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../demod/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../demod Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../demod/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../demod/../common .......................................................................................................................................................................................................................................Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../ncr_time_table/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../ncr_time_table Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../ncr_time_table/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../ncr_time_table/../common ...............Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../interrupt_ctrl/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../interrupt_ctrl Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../interrupt_ctrl/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../interrupt_ctrl/../common ................Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../register_ctrl/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../register_ctrl Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../register_ctrl/../project_cfg/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../register_ctrl/../project_cfg ..Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../register_ctrl/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../register_ctrl/../common ............Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../vector_capture/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../vector_capture Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../vector_capture/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../vector_capture/../common ................Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../vector_player/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../vector_player Adding submodules... /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj Entering add_sources... ../../modules/fpga1_fabric_wrapper/../vector_player/../common/scripts/proj_src.tcl ../../modules/fpga1_fabric_wrapper/../vector_player/../common ....................................Done. Info (23030): Evaluation of Tcl script /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/scripts/create_target_project.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 1 warning Info: Peak virtual memory: 1023 megabytes Info: Processing ended: Wed Jul 6 16:25:01 2022 Info: Elapsed time: 00:00:00 Info: System process ID: 10719 [tao-2] $ /bin/sh -xe /tmp/jenkins12720077413586409188.sh + echo stage 2 stage 2 + cd /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj + quartus_ipgenerate --generate_project_ip_files --synthesis=verilog --simulation=verilog --clear_ip_generation_dirs mcd4 --rev top Warning (292006): Can't contact license server "1717@192.168.22.11" -- this server will be ignored. Info: ******************************************************************* Info: Running Quartus Prime IP Generation Tool Info: Version 21.2.0 Build 72 06/14/2021 SC Pro Edition Info: Copyright (C) 2021 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Jul 6 16:25:03 2022 Info: System process ID: 10745 Info: Command: quartus_ipgenerate --generate_project_ip_files --synthesis=verilog --simulation=verilog --clear_ip_generation_dirs mcd4 --rev=top Info: Found 61 IP file(s) in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect.qsys was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7.ip was found in the project. Info: IP file /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in.ip was found in the project. Info: Started running qsys-validate on Platform Designer system ../../modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim.qsys Info: emif_x3rdimm16GB_x8dq_sim: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux/cores/demux_adapter.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/../demux/cores/demux_adapter.qsys Info: demux_adapter: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux/cores/demux_adapter.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture/cores/avst_capture_fifo.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture/cores/avst_capture_fifo.qsys Info: avst_capture_fifo: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture/cores/avst_capture_fifo.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_ac_emif_afifo_98_pl.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_ac_emif_afifo_98_pl.qsys Info: amr_ac_emif_afifo_98_pl: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_ac_emif_afifo_98_pl.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_ac_emif_afifo_pl.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_ac_emif_afifo_pl.qsys Info: amr_ac_emif_afifo_pl: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_ac_emif_afifo_pl.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_d_emif_afifo_pl.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_d_emif_afifo_pl.qsys Info: amr_d_emif_afifo_pl: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_d_emif_afifo_pl.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amw_acd_emif_afifo_610_pl.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amw_acd_emif_afifo_610_pl.qsys Info: amw_acd_emif_afifo_610_pl: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amw_acd_emif_afifo_610_pl.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amw_acd_emif_afifo_pl.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amw_acd_emif_afifo_pl.qsys Info: amw_acd_emif_afifo_pl: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amw_acd_emif_afifo_pl.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/cores/rct_adapter.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/cores/rct_adapter.qsys Info: rct_adapter: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/cores/rct_adapter.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../interrupt_ctrl/cores/interrupt_avst_sc_fifo.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/../interrupt_ctrl/cores/interrupt_avst_sc_fifo.qsys Info: interrupt_avst_sc_fifo: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../interrupt_ctrl/cores/interrupt_avst_sc_fifo.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../vector_capture/cores/avst_capture_fifo.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/../vector_capture/cores/avst_capture_fifo.qsys Info: avst_capture_fifo: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../vector_capture/cores/avst_capture_fifo.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../vector_player/cores/storage.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/../vector_player/cores/storage.qsys Info: storage: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/../vector_player/cores/storage.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux.qsys Info: fpga1_pcie_avst_snk_mux: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux.qsys Info: fpga1_pcie_avst_src_demux: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux.qsys Info: Started running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect.qsys Info: Performing Platform Designer system validation using the command line: /INTELFPGA_PRO_21.2/quartus/../qsys/bin/qsys-validate ../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect.qsys Info: fpga1_pcie_avmm_interconnect: All Generic Component instances match their respective ip files. Info: Finished running qsys-validate on Platform Designer system ../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect.qsys Info: Both synthesis and simulation files will be generated. Info: Performing IP Generation using the command line: /INTELFPGA_PRO_21.2/quartus/sopc_builder/bin/qsys-generate --family=Agilex --part=AGFB014R24A2E2VR0 --block-symbol-file --quartus-project=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj/mcd4 --rev=top --top-level-generation=true {--bypass-quartus-project } --clear-output-directory --synthesis=verilog --simulation=verilog --simulator= --parallel --batch=../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in.ip --batch=../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7.ip --batch=../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6.ip --batch=../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5.ip --batch=../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4.ip --batch=../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3.ip --batch=../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2.ip --batch=../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1.ip --batch=../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0.ip --batch=../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in.ip --batch=../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0.ip --batch=../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0.ip --batch=../../modules/fpga1_fabric_wrapper/../vector_player/cores/tb_ram.ip --batch=../../modules/fpga1_fabric_wrapper/../vector_player/cores/tb_fifo.ip --batch=../../modules/fpga1_fabric_wrapper/../vector_player/cores/ip/storage/storage_dcfifo.ip --batch=../../modules/fpga1_fabric_wrapper/../vector_player/cores/ip/storage/storage_dcdpram.ip --batch=../../modules/fpga1_fabric_wrapper/../vector_capture/cores/tb_256_256_dc_fifo.ip --batch=../../modules/fpga1_fabric_wrapper/../vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo.ip --batch=../../modules/fpga1_fabric_wrapper/../interrupt_ctrl/cores/tb_32_256_sc_fifo.ip --batch=../../modules/fpga1_fabric_wrapper/../interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo.ip --batch=../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow.ip --batch=../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser.ip --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/clock_switch.ip --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/dcfifo_desc.ip --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/dcfifo_512_256.ip --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/dcfifo_512_128.ip --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/dcfifo_128_512.ip --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0.ip --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0.ip --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0.ip --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0.ip --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0.ip --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture/cores/tb_256_256_dc_fifo.ip --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo.ip --batch=../../modules/fpga1_fabric_wrapper/../demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow.ip --batch=../../modules/fpga1_fabric_wrapper/../demux/cores/ip/demux_adapter/demux_avst_clk_crosser.ip --batch=../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2.ip --batch=../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1.ip --batch=../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0.ip --batch=../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst.ip --batch=../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3.ip --batch=../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2.ip --batch=../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1.ip --batch=../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0.ip --batch=../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1.ip --batch=../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2.ip --batch=../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect.qsys --batch=../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux.qsys --batch=../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux.qsys --batch=../../modules/fpga1_fabric_wrapper/../vector_player/cores/storage.qsys --batch=../../modules/fpga1_fabric_wrapper/../vector_capture/cores/avst_capture_fifo.qsys --batch=../../modules/fpga1_fabric_wrapper/../interrupt_ctrl/cores/interrupt_avst_sc_fifo.qsys --batch=../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/cores/rct_adapter.qsys --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amw_acd_emif_afifo_pl.qsys --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amw_acd_emif_afifo_610_pl.qsys --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_d_emif_afifo_pl.qsys --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_ac_emif_afifo_pl.qsys --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_ac_emif_afifo_98_pl.qsys --batch=../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture/cores/avst_capture_fifo.qsys --batch=../../modules/fpga1_fabric_wrapper/../demux/cores/demux_adapter.qsys ../../modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim.qsys Info: Batch generation will generate the listed files in this order: /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim.qsys, ../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect.qsys, ../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux.qsys, ../../modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux.qsys, ../../modules/fpga1_fabric_wrapper/../vector_player/cores/storage.qsys, ../../modules/fpga1_fabric_wrapper/../vector_capture/cores/avst_capture_fifo.qsys, ../../modules/fpga1_fabric_wrapper/../interrupt_ctrl/cores/interrupt_avst_sc_fifo.qsys, ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/cores/rct_adapter.qsys, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amw_acd_emif_afifo_pl.qsys, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amw_acd_emif_afifo_610_pl.qsys, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_d_emif_afifo_pl.qsys, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_ac_emif_afifo_pl.qsys, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/amr_ac_emif_afifo_98_pl.qsys, ../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture/cores/avst_capture_fifo.qsys, ../../modules/fpga1_fabric_wrapper/../demux/cores/demux_adapter.qsys, ../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in.ip, ../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7.ip, ../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6.ip, ../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5.ip, ../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4.ip, ../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3.ip, ../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2.ip, ../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1.ip, ../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0.ip, ../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in.ip, ../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0.ip, ../../modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0.ip, ../../modules/fpga1_fabric_wrapper/../vector_player/cores/tb_ram.ip, ../../modules/fpga1_fabric_wrapper/../vector_player/cores/tb_fifo.ip, ../../modules/fpga1_fabric_wrapper/../vector_player/cores/ip/storage/storage_dcfifo.ip, ../../modules/fpga1_fabric_wrapper/../vector_player/cores/ip/storage/storage_dcdpram.ip, ../../modules/fpga1_fabric_wrapper/../vector_capture/cores/tb_256_256_dc_fifo.ip, ../../modules/fpga1_fabric_wrapper/../vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo.ip, ../../modules/fpga1_fabric_wrapper/../interrupt_ctrl/cores/tb_32_256_sc_fifo.ip, ../../modules/fpga1_fabric_wrapper/../interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo.ip, ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow.ip, ../../modules/fpga1_fabric_wrapper/../rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser.ip, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/clock_switch.ip, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/dcfifo_desc.ip, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/dcfifo_512_256.ip, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/dcfifo_512_128.ip, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/dcfifo_128_512.ip, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0.ip, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0.ip, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0.ip, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0.ip, ../../modules/fpga1_fabric_wrapper/../demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0.ip, ../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture/cores/tb_256_256_dc_fifo.ip, ../../modules/fpga1_fabric_wrapper/../demux_emif/../vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo.ip, ../../modules/fpga1_fabric_wrapper/../demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow.ip, ../../modules/fpga1_fabric_wrapper/../demux/cores/ip/demux_adapter/demux_avst_clk_crosser.ip, ../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2.ip, ../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1.ip, ../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0.ip, ../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst.ip, ../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3.ip, ../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2.ip, ../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1.ip, ../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0.ip, ../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1.ip, ../../modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2.ip Info: Parallel IP Generation is enabled. Info: Platform Designer will attempt to use 6 processors for parallel IP generation based on available number of processors and the total number of IP to be generated. Info: Starting: Platform Designer system generation Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/rct_avst_clk_crosser_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser --family=Agilex --part=AGFB014R24A2E2VR0 Info: rct_avst_clk_crosser: "Transforming system: rct_avst_clk_crosser" Info: rct_avst_clk_crosser: "Naming system components in system: rct_avst_clk_crosser" Info: rct_avst_clk_crosser: "Processing generation queue" Info: rct_avst_clk_crosser: "Generating: rct_avst_clk_crosser" Info: rct_avst_clk_crosser: "Generating: rct_avst_clk_crosser_hs_clk_xer_1931_7vhe7xa" Info: rct_avst_clk_crosser: Done "rct_avst_clk_crosser" with 2 modules, 6 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avst_clk_crosser --family=Agilex --part=AGFB014R24A2E2VR0 Info: rct_avst_clk_crosser: "Transforming system: rct_avst_clk_crosser" Info: rct_avst_clk_crosser: "Naming system components in system: rct_avst_clk_crosser" Info: rct_avst_clk_crosser: "Processing generation queue" Info: rct_avst_clk_crosser: "Generating: rct_avst_clk_crosser" Info: rct_avst_clk_crosser: "Generating: rct_avst_clk_crosser_hs_clk_xer_1931_7vhe7xa" Info: rct_avst_clk_crosser: Done "rct_avst_clk_crosser" with 2 modules, 6 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/amr_ac_emif_afifo_pl_dc_fifo_0_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: amr_ac_emif_afifo_pl_dc_fifo_0: "Transforming system: amr_ac_emif_afifo_pl_dc_fifo_0" Info: amr_ac_emif_afifo_pl_dc_fifo_0: "Naming system components in system: amr_ac_emif_afifo_pl_dc_fifo_0" Info: amr_ac_emif_afifo_pl_dc_fifo_0: "Processing generation queue" Info: amr_ac_emif_afifo_pl_dc_fifo_0: "Generating: amr_ac_emif_afifo_pl_dc_fifo_0" Info: amr_ac_emif_afifo_pl_dc_fifo_0: "Generating: amr_ac_emif_afifo_pl_dc_fifo_0_st_dc_fifo_1940_r4vdppy" Info: amr_ac_emif_afifo_pl_dc_fifo_0: Done "amr_ac_emif_afifo_pl_dc_fifo_0" with 2 modules, 4 files Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/vcsmx_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ --use-relative-paths=true Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: amr_ac_emif_afifo_pl_dc_fifo_0: "Transforming system: amr_ac_emif_afifo_pl_dc_fifo_0" Info: amr_ac_emif_afifo_pl_dc_fifo_0: "Naming system components in system: amr_ac_emif_afifo_pl_dc_fifo_0" Info: amr_ac_emif_afifo_pl_dc_fifo_0: "Processing generation queue" Info: amr_ac_emif_afifo_pl_dc_fifo_0: "Generating: amr_ac_emif_afifo_pl_dc_fifo_0" Info: amr_ac_emif_afifo_pl_dc_fifo_0: "Generating: amr_ac_emif_afifo_pl_dc_fifo_0_st_dc_fifo_1940_r4vdppy" Info: amr_ac_emif_afifo_pl_dc_fifo_0: Done "amr_ac_emif_afifo_pl_dc_fifo_0" with 2 modules, 5 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/local_reset_combiner_x3_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3 --family=Agilex --part=AGFB014R24A2E2VR0 Info: local_reset_combiner_x3: "Transforming system: local_reset_combiner_x3" Info: local_reset_combiner_x3: "Naming system components in system: local_reset_combiner_x3" Info: local_reset_combiner_x3: "Processing generation queue" Info: local_reset_combiner_x3: "Generating: local_reset_combiner_x3" Info: local_reset_combiner_x3: "Generating: altera_emif_local_reset_combiner" Info: local_reset_combiner_x3: Done "local_reset_combiner_x3" with 2 modules, 3 files Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ directory: Info: common/vcs_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ --use-relative-paths=true Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/local_reset_combiner_x3 --family=Agilex --part=AGFB014R24A2E2VR0 Info: local_reset_combiner_x3: "Transforming system: local_reset_combiner_x3" Info: local_reset_combiner_x3: "Naming system components in system: local_reset_combiner_x3" Info: local_reset_combiner_x3: "Processing generation queue" Info: local_reset_combiner_x3: "Generating: local_reset_combiner_x3" Info: local_reset_combiner_x3: "Generating: altera_emif_local_reset_combiner" Info: local_reset_combiner_x3: Done "local_reset_combiner_x3" with 2 modules, 4 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/avst_sc_fifo_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: avst_sc_fifo: "Transforming system: avst_sc_fifo" Info: avst_sc_fifo: "Naming system components in system: avst_sc_fifo" Info: avst_sc_fifo: "Processing generation queue" Info: avst_sc_fifo: "Generating: avst_sc_fifo" Info: avst_sc_fifo: "Generating: avst_sc_fifo_altera_avalon_sc_fifo_1930_yl7a2ny" Info: avst_sc_fifo: Done "avst_sc_fifo" with 2 modules, 2 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/ip/interrupt_avst_sc_fifo/avst_sc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: avst_sc_fifo: "Transforming system: avst_sc_fifo" Info: avst_sc_fifo: "Naming system components in system: avst_sc_fifo" Info: avst_sc_fifo: "Processing generation queue" Info: avst_sc_fifo: "Generating: avst_sc_fifo" Info: avst_sc_fifo: "Generating: avst_sc_fifo_altera_avalon_sc_fifo_1930_yl7a2ny" Info: avst_sc_fifo: Done "avst_sc_fifo" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: fpga1_pcie_avst_src_demux: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/fpga1_pcie_avst_src_demux.qsys Info: Reading input file Info: Adding demultiplexer_0 [altera_generic_component 1.0] Info: Parameterizing module demultiplexer_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: fpga1_pcie_avst_src_demux: "Transforming system: fpga1_pcie_avst_src_demux" Info: fpga1_pcie_avst_src_demux: "Naming system components in system: fpga1_pcie_avst_src_demux" Info: fpga1_pcie_avst_src_demux: "Processing generation queue" Info: fpga1_pcie_avst_src_demux: "Generating: fpga1_pcie_avst_src_demux" Info: fpga1_pcie_avst_src_demux: "Generating: fpga1_pcie_avst_src_demux_demultiplexer_0" Info: fpga1_pcie_avst_src_demux: Done "fpga1_pcie_avst_src_demux" with 2 modules, 1 files Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ --use-relative-paths=true Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/fpga1_pcie_avst_src_demux.qsys Info: Reading input file Info: Adding demultiplexer_0 [altera_generic_component 1.0] Info: Parameterizing module demultiplexer_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_src_demux --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/fpga1_pcie_avst_src_demux.qsys Info: Reading input file Info: Adding demultiplexer_0 [altera_generic_component 1.0] Info: Parameterizing module demultiplexer_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: fpga1_pcie_avst_src_demux: "Transforming system: fpga1_pcie_avst_src_demux" Info: fpga1_pcie_avst_src_demux: "Naming system components in system: fpga1_pcie_avst_src_demux" Info: fpga1_pcie_avst_src_demux: "Processing generation queue" Info: fpga1_pcie_avst_src_demux: "Generating: fpga1_pcie_avst_src_demux" Info: fpga1_pcie_avst_src_demux: "Generating: fpga1_pcie_avst_src_demux_demultiplexer_0" Info: fpga1_pcie_avst_src_demux: Done "fpga1_pcie_avst_src_demux" with 2 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/fpga1_pcie_avmm_interconnect_clock_in_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_clock_in: "Transforming system: fpga1_pcie_avmm_interconnect_clock_in" Info: fpga1_pcie_avmm_interconnect_clock_in: "Naming system components in system: fpga1_pcie_avmm_interconnect_clock_in" Info: fpga1_pcie_avmm_interconnect_clock_in: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_clock_in: "Generating: fpga1_pcie_avmm_interconnect_clock_in" Info: fpga1_pcie_avmm_interconnect_clock_in: Done "fpga1_pcie_avmm_interconnect_clock_in" with 1 modules, 1 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_clock_in --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_clock_in: "Transforming system: fpga1_pcie_avmm_interconnect_clock_in" Info: fpga1_pcie_avmm_interconnect_clock_in: "Naming system components in system: fpga1_pcie_avmm_interconnect_clock_in" Info: fpga1_pcie_avmm_interconnect_clock_in: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_clock_in: "Generating: fpga1_pcie_avmm_interconnect_clock_in" Info: fpga1_pcie_avmm_interconnect_clock_in: Done "fpga1_pcie_avmm_interconnect_clock_in" with 1 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/fpga1_pcie_avmm_interconnect_mm_bridge_3_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_3: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_3" Info: fpga1_pcie_avmm_interconnect_mm_bridge_3: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_3" Info: fpga1_pcie_avmm_interconnect_mm_bridge_3: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_3: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_3" Info: fpga1_pcie_avmm_interconnect_mm_bridge_3: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_3_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_3: Done "fpga1_pcie_avmm_interconnect_mm_bridge_3" with 2 modules, 2 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_3 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_3: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_3" Info: fpga1_pcie_avmm_interconnect_mm_bridge_3: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_3" Info: fpga1_pcie_avmm_interconnect_mm_bridge_3: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_3: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_3" Info: fpga1_pcie_avmm_interconnect_mm_bridge_3: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_3_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_3: Done "fpga1_pcie_avmm_interconnect_mm_bridge_3" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/fpga1_pcie_avmm_interconnect_mm_bridge_7_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_7: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_7" Info: fpga1_pcie_avmm_interconnect_mm_bridge_7: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_7" Info: fpga1_pcie_avmm_interconnect_mm_bridge_7: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_7: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_7" Info: fpga1_pcie_avmm_interconnect_mm_bridge_7: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_7_altera_avalon_mm_bridge_2001_k2bg7dq" Info: fpga1_pcie_avmm_interconnect_mm_bridge_7: Done "fpga1_pcie_avmm_interconnect_mm_bridge_7" with 2 modules, 2 files Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ directory: Info: common/vcs_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ --use-relative-paths=true Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_7 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_7: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_7" Info: fpga1_pcie_avmm_interconnect_mm_bridge_7: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_7" Info: fpga1_pcie_avmm_interconnect_mm_bridge_7: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_7: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_7" Info: fpga1_pcie_avmm_interconnect_mm_bridge_7: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_7_altera_avalon_mm_bridge_2001_k2bg7dq" Info: fpga1_pcie_avmm_interconnect_mm_bridge_7: Done "fpga1_pcie_avmm_interconnect_mm_bridge_7" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/dcfifo_desc_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc --family=Agilex --part=AGFB014R24A2E2VR0 Info: dcfifo_desc.fifo_0: Targeting device family: Agilex. Info: dcfifo_desc.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: dcfifo_desc.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: dcfifo_desc.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: dcfifo_desc.fifo_0: Embedded set_false_path assignment is disabled. Info: dcfifo_desc: "Transforming system: dcfifo_desc" Info: dcfifo_desc: "Naming system components in system: dcfifo_desc" Info: dcfifo_desc: "Processing generation queue" Info: dcfifo_desc: "Generating: dcfifo_desc" Info: dcfifo_desc: "Generating: dcfifo_desc_fifo_1910_7ef6usq" Info: dcfifo_desc: Done "dcfifo_desc" with 2 modules, 3 files Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ --use-relative-paths=true Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc --family=Agilex --part=AGFB014R24A2E2VR0 Info: dcfifo_desc.fifo_0: Targeting device family: Agilex. Info: dcfifo_desc.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: dcfifo_desc.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: dcfifo_desc.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: dcfifo_desc.fifo_0: Embedded set_false_path assignment is disabled. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_desc --family=Agilex --part=AGFB014R24A2E2VR0 Info: dcfifo_desc.fifo_0: Targeting device family: Agilex. Info: dcfifo_desc.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: dcfifo_desc.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: dcfifo_desc.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: dcfifo_desc.fifo_0: Embedded set_false_path assignment is disabled. Info: dcfifo_desc: "Transforming system: dcfifo_desc" Info: dcfifo_desc: "Naming system components in system: dcfifo_desc" Info: dcfifo_desc: "Processing generation queue" Info: dcfifo_desc: "Generating: dcfifo_desc" Info: dcfifo_desc: "Generating: dcfifo_desc_fifo_1910_7ef6usq" Info: dcfifo_desc: Done "dcfifo_desc" with 2 modules, 3 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/emif_cal_0_x2_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_cal_0_x2: "Transforming system: emif_cal_0_x2" Info: emif_cal_0_x2: "Naming system components in system: emif_cal_0_x2" Info: emif_cal_0_x2: "Processing generation queue" Info: emif_cal_0_x2: "Generating: emif_cal_0_x2" Info: emif_cal_0_x2: "Generating: emif_cal_0_x2_altera_emif_cal_242_3fqyaey" Info: emif_cal_0_x2: "Generating: emif_cal_0_x2_altera_emif_cal_iossm_242_4lkxlny" Info: emif_cal_0_x2: Done "emif_cal_0_x2" with 3 modules, 11 files Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ directory: Info: common/vcsmx_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ --use-relative-paths=true Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 3 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 3 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_0_x2 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_cal_0_x2: "Transforming system: emif_cal_0_x2" Info: emif_cal_0_x2: "Naming system components in system: emif_cal_0_x2" Info: emif_cal_0_x2: "Processing generation queue" Info: emif_cal_0_x2: "Generating: emif_cal_0_x2" Info: emif_cal_0_x2: "Generating: emif_cal_0_x2_altera_emif_cal_242_3fqyaey" Info: emif_cal_0_x2: "Generating: emif_cal_0_x2_altera_emif_cal_iossm_242_4lkxlny" Info: emif_cal_0_x2: Done "emif_cal_0_x2" with 3 modules, 11 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: interrupt_avst_sc_fifo: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/interrupt_avst_sc_fifo_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/interrupt_avst_sc_fifo.qsys Info: Reading input file Info: Adding avst_sc_fifo [altera_generic_component 1.0] Info: Parameterizing module avst_sc_fifo Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: interrupt_avst_sc_fifo: "Transforming system: interrupt_avst_sc_fifo" Info: interrupt_avst_sc_fifo: "Naming system components in system: interrupt_avst_sc_fifo" Info: interrupt_avst_sc_fifo: "Processing generation queue" Info: interrupt_avst_sc_fifo: "Generating: interrupt_avst_sc_fifo" Info: interrupt_avst_sc_fifo: "Generating: avst_sc_fifo" Info: interrupt_avst_sc_fifo: Done "interrupt_avst_sc_fifo" with 2 modules, 1 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/interrupt_avst_sc_fifo.qsys Info: Reading input file Info: Adding avst_sc_fifo [altera_generic_component 1.0] Info: Parameterizing module avst_sc_fifo Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/interrupt_avst_sc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/interrupt_avst_sc_fifo.qsys Info: Reading input file Info: Adding avst_sc_fifo [altera_generic_component 1.0] Info: Parameterizing module avst_sc_fifo Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: interrupt_avst_sc_fifo: "Transforming system: interrupt_avst_sc_fifo" Info: interrupt_avst_sc_fifo: "Naming system components in system: interrupt_avst_sc_fifo" Info: interrupt_avst_sc_fifo: "Processing generation queue" Info: interrupt_avst_sc_fifo: "Generating: interrupt_avst_sc_fifo" Info: interrupt_avst_sc_fifo: "Generating: avst_sc_fifo" Info: interrupt_avst_sc_fifo: Done "interrupt_avst_sc_fifo" with 2 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/fpga1_pcie_avst_snk_mux_multiplexer_0_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avst_snk_mux_multiplexer_0: "Transforming system: fpga1_pcie_avst_snk_mux_multiplexer_0" Info: fpga1_pcie_avst_snk_mux_multiplexer_0: "Naming system components in system: fpga1_pcie_avst_snk_mux_multiplexer_0" Info: fpga1_pcie_avst_snk_mux_multiplexer_0: "Processing generation queue" Info: fpga1_pcie_avst_snk_mux_multiplexer_0: "Generating: fpga1_pcie_avst_snk_mux_multiplexer_0" Info: fpga1_pcie_avst_snk_mux_multiplexer_0: "Generating: fpga1_pcie_avst_snk_mux_multiplexer_0_multiplexer_1920_p3bbvni" Info: fpga1_pcie_avst_snk_mux_multiplexer_0: Done "fpga1_pcie_avst_snk_mux_multiplexer_0" with 2 modules, 2 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_multiplexer_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avst_snk_mux_multiplexer_0: "Transforming system: fpga1_pcie_avst_snk_mux_multiplexer_0" Info: fpga1_pcie_avst_snk_mux_multiplexer_0: "Naming system components in system: fpga1_pcie_avst_snk_mux_multiplexer_0" Info: fpga1_pcie_avst_snk_mux_multiplexer_0: "Processing generation queue" Info: fpga1_pcie_avst_snk_mux_multiplexer_0: "Generating: fpga1_pcie_avst_snk_mux_multiplexer_0" Info: fpga1_pcie_avst_snk_mux_multiplexer_0: "Generating: fpga1_pcie_avst_snk_mux_multiplexer_0_multiplexer_1920_p3bbvni" Info: fpga1_pcie_avst_snk_mux_multiplexer_0: Done "fpga1_pcie_avst_snk_mux_multiplexer_0" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/dcfifo_512_128_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128 --family=Agilex --part=AGFB014R24A2E2VR0 Info: dcfifo_512_128.fifo_0: Targeting device family: Agilex. Info: dcfifo_512_128.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: dcfifo_512_128.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: dcfifo_512_128.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: dcfifo_512_128.fifo_0: Embedded set_false_path assignment is disabled. Info: dcfifo_512_128: "Transforming system: dcfifo_512_128" Info: dcfifo_512_128: "Naming system components in system: dcfifo_512_128" Info: dcfifo_512_128: "Processing generation queue" Info: dcfifo_512_128: "Generating: dcfifo_512_128" Info: dcfifo_512_128: "Generating: dcfifo_512_128_fifo_1910_2m4gqfa" Info: dcfifo_512_128: Done "dcfifo_512_128" with 2 modules, 3 files Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ directory: Info: common/vcs_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ --use-relative-paths=true Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128 --family=Agilex --part=AGFB014R24A2E2VR0 Info: dcfifo_512_128.fifo_0: Targeting device family: Agilex. Info: dcfifo_512_128.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: dcfifo_512_128.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: dcfifo_512_128.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: dcfifo_512_128.fifo_0: Embedded set_false_path assignment is disabled. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_128 --family=Agilex --part=AGFB014R24A2E2VR0 Info: dcfifo_512_128.fifo_0: Targeting device family: Agilex. Info: dcfifo_512_128.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: dcfifo_512_128.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: dcfifo_512_128.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: dcfifo_512_128.fifo_0: Embedded set_false_path assignment is disabled. Info: dcfifo_512_128: "Transforming system: dcfifo_512_128" Info: dcfifo_512_128: "Naming system components in system: dcfifo_512_128" Info: dcfifo_512_128: "Processing generation queue" Info: dcfifo_512_128: "Generating: dcfifo_512_128" Info: dcfifo_512_128: "Generating: dcfifo_512_128_fifo_1910_2m4gqfa" Info: dcfifo_512_128: Done "dcfifo_512_128" with 2 modules, 3 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/tb_fifo_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: tb_fifo.fifo_0: Targeting device family: Agilex. Info: tb_fifo.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: tb_fifo.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: tb_fifo.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: tb_fifo.fifo_0: Embedded set_false_path assignment is disabled. Info: tb_fifo: "Transforming system: tb_fifo" Info: tb_fifo: "Naming system components in system: tb_fifo" Info: tb_fifo: "Processing generation queue" Info: tb_fifo: "Generating: tb_fifo" Info: tb_fifo: "Generating: tb_fifo_fifo_1910_vfphz5i" Info: tb_fifo: Done "tb_fifo" with 2 modules, 3 files Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ --use-relative-paths=true Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: tb_fifo.fifo_0: Targeting device family: Agilex. Info: tb_fifo.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: tb_fifo.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: tb_fifo.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: tb_fifo.fifo_0: Embedded set_false_path assignment is disabled. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: tb_fifo.fifo_0: Targeting device family: Agilex. Info: tb_fifo.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: tb_fifo.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: tb_fifo.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: tb_fifo.fifo_0: Embedded set_false_path assignment is disabled. Info: tb_fifo: "Transforming system: tb_fifo" Info: tb_fifo: "Naming system components in system: tb_fifo" Info: tb_fifo: "Processing generation queue" Info: tb_fifo: "Generating: tb_fifo" Info: tb_fifo: "Generating: tb_fifo_fifo_1910_vfphz5i" Info: tb_fifo: Done "tb_fifo" with 2 modules, 3 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/mem_rdimm16GB_x8dq_1_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1 --family=Agilex --part=AGFB014R24A2E2VR0 Info: mem_rdimm16GB_x8dq_1: "Transforming system: mem_rdimm16GB_x8dq_1" Info: mem_rdimm16GB_x8dq_1: "Naming system components in system: mem_rdimm16GB_x8dq_1" Info: mem_rdimm16GB_x8dq_1: "Processing generation queue" Info: mem_rdimm16GB_x8dq_1: "Generating: mem_rdimm16GB_x8dq_1" Info: mem_rdimm16GB_x8dq_1: "Generating: mem_rdimm16GB_x8dq_1_altera_emif_mem_model_191_uuepuhy" Info: mem_rdimm16GB_x8dq_1: "Generating: altera_emif_ddrx_model" Info: mem_rdimm16GB_x8dq_1: Done "mem_rdimm16GB_x8dq_1" with 3 modules, 9 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 3 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 3 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_1 --family=Agilex --part=AGFB014R24A2E2VR0 Info: mem_rdimm16GB_x8dq_1: "Transforming system: mem_rdimm16GB_x8dq_1" Info: mem_rdimm16GB_x8dq_1: "Naming system components in system: mem_rdimm16GB_x8dq_1" Info: mem_rdimm16GB_x8dq_1: "Processing generation queue" Info: mem_rdimm16GB_x8dq_1: "Generating: mem_rdimm16GB_x8dq_1" Info: mem_rdimm16GB_x8dq_1: "Generating: mem_rdimm16GB_x8dq_1_altera_emif_mem_model_191_uuepuhy" Info: mem_rdimm16GB_x8dq_1: "Generating: altera_emif_ddrx_model" Info: mem_rdimm16GB_x8dq_1: Done "mem_rdimm16GB_x8dq_1" with 3 modules, 9 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/avst_dc_fifo_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: avst_dc_fifo: "Transforming system: avst_dc_fifo" Info: avst_dc_fifo: "Naming system components in system: avst_dc_fifo" Info: avst_dc_fifo: "Processing generation queue" Info: avst_dc_fifo: "Generating: avst_dc_fifo" Info: avst_dc_fifo: "Generating: avst_dc_fifo_st_dc_fifo_1940_r4vdppy" Info: avst_dc_fifo: Done "avst_dc_fifo" with 2 modules, 4 files Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ directory: Info: common/vcsmx_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ --use-relative-paths=true Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/ip/avst_capture_fifo/avst_dc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: avst_dc_fifo: "Transforming system: avst_dc_fifo" Info: avst_dc_fifo: "Naming system components in system: avst_dc_fifo" Info: avst_dc_fifo: "Processing generation queue" Info: avst_dc_fifo: "Generating: avst_dc_fifo" Info: avst_dc_fifo: "Generating: avst_dc_fifo_st_dc_fifo_1940_r4vdppy" Info: avst_dc_fifo: Done "avst_dc_fifo" with 2 modules, 5 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/fpga1_pcie_avmm_interconnect_mm_bridge_2_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_2: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_2" Info: fpga1_pcie_avmm_interconnect_mm_bridge_2: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_2" Info: fpga1_pcie_avmm_interconnect_mm_bridge_2: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_2: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_2" Info: fpga1_pcie_avmm_interconnect_mm_bridge_2: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_2_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_2: Done "fpga1_pcie_avmm_interconnect_mm_bridge_2" with 2 modules, 2 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_2 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_2: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_2" Info: fpga1_pcie_avmm_interconnect_mm_bridge_2: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_2" Info: fpga1_pcie_avmm_interconnect_mm_bridge_2: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_2: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_2" Info: fpga1_pcie_avmm_interconnect_mm_bridge_2: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_2_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_2: Done "fpga1_pcie_avmm_interconnect_mm_bridge_2" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/amw_acd_emif_afifo_pl_dc_fifo_0_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: amw_acd_emif_afifo_pl_dc_fifo_0: "Transforming system: amw_acd_emif_afifo_pl_dc_fifo_0" Info: amw_acd_emif_afifo_pl_dc_fifo_0: "Naming system components in system: amw_acd_emif_afifo_pl_dc_fifo_0" Info: amw_acd_emif_afifo_pl_dc_fifo_0: "Processing generation queue" Info: amw_acd_emif_afifo_pl_dc_fifo_0: "Generating: amw_acd_emif_afifo_pl_dc_fifo_0" Info: amw_acd_emif_afifo_pl_dc_fifo_0: "Generating: amw_acd_emif_afifo_pl_dc_fifo_0_st_dc_fifo_1940_r4vdppy" Info: amw_acd_emif_afifo_pl_dc_fifo_0: Done "amw_acd_emif_afifo_pl_dc_fifo_0" with 2 modules, 4 files Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ --use-relative-paths=true Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: amw_acd_emif_afifo_pl_dc_fifo_0: "Transforming system: amw_acd_emif_afifo_pl_dc_fifo_0" Info: amw_acd_emif_afifo_pl_dc_fifo_0: "Naming system components in system: amw_acd_emif_afifo_pl_dc_fifo_0" Info: amw_acd_emif_afifo_pl_dc_fifo_0: "Processing generation queue" Info: amw_acd_emif_afifo_pl_dc_fifo_0: "Generating: amw_acd_emif_afifo_pl_dc_fifo_0" Info: amw_acd_emif_afifo_pl_dc_fifo_0: "Generating: amw_acd_emif_afifo_pl_dc_fifo_0_st_dc_fifo_1940_r4vdppy" Info: amw_acd_emif_afifo_pl_dc_fifo_0: Done "amw_acd_emif_afifo_pl_dc_fifo_0" with 2 modules, 5 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: rct_adapter: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/rct_adapter_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/rct_adapter.qsys Info: Reading input file Info: Adding rct_avst_clk_crosser [altera_generic_component 1.0] Info: Parameterizing module rct_avst_clk_crosser Info: Adding rct_avstadapt_wide2narrow [altera_generic_component 1.0] Info: Parameterizing module rct_avstadapt_wide2narrow Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: rct_adapter: "Transforming system: rct_adapter" Info: rct_adapter: "Naming system components in system: rct_adapter" Info: rct_adapter: "Processing generation queue" Info: rct_adapter: "Generating: rct_adapter" Info: rct_adapter: "Generating: rct_avst_clk_crosser" Info: rct_adapter: "Generating: rct_avstadapt_wide2narrow" Info: rct_adapter: Done "rct_adapter" with 3 modules, 1 files Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ directory: Info: common/vcs_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ --use-relative-paths=true Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/rct_adapter.qsys Info: Reading input file Info: Adding rct_avst_clk_crosser [altera_generic_component 1.0] Info: Parameterizing module rct_avst_clk_crosser Info: Adding rct_avstadapt_wide2narrow [altera_generic_component 1.0] Info: Parameterizing module rct_avstadapt_wide2narrow Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/rct_adapter --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/rct_adapter.qsys Info: Reading input file Info: Adding rct_avst_clk_crosser [altera_generic_component 1.0] Info: Parameterizing module rct_avst_clk_crosser Info: Adding rct_avstadapt_wide2narrow [altera_generic_component 1.0] Info: Parameterizing module rct_avstadapt_wide2narrow Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: rct_adapter: "Transforming system: rct_adapter" Info: rct_adapter: "Naming system components in system: rct_adapter" Info: rct_adapter: "Processing generation queue" Info: rct_adapter: "Generating: rct_adapter" Info: rct_adapter: "Generating: rct_avst_clk_crosser" Info: rct_adapter: "Generating: rct_avstadapt_wide2narrow" Info: rct_adapter: Done "rct_adapter" with 3 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/dcfifo_512_256_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256 --family=Agilex --part=AGFB014R24A2E2VR0 Info: dcfifo_512_256.fifo_0: Targeting device family: Agilex. Info: dcfifo_512_256.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: dcfifo_512_256.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: dcfifo_512_256.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: dcfifo_512_256.fifo_0: Embedded set_false_path assignment is disabled. Info: dcfifo_512_256: "Transforming system: dcfifo_512_256" Info: dcfifo_512_256: "Naming system components in system: dcfifo_512_256" Info: dcfifo_512_256: "Processing generation queue" Info: dcfifo_512_256: "Generating: dcfifo_512_256" Info: dcfifo_512_256: "Generating: dcfifo_512_256_fifo_1910_m77qfwi" Info: dcfifo_512_256: Done "dcfifo_512_256" with 2 modules, 3 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256 --family=Agilex --part=AGFB014R24A2E2VR0 Info: dcfifo_512_256.fifo_0: Targeting device family: Agilex. Info: dcfifo_512_256.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: dcfifo_512_256.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: dcfifo_512_256.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: dcfifo_512_256.fifo_0: Embedded set_false_path assignment is disabled. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_512_256 --family=Agilex --part=AGFB014R24A2E2VR0 Info: dcfifo_512_256.fifo_0: Targeting device family: Agilex. Info: dcfifo_512_256.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: dcfifo_512_256.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: dcfifo_512_256.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: dcfifo_512_256.fifo_0: Embedded set_false_path assignment is disabled. Info: dcfifo_512_256: "Transforming system: dcfifo_512_256" Info: dcfifo_512_256: "Naming system components in system: dcfifo_512_256" Info: dcfifo_512_256: "Processing generation queue" Info: dcfifo_512_256: "Generating: dcfifo_512_256" Info: dcfifo_512_256: "Generating: dcfifo_512_256_fifo_1910_m77qfwi" Info: dcfifo_512_256: Done "dcfifo_512_256" with 2 modules, 3 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: fpga1_pcie_avst_snk_mux: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/fpga1_pcie_avst_snk_mux_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/fpga1_pcie_avst_snk_mux.qsys Info: Reading input file Info: Adding multiplexer_0 [altera_generic_component 1.0] Info: Parameterizing module multiplexer_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: fpga1_pcie_avst_snk_mux: "Transforming system: fpga1_pcie_avst_snk_mux" Info: fpga1_pcie_avst_snk_mux: "Naming system components in system: fpga1_pcie_avst_snk_mux" Info: fpga1_pcie_avst_snk_mux: "Processing generation queue" Info: fpga1_pcie_avst_snk_mux: "Generating: fpga1_pcie_avst_snk_mux" Info: fpga1_pcie_avst_snk_mux: "Generating: fpga1_pcie_avst_snk_mux_multiplexer_0" Info: fpga1_pcie_avst_snk_mux: Done "fpga1_pcie_avst_snk_mux" with 2 modules, 1 files Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ directory: Info: common/vcsmx_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ --use-relative-paths=true Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/fpga1_pcie_avst_snk_mux.qsys Info: Reading input file Info: Adding multiplexer_0 [altera_generic_component 1.0] Info: Parameterizing module multiplexer_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avst_snk_mux --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/fpga1_pcie_avst_snk_mux.qsys Info: Reading input file Info: Adding multiplexer_0 [altera_generic_component 1.0] Info: Parameterizing module multiplexer_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: fpga1_pcie_avst_snk_mux: "Transforming system: fpga1_pcie_avst_snk_mux" Info: fpga1_pcie_avst_snk_mux: "Naming system components in system: fpga1_pcie_avst_snk_mux" Info: fpga1_pcie_avst_snk_mux: "Processing generation queue" Info: fpga1_pcie_avst_snk_mux: "Generating: fpga1_pcie_avst_snk_mux" Info: fpga1_pcie_avst_snk_mux: "Generating: fpga1_pcie_avst_snk_mux_multiplexer_0" Info: fpga1_pcie_avst_snk_mux: Done "fpga1_pcie_avst_snk_mux" with 2 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/fpga1_pcie_avmm_interconnect_mm_bridge_6_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_6: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_6" Info: fpga1_pcie_avmm_interconnect_mm_bridge_6: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_6" Info: fpga1_pcie_avmm_interconnect_mm_bridge_6: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_6: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_6" Info: fpga1_pcie_avmm_interconnect_mm_bridge_6: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_6_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_6: Done "fpga1_pcie_avmm_interconnect_mm_bridge_6" with 2 modules, 2 files Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ --use-relative-paths=true Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_6 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_6: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_6" Info: fpga1_pcie_avmm_interconnect_mm_bridge_6: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_6" Info: fpga1_pcie_avmm_interconnect_mm_bridge_6: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_6: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_6" Info: fpga1_pcie_avmm_interconnect_mm_bridge_6: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_6_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_6: Done "fpga1_pcie_avmm_interconnect_mm_bridge_6" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/rct_avstadapt_wide2narrow_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow --family=Agilex --part=AGFB014R24A2E2VR0 Info: rct_avstadapt_wide2narrow: "Transforming system: rct_avstadapt_wide2narrow" Info: rct_avstadapt_wide2narrow: "Naming system components in system: rct_avstadapt_wide2narrow" Info: rct_avstadapt_wide2narrow: "Processing generation queue" Info: rct_avstadapt_wide2narrow: "Generating: rct_avstadapt_wide2narrow" Info: rct_avstadapt_wide2narrow: "Generating: rct_avstadapt_wide2narrow_data_format_adapter_1920_mgwpika" Info: rct_avstadapt_wide2narrow: Done "rct_avstadapt_wide2narrow" with 2 modules, 4 files Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ directory: Info: common/vcs_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ --use-relative-paths=true Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/rateconverter_tsync/cores/ip/rct_adapter/rct_avstadapt_wide2narrow --family=Agilex --part=AGFB014R24A2E2VR0 Info: rct_avstadapt_wide2narrow: "Transforming system: rct_avstadapt_wide2narrow" Info: rct_avstadapt_wide2narrow: "Naming system components in system: rct_avstadapt_wide2narrow" Info: rct_avstadapt_wide2narrow: "Processing generation queue" Info: rct_avstadapt_wide2narrow: "Generating: rct_avstadapt_wide2narrow" Info: rct_avstadapt_wide2narrow: "Generating: rct_avstadapt_wide2narrow_data_format_adapter_1920_mgwpika" Info: rct_avstadapt_wide2narrow: Done "rct_avstadapt_wide2narrow" with 2 modules, 4 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/fpga1_pcie_avmm_interconnect_reset_in_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_reset_in: "Transforming system: fpga1_pcie_avmm_interconnect_reset_in" Info: fpga1_pcie_avmm_interconnect_reset_in: "Naming system components in system: fpga1_pcie_avmm_interconnect_reset_in" Info: fpga1_pcie_avmm_interconnect_reset_in: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_reset_in: "Generating: fpga1_pcie_avmm_interconnect_reset_in" Info: fpga1_pcie_avmm_interconnect_reset_in: Done "fpga1_pcie_avmm_interconnect_reset_in" with 1 modules, 1 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_reset_in --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_reset_in: "Transforming system: fpga1_pcie_avmm_interconnect_reset_in" Info: fpga1_pcie_avmm_interconnect_reset_in: "Naming system components in system: fpga1_pcie_avmm_interconnect_reset_in" Info: fpga1_pcie_avmm_interconnect_reset_in: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_reset_in: "Generating: fpga1_pcie_avmm_interconnect_reset_in" Info: fpga1_pcie_avmm_interconnect_reset_in: Done "fpga1_pcie_avmm_interconnect_reset_in" with 1 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/emif_cal_1_x1_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_cal_1_x1: "Transforming system: emif_cal_1_x1" Info: emif_cal_1_x1: "Naming system components in system: emif_cal_1_x1" Info: emif_cal_1_x1: "Processing generation queue" Info: emif_cal_1_x1: "Generating: emif_cal_1_x1" Info: emif_cal_1_x1: "Generating: emif_cal_1_x1_altera_emif_cal_242_rescudq" Info: emif_cal_1_x1: "Generating: emif_cal_1_x1_altera_emif_cal_iossm_242_7dq7ezy" Info: emif_cal_1_x1: Done "emif_cal_1_x1" with 3 modules, 11 files Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ directory: Info: common/vcsmx_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ --use-relative-paths=true Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 3 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 3 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_cal_1_x1 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_cal_1_x1: "Transforming system: emif_cal_1_x1" Info: emif_cal_1_x1: "Naming system components in system: emif_cal_1_x1" Info: emif_cal_1_x1: "Processing generation queue" Info: emif_cal_1_x1: "Generating: emif_cal_1_x1" Info: emif_cal_1_x1: "Generating: emif_cal_1_x1_altera_emif_cal_242_rescudq" Info: emif_cal_1_x1: "Generating: emif_cal_1_x1_altera_emif_cal_iossm_242_7dq7ezy" Info: emif_cal_1_x1: Done "emif_cal_1_x1" with 3 modules, 11 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/amr_ac_emif_afifo_98_pl_dc_fifo_0_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: amr_ac_emif_afifo_98_pl_dc_fifo_0: "Transforming system: amr_ac_emif_afifo_98_pl_dc_fifo_0" Info: amr_ac_emif_afifo_98_pl_dc_fifo_0: "Naming system components in system: amr_ac_emif_afifo_98_pl_dc_fifo_0" Info: amr_ac_emif_afifo_98_pl_dc_fifo_0: "Processing generation queue" Info: amr_ac_emif_afifo_98_pl_dc_fifo_0: "Generating: amr_ac_emif_afifo_98_pl_dc_fifo_0" Info: amr_ac_emif_afifo_98_pl_dc_fifo_0: "Generating: amr_ac_emif_afifo_98_pl_dc_fifo_0_st_dc_fifo_1940_r4vdppy" Info: amr_ac_emif_afifo_98_pl_dc_fifo_0: Done "amr_ac_emif_afifo_98_pl_dc_fifo_0" with 2 modules, 4 files Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ --use-relative-paths=true Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: amr_ac_emif_afifo_98_pl_dc_fifo_0: "Transforming system: amr_ac_emif_afifo_98_pl_dc_fifo_0" Info: amr_ac_emif_afifo_98_pl_dc_fifo_0: "Naming system components in system: amr_ac_emif_afifo_98_pl_dc_fifo_0" Info: amr_ac_emif_afifo_98_pl_dc_fifo_0: "Processing generation queue" Info: amr_ac_emif_afifo_98_pl_dc_fifo_0: "Generating: amr_ac_emif_afifo_98_pl_dc_fifo_0" Info: amr_ac_emif_afifo_98_pl_dc_fifo_0: "Generating: amr_ac_emif_afifo_98_pl_dc_fifo_0_st_dc_fifo_1940_r4vdppy" Info: amr_ac_emif_afifo_98_pl_dc_fifo_0: Done "amr_ac_emif_afifo_98_pl_dc_fifo_0" with 2 modules, 5 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: avst_capture_fifo: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/avst_capture_fifo_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/avst_capture_fifo.qsys Info: Reading input file Info: Adding avst_dc_fifo [altera_generic_component 1.0] Info: Parameterizing module avst_dc_fifo Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: avst_capture_fifo: "Transforming system: avst_capture_fifo" Info: avst_capture_fifo: "Naming system components in system: avst_capture_fifo" Info: avst_capture_fifo: "Processing generation queue" Info: avst_capture_fifo: "Generating: avst_capture_fifo" Info: avst_capture_fifo: "Generating: avst_dc_fifo" Info: avst_capture_fifo: Done "avst_capture_fifo" with 2 modules, 1 files Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ directory: Info: common/vcs_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ --use-relative-paths=true Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/avst_capture_fifo.qsys Info: Reading input file Info: Adding avst_dc_fifo [altera_generic_component 1.0] Info: Parameterizing module avst_dc_fifo Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/avst_capture_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/avst_capture_fifo.qsys Info: Reading input file Info: Adding avst_dc_fifo [altera_generic_component 1.0] Info: Parameterizing module avst_dc_fifo Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: avst_capture_fifo: "Transforming system: avst_capture_fifo" Info: avst_capture_fifo: "Naming system components in system: avst_capture_fifo" Info: avst_capture_fifo: "Processing generation queue" Info: avst_capture_fifo: "Generating: avst_capture_fifo" Info: avst_capture_fifo: "Generating: avst_dc_fifo" Info: avst_capture_fifo: Done "avst_capture_fifo" with 2 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/mem_rdimm16GB_x8dq_2_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2 --family=Agilex --part=AGFB014R24A2E2VR0 Info: mem_rdimm16GB_x8dq_2: "Transforming system: mem_rdimm16GB_x8dq_2" Info: mem_rdimm16GB_x8dq_2: "Naming system components in system: mem_rdimm16GB_x8dq_2" Info: mem_rdimm16GB_x8dq_2: "Processing generation queue" Info: mem_rdimm16GB_x8dq_2: "Generating: mem_rdimm16GB_x8dq_2" Info: mem_rdimm16GB_x8dq_2: "Generating: mem_rdimm16GB_x8dq_2_altera_emif_mem_model_191_uuepuhy" Info: mem_rdimm16GB_x8dq_2: "Generating: altera_emif_ddrx_model" Info: mem_rdimm16GB_x8dq_2: Done "mem_rdimm16GB_x8dq_2" with 3 modules, 9 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 3 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 3 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_2 --family=Agilex --part=AGFB014R24A2E2VR0 Info: mem_rdimm16GB_x8dq_2: "Transforming system: mem_rdimm16GB_x8dq_2" Info: mem_rdimm16GB_x8dq_2: "Naming system components in system: mem_rdimm16GB_x8dq_2" Info: mem_rdimm16GB_x8dq_2: "Processing generation queue" Info: mem_rdimm16GB_x8dq_2: "Generating: mem_rdimm16GB_x8dq_2" Info: mem_rdimm16GB_x8dq_2: "Generating: mem_rdimm16GB_x8dq_2_altera_emif_mem_model_191_uuepuhy" Info: mem_rdimm16GB_x8dq_2: "Generating: altera_emif_ddrx_model" Info: mem_rdimm16GB_x8dq_2: Done "mem_rdimm16GB_x8dq_2" with 3 modules, 9 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/storage_dcfifo_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: storage_dcfifo.storage_dcfifo: Targeting device family: Agilex. Info: storage_dcfifo.storage_dcfifo: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: storage_dcfifo.storage_dcfifo: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: storage_dcfifo.storage_dcfifo: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: storage_dcfifo.storage_dcfifo: Embedded set_false_path assignment is disabled. Info: storage_dcfifo: "Transforming system: storage_dcfifo" Info: storage_dcfifo: "Naming system components in system: storage_dcfifo" Info: storage_dcfifo: "Processing generation queue" Info: storage_dcfifo: "Generating: storage_dcfifo" Info: storage_dcfifo: "Generating: storage_dcfifo_fifo_1910_7ahywmi" Info: storage_dcfifo: Done "storage_dcfifo" with 2 modules, 3 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: storage_dcfifo.storage_dcfifo: Targeting device family: Agilex. Info: storage_dcfifo.storage_dcfifo: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: storage_dcfifo.storage_dcfifo: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: storage_dcfifo.storage_dcfifo: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: storage_dcfifo.storage_dcfifo: Embedded set_false_path assignment is disabled. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcfifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: storage_dcfifo.storage_dcfifo: Targeting device family: Agilex. Info: storage_dcfifo.storage_dcfifo: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: storage_dcfifo.storage_dcfifo: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: storage_dcfifo.storage_dcfifo: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: storage_dcfifo.storage_dcfifo: Embedded set_false_path assignment is disabled. Info: storage_dcfifo: "Transforming system: storage_dcfifo" Info: storage_dcfifo: "Naming system components in system: storage_dcfifo" Info: storage_dcfifo: "Processing generation queue" Info: storage_dcfifo: "Generating: storage_dcfifo" Info: storage_dcfifo: "Generating: storage_dcfifo_fifo_1910_7ahywmi" Info: storage_dcfifo: Done "storage_dcfifo" with 2 modules, 3 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/fpga1_pcie_avmm_interconnect_mm_bridge_1_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_1: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_1" Info: fpga1_pcie_avmm_interconnect_mm_bridge_1: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_1" Info: fpga1_pcie_avmm_interconnect_mm_bridge_1: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_1: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_1" Info: fpga1_pcie_avmm_interconnect_mm_bridge_1: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_1_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_1: Done "fpga1_pcie_avmm_interconnect_mm_bridge_1" with 2 modules, 2 files Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ --use-relative-paths=true Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_1 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_1: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_1" Info: fpga1_pcie_avmm_interconnect_mm_bridge_1: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_1" Info: fpga1_pcie_avmm_interconnect_mm_bridge_1: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_1: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_1" Info: fpga1_pcie_avmm_interconnect_mm_bridge_1: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_1_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_1: Done "fpga1_pcie_avmm_interconnect_mm_bridge_1" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/amw_acd_emif_afifo_610_pl_dc_fifo_0_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: amw_acd_emif_afifo_610_pl_dc_fifo_0: "Transforming system: amw_acd_emif_afifo_610_pl_dc_fifo_0" Info: amw_acd_emif_afifo_610_pl_dc_fifo_0: "Naming system components in system: amw_acd_emif_afifo_610_pl_dc_fifo_0" Info: amw_acd_emif_afifo_610_pl_dc_fifo_0: "Processing generation queue" Info: amw_acd_emif_afifo_610_pl_dc_fifo_0: "Generating: amw_acd_emif_afifo_610_pl_dc_fifo_0" Info: amw_acd_emif_afifo_610_pl_dc_fifo_0: "Generating: amw_acd_emif_afifo_610_pl_dc_fifo_0_st_dc_fifo_1940_r4vdppy" Info: amw_acd_emif_afifo_610_pl_dc_fifo_0: Done "amw_acd_emif_afifo_610_pl_dc_fifo_0" with 2 modules, 4 files Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ directory: Info: common/vcs_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ --use-relative-paths=true Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: amw_acd_emif_afifo_610_pl_dc_fifo_0: "Transforming system: amw_acd_emif_afifo_610_pl_dc_fifo_0" Info: amw_acd_emif_afifo_610_pl_dc_fifo_0: "Naming system components in system: amw_acd_emif_afifo_610_pl_dc_fifo_0" Info: amw_acd_emif_afifo_610_pl_dc_fifo_0: "Processing generation queue" Info: amw_acd_emif_afifo_610_pl_dc_fifo_0: "Generating: amw_acd_emif_afifo_610_pl_dc_fifo_0" Info: amw_acd_emif_afifo_610_pl_dc_fifo_0: "Generating: amw_acd_emif_afifo_610_pl_dc_fifo_0_st_dc_fifo_1940_r4vdppy" Info: amw_acd_emif_afifo_610_pl_dc_fifo_0: Done "amw_acd_emif_afifo_610_pl_dc_fifo_0" with 2 modules, 5 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/dcfifo_128_512_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512 --family=Agilex --part=AGFB014R24A2E2VR0 Info: dcfifo_128_512.fifo_0: Targeting device family: Agilex. Info: dcfifo_128_512.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: dcfifo_128_512.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: dcfifo_128_512.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: dcfifo_128_512.fifo_0: Embedded set_false_path assignment is disabled. Info: dcfifo_128_512: "Transforming system: dcfifo_128_512" Info: dcfifo_128_512: "Naming system components in system: dcfifo_128_512" Info: dcfifo_128_512: "Processing generation queue" Info: dcfifo_128_512: "Generating: dcfifo_128_512" Info: dcfifo_128_512: "Generating: dcfifo_128_512_fifo_1910_gujwa4q" Info: dcfifo_128_512: Done "dcfifo_128_512" with 2 modules, 3 files Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ directory: Info: common/vcsmx_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ --use-relative-paths=true Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512 --family=Agilex --part=AGFB014R24A2E2VR0 Info: dcfifo_128_512.fifo_0: Targeting device family: Agilex. Info: dcfifo_128_512.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: dcfifo_128_512.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: dcfifo_128_512.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: dcfifo_128_512.fifo_0: Embedded set_false_path assignment is disabled. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/dcfifo_128_512 --family=Agilex --part=AGFB014R24A2E2VR0 Info: dcfifo_128_512.fifo_0: Targeting device family: Agilex. Info: dcfifo_128_512.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: dcfifo_128_512.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: dcfifo_128_512.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: dcfifo_128_512.fifo_0: Embedded set_false_path assignment is disabled. Info: dcfifo_128_512: "Transforming system: dcfifo_128_512" Info: dcfifo_128_512: "Naming system components in system: dcfifo_128_512" Info: dcfifo_128_512: "Processing generation queue" Info: dcfifo_128_512: "Generating: dcfifo_128_512" Info: dcfifo_128_512: "Generating: dcfifo_128_512_fifo_1910_gujwa4q" Info: dcfifo_128_512: Done "dcfifo_128_512" with 2 modules, 3 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: amr_ac_emif_afifo_98_pl: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/amr_ac_emif_afifo_98_pl_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amr_ac_emif_afifo_98_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: amr_ac_emif_afifo_98_pl: "Transforming system: amr_ac_emif_afifo_98_pl" Info: amr_ac_emif_afifo_98_pl: "Naming system components in system: amr_ac_emif_afifo_98_pl" Info: amr_ac_emif_afifo_98_pl: "Processing generation queue" Info: amr_ac_emif_afifo_98_pl: "Generating: amr_ac_emif_afifo_98_pl" Info: amr_ac_emif_afifo_98_pl: "Generating: amr_ac_emif_afifo_98_pl_dc_fifo_0" Info: amr_ac_emif_afifo_98_pl: Done "amr_ac_emif_afifo_98_pl" with 2 modules, 1 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amr_ac_emif_afifo_98_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_98_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amr_ac_emif_afifo_98_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: amr_ac_emif_afifo_98_pl: "Transforming system: amr_ac_emif_afifo_98_pl" Info: amr_ac_emif_afifo_98_pl: "Naming system components in system: amr_ac_emif_afifo_98_pl" Info: amr_ac_emif_afifo_98_pl: "Processing generation queue" Info: amr_ac_emif_afifo_98_pl: "Generating: amr_ac_emif_afifo_98_pl" Info: amr_ac_emif_afifo_98_pl: "Generating: amr_ac_emif_afifo_98_pl_dc_fifo_0" Info: amr_ac_emif_afifo_98_pl: Done "amr_ac_emif_afifo_98_pl" with 2 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: amr_ac_emif_afifo_pl: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/amr_ac_emif_afifo_pl_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amr_ac_emif_afifo_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Warning: amr_ac_emif_afifo_pl.dc_fifo_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Info: amr_ac_emif_afifo_pl: "Transforming system: amr_ac_emif_afifo_pl" Info: amr_ac_emif_afifo_pl: "Naming system components in system: amr_ac_emif_afifo_pl" Info: amr_ac_emif_afifo_pl: "Processing generation queue" Info: amr_ac_emif_afifo_pl: "Generating: amr_ac_emif_afifo_pl" Info: amr_ac_emif_afifo_pl: "Generating: amr_ac_emif_afifo_pl_dc_fifo_0" Info: amr_ac_emif_afifo_pl: Done "amr_ac_emif_afifo_pl" with 2 modules, 1 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amr_ac_emif_afifo_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Warning: amr_ac_emif_afifo_pl.dc_fifo_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_ac_emif_afifo_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amr_ac_emif_afifo_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Warning: amr_ac_emif_afifo_pl.dc_fifo_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Info: amr_ac_emif_afifo_pl: "Transforming system: amr_ac_emif_afifo_pl" Info: amr_ac_emif_afifo_pl: "Naming system components in system: amr_ac_emif_afifo_pl" Info: amr_ac_emif_afifo_pl: "Processing generation queue" Info: amr_ac_emif_afifo_pl: "Generating: amr_ac_emif_afifo_pl" Info: amr_ac_emif_afifo_pl: "Generating: amr_ac_emif_afifo_pl_dc_fifo_0" Info: amr_ac_emif_afifo_pl: Done "amr_ac_emif_afifo_pl" with 2 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/demux_avst_clk_crosser_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser --family=Agilex --part=AGFB014R24A2E2VR0 Info: demux_avst_clk_crosser: "Transforming system: demux_avst_clk_crosser" Info: demux_avst_clk_crosser: "Naming system components in system: demux_avst_clk_crosser" Info: demux_avst_clk_crosser: "Processing generation queue" Info: demux_avst_clk_crosser: "Generating: demux_avst_clk_crosser" Info: demux_avst_clk_crosser: "Generating: demux_avst_clk_crosser_hs_clk_xer_1931_7vhe7xa" Info: demux_avst_clk_crosser: Done "demux_avst_clk_crosser" with 2 modules, 6 files Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ directory: Info: common/vcsmx_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ --use-relative-paths=true Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avst_clk_crosser --family=Agilex --part=AGFB014R24A2E2VR0 Info: demux_avst_clk_crosser: "Transforming system: demux_avst_clk_crosser" Info: demux_avst_clk_crosser: "Naming system components in system: demux_avst_clk_crosser" Info: demux_avst_clk_crosser: "Processing generation queue" Info: demux_avst_clk_crosser: "Generating: demux_avst_clk_crosser" Info: demux_avst_clk_crosser: "Generating: demux_avst_clk_crosser_hs_clk_xer_1931_7vhe7xa" Info: demux_avst_clk_crosser: Done "demux_avst_clk_crosser" with 2 modules, 6 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/storage_dcdpram_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram --family=Agilex --part=AGFB014R24A2E2VR0 Info: storage_dcdpram.storage_dcdpram: Targeting device family: Agilex. Info: storage_dcdpram.storage_dcdpram: 'Mixed Port Read-During-Write' tab is unavailable while using "Dual clock: use separate 'read' and 'write' clocks" clocking method. Info: storage_dcdpram.storage_dcdpram: 'Same Port Read-During-Write' tab is unavailable while using one read port and one write port. Info: storage_dcdpram.storage_dcdpram: In 'Performance Optimization' tab, 'Timing/Power Optimization' feature is only supported for M20K ram block type. Info: storage_dcdpram: "Transforming system: storage_dcdpram" Info: storage_dcdpram: "Naming system components in system: storage_dcdpram" Info: storage_dcdpram: "Processing generation queue" Info: storage_dcdpram: "Generating: storage_dcdpram" Info: storage_dcdpram: "Generating: storage_dcdpram_ram_2port_2021_gu3vvvq" Info: storage_dcdpram: Done "storage_dcdpram" with 2 modules, 2 files Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ directory: Info: common/vcs_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ --use-relative-paths=true Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram --family=Agilex --part=AGFB014R24A2E2VR0 Info: storage_dcdpram.storage_dcdpram: Targeting device family: Agilex. Info: storage_dcdpram.storage_dcdpram: 'Mixed Port Read-During-Write' tab is unavailable while using "Dual clock: use separate 'read' and 'write' clocks" clocking method. Info: storage_dcdpram.storage_dcdpram: 'Same Port Read-During-Write' tab is unavailable while using one read port and one write port. Info: storage_dcdpram.storage_dcdpram: In 'Performance Optimization' tab, 'Timing/Power Optimization' feature is only supported for M20K ram block type. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/ip/storage/storage_dcdpram --family=Agilex --part=AGFB014R24A2E2VR0 Info: storage_dcdpram.storage_dcdpram: Targeting device family: Agilex. Info: storage_dcdpram.storage_dcdpram: 'Mixed Port Read-During-Write' tab is unavailable while using "Dual clock: use separate 'read' and 'write' clocks" clocking method. Info: storage_dcdpram.storage_dcdpram: 'Same Port Read-During-Write' tab is unavailable while using one read port and one write port. Info: storage_dcdpram.storage_dcdpram: In 'Performance Optimization' tab, 'Timing/Power Optimization' feature is only supported for M20K ram block type. Info: storage_dcdpram: "Transforming system: storage_dcdpram" Info: storage_dcdpram: "Naming system components in system: storage_dcdpram" Info: storage_dcdpram: "Processing generation queue" Info: storage_dcdpram: "Generating: storage_dcdpram" Info: storage_dcdpram: "Generating: storage_dcdpram_ram_2port_2021_gu3vvvq" Info: storage_dcdpram: Done "storage_dcdpram" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: amw_acd_emif_afifo_610_pl: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/amw_acd_emif_afifo_610_pl_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amw_acd_emif_afifo_610_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: amw_acd_emif_afifo_610_pl: "Transforming system: amw_acd_emif_afifo_610_pl" Info: amw_acd_emif_afifo_610_pl: "Naming system components in system: amw_acd_emif_afifo_610_pl" Info: amw_acd_emif_afifo_610_pl: "Processing generation queue" Info: amw_acd_emif_afifo_610_pl: "Generating: amw_acd_emif_afifo_610_pl" Info: amw_acd_emif_afifo_610_pl: "Generating: amw_acd_emif_afifo_610_pl_dc_fifo_0" Info: amw_acd_emif_afifo_610_pl: Done "amw_acd_emif_afifo_610_pl" with 2 modules, 1 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amw_acd_emif_afifo_610_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_610_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amw_acd_emif_afifo_610_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: amw_acd_emif_afifo_610_pl: "Transforming system: amw_acd_emif_afifo_610_pl" Info: amw_acd_emif_afifo_610_pl: "Naming system components in system: amw_acd_emif_afifo_610_pl" Info: amw_acd_emif_afifo_610_pl: "Processing generation queue" Info: amw_acd_emif_afifo_610_pl: "Generating: amw_acd_emif_afifo_610_pl" Info: amw_acd_emif_afifo_610_pl: "Generating: amw_acd_emif_afifo_610_pl_dc_fifo_0" Info: amw_acd_emif_afifo_610_pl: Done "amw_acd_emif_afifo_610_pl" with 2 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/tb_ram_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram --family=Agilex --part=AGFB014R24A2E2VR0 Info: tb_ram.ram_2port_0: Targeting device family: Agilex. Info: tb_ram.ram_2port_0: In 'Widths/Blk Type' tab, field for 'q_a' output bus will be ignored while using one read port and one write port mode. Info: tb_ram.ram_2port_0: 'Mixed Port Read-During-Write' tab is unavailable while using "Dual clock: use separate 'read' and 'write' clocks" clocking method. Info: tb_ram.ram_2port_0: 'Same Port Read-During-Write' tab is unavailable while using one read port and one write port. Info: tb_ram.ram_2port_0: In 'Performance Optimization' tab, 'Timing/Power Optimization' feature is only supported for M20K ram block type. Info: tb_ram: "Transforming system: tb_ram" Info: tb_ram: "Naming system components in system: tb_ram" Info: tb_ram: "Processing generation queue" Info: tb_ram: "Generating: tb_ram" Info: tb_ram: "Generating: tb_ram_ram_2port_2021_x3jc2oq" Info: tb_ram: Done "tb_ram" with 2 modules, 2 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram --family=Agilex --part=AGFB014R24A2E2VR0 Info: tb_ram.ram_2port_0: Targeting device family: Agilex. Info: tb_ram.ram_2port_0: In 'Widths/Blk Type' tab, field for 'q_a' output bus will be ignored while using one read port and one write port mode. Info: tb_ram.ram_2port_0: 'Mixed Port Read-During-Write' tab is unavailable while using "Dual clock: use separate 'read' and 'write' clocks" clocking method. Info: tb_ram.ram_2port_0: 'Same Port Read-During-Write' tab is unavailable while using one read port and one write port. Info: tb_ram.ram_2port_0: In 'Performance Optimization' tab, 'Timing/Power Optimization' feature is only supported for M20K ram block type. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/tb_ram --family=Agilex --part=AGFB014R24A2E2VR0 Info: tb_ram.ram_2port_0: Targeting device family: Agilex. Info: tb_ram.ram_2port_0: In 'Widths/Blk Type' tab, field for 'q_a' output bus will be ignored while using one read port and one write port mode. Info: tb_ram.ram_2port_0: 'Mixed Port Read-During-Write' tab is unavailable while using "Dual clock: use separate 'read' and 'write' clocks" clocking method. Info: tb_ram.ram_2port_0: 'Same Port Read-During-Write' tab is unavailable while using one read port and one write port. Info: tb_ram.ram_2port_0: In 'Performance Optimization' tab, 'Timing/Power Optimization' feature is only supported for M20K ram block type. Info: tb_ram: "Transforming system: tb_ram" Info: tb_ram: "Naming system components in system: tb_ram" Info: tb_ram: "Processing generation queue" Info: tb_ram: "Generating: tb_ram" Info: tb_ram: "Generating: tb_ram_ram_2port_2021_x3jc2oq" Info: tb_ram: Done "tb_ram" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: demux_adapter: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/demux_adapter_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/demux_adapter.qsys Info: Reading input file Info: Adding demux_avst_clk_crosser [altera_generic_component 1.0] Info: Parameterizing module demux_avst_clk_crosser Info: Adding demux_avstadapt_wide2narrow [altera_generic_component 1.0] Info: Parameterizing module demux_avstadapt_wide2narrow Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: demux_adapter: "Transforming system: demux_adapter" Info: demux_adapter: "Naming system components in system: demux_adapter" Info: demux_adapter: "Processing generation queue" Info: demux_adapter: "Generating: demux_adapter" Info: demux_adapter: "Generating: demux_avst_clk_crosser" Info: demux_adapter: "Generating: demux_avstadapt_wide2narrow" Info: demux_adapter: Done "demux_adapter" with 3 modules, 1 files Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ directory: Info: common/vcsmx_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ --use-relative-paths=true Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/demux_adapter.qsys Info: Reading input file Info: Adding demux_avst_clk_crosser [altera_generic_component 1.0] Info: Parameterizing module demux_avst_clk_crosser Info: Adding demux_avstadapt_wide2narrow [altera_generic_component 1.0] Info: Parameterizing module demux_avstadapt_wide2narrow Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/demux_adapter --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/demux_adapter.qsys Info: Reading input file Info: Adding demux_avst_clk_crosser [altera_generic_component 1.0] Info: Parameterizing module demux_avst_clk_crosser Info: Adding demux_avstadapt_wide2narrow [altera_generic_component 1.0] Info: Parameterizing module demux_avstadapt_wide2narrow Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: demux_adapter: "Transforming system: demux_adapter" Info: demux_adapter: "Naming system components in system: demux_adapter" Info: demux_adapter: "Processing generation queue" Info: demux_adapter: "Generating: demux_adapter" Info: demux_adapter: "Generating: demux_avst_clk_crosser" Info: demux_adapter: "Generating: demux_avstadapt_wide2narrow" Info: demux_adapter: Done "demux_adapter" with 3 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/fpga1_pcie_avmm_interconnect_mm_bridge_5_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_5: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_5" Info: fpga1_pcie_avmm_interconnect_mm_bridge_5: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_5" Info: fpga1_pcie_avmm_interconnect_mm_bridge_5: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_5: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_5" Info: fpga1_pcie_avmm_interconnect_mm_bridge_5: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_5_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_5: Done "fpga1_pcie_avmm_interconnect_mm_bridge_5" with 2 modules, 2 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_5 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_5: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_5" Info: fpga1_pcie_avmm_interconnect_mm_bridge_5: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_5" Info: fpga1_pcie_avmm_interconnect_mm_bridge_5: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_5: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_5" Info: fpga1_pcie_avmm_interconnect_mm_bridge_5: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_5_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_5: Done "fpga1_pcie_avmm_interconnect_mm_bridge_5" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/tb_256_256_dc_fifo_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: tb_256_256_dc_fifo.fifo_0: Targeting device family: Agilex. Info: tb_256_256_dc_fifo.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: tb_256_256_dc_fifo.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: tb_256_256_dc_fifo.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: tb_256_256_dc_fifo.fifo_0: Embedded set_false_path assignment is disabled. Info: tb_256_256_dc_fifo: "Transforming system: tb_256_256_dc_fifo" Info: tb_256_256_dc_fifo: "Naming system components in system: tb_256_256_dc_fifo" Info: tb_256_256_dc_fifo: "Processing generation queue" Info: tb_256_256_dc_fifo: "Generating: tb_256_256_dc_fifo" Info: tb_256_256_dc_fifo: "Generating: tb_256_256_dc_fifo_fifo_1910_ftj7f3q" Info: tb_256_256_dc_fifo: Done "tb_256_256_dc_fifo" with 2 modules, 3 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: tb_256_256_dc_fifo.fifo_0: Targeting device family: Agilex. Info: tb_256_256_dc_fifo.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: tb_256_256_dc_fifo.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: tb_256_256_dc_fifo.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: tb_256_256_dc_fifo.fifo_0: Embedded set_false_path assignment is disabled. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_capture/cores/tb_256_256_dc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: tb_256_256_dc_fifo.fifo_0: Targeting device family: Agilex. Info: tb_256_256_dc_fifo.fifo_0: Tab: 'SCFIFO Options' is unavailable while using Dual-Clock FIFO. Info: tb_256_256_dc_fifo.fifo_0: 'Output register option' is unavailable while using Dual-Clock FIFO. Info: tb_256_256_dc_fifo.fifo_0: SDC file will be generated to apply correct constraints. User may experience increase in fitter compilation time Info: tb_256_256_dc_fifo.fifo_0: Embedded set_false_path assignment is disabled. Info: tb_256_256_dc_fifo: "Transforming system: tb_256_256_dc_fifo" Info: tb_256_256_dc_fifo: "Naming system components in system: tb_256_256_dc_fifo" Info: tb_256_256_dc_fifo: "Processing generation queue" Info: tb_256_256_dc_fifo: "Generating: tb_256_256_dc_fifo" Info: tb_256_256_dc_fifo: "Generating: tb_256_256_dc_fifo_fifo_1910_ftj7f3q" Info: tb_256_256_dc_fifo: Done "tb_256_256_dc_fifo" with 2 modules, 3 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/fpga1_pcie_avmm_interconnect_mm_bridge_0_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_0: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_0" Info: fpga1_pcie_avmm_interconnect_mm_bridge_0: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_0" Info: fpga1_pcie_avmm_interconnect_mm_bridge_0: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_0: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_0" Info: fpga1_pcie_avmm_interconnect_mm_bridge_0: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_0_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_0: Done "fpga1_pcie_avmm_interconnect_mm_bridge_0" with 2 modules, 2 files Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ directory: Info: common/vcsmx_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ --use-relative-paths=true Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_0: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_0" Info: fpga1_pcie_avmm_interconnect_mm_bridge_0: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_0" Info: fpga1_pcie_avmm_interconnect_mm_bridge_0: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_0: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_0" Info: fpga1_pcie_avmm_interconnect_mm_bridge_0: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_0_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_0: Done "fpga1_pcie_avmm_interconnect_mm_bridge_0" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: amr_d_emif_afifo_pl: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amr_d_emif_afifo_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Warning: amr_d_emif_afifo_pl.dc_fifo_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Info: amr_d_emif_afifo_pl: "Transforming system: amr_d_emif_afifo_pl" Info: amr_d_emif_afifo_pl: "Naming system components in system: amr_d_emif_afifo_pl" Info: amr_d_emif_afifo_pl: "Processing generation queue" Info: amr_d_emif_afifo_pl: "Generating: amr_d_emif_afifo_pl" Info: amr_d_emif_afifo_pl: "Generating: amr_d_emif_afifo_pl_dc_fifo_0" Info: amr_d_emif_afifo_pl: Done "amr_d_emif_afifo_pl" with 2 modules, 1 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amr_d_emif_afifo_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Warning: amr_d_emif_afifo_pl.dc_fifo_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amr_d_emif_afifo_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amr_d_emif_afifo_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Warning: amr_d_emif_afifo_pl.dc_fifo_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Info: amr_d_emif_afifo_pl: "Transforming system: amr_d_emif_afifo_pl" Info: amr_d_emif_afifo_pl: "Naming system components in system: amr_d_emif_afifo_pl" Info: amr_d_emif_afifo_pl: "Processing generation queue" Info: amr_d_emif_afifo_pl: "Generating: amr_d_emif_afifo_pl" Info: amr_d_emif_afifo_pl: "Generating: amr_d_emif_afifo_pl_dc_fifo_0" Info: amr_d_emif_afifo_pl: Done "amr_d_emif_afifo_pl" with 2 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: emif_x3rdimm16GB_x8dq_sim: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/emif_x3rdimm16GB_x8dq_sim_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/emif_x3rdimm16GB_x8dq_sim.qsys Info: Reading input file Info: Adding emif_cal_0 [altera_generic_component 1.0] Info: Parameterizing module emif_cal_0 Info: Adding emif_cal_1 [altera_generic_component 1.0] Info: Parameterizing module emif_cal_1 Info: Adding emif_fm_0 [altera_generic_component 1.0] Info: Parameterizing module emif_fm_0 Info: Adding emif_fm_1 [altera_generic_component 1.0] Info: Parameterizing module emif_fm_1 Info: Adding emif_fm_2 [altera_generic_component 1.0] Info: Parameterizing module emif_fm_2 Info: Adding emif_local_reset_combiner_0 [altera_generic_component 1.0] Info: Parameterizing module emif_local_reset_combiner_0 Info: Adding emif_mem_model_0 [altera_generic_component 1.0] Info: Parameterizing module emif_mem_model_0 Info: Adding emif_mem_model_1 [altera_generic_component 1.0] Info: Parameterizing module emif_mem_model_1 Info: Adding emif_mem_model_2 [altera_generic_component 1.0] Info: Parameterizing module emif_mem_model_2 Info: Adding s10_user_rst_clkgate_0 [altera_generic_component 1.0] Info: Parameterizing module s10_user_rst_clkgate_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Warning: emif_x3rdimm16GB_x8dq_sim.emif_cal_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_cal_1: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_fm_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_fm_1: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_fm_2: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_local_reset_combiner_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_mem_model_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_mem_model_1: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_mem_model_2: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.s10_user_rst_clkgate_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Info: emif_x3rdimm16GB_x8dq_sim: "Transforming system: emif_x3rdimm16GB_x8dq_sim" Info: emif_x3rdimm16GB_x8dq_sim: "Naming system components in system: emif_x3rdimm16GB_x8dq_sim" Info: emif_x3rdimm16GB_x8dq_sim: "Processing generation queue" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: emif_x3rdimm16GB_x8dq_sim" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: emif_cal_0_x2" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: emif_cal_1_x1" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: emif_fm_0" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: emif_fm_1" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: emif_fm_2" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: local_reset_combiner_x3" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: mem_rdimm16GB_x8dq_0" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: mem_rdimm16GB_x8dq_1" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: mem_rdimm16GB_x8dq_2" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: ninit_done_inst" Info: emif_x3rdimm16GB_x8dq_sim: Done "emif_x3rdimm16GB_x8dq_sim" with 11 modules, 1 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/emif_x3rdimm16GB_x8dq_sim.qsys Info: Reading input file Info: Adding emif_cal_0 [altera_generic_component 1.0] Info: Parameterizing module emif_cal_0 Info: Adding emif_cal_1 [altera_generic_component 1.0] Info: Parameterizing module emif_cal_1 Info: Adding emif_fm_0 [altera_generic_component 1.0] Info: Parameterizing module emif_fm_0 Info: Adding emif_fm_1 [altera_generic_component 1.0] Info: Parameterizing module emif_fm_1 Info: Adding emif_fm_2 [altera_generic_component 1.0] Info: Parameterizing module emif_fm_2 Info: Adding emif_local_reset_combiner_0 [altera_generic_component 1.0] Info: Parameterizing module emif_local_reset_combiner_0 Info: Adding emif_mem_model_0 [altera_generic_component 1.0] Info: Parameterizing module emif_mem_model_0 Info: Adding emif_mem_model_1 [altera_generic_component 1.0] Info: Parameterizing module emif_mem_model_1 Info: Adding emif_mem_model_2 [altera_generic_component 1.0] Info: Parameterizing module emif_mem_model_2 Info: Adding s10_user_rst_clkgate_0 [altera_generic_component 1.0] Info: Parameterizing module s10_user_rst_clkgate_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Warning: emif_x3rdimm16GB_x8dq_sim.emif_cal_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_cal_1: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_fm_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_fm_1: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_fm_2: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_local_reset_combiner_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_mem_model_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_mem_model_1: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_mem_model_2: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.s10_user_rst_clkgate_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/emif_x3rdimm16GB_x8dq_sim --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/emif_x3rdimm16GB_x8dq_sim.qsys Info: Reading input file Info: Adding emif_cal_0 [altera_generic_component 1.0] Info: Parameterizing module emif_cal_0 Info: Adding emif_cal_1 [altera_generic_component 1.0] Info: Parameterizing module emif_cal_1 Info: Adding emif_fm_0 [altera_generic_component 1.0] Info: Parameterizing module emif_fm_0 Info: Adding emif_fm_1 [altera_generic_component 1.0] Info: Parameterizing module emif_fm_1 Info: Adding emif_fm_2 [altera_generic_component 1.0] Info: Parameterizing module emif_fm_2 Info: Adding emif_local_reset_combiner_0 [altera_generic_component 1.0] Info: Parameterizing module emif_local_reset_combiner_0 Info: Adding emif_mem_model_0 [altera_generic_component 1.0] Info: Parameterizing module emif_mem_model_0 Info: Adding emif_mem_model_1 [altera_generic_component 1.0] Info: Parameterizing module emif_mem_model_1 Info: Adding emif_mem_model_2 [altera_generic_component 1.0] Info: Parameterizing module emif_mem_model_2 Info: Adding s10_user_rst_clkgate_0 [altera_generic_component 1.0] Info: Parameterizing module s10_user_rst_clkgate_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Warning: emif_x3rdimm16GB_x8dq_sim.emif_cal_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_cal_1: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_fm_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_fm_1: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_fm_2: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_local_reset_combiner_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_mem_model_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_mem_model_1: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.emif_mem_model_2: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Warning: emif_x3rdimm16GB_x8dq_sim.s10_user_rst_clkgate_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Info: emif_x3rdimm16GB_x8dq_sim: "Transforming system: emif_x3rdimm16GB_x8dq_sim" Info: emif_x3rdimm16GB_x8dq_sim: "Naming system components in system: emif_x3rdimm16GB_x8dq_sim" Info: emif_x3rdimm16GB_x8dq_sim: "Processing generation queue" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: emif_x3rdimm16GB_x8dq_sim" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: emif_cal_0_x2" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: emif_cal_1_x1" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: emif_fm_0" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: emif_fm_1" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: emif_fm_2" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: local_reset_combiner_x3" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: mem_rdimm16GB_x8dq_0" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: mem_rdimm16GB_x8dq_1" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: mem_rdimm16GB_x8dq_2" Info: emif_x3rdimm16GB_x8dq_sim: "Generating: ninit_done_inst" Info: emif_x3rdimm16GB_x8dq_sim: Done "emif_x3rdimm16GB_x8dq_sim" with 11 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/fpga1_pcie_avmm_interconnect_mm_bridge_4_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_4: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_4" Info: fpga1_pcie_avmm_interconnect_mm_bridge_4: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_4" Info: fpga1_pcie_avmm_interconnect_mm_bridge_4: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_4: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_4" Info: fpga1_pcie_avmm_interconnect_mm_bridge_4: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_4_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_4: Done "fpga1_pcie_avmm_interconnect_mm_bridge_4" with 2 modules, 2 files Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ directory: Info: common/vcsmx_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ --use-relative-paths=true Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_mm_bridge_4 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avmm_interconnect_mm_bridge_4: "Transforming system: fpga1_pcie_avmm_interconnect_mm_bridge_4" Info: fpga1_pcie_avmm_interconnect_mm_bridge_4: "Naming system components in system: fpga1_pcie_avmm_interconnect_mm_bridge_4" Info: fpga1_pcie_avmm_interconnect_mm_bridge_4: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect_mm_bridge_4: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_4" Info: fpga1_pcie_avmm_interconnect_mm_bridge_4: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_4_altera_avalon_mm_bridge_2001_nukioay" Info: fpga1_pcie_avmm_interconnect_mm_bridge_4: Done "fpga1_pcie_avmm_interconnect_mm_bridge_4" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/demux_avstadapt_wide2narrow_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow --family=Agilex --part=AGFB014R24A2E2VR0 Info: demux_avstadapt_wide2narrow: "Transforming system: demux_avstadapt_wide2narrow" Info: demux_avstadapt_wide2narrow: "Naming system components in system: demux_avstadapt_wide2narrow" Info: demux_avstadapt_wide2narrow: "Processing generation queue" Info: demux_avstadapt_wide2narrow: "Generating: demux_avstadapt_wide2narrow" Info: demux_avstadapt_wide2narrow: "Generating: demux_avstadapt_wide2narrow_data_format_adapter_1920_mgwpika" Info: demux_avstadapt_wide2narrow: Done "demux_avstadapt_wide2narrow" with 2 modules, 4 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux/cores/ip/demux_adapter/demux_avstadapt_wide2narrow --family=Agilex --part=AGFB014R24A2E2VR0 Info: demux_avstadapt_wide2narrow: "Transforming system: demux_avstadapt_wide2narrow" Info: demux_avstadapt_wide2narrow: "Naming system components in system: demux_avstadapt_wide2narrow" Info: demux_avstadapt_wide2narrow: "Processing generation queue" Info: demux_avstadapt_wide2narrow: "Generating: demux_avstadapt_wide2narrow" Info: demux_avstadapt_wide2narrow: "Generating: demux_avstadapt_wide2narrow_data_format_adapter_1920_mgwpika" Info: demux_avstadapt_wide2narrow: Done "demux_avstadapt_wide2narrow" with 2 modules, 4 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/mem_rdimm16GB_x8dq_0_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: mem_rdimm16GB_x8dq_0: "Transforming system: mem_rdimm16GB_x8dq_0" Info: mem_rdimm16GB_x8dq_0: "Naming system components in system: mem_rdimm16GB_x8dq_0" Info: mem_rdimm16GB_x8dq_0: "Processing generation queue" Info: mem_rdimm16GB_x8dq_0: "Generating: mem_rdimm16GB_x8dq_0" Info: mem_rdimm16GB_x8dq_0: "Generating: mem_rdimm16GB_x8dq_0_altera_emif_mem_model_191_uuepuhy" Info: mem_rdimm16GB_x8dq_0: "Generating: altera_emif_ddrx_model" Info: mem_rdimm16GB_x8dq_0: Done "mem_rdimm16GB_x8dq_0" with 3 modules, 9 files Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ directory: Info: common/vcs_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ --use-relative-paths=true Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 3 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 3 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/mem_rdimm16GB_x8dq_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: mem_rdimm16GB_x8dq_0: "Transforming system: mem_rdimm16GB_x8dq_0" Info: mem_rdimm16GB_x8dq_0: "Naming system components in system: mem_rdimm16GB_x8dq_0" Info: mem_rdimm16GB_x8dq_0: "Processing generation queue" Info: mem_rdimm16GB_x8dq_0: "Generating: mem_rdimm16GB_x8dq_0" Info: mem_rdimm16GB_x8dq_0: "Generating: mem_rdimm16GB_x8dq_0_altera_emif_mem_model_191_uuepuhy" Info: mem_rdimm16GB_x8dq_0: "Generating: altera_emif_ddrx_model" Info: mem_rdimm16GB_x8dq_0: Done "mem_rdimm16GB_x8dq_0" with 3 modules, 9 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/fpga1_pcie_avst_src_demux_demultiplexer_0_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avst_src_demux_demultiplexer_0: "Transforming system: fpga1_pcie_avst_src_demux_demultiplexer_0" Info: fpga1_pcie_avst_src_demux_demultiplexer_0: "Naming system components in system: fpga1_pcie_avst_src_demux_demultiplexer_0" Info: fpga1_pcie_avst_src_demux_demultiplexer_0: "Processing generation queue" Info: fpga1_pcie_avst_src_demux_demultiplexer_0: "Generating: fpga1_pcie_avst_src_demux_demultiplexer_0" Info: fpga1_pcie_avst_src_demux_demultiplexer_0: "Generating: fpga1_pcie_avst_src_demux_demultiplexer_0_demultiplexer_1920_5mpz32a" Info: fpga1_pcie_avst_src_demux_demultiplexer_0: Done "fpga1_pcie_avst_src_demux_demultiplexer_0" with 2 modules, 2 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/ip/fpga1_pcie_avst_src_demux/fpga1_pcie_avst_src_demux_demultiplexer_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: fpga1_pcie_avst_src_demux_demultiplexer_0: "Transforming system: fpga1_pcie_avst_src_demux_demultiplexer_0" Info: fpga1_pcie_avst_src_demux_demultiplexer_0: "Naming system components in system: fpga1_pcie_avst_src_demux_demultiplexer_0" Info: fpga1_pcie_avst_src_demux_demultiplexer_0: "Processing generation queue" Info: fpga1_pcie_avst_src_demux_demultiplexer_0: "Generating: fpga1_pcie_avst_src_demux_demultiplexer_0" Info: fpga1_pcie_avst_src_demux_demultiplexer_0: "Generating: fpga1_pcie_avst_src_demux_demultiplexer_0_demultiplexer_1920_5mpz32a" Info: fpga1_pcie_avst_src_demux_demultiplexer_0: Done "fpga1_pcie_avst_src_demux_demultiplexer_0" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/amr_d_emif_afifo_pl_dc_fifo_0_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: amr_d_emif_afifo_pl_dc_fifo_0: "Transforming system: amr_d_emif_afifo_pl_dc_fifo_0" Info: amr_d_emif_afifo_pl_dc_fifo_0: "Naming system components in system: amr_d_emif_afifo_pl_dc_fifo_0" Info: amr_d_emif_afifo_pl_dc_fifo_0: "Processing generation queue" Info: amr_d_emif_afifo_pl_dc_fifo_0: "Generating: amr_d_emif_afifo_pl_dc_fifo_0" Info: amr_d_emif_afifo_pl_dc_fifo_0: "Generating: amr_d_emif_afifo_pl_dc_fifo_0_st_dc_fifo_1940_r4vdppy" Info: amr_d_emif_afifo_pl_dc_fifo_0: Done "amr_d_emif_afifo_pl_dc_fifo_0" with 2 modules, 4 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: common/ncsim_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/ip/amr_d_emif_afifo_pl/amr_d_emif_afifo_pl_dc_fifo_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: amr_d_emif_afifo_pl_dc_fifo_0: "Transforming system: amr_d_emif_afifo_pl_dc_fifo_0" Info: amr_d_emif_afifo_pl_dc_fifo_0: "Naming system components in system: amr_d_emif_afifo_pl_dc_fifo_0" Info: amr_d_emif_afifo_pl_dc_fifo_0: "Processing generation queue" Info: amr_d_emif_afifo_pl_dc_fifo_0: "Generating: amr_d_emif_afifo_pl_dc_fifo_0" Info: amr_d_emif_afifo_pl_dc_fifo_0: "Generating: amr_d_emif_afifo_pl_dc_fifo_0_st_dc_fifo_1940_r4vdppy" Info: amr_d_emif_afifo_pl_dc_fifo_0: Done "amr_d_emif_afifo_pl_dc_fifo_0" with 2 modules, 5 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/emif_fm_2_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_fm_2.emif_fm_2: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. Info: emif_fm_2.emif_fm_2: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. Info: emif_fm_2.emif_fm_2.arch: Agilex EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. Warning: emif_fm_2.emif_fm_2.arch: Per-rank calibration using shadow register cannot be enabled for the current interface and for the currently selected engineering sample device. Interface will be calibrated to the average across ranks instead. Production devices do not have this limitation. Info: emif_fm_2.emif_fm_2.arch: PHY and controller running at quarter-rate for the currently selected engineering sample device. Production devices can run the PHY and controller at half-rate, reducing latency and improving efficiency. Info: emif_fm_2.emif_fm_2.arch: Placement of address/command pins must follow "DDR4 Scheme 2: Component and DIMM". Info: emif_fm_2.emif_fm_2.arch: Interface estimated to require 2 I/O Bank(s) and 3 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. Info: emif_fm_2.emif_fm_2.arch: Valid memory frequencies for the current PLL reference clock of 300.0 MHz and user clock rate, in MHz: 1200.0 Info: emif_fm_2.emif_fm_2.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. Info: emif_fm_2: "Transforming system: emif_fm_2" Info: emif_fm_2: "Naming system components in system: emif_fm_2" Info: emif_fm_2: "Processing generation queue" Info: emif_fm_2: "Generating: emif_fm_2" Info: emif_fm_2: "Generating: emif_fm_2_altera_emif_fm_242_p3vad3i" Info: emif_fm_2: "Generating: emif_fm_2_altera_emif_arch_fm_191_zvcrrty" Info: emif_fm_2: "Generating: emif_fm_2_altera_emif_ecc_191_z6y6kzy" Info: emif_fm_2: "Generating: altera_emif_ecc_core" Info: emif_fm_2: Done "emif_fm_2" with 5 modules, 61 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 5 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 5 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_fm_2.emif_fm_2: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. Info: emif_fm_2.emif_fm_2: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. Info: emif_fm_2.emif_fm_2.arch: Agilex EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. Warning: emif_fm_2.emif_fm_2.arch: Per-rank calibration using shadow register cannot be enabled for the current interface and for the currently selected engineering sample device. Interface will be calibrated to the average across ranks instead. Production devices do not have this limitation. Info: emif_fm_2.emif_fm_2.arch: PHY and controller running at quarter-rate for the currently selected engineering sample device. Production devices can run the PHY and controller at half-rate, reducing latency and improving efficiency. Info: emif_fm_2.emif_fm_2.arch: Placement of address/command pins must follow "DDR4 Scheme 2: Component and DIMM". Info: emif_fm_2.emif_fm_2.arch: Interface estimated to require 2 I/O Bank(s) and 3 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. Info: emif_fm_2.emif_fm_2.arch: Valid memory frequencies for the current PLL reference clock of 300.0 MHz and user clock rate, in MHz: 1200.0 Info: emif_fm_2.emif_fm_2.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_2 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_fm_2.emif_fm_2: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. Info: emif_fm_2.emif_fm_2: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. Info: emif_fm_2.emif_fm_2.arch: Agilex EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. Warning: emif_fm_2.emif_fm_2.arch: Per-rank calibration using shadow register cannot be enabled for the current interface and for the currently selected engineering sample device. Interface will be calibrated to the average across ranks instead. Production devices do not have this limitation. Info: emif_fm_2.emif_fm_2.arch: PHY and controller running at quarter-rate for the currently selected engineering sample device. Production devices can run the PHY and controller at half-rate, reducing latency and improving efficiency. Info: emif_fm_2.emif_fm_2.arch: Placement of address/command pins must follow "DDR4 Scheme 2: Component and DIMM". Info: emif_fm_2.emif_fm_2.arch: Interface estimated to require 2 I/O Bank(s) and 3 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. Info: emif_fm_2.emif_fm_2.arch: Valid memory frequencies for the current PLL reference clock of 300.0 MHz and user clock rate, in MHz: 1200.0 Info: emif_fm_2.emif_fm_2.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. Info: emif_fm_2: "Transforming system: emif_fm_2" Info: emif_fm_2: "Naming system components in system: emif_fm_2" Info: emif_fm_2: "Processing generation queue" Info: emif_fm_2: "Generating: emif_fm_2" Info: emif_fm_2: "Generating: emif_fm_2_altera_emif_fm_242_p3vad3i" Info: emif_fm_2: "Generating: emif_fm_2_altera_emif_arch_fm_191_zvcrrty" Info: emif_fm_2: "Generating: emif_fm_2_altera_emif_ecc_191_z6y6kzy" Info: emif_fm_2: "Generating: altera_emif_ecc_core" Info: emif_fm_2: Done "emif_fm_2" with 5 modules, 71 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: storage: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/storage_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/storage.qsys Info: Reading input file Info: Adding storage_dcdpram [altera_generic_component 1.0] Info: Parameterizing module storage_dcdpram Info: Adding storage_dcfifo [altera_generic_component 1.0] Info: Parameterizing module storage_dcfifo Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: storage: "Transforming system: storage" Info: storage: "Naming system components in system: storage" Info: storage: "Processing generation queue" Info: storage: "Generating: storage" Info: storage: "Generating: storage_dcdpram" Info: storage: "Generating: storage_dcfifo" Info: storage: Done "storage" with 3 modules, 1 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/storage.qsys Info: Reading input file Info: Adding storage_dcdpram [altera_generic_component 1.0] Info: Parameterizing module storage_dcdpram Info: Adding storage_dcfifo [altera_generic_component 1.0] Info: Parameterizing module storage_dcfifo Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/vector_player/cores/storage --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/storage.qsys Info: Reading input file Info: Adding storage_dcdpram [altera_generic_component 1.0] Info: Parameterizing module storage_dcdpram Info: Adding storage_dcfifo [altera_generic_component 1.0] Info: Parameterizing module storage_dcfifo Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: storage: "Transforming system: storage" Info: storage: "Naming system components in system: storage" Info: storage: "Processing generation queue" Info: storage: "Generating: storage" Info: storage: "Generating: storage_dcdpram" Info: storage: "Generating: storage_dcfifo" Info: storage: Done "storage" with 3 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/clock_switch_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch --family=Agilex --part=AGFB014R24A2E2VR0 Warning: clock_switch.intelclkctrl_0: Not enabling glitch free switchover because it is not supported by this Quartus release Info: clock_switch: "Transforming system: clock_switch" Info: clock_switch: "Naming system components in system: clock_switch" Info: clock_switch: "Processing generation queue" Info: clock_switch: "Generating: clock_switch" Info: clock_switch: "Generating: clock_switch_intelclkctrl_200_gwjcydi" Info: intelclkctrl_0: Generating top-level entity clock_switch_intelclkctrl_200_gwjcydi. Info: intelclkctrl_0: Verilog entity generation was successful Info: clock_switch: Done "clock_switch" with 2 modules, 2 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch --family=Agilex --part=AGFB014R24A2E2VR0 Warning: clock_switch.intelclkctrl_0: Not enabling glitch free switchover because it is not supported by this Quartus release Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/clock_switch --family=Agilex --part=AGFB014R24A2E2VR0 Warning: clock_switch.intelclkctrl_0: Not enabling glitch free switchover because it is not supported by this Quartus release Info: clock_switch: "Transforming system: clock_switch" Info: clock_switch: "Naming system components in system: clock_switch" Info: clock_switch: "Processing generation queue" Info: clock_switch: "Generating: clock_switch" Info: clock_switch: "Generating: clock_switch_intelclkctrl_200_gwjcydi" Info: intelclkctrl_0: Generating top-level entity clock_switch_intelclkctrl_200_gwjcydi. Info: intelclkctrl_0: Verilog entity generation was successful Info: clock_switch: Done "clock_switch" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/ninit_done_inst_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst --family=Agilex --part=AGFB014R24A2E2VR0 Info: ninit_done_inst: "Transforming system: ninit_done_inst" Info: ninit_done_inst: "Naming system components in system: ninit_done_inst" Info: ninit_done_inst: "Processing generation queue" Info: ninit_done_inst: "Generating: ninit_done_inst" Info: ninit_done_inst: "Generating: altera_s10_user_rst_clkgate" Info: ninit_done_inst: Done "ninit_done_inst" with 2 modules, 2 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst --family=Agilex --part=AGFB014R24A2E2VR0 Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/ninit_done_inst --family=Agilex --part=AGFB014R24A2E2VR0 Info: ninit_done_inst: "Transforming system: ninit_done_inst" Info: ninit_done_inst: "Naming system components in system: ninit_done_inst" Info: ninit_done_inst: "Processing generation queue" Info: ninit_done_inst: "Generating: ninit_done_inst" Info: ninit_done_inst: "Generating: altera_s10_user_rst_clkgate" Info: ninit_done_inst: generating top-level entity altera_s10_user_rst_clkgate Info: ninit_done_inst: Done "ninit_done_inst" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/emif_fm_1_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_fm_1.emif_fm_1: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. Info: emif_fm_1.emif_fm_1: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. Info: emif_fm_1.emif_fm_1.arch: Agilex EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. Warning: emif_fm_1.emif_fm_1.arch: Per-rank calibration using shadow register cannot be enabled for the current interface and for the currently selected engineering sample device. Interface will be calibrated to the average across ranks instead. Production devices do not have this limitation. Info: emif_fm_1.emif_fm_1.arch: PHY and controller running at quarter-rate for the currently selected engineering sample device. Production devices can run the PHY and controller at half-rate, reducing latency and improving efficiency. Info: emif_fm_1.emif_fm_1.arch: Placement of address/command pins must follow "DDR4 Scheme 2: Component and DIMM". Info: emif_fm_1.emif_fm_1.arch: Interface estimated to require 2 I/O Bank(s) and 3 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. Info: emif_fm_1.emif_fm_1.arch: Valid memory frequencies for the current PLL reference clock of 300.0 MHz and user clock rate, in MHz: 1200.0 Info: emif_fm_1.emif_fm_1.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. Info: emif_fm_1: "Transforming system: emif_fm_1" Info: emif_fm_1: "Naming system components in system: emif_fm_1" Info: emif_fm_1: "Processing generation queue" Info: emif_fm_1: "Generating: emif_fm_1" Info: emif_fm_1: "Generating: emif_fm_1_altera_emif_fm_242_litxrma" Info: emif_fm_1: "Generating: emif_fm_1_altera_emif_arch_fm_191_ukhdmsa" Info: emif_fm_1: "Generating: emif_fm_1_altera_emif_ecc_191_v6dxdoi" Info: emif_fm_1: "Generating: altera_emif_ecc_core" Info: emif_fm_1: Done "emif_fm_1" with 5 modules, 61 files Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ --use-relative-paths=true Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 5 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 5 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_fm_1.emif_fm_1: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. Info: emif_fm_1.emif_fm_1: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. Info: emif_fm_1.emif_fm_1.arch: Agilex EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. Warning: emif_fm_1.emif_fm_1.arch: Per-rank calibration using shadow register cannot be enabled for the current interface and for the currently selected engineering sample device. Interface will be calibrated to the average across ranks instead. Production devices do not have this limitation. Info: emif_fm_1.emif_fm_1.arch: PHY and controller running at quarter-rate for the currently selected engineering sample device. Production devices can run the PHY and controller at half-rate, reducing latency and improving efficiency. Info: emif_fm_1.emif_fm_1.arch: Placement of address/command pins must follow "DDR4 Scheme 2: Component and DIMM". Info: emif_fm_1.emif_fm_1.arch: Interface estimated to require 2 I/O Bank(s) and 3 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. Info: emif_fm_1.emif_fm_1.arch: Valid memory frequencies for the current PLL reference clock of 300.0 MHz and user clock rate, in MHz: 1200.0 Info: emif_fm_1.emif_fm_1.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_1 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_fm_1.emif_fm_1: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. Info: emif_fm_1.emif_fm_1: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. Info: emif_fm_1.emif_fm_1.arch: Agilex EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. Warning: emif_fm_1.emif_fm_1.arch: Per-rank calibration using shadow register cannot be enabled for the current interface and for the currently selected engineering sample device. Interface will be calibrated to the average across ranks instead. Production devices do not have this limitation. Info: emif_fm_1.emif_fm_1.arch: PHY and controller running at quarter-rate for the currently selected engineering sample device. Production devices can run the PHY and controller at half-rate, reducing latency and improving efficiency. Info: emif_fm_1.emif_fm_1.arch: Placement of address/command pins must follow "DDR4 Scheme 2: Component and DIMM". Info: emif_fm_1.emif_fm_1.arch: Interface estimated to require 2 I/O Bank(s) and 3 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. Info: emif_fm_1.emif_fm_1.arch: Valid memory frequencies for the current PLL reference clock of 300.0 MHz and user clock rate, in MHz: 1200.0 Info: emif_fm_1.emif_fm_1.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. Info: emif_fm_1: "Transforming system: emif_fm_1" Info: emif_fm_1: "Naming system components in system: emif_fm_1" Info: emif_fm_1: "Processing generation queue" Info: emif_fm_1: "Generating: emif_fm_1" Info: emif_fm_1: "Generating: emif_fm_1_altera_emif_fm_242_litxrma" Info: emif_fm_1: "Generating: emif_fm_1_altera_emif_arch_fm_191_ukhdmsa" Info: emif_fm_1: "Generating: emif_fm_1_altera_emif_ecc_191_v6dxdoi" Info: emif_fm_1: "Generating: altera_emif_ecc_core" Info: emif_fm_1: Done "emif_fm_1" with 5 modules, 71 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: amw_acd_emif_afifo_pl: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/amw_acd_emif_afifo_pl_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amw_acd_emif_afifo_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Warning: amw_acd_emif_afifo_pl.dc_fifo_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Info: amw_acd_emif_afifo_pl: "Transforming system: amw_acd_emif_afifo_pl" Info: amw_acd_emif_afifo_pl: "Naming system components in system: amw_acd_emif_afifo_pl" Info: amw_acd_emif_afifo_pl: "Processing generation queue" Info: amw_acd_emif_afifo_pl: "Generating: amw_acd_emif_afifo_pl" Info: amw_acd_emif_afifo_pl: "Generating: amw_acd_emif_afifo_pl_dc_fifo_0" Info: amw_acd_emif_afifo_pl: Done "amw_acd_emif_afifo_pl" with 2 modules, 1 files Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amw_acd_emif_afifo_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Warning: amw_acd_emif_afifo_pl.dc_fifo_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/demux_emif/cores/amw_acd_emif_afifo_pl --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/amw_acd_emif_afifo_pl.qsys Info: Reading input file Info: Adding dc_fifo_0 [altera_generic_component 1.0] Info: Parameterizing module dc_fifo_0 Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Warning: amw_acd_emif_afifo_pl.dc_fifo_0: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab. Info: amw_acd_emif_afifo_pl: "Transforming system: amw_acd_emif_afifo_pl" Info: amw_acd_emif_afifo_pl: "Naming system components in system: amw_acd_emif_afifo_pl" Info: amw_acd_emif_afifo_pl: "Processing generation queue" Info: amw_acd_emif_afifo_pl: "Generating: amw_acd_emif_afifo_pl" Info: amw_acd_emif_afifo_pl: "Generating: amw_acd_emif_afifo_pl_dc_fifo_0" Info: amw_acd_emif_afifo_pl: Done "amw_acd_emif_afifo_pl" with 2 modules, 1 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: fpga1_pcie_avmm_interconnect: All Generic Component instances match their respective ip files. Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/fpga1_pcie_avmm_interconnect_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/fpga1_pcie_avmm_interconnect.qsys Info: Reading input file Info: Adding clock_in [altera_generic_component 1.0] Info: Parameterizing module clock_in Info: Adding mm_bridge_0 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_0 Info: Adding mm_bridge_1 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_1 Info: Adding mm_bridge_2 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_2 Info: Adding mm_bridge_3 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_3 Info: Adding mm_bridge_4 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_4 Info: Adding mm_bridge_5 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_5 Info: Adding mm_bridge_6 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_6 Info: Adding mm_bridge_7 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_7 Info: Adding reset_in [altera_generic_component 1.0] Info: Parameterizing module reset_in Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: fpga1_pcie_avmm_interconnect: "Transforming system: fpga1_pcie_avmm_interconnect" Info: fpga1_pcie_avmm_interconnect: "Naming system components in system: fpga1_pcie_avmm_interconnect" Info: fpga1_pcie_avmm_interconnect: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_clock_in" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_0" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_1" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_2" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_3" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_4" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_5" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_6" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_7" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_reset_in" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_mm_interconnect_1920_xikvu6q" Info: fpga1_pcie_avmm_interconnect: "Generating: altera_reset_controller" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_master_translator_191_g7h47bq" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_slave_translator_191_x56fcki" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_master_agent_191_mpbm6tq" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_slave_agent_191_ncfkfri" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_avalon_sc_fifo_1930_k6mjsxi" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_router_1920_b56cyli" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_router_1920_ftclxay" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_traffic_limiter_191_6blplji" Info: my_altera_avalon_sc_fifo_dest_id_fifo: "Generating: my_altera_avalon_sc_fifo_dest_id_fifo" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_burst_adapter_1920_uyulddi" Info: my_altera_avalon_st_pipeline_stage: "Generating: my_altera_avalon_st_pipeline_stage" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_demultiplexer_1921_npiposq" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_multiplexer_1921_dme2pii" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_demultiplexer_1921_w5mwr4i" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_multiplexer_1921_2rh47ea" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_191_l4xxshq" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1920_clng4ly" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_avalon_st_pipeline_stage_1920_zterisq" Info: fpga1_pcie_avmm_interconnect: Done "fpga1_pcie_avmm_interconnect" with 29 modules, 34 files Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect.qsys --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ --use-relative-paths=true Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 1 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 1 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect.qsys --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/fpga1_pcie_avmm_interconnect.qsys Info: Reading input file Info: Adding clock_in [altera_generic_component 1.0] Info: Parameterizing module clock_in Info: Adding mm_bridge_0 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_0 Info: Adding mm_bridge_1 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_1 Info: Adding mm_bridge_2 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_2 Info: Adding mm_bridge_3 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_3 Info: Adding mm_bridge_4 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_4 Info: Adding mm_bridge_5 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_5 Info: Adding mm_bridge_6 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_6 Info: Adding mm_bridge_7 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_7 Info: Adding reset_in [altera_generic_component 1.0] Info: Parameterizing module reset_in Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect.qsys --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/fpga1_fabric_wrapper/cores/fpga1_pcie_avmm_interconnect --family=Agilex --part=AGFB014R24A2E2VR0 Info: Loading cores/fpga1_pcie_avmm_interconnect.qsys Info: Reading input file Info: Adding clock_in [altera_generic_component 1.0] Info: Parameterizing module clock_in Info: Adding mm_bridge_0 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_0 Info: Adding mm_bridge_1 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_1 Info: Adding mm_bridge_2 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_2 Info: Adding mm_bridge_3 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_3 Info: Adding mm_bridge_4 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_4 Info: Adding mm_bridge_5 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_5 Info: Adding mm_bridge_6 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_6 Info: Adding mm_bridge_7 [altera_generic_component 1.0] Info: Parameterizing module mm_bridge_7 Info: Adding reset_in [altera_generic_component 1.0] Info: Parameterizing module reset_in Info: Building connections Info: Parameterizing connections Info: Validating Info: Done reading input file Info: fpga1_pcie_avmm_interconnect: "Transforming system: fpga1_pcie_avmm_interconnect" Info: fpga1_pcie_avmm_interconnect: "Naming system components in system: fpga1_pcie_avmm_interconnect" Info: fpga1_pcie_avmm_interconnect: "Processing generation queue" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_clock_in" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_0" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_1" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_2" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_3" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_4" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_5" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_6" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_mm_bridge_7" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_reset_in" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_mm_interconnect_1920_xikvu6q" Info: fpga1_pcie_avmm_interconnect: "Generating: altera_reset_controller" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_master_translator_191_g7h47bq" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_slave_translator_191_x56fcki" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_master_agent_191_mpbm6tq" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_slave_agent_191_ncfkfri" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_avalon_sc_fifo_1930_k6mjsxi" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_router_1920_b56cyli" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_router_1920_ftclxay" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_traffic_limiter_191_6blplji" Info: my_altera_avalon_sc_fifo_dest_id_fifo: "Generating: my_altera_avalon_sc_fifo_dest_id_fifo" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_burst_adapter_1920_uyulddi" Info: my_altera_avalon_st_pipeline_stage: "Generating: my_altera_avalon_st_pipeline_stage" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_demultiplexer_1921_npiposq" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_multiplexer_1921_dme2pii" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_demultiplexer_1921_w5mwr4i" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_multiplexer_1921_2rh47ea" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_191_l4xxshq" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1920_clng4ly" Info: fpga1_pcie_avmm_interconnect: "Generating: fpga1_pcie_avmm_interconnect_altera_avalon_st_pipeline_stage_1920_zterisq" Info: fpga1_pcie_avmm_interconnect: Done "fpga1_pcie_avmm_interconnect" with 29 modules, 34 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/tb_32_256_sc_fifo_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: tb_32_256_sc_fifo.fifo_0: Targeting device family: Agilex. Info: tb_32_256_sc_fifo.fifo_0: Tab: 'DCFIFO 1' is unavailable while using Single-Clock FIFO. Info: tb_32_256_sc_fifo.fifo_0: Tab: 'DCFIFO 2' is unavailable while using Single-Clock FIFO. Info: tb_32_256_sc_fifo: "Transforming system: tb_32_256_sc_fifo" Info: tb_32_256_sc_fifo: "Naming system components in system: tb_32_256_sc_fifo" Info: tb_32_256_sc_fifo: "Processing generation queue" Info: tb_32_256_sc_fifo: "Generating: tb_32_256_sc_fifo" Info: tb_32_256_sc_fifo: "Generating: tb_32_256_sc_fifo_fifo_1910_2sdi6ga" Info: tb_32_256_sc_fifo: Done "tb_32_256_sc_fifo" with 2 modules, 2 files Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ directory: Info: common/vcs_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ directory: Info: common/xcelium_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ --use-relative-paths=true Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 2 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 2 .cds.lib files in xcelium/cds_libs/ directory Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: tb_32_256_sc_fifo.fifo_0: Targeting device family: Agilex. Info: tb_32_256_sc_fifo.fifo_0: Tab: 'DCFIFO 1' is unavailable while using Single-Clock FIFO. Info: tb_32_256_sc_fifo.fifo_0: Tab: 'DCFIFO 2' is unavailable while using Single-Clock FIFO. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/interrupt_ctrl/cores/tb_32_256_sc_fifo --family=Agilex --part=AGFB014R24A2E2VR0 Info: tb_32_256_sc_fifo.fifo_0: Targeting device family: Agilex. Info: tb_32_256_sc_fifo.fifo_0: Tab: 'DCFIFO 1' is unavailable while using Single-Clock FIFO. Info: tb_32_256_sc_fifo.fifo_0: Tab: 'DCFIFO 2' is unavailable while using Single-Clock FIFO. Info: tb_32_256_sc_fifo: "Transforming system: tb_32_256_sc_fifo" Info: tb_32_256_sc_fifo: "Naming system components in system: tb_32_256_sc_fifo" Info: tb_32_256_sc_fifo: "Processing generation queue" Info: tb_32_256_sc_fifo: "Generating: tb_32_256_sc_fifo" Info: tb_32_256_sc_fifo: "Generating: tb_32_256_sc_fifo_fifo_1910_2sdi6ga" Info: tb_32_256_sc_fifo: Done "tb_32_256_sc_fifo" with 2 modules, 2 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Saving generation log to /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/emif_fm_0_generation.rpt Info: Generated by version: 21.2 build 72 Info: Starting: Create simulation model Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_fm_0.emif_fm_0: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. Info: emif_fm_0.emif_fm_0: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. Info: emif_fm_0.emif_fm_0.arch: Agilex EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. Warning: emif_fm_0.emif_fm_0.arch: Per-rank calibration using shadow register cannot be enabled for the current interface and for the currently selected engineering sample device. Interface will be calibrated to the average across ranks instead. Production devices do not have this limitation. Info: emif_fm_0.emif_fm_0.arch: PHY and controller running at quarter-rate for the currently selected engineering sample device. Production devices can run the PHY and controller at half-rate, reducing latency and improving efficiency. Info: emif_fm_0.emif_fm_0.arch: Placement of address/command pins must follow "DDR4 Scheme 2: Component and DIMM". Info: emif_fm_0.emif_fm_0.arch: Interface estimated to require 2 I/O Bank(s) and 3 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. Info: emif_fm_0.emif_fm_0.arch: Valid memory frequencies for the current PLL reference clock of 300.0 MHz and user clock rate, in MHz: 1200.0 Info: emif_fm_0.emif_fm_0.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. Info: emif_fm_0: "Transforming system: emif_fm_0" Info: emif_fm_0: "Naming system components in system: emif_fm_0" Info: emif_fm_0: "Processing generation queue" Info: emif_fm_0: "Generating: emif_fm_0" Info: emif_fm_0: "Generating: emif_fm_0_altera_emif_fm_242_nc44ggy" Info: emif_fm_0: "Generating: emif_fm_0_altera_emif_arch_fm_191_vvqzb7y" Info: emif_fm_0: "Generating: emif_fm_0_altera_emif_ecc_191_futgawq" Info: emif_fm_0: "Generating: altera_emif_ecc_core" Info: emif_fm_0: Done "emif_fm_0" with 5 modules, 61 files Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ directory: Info: common/xcelium_files.tcl Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ directory: Info: common/riviera_files.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ directory: Info: common/modelsim_files.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ directory: Info: common/vcsmx_files.tcl Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ directory: Info: common/ncsim_files.tcl Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ directory: Info: common/vcs_files.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --system-file=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0.ip --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ --use-relative-paths=true Info: Generating the following file(s) for XCELIUM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ directory: Info: xcelium/cds.lib Info: xcelium/hdl.var Info: xcelium/xcelium_setup.sh Info: 5 .cds.lib files in xcelium/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ directory: Info: aldec/rivierapro_setup.tcl Info: Generating the following file(s) for MODELSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCSMX simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 5 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for VCS simulator in /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/ directory: Info: synopsys/vcs/vcs_setup.sh Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0/sim/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0.ip --block-symbol-file --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_fm_0.emif_fm_0: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. Info: emif_fm_0.emif_fm_0: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. Info: emif_fm_0.emif_fm_0.arch: Agilex EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. Warning: emif_fm_0.emif_fm_0.arch: Per-rank calibration using shadow register cannot be enabled for the current interface and for the currently selected engineering sample device. Interface will be calibrated to the average across ranks instead. Production devices do not have this limitation. Info: emif_fm_0.emif_fm_0.arch: PHY and controller running at quarter-rate for the currently selected engineering sample device. Production devices can run the PHY and controller at half-rate, reducing latency and improving efficiency. Info: emif_fm_0.emif_fm_0.arch: Placement of address/command pins must follow "DDR4 Scheme 2: Component and DIMM". Info: emif_fm_0.emif_fm_0.arch: Interface estimated to require 2 I/O Bank(s) and 3 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. Info: emif_fm_0.emif_fm_0.arch: Valid memory frequencies for the current PLL reference clock of 300.0 MHz and user clock rate, in MHz: 1200.0 Info: emif_fm_0.emif_fm_0.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Starting: Create HDL design files for synthesis Info: qsys-generate /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0.ip --synthesis=VERILOG --output-directory=/tmp/workspace/MCD4_UVM_Simulation/default/tao-2/modules/emif_core_SIM_x3/cores/ip/emif_x3rdimm16GB_x8dq_sim/emif_fm_0 --family=Agilex --part=AGFB014R24A2E2VR0 Info: emif_fm_0.emif_fm_0: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. Info: emif_fm_0.emif_fm_0: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. Info: emif_fm_0.emif_fm_0.arch: Agilex EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. Warning: emif_fm_0.emif_fm_0.arch: Per-rank calibration using shadow register cannot be enabled for the current interface and for the currently selected engineering sample device. Interface will be calibrated to the average across ranks instead. Production devices do not have this limitation. Info: emif_fm_0.emif_fm_0.arch: PHY and controller running at quarter-rate for the currently selected engineering sample device. Production devices can run the PHY and controller at half-rate, reducing latency and improving efficiency. Info: emif_fm_0.emif_fm_0.arch: Placement of address/command pins must follow "DDR4 Scheme 2: Component and DIMM". Info: emif_fm_0.emif_fm_0.arch: Interface estimated to require 2 I/O Bank(s) and 3 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. Info: emif_fm_0.emif_fm_0.arch: Valid memory frequencies for the current PLL reference clock of 300.0 MHz and user clock rate, in MHz: 1200.0 Info: emif_fm_0.emif_fm_0.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. Info: emif_fm_0: "Transforming system: emif_fm_0" Info: emif_fm_0: "Naming system components in system: emif_fm_0" Info: emif_fm_0: "Processing generation queue" Info: emif_fm_0: "Generating: emif_fm_0" Info: emif_fm_0: "Generating: emif_fm_0_altera_emif_fm_242_nc44ggy" Info: emif_fm_0: "Generating: emif_fm_0_altera_emif_arch_fm_191_vvqzb7y" Info: emif_fm_0: "Generating: emif_fm_0_altera_emif_ecc_191_futgawq" Info: emif_fm_0: "Generating: altera_emif_ecc_core" Info: emif_fm_0: Done "emif_fm_0" with 5 modules, 71 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis Info: Finished: Platform Designer system generation Info: Finished generating IP file(s) in the project. Info: Quartus Prime IP Generation Tool was successful. 0 errors, 52 warnings Info: Peak virtual memory: 1018 megabytes Info: Processing ended: Wed Jul 6 16:28:28 2022 Info: Elapsed time: 00:03:25 Info: System process ID: 10745 [tao-2] $ /bin/sh -xe /tmp/jenkins5542745835830086039.sh + echo stage 3 stage 3 + cd /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj + /INTELFPGA_PRO_21.2/qsys/bin/ip-setup-simulation --quartus-project=mcd4 --simulator=RIVIERA 2022.07.06.16:28:34 Error: No spd files are included in quartus project /tmp/workspace/MCD4_UVM_Simulation/default/tao-2/mcd4/quartus_proj/mcd4.qpf, revision mcd4. *************************************************************** Quartus is a registered trademark of Intel Corporation in the US and other countries. Portions of the Quartus Prime software code, and other portions of the code included in this download or on this DVD, are licensed to Intel Corporation and are the copyrighted property of third parties. For license details, refer to the End User License Agreement at http://fpgasoftware.intel.com/eula. *************************************************************** Build step 'Execute shell' marked build as failure Sending e-mails to: greg.beaton@spacebridge.com No GitLab connection configured Started calculate disk usage of build Finished Calculation of disk usage of build in 0 seconds Started calculate disk usage of workspace Finished Calculation of disk usage of workspace in 0 seconds Finished: FAILURE