# Copyright (C) 2023  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the Intel FPGA Software License Subscription Agreements 
# on the Quartus Prime software download page.

# Quartus Prime: Generate Tcl File for Project
# File: project.tcl
# Generated on: Wed Oct 18 17:00:18 2023

# Load Quartus Prime Tcl Project package
package require ::quartus::project

set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
	if {[string compare $quartus(project) "test"]} {
		puts "Project test is not open"
		set make_assignments 0
	}
} else {
	# Only open if not already open
	if {[project_exists test]} {
		project_open -revision test test
	} else {
		project_new -revision test test
	}
	set need_to_close_project 1
}

# Make assignments
if {$make_assignments} {
	set_global_assignment -name TOP_LEVEL_ENTITY IPM_IOPLL_BASIC_Wrapper
	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 23.3.0
	set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:31:47  JULY 31, 2023"
	set_global_assignment -name LAST_QUARTUS_VERSION "23.3.0 Pro Edition"
	set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
	set_global_assignment -name DEVICE AGFB014R24A3E3V
	set_global_assignment -name FAMILY "Agilex 7"
	set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
	set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
	set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
	set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
	set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON
	set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2012
	set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL
	set_global_assignment -name VHDL_FILE IPM_IOPLL_BASIC_Wrapper.vhd
	set_parameter -name REFERENCE_CLOCK_FREQUENCY "1000000.0 MHz"

	# Commit assignments
	export_assignments

	# Close project
	if {$need_to_close_project} {
		project_close
	}
}