Compiler Command: aoc -v --report --board a10gx device/hello_world.cl -o bin/hello_world.aocx +--------------------------------------------------------------------+ ; Estimated Resource Usage Summary ; +----------------------------------------+---------------------------+ ; Resource + Usage ; +----------------------------------------+---------------------------+ ; Logic utilization ; 17% ; ; ALUTs ; 9% ; ; Dedicated logic registers ; 9% ; ; Memory blocks ; 8% ; ; DSP blocks ; 0% ; +----------------------------------------+---------------------------; System name: hello_world 2017.05.23.17:58:13 Info: Doing: qsys-script --quartus-project=top --script=kernel_system.tcl --Xmx512M --XX:+UseSerialGC 2017.05.23.17:58:18 Info: set_validation_property AUTOMATIC_VALIDATION false 2017.05.23.17:58:18 Info: add_instance clk_1x altera_clock_bridge 2017.05.23.17:58:18 Info: set_instance_parameter_value clk_1x EXPLICIT_CLOCK_RATE 0 2017.05.23.17:58:18 Info: set_instance_parameter_value clk_1x NUM_CLOCK_OUTPUTS 1 2017.05.23.17:58:18 Info: add_interface clock_reset clock sink 2017.05.23.17:58:18 Info: set_interface_property clock_reset EXPORT_OF clk_1x.in_clk 2017.05.23.17:58:18 Info: add_instance clk_2x altera_clock_bridge 2017.05.23.17:58:18 Info: set_instance_parameter_value clk_2x EXPLICIT_CLOCK_RATE 0 2017.05.23.17:58:18 Info: set_instance_parameter_value clk_2x NUM_CLOCK_OUTPUTS 1 2017.05.23.17:58:18 Info: add_interface clock_reset2x clock sink 2017.05.23.17:58:18 Info: set_interface_property clock_reset2x EXPORT_OF clk_2x.in_clk 2017.05.23.17:58:18 Info: add_instance clk_snoop altera_clock_bridge 2017.05.23.17:58:18 Info: set_instance_parameter_value clk_snoop EXPLICIT_CLOCK_RATE 0 2017.05.23.17:58:18 Info: set_instance_parameter_value clk_snoop NUM_CLOCK_OUTPUTS 1 2017.05.23.17:58:18 Info: add_interface cc_snoop_clk clock sink 2017.05.23.17:58:18 Info: set_interface_property cc_snoop_clk EXPORT_OF clk_snoop.in_clk 2017.05.23.17:58:18 Info: add_instance reset altera_reset_bridge 2017.05.23.17:58:18 Info: set_instance_parameter_value reset ACTIVE_LOW_RESET 1 2017.05.23.17:58:18 Info: set_instance_parameter_value reset SYNCHRONOUS_EDGES deassert 2017.05.23.17:58:18 Info: set_instance_parameter_value reset NUM_RESET_OUTPUTS 1 2017.05.23.17:58:18 Info: add_interface clock_reset_reset reset sink 2017.05.23.17:58:18 Info: set_interface_property clock_reset_reset EXPORT_OF reset.in_reset 2017.05.23.17:58:18 Info: add_connection clk_1x.out_clk reset.clk 2017.05.23.17:58:18 Info: add_instance hello_world_system hello_world_system 2017.05.23.17:58:19 Info: add_connection clk_1x.out_clk hello_world_system.clock_reset 2017.05.23.17:58:19 Info: add_connection clk_2x.out_clk hello_world_system.clock_reset2x 2017.05.23.17:58:19 Info: add_connection reset.out_reset hello_world_system.clock_reset_reset 2017.05.23.17:58:19 Info: add_instance kernel_mem0 altera_avalon_mm_bridge 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_mem0 DATA_WIDTH 512 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_mem0 SYMBOL_WIDTH 8 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_mem0 ADDRESS_WIDTH 31 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_mem0 USE_AUTO_ADDRESS_WIDTH 0 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_mem0 ADDRESS_UNITS SYMBOLS 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_mem0 MAX_BURST_SIZE 16 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_mem0 MAX_PENDING_RESPONSES 64 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_mem0 LINEWRAPBURSTS 0 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_mem0 PIPELINE_COMMAND 1 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_mem0 PIPELINE_RESPONSE 1 2017.05.23.17:58:19 Info: add_connection clk_1x.out_clk kernel_mem0.clk 2017.05.23.17:58:19 Info: add_connection reset.out_reset kernel_mem0.reset 2017.05.23.17:58:19 Info: add_interface kernel_mem0 avalon slave 2017.05.23.17:58:19 Info: set_interface_property kernel_mem0 EXPORT_OF kernel_mem0.m0 2017.05.23.17:58:19 Info: add_connection hello_world_system.avm_memgmem0_DDR_port_0_0_rw kernel_mem0.s0 2017.05.23.17:58:19 Info: add_instance kernel_irq altera_irq_bridge 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_irq IRQ_WIDTH 1 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_irq IRQ_N 0 2017.05.23.17:58:19 Info: add_interface kernel_irq irq sender 2017.05.23.17:58:19 Info: set_interface_property kernel_irq EXPORT_OF kernel_irq.sender0_irq 2017.05.23.17:58:19 Info: add_connection clk_1x.out_clk kernel_irq.clk 2017.05.23.17:58:19 Info: add_connection reset.out_reset kernel_irq.clk_reset 2017.05.23.17:58:19 Info: add_connection kernel_irq.receiver_irq hello_world_system.kernel_irq 2017.05.23.17:58:19 Info: add_instance kernel_cra altera_avalon_mm_bridge 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_cra DATA_WIDTH 64 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_cra SYMBOL_WIDTH 8 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_cra ADDRESS_WIDTH 30 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_cra USE_AUTO_ADDRESS_WIDTH 0 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_cra ADDRESS_UNITS SYMBOLS 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_cra MAX_BURST_SIZE 1 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_cra MAX_PENDING_RESPONSES 1 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_cra LINEWRAPBURSTS 0 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_cra PIPELINE_COMMAND 0 2017.05.23.17:58:19 Info: set_instance_parameter_value kernel_cra PIPELINE_RESPONSE 0 2017.05.23.17:58:19 Info: add_connection clk_1x.out_clk kernel_cra.clk 2017.05.23.17:58:19 Info: add_connection reset.out_reset kernel_cra.reset 2017.05.23.17:58:19 Info: add_interface avs_kernel_cra avalon slave 2017.05.23.17:58:19 Info: set_interface_property kernel_cra EXPORT_OF kernel_cra.s0 2017.05.23.17:58:19 Info: add_instance cra_root cra_ring_root 2017.05.23.17:58:19 Info: set_instance_parameter_value cra_root DATA_W 64 2017.05.23.17:58:19 Info: set_instance_parameter_value cra_root ADDR_W 4 2017.05.23.17:58:19 Info: set_instance_parameter_value cra_root ID_W 0 2017.05.23.17:58:19 Info: set_instance_parameter_value cra_root ROM_ENABLE 1 2017.05.23.17:58:19 Info: add_connection clk_1x.out_clk cra_root.clock 2017.05.23.17:58:19 Info: add_connection reset.out_reset cra_root.reset 2017.05.23.17:58:19 Info: add_connection kernel_cra.m0 cra_root.cra_slave 2017.05.23.17:58:19 Info: set_connection_parameter_value kernel_cra.m0/cra_root.cra_slave baseAddress 0x0 2017.05.23.17:58:19 Info: add_instance cra_ring_rom cra_ring_rom 2017.05.23.17:58:19 Info: set_instance_parameter_value cra_ring_rom DATA_W 64 2017.05.23.17:58:19 Info: set_instance_parameter_value cra_ring_rom RING_ADDR_W 4 2017.05.23.17:58:19 Info: set_instance_parameter_value cra_ring_rom ID_W 0 2017.05.23.17:58:19 Info: add_connection cra_root.ring_out cra_ring_rom.ring_in 2017.05.23.17:58:19 Info: add_connection clk_1x.out_clk cra_ring_rom.clock 2017.05.23.17:58:19 Info: add_connection reset.out_reset cra_ring_rom.reset 2017.05.23.17:58:19 Info: add_instance avs_hello_world_cra_cra_ring cra_ring_node 2017.05.23.17:58:19 Info: set_instance_parameter_value avs_hello_world_cra_cra_ring DATA_W 64 2017.05.23.17:58:19 Info: set_instance_parameter_value avs_hello_world_cra_cra_ring RING_ADDR_W 4 2017.05.23.17:58:19 Info: set_instance_parameter_value avs_hello_world_cra_cra_ring CRA_ADDR_W 4 2017.05.23.17:58:19 Info: set_instance_parameter_value avs_hello_world_cra_cra_ring ID_W 0 2017.05.23.17:58:19 Info: set_instance_parameter_value avs_hello_world_cra_cra_ring ID 0 2017.05.23.17:58:19 Info: add_connection clk_1x.out_clk avs_hello_world_cra_cra_ring.clock 2017.05.23.17:58:19 Info: add_connection reset.out_reset avs_hello_world_cra_cra_ring.reset 2017.05.23.17:58:19 Info: add_connection cra_ring_rom.ring_out avs_hello_world_cra_cra_ring.ring_in 2017.05.23.17:58:19 Info: add_connection avs_hello_world_cra_cra_ring.cra_master hello_world_system.avs_hello_world_cra 2017.05.23.17:58:19 Info: set_connection_parameter_value avs_hello_world_cra_cra_ring.cra_master/hello_world_system.avs_hello_world_cra baseAddress 0x0 2017.05.23.17:58:19 Info: add_connection avs_hello_world_cra_cra_ring.ring_out cra_root.ring_in 2017.05.23.17:58:19 Info: add_instance acl_internal_snoop altera_avalon_st_adapter 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop inBitsPerSymbol 31 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop inUsePackets 0 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop inDataWidth 31 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop inMaxChannel 0 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop inChannelWidth 0 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop inErrorWidth 0 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop inErrorDescriptor 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop inUseEmptyPort 0 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop inUseValid 1 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop inUseReady 1 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop inReadyLatency 0 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop outDataWidth 31 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop outMaxChannel 0 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop outChannelWidth 0 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop outErrorWidth 0 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop outErrorDescriptor 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop outUseEmptyPort 0 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop outUseValid 1 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop outUseReady 1 2017.05.23.17:58:19 Info: set_instance_parameter_value acl_internal_snoop outReadyLatency 0 2017.05.23.17:58:19 Info: add_connection clk_snoop.out_clk acl_internal_snoop.in_clk_0 2017.05.23.17:58:19 Info: add_connection reset.out_reset acl_internal_snoop.in_rst_0 2017.05.23.17:58:19 Info: add_interface cc_snoop avalon_streaming sink 2017.05.23.17:58:19 Info: set_interface_property cc_snoop EXPORT_OF acl_internal_snoop.in_0 2017.05.23.17:58:19 Info: add_instance sys_description_rom acl_rom_module 2017.05.23.17:58:19 Info: set_instance_parameter_value sys_description_rom INIT_FILE sys_description.hex 2017.05.23.17:58:19 Info: set_instance_parameter_value sys_description_rom ADDRESS_WIDTH 4 2017.05.23.17:58:19 Warning: add_connection: Extra arguments ignored clock 2017.05.23.17:58:19 Info: add_connection clk_1x.out_clk sys_description_rom.clk0 2017.05.23.17:58:19 Warning: add_connection: Extra arguments ignored reset 2017.05.23.17:58:19 Info: add_connection reset.out_reset sys_description_rom.reset0 2017.05.23.17:58:19 Info: set_instance_parameter_value sys_description_rom DATA_WIDTH 64 2017.05.23.17:58:19 Warning: add_connection: Extra arguments ignored avalon 2017.05.23.17:58:19 Info: add_connection cra_ring_rom.cra_master sys_description_rom.s0 2017.05.23.17:58:19 Info: set_instance_parameter_value sys_description_rom ADDRESS_WIDTH 5 2017.05.23.17:58:19 Info: set_instance_parameter_value cra_ring_rom ROM_W 5 2017.05.23.17:58:19 Info: set_instance_parameter_value cra_ring_rom ROM_EXT_W 1 2017.05.23.17:58:19 Info: set_instance_parameter_value cra_root ROM_EXT_W 1 2017.05.23.17:58:19 Info: save_system kernel_system.qsys 2017.05.23.17:58:19 Info: Replacing kernel_system.clk_1x with generic component 2017.05.23.17:58:20 Info: Replacing kernel_system.clk_2x with generic component 2017.05.23.17:58:20 Info: Replacing kernel_system.clk_snoop with generic component 2017.05.23.17:58:20 Info: Replacing kernel_system.reset with generic component 2017.05.23.17:58:20 Info: Replacing kernel_system.hello_world_system with generic component 2017.05.23.17:58:21 Info: Replacing kernel_system.kernel_mem0 with generic component 2017.05.23.17:58:21 Info: Replacing kernel_system.kernel_irq with generic component 2017.05.23.17:58:21 Info: Replacing kernel_system.kernel_cra with generic component 2017.05.23.17:58:21 Info: Replacing kernel_system.cra_root with generic component 2017.05.23.17:58:21 Info: Replacing kernel_system.cra_ring_rom with generic component 2017.05.23.17:58:22 Info: Replacing kernel_system.avs_hello_world_cra_cra_ring with generic component 2017.05.23.17:58:22 Info: Replacing kernel_system.acl_internal_snoop with generic component 2017.05.23.17:58:22 Info: Replacing kernel_system.sys_description_rom with generic component 2017.05.23.17:58:22 Info: Info: All modules have been converted to Generic Components. Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 17.0.0 Build 290 04/26/2017 SJ Pro Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Intel and sold by Intel or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Tue May 23 17:58:28 2017 Info: Command: quartus_sh --restore -output . base.qar Info: Quartus(args): -unqar -output . base.qar Info: Using INI file /root/Documents/hello_world/bin/hello_world/quartus.ini Info: qar.tcl version #3 Info (125061): Changed top-level design entity name to "top" Info (125061): Changed top-level design entity name to "kernel_system" Info: Successfully restored '/root/Documents/hello_world/bin/hello_world/base.qar' into the '.' directory Info: Generated report 'opencl_bsp_ip.restore.rpt' Info (23030): Evaluation of Tcl script /root/intelFPGA_pro/17.0/quartus/common/tcl/apps/qpm/qar.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1288 megabytes Info: Processing ended: Tue May 23 17:58:35 2017 Info: Elapsed time: 00:00:07 Info: Total CPU time (on all processors): 00:00:07 2017.05.23.17:58:36 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision. 2017.05.23.17:58:41 Info: kernel_system: All Generic Component instances match their respective ip files. 2017.05.23.17:58:41 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_kernel_cra/kernel_system_kernel_cra_generation.rpt 2017.05.23.17:58:41 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:41 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:41 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_kernel_cra.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_kernel_cra --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:42 Info: kernel_system_kernel_cra: "Transforming system: kernel_system_kernel_cra" 2017.05.23.17:58:42 Info: kernel_system_kernel_cra: Running transform generation_view_transform 2017.05.23.17:58:42 Info: kernel_system_kernel_cra: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:42 Info: kernel_cra: Running transform generation_view_transform 2017.05.23.17:58:42 Info: kernel_cra: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:42 Info: kernel_system_kernel_cra: Running transform interconnect_transform_chooser 2017.05.23.17:58:42 Info: kernel_system_kernel_cra: Running transform interconnect_transform_chooser took 0.036s 2017.05.23.17:58:42 Info: kernel_system_kernel_cra: "Naming system components in system: kernel_system_kernel_cra" 2017.05.23.17:58:42 Info: kernel_system_kernel_cra: "Processing generation queue" 2017.05.23.17:58:42 Info: kernel_system_kernel_cra: "Generating: kernel_system_kernel_cra" 2017.05.23.17:58:42 Info: kernel_system_kernel_cra: "Generating: altera_avalon_mm_bridge" 2017.05.23.17:58:42 Info: kernel_system_kernel_cra: Done "kernel_system_kernel_cra" with 2 modules, 2 files 2017.05.23.17:58:42 Info: qsys-generate succeeded. 2017.05.23.17:58:42 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:42 Info: 2017.05.23.17:58:42 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_acl_internal_snoop/kernel_system_acl_internal_snoop_generation.rpt 2017.05.23.17:58:42 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:42 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:42 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_acl_internal_snoop.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_acl_internal_snoop --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:42 Warning: kernel_system_acl_internal_snoop.acl_internal_snoop: No adaptation is needed; a pass through bridge is inserted 2017.05.23.17:58:42 Info: kernel_system_acl_internal_snoop.acl_internal_snoop: Inserting channel_adapter: pass_through_0 2017.05.23.17:58:42 Info: kernel_system_acl_internal_snoop: "Transforming system: kernel_system_acl_internal_snoop" 2017.05.23.17:58:42 Info: kernel_system_acl_internal_snoop: Running transform generation_view_transform 2017.05.23.17:58:42 Info: kernel_system_acl_internal_snoop: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:42 Info: acl_internal_snoop: Running transform generation_view_transform 2017.05.23.17:58:42 Info: acl_internal_snoop: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:42 Info: clk_bridge_0: Running transform generation_view_transform 2017.05.23.17:58:42 Info: clk_bridge_0: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:42 Info: rst_bridge_0: Running transform generation_view_transform 2017.05.23.17:58:42 Info: rst_bridge_0: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:42 Info: pass_through_0: Running transform generation_view_transform 2017.05.23.17:58:42 Info: pass_through_0: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:42 Info: kernel_system_acl_internal_snoop: Running transform interconnect_transform_chooser 2017.05.23.17:58:42 Info: kernel_system_acl_internal_snoop: Running transform interconnect_transform_chooser took 0.008s 2017.05.23.17:58:42 Info: acl_internal_snoop: Running transform interconnect_transform_chooser 2017.05.23.17:58:42 Info: acl_internal_snoop: Running transform interconnect_transform_chooser took 0.009s 2017.05.23.17:58:42 Info: kernel_system_acl_internal_snoop: "Naming system components in system: kernel_system_acl_internal_snoop" 2017.05.23.17:58:42 Info: kernel_system_acl_internal_snoop: "Processing generation queue" 2017.05.23.17:58:42 Info: kernel_system_acl_internal_snoop: "Generating: kernel_system_acl_internal_snoop" 2017.05.23.17:58:42 Info: kernel_system_acl_internal_snoop: "Generating: kernel_system_acl_internal_snoop_altera_avalon_st_adapter_170_i6koa2q" 2017.05.23.17:58:42 Info: kernel_system_acl_internal_snoop: "Generating: kernel_system_acl_internal_snoop_channel_adapter_170_rzlgisa" 2017.05.23.17:58:42 Info: kernel_system_acl_internal_snoop: Done "kernel_system_acl_internal_snoop" with 3 modules, 3 files 2017.05.23.17:58:42 Info: qsys-generate succeeded. 2017.05.23.17:58:42 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:42 Info: 2017.05.23.17:58:42 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_kernel_irq/kernel_system_kernel_irq_generation.rpt 2017.05.23.17:58:42 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:42 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:42 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_kernel_irq.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_kernel_irq --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:43 Info: kernel_system_kernel_irq: "Transforming system: kernel_system_kernel_irq" 2017.05.23.17:58:43 Info: kernel_system_kernel_irq: Running transform generation_view_transform 2017.05.23.17:58:43 Info: kernel_system_kernel_irq: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:43 Info: kernel_irq: Running transform generation_view_transform 2017.05.23.17:58:43 Info: kernel_irq: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:43 Info: kernel_system_kernel_irq: Running transform interconnect_transform_chooser 2017.05.23.17:58:43 Info: kernel_system_kernel_irq: Running transform interconnect_transform_chooser took 0.008s 2017.05.23.17:58:43 Info: kernel_system_kernel_irq: "Naming system components in system: kernel_system_kernel_irq" 2017.05.23.17:58:43 Info: kernel_system_kernel_irq: "Processing generation queue" 2017.05.23.17:58:43 Info: kernel_system_kernel_irq: "Generating: kernel_system_kernel_irq" 2017.05.23.17:58:43 Info: kernel_system_kernel_irq: "Generating: altera_irq_bridge" 2017.05.23.17:58:43 Info: kernel_system_kernel_irq: Done "kernel_system_kernel_irq" with 2 modules, 2 files 2017.05.23.17:58:43 Info: qsys-generate succeeded. 2017.05.23.17:58:43 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:43 Info: 2017.05.23.17:58:43 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_clk_1x/kernel_system_clk_1x_generation.rpt 2017.05.23.17:58:43 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:43 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:43 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_clk_1x.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_clk_1x --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:43 Info: kernel_system_clk_1x: "Transforming system: kernel_system_clk_1x" 2017.05.23.17:58:43 Info: kernel_system_clk_1x: Running transform generation_view_transform 2017.05.23.17:58:43 Info: kernel_system_clk_1x: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:43 Info: clk_1x: Running transform generation_view_transform 2017.05.23.17:58:43 Info: clk_1x: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:43 Info: kernel_system_clk_1x: Running transform interconnect_transform_chooser 2017.05.23.17:58:43 Info: kernel_system_clk_1x: Running transform interconnect_transform_chooser took 0.007s 2017.05.23.17:58:43 Info: kernel_system_clk_1x: "Naming system components in system: kernel_system_clk_1x" 2017.05.23.17:58:43 Info: kernel_system_clk_1x: "Processing generation queue" 2017.05.23.17:58:43 Info: kernel_system_clk_1x: "Generating: kernel_system_clk_1x" 2017.05.23.17:58:43 Info: kernel_system_clk_1x: Done "kernel_system_clk_1x" with 1 modules, 1 files 2017.05.23.17:58:43 Info: qsys-generate succeeded. 2017.05.23.17:58:43 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:43 Info: 2017.05.23.17:58:43 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_clk_snoop/kernel_system_clk_snoop_generation.rpt 2017.05.23.17:58:43 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:43 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:43 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_clk_snoop.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_clk_snoop --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:43 Info: kernel_system_clk_snoop: "Transforming system: kernel_system_clk_snoop" 2017.05.23.17:58:43 Info: kernel_system_clk_snoop: Running transform generation_view_transform 2017.05.23.17:58:43 Info: kernel_system_clk_snoop: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:43 Info: clk_snoop: Running transform generation_view_transform 2017.05.23.17:58:43 Info: clk_snoop: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:43 Info: kernel_system_clk_snoop: Running transform interconnect_transform_chooser 2017.05.23.17:58:43 Info: kernel_system_clk_snoop: Running transform interconnect_transform_chooser took 0.008s 2017.05.23.17:58:43 Info: kernel_system_clk_snoop: "Naming system components in system: kernel_system_clk_snoop" 2017.05.23.17:58:43 Info: kernel_system_clk_snoop: "Processing generation queue" 2017.05.23.17:58:43 Info: kernel_system_clk_snoop: "Generating: kernel_system_clk_snoop" 2017.05.23.17:58:43 Info: kernel_system_clk_snoop: Done "kernel_system_clk_snoop" with 1 modules, 1 files 2017.05.23.17:58:43 Info: qsys-generate succeeded. 2017.05.23.17:58:43 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:43 Info: 2017.05.23.17:58:43 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_hello_world_cra_cra_ring/kernel_system_avs_hello_world_cra_cra_ring_generation.rpt 2017.05.23.17:58:43 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:43 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:43 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_hello_world_cra_cra_ring.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_hello_world_cra_cra_ring --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:44 Info: kernel_system_avs_hello_world_cra_cra_ring: "Transforming system: kernel_system_avs_hello_world_cra_cra_ring" 2017.05.23.17:58:44 Info: kernel_system_avs_hello_world_cra_cra_ring: Running transform generation_view_transform 2017.05.23.17:58:44 Info: kernel_system_avs_hello_world_cra_cra_ring: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:44 Info: avs_hello_world_cra_cra_ring: Running transform generation_view_transform 2017.05.23.17:58:44 Info: avs_hello_world_cra_cra_ring: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:44 Info: kernel_system_avs_hello_world_cra_cra_ring: Running transform interconnect_transform_chooser 2017.05.23.17:58:44 Info: kernel_system_avs_hello_world_cra_cra_ring: Running transform interconnect_transform_chooser took 0.008s 2017.05.23.17:58:44 Info: kernel_system_avs_hello_world_cra_cra_ring: "Naming system components in system: kernel_system_avs_hello_world_cra_cra_ring" 2017.05.23.17:58:44 Info: kernel_system_avs_hello_world_cra_cra_ring: "Processing generation queue" 2017.05.23.17:58:44 Info: kernel_system_avs_hello_world_cra_cra_ring: "Generating: kernel_system_avs_hello_world_cra_cra_ring" 2017.05.23.17:58:44 Info: kernel_system_avs_hello_world_cra_cra_ring: "Generating: cra_ring_node" 2017.05.23.17:58:44 Info: kernel_system_avs_hello_world_cra_cra_ring: Done "kernel_system_avs_hello_world_cra_cra_ring" with 2 modules, 2 files 2017.05.23.17:58:44 Info: qsys-generate succeeded. 2017.05.23.17:58:44 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:44 Info: 2017.05.23.17:58:44 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_sys_description_rom/kernel_system_sys_description_rom_generation.rpt 2017.05.23.17:58:44 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:44 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:44 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_sys_description_rom.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_sys_description_rom --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:44 Info: kernel_system_sys_description_rom: "Transforming system: kernel_system_sys_description_rom" 2017.05.23.17:58:44 Info: kernel_system_sys_description_rom: Running transform generation_view_transform 2017.05.23.17:58:44 Info: kernel_system_sys_description_rom: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:44 Info: sys_description_rom: Running transform generation_view_transform 2017.05.23.17:58:44 Info: sys_description_rom: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:44 Info: kernel_system_sys_description_rom: Running transform interconnect_transform_chooser 2017.05.23.17:58:44 Info: kernel_system_sys_description_rom: Running transform interconnect_transform_chooser took 0.009s 2017.05.23.17:58:44 Info: kernel_system_sys_description_rom: "Naming system components in system: kernel_system_sys_description_rom" 2017.05.23.17:58:44 Info: kernel_system_sys_description_rom: "Processing generation queue" 2017.05.23.17:58:44 Info: kernel_system_sys_description_rom: "Generating: kernel_system_sys_description_rom" 2017.05.23.17:58:44 Info: kernel_system_sys_description_rom: "Generating: acl_rom_module" 2017.05.23.17:58:44 Info: kernel_system_sys_description_rom: Done "kernel_system_sys_description_rom" with 2 modules, 2 files 2017.05.23.17:58:44 Info: qsys-generate succeeded. 2017.05.23.17:58:44 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:44 Info: 2017.05.23.17:58:44 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_reset/kernel_system_reset_generation.rpt 2017.05.23.17:58:44 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:44 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:44 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_reset.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_reset --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:44 Info: kernel_system_reset: "Transforming system: kernel_system_reset" 2017.05.23.17:58:44 Info: kernel_system_reset: Running transform generation_view_transform 2017.05.23.17:58:44 Info: kernel_system_reset: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:44 Info: reset: Running transform generation_view_transform 2017.05.23.17:58:44 Info: reset: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:44 Info: kernel_system_reset: Running transform interconnect_transform_chooser 2017.05.23.17:58:44 Info: kernel_system_reset: Running transform interconnect_transform_chooser took 0.008s 2017.05.23.17:58:44 Info: kernel_system_reset: "Naming system components in system: kernel_system_reset" 2017.05.23.17:58:44 Info: kernel_system_reset: "Processing generation queue" 2017.05.23.17:58:44 Info: kernel_system_reset: "Generating: kernel_system_reset" 2017.05.23.17:58:44 Info: kernel_system_reset: Done "kernel_system_reset" with 1 modules, 1 files 2017.05.23.17:58:44 Info: qsys-generate succeeded. 2017.05.23.17:58:44 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:44 Info: 2017.05.23.17:58:45 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_kernel_mem0/kernel_system_kernel_mem0_generation.rpt 2017.05.23.17:58:45 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:45 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:45 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_kernel_mem0.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_kernel_mem0 --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:45 Info: kernel_system_kernel_mem0: "Transforming system: kernel_system_kernel_mem0" 2017.05.23.17:58:45 Info: kernel_system_kernel_mem0: Running transform generation_view_transform 2017.05.23.17:58:45 Info: kernel_system_kernel_mem0: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:45 Info: kernel_mem0: Running transform generation_view_transform 2017.05.23.17:58:45 Info: kernel_mem0: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:45 Info: kernel_system_kernel_mem0: Running transform interconnect_transform_chooser 2017.05.23.17:58:45 Info: kernel_system_kernel_mem0: Running transform interconnect_transform_chooser took 0.008s 2017.05.23.17:58:45 Info: kernel_system_kernel_mem0: "Naming system components in system: kernel_system_kernel_mem0" 2017.05.23.17:58:45 Info: kernel_system_kernel_mem0: "Processing generation queue" 2017.05.23.17:58:45 Info: kernel_system_kernel_mem0: "Generating: kernel_system_kernel_mem0" 2017.05.23.17:58:45 Info: kernel_system_kernel_mem0: "Generating: altera_avalon_mm_bridge" 2017.05.23.17:58:45 Info: kernel_system_kernel_mem0: Done "kernel_system_kernel_mem0" with 2 modules, 2 files 2017.05.23.17:58:45 Info: qsys-generate succeeded. 2017.05.23.17:58:45 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:45 Info: 2017.05.23.17:58:45 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_hello_world_system/kernel_system_hello_world_system_generation.rpt 2017.05.23.17:58:45 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:45 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:45 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_hello_world_system.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_hello_world_system --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:45 Info: kernel_system_hello_world_system: "Transforming system: kernel_system_hello_world_system" 2017.05.23.17:58:45 Info: kernel_system_hello_world_system: Running transform generation_view_transform 2017.05.23.17:58:45 Info: kernel_system_hello_world_system: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:45 Info: hello_world_system: Running transform generation_view_transform 2017.05.23.17:58:45 Info: hello_world_system: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:45 Info: kernel_system_hello_world_system: Running transform interconnect_transform_chooser 2017.05.23.17:58:45 Info: kernel_system_hello_world_system: Running transform interconnect_transform_chooser took 0.008s 2017.05.23.17:58:45 Info: kernel_system_hello_world_system: "Naming system components in system: kernel_system_hello_world_system" 2017.05.23.17:58:45 Info: kernel_system_hello_world_system: "Processing generation queue" 2017.05.23.17:58:45 Info: kernel_system_hello_world_system: "Generating: kernel_system_hello_world_system" 2017.05.23.17:58:45 Info: kernel_system_hello_world_system: "Generating: hello_world_system" 2017.05.23.17:58:45 Info: kernel_system_hello_world_system: Done "kernel_system_hello_world_system" with 2 modules, 63 files 2017.05.23.17:58:45 Info: qsys-generate succeeded. 2017.05.23.17:58:45 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:45 Info: 2017.05.23.17:58:45 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_clk_2x/kernel_system_clk_2x_generation.rpt 2017.05.23.17:58:45 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:45 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:45 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_clk_2x.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_clk_2x --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:45 Info: kernel_system_clk_2x: "Transforming system: kernel_system_clk_2x" 2017.05.23.17:58:45 Info: kernel_system_clk_2x: Running transform generation_view_transform 2017.05.23.17:58:45 Info: kernel_system_clk_2x: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:45 Info: clk_2x: Running transform generation_view_transform 2017.05.23.17:58:45 Info: clk_2x: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:45 Info: kernel_system_clk_2x: Running transform interconnect_transform_chooser 2017.05.23.17:58:45 Info: kernel_system_clk_2x: Running transform interconnect_transform_chooser took 0.008s 2017.05.23.17:58:45 Info: kernel_system_clk_2x: "Naming system components in system: kernel_system_clk_2x" 2017.05.23.17:58:45 Info: kernel_system_clk_2x: "Processing generation queue" 2017.05.23.17:58:45 Info: kernel_system_clk_2x: "Generating: kernel_system_clk_2x" 2017.05.23.17:58:45 Info: kernel_system_clk_2x: Done "kernel_system_clk_2x" with 1 modules, 1 files 2017.05.23.17:58:45 Info: qsys-generate succeeded. 2017.05.23.17:58:45 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:45 Info: 2017.05.23.17:58:46 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_cra_root/kernel_system_cra_root_generation.rpt 2017.05.23.17:58:46 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:46 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:46 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_cra_root.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_cra_root --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:46 Info: kernel_system_cra_root: "Transforming system: kernel_system_cra_root" 2017.05.23.17:58:46 Info: kernel_system_cra_root: Running transform generation_view_transform 2017.05.23.17:58:46 Info: kernel_system_cra_root: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:46 Info: cra_root: Running transform generation_view_transform 2017.05.23.17:58:46 Info: cra_root: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:46 Info: kernel_system_cra_root: Running transform interconnect_transform_chooser 2017.05.23.17:58:46 Info: kernel_system_cra_root: Running transform interconnect_transform_chooser took 0.009s 2017.05.23.17:58:46 Info: kernel_system_cra_root: "Naming system components in system: kernel_system_cra_root" 2017.05.23.17:58:46 Info: kernel_system_cra_root: "Processing generation queue" 2017.05.23.17:58:46 Info: kernel_system_cra_root: "Generating: kernel_system_cra_root" 2017.05.23.17:58:46 Info: kernel_system_cra_root: "Generating: cra_ring_root" 2017.05.23.17:58:46 Info: kernel_system_cra_root: Done "kernel_system_cra_root" with 2 modules, 2 files 2017.05.23.17:58:46 Info: qsys-generate succeeded. 2017.05.23.17:58:46 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:46 Info: 2017.05.23.17:58:46 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_cra_ring_rom/kernel_system_cra_ring_rom_generation.rpt 2017.05.23.17:58:46 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:46 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:46 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_cra_ring_rom.ip --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/ip/kernel_system/kernel_system_cra_ring_rom --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:46 Info: kernel_system_cra_ring_rom: "Transforming system: kernel_system_cra_ring_rom" 2017.05.23.17:58:46 Info: kernel_system_cra_ring_rom: Running transform generation_view_transform 2017.05.23.17:58:46 Info: kernel_system_cra_ring_rom: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:46 Info: cra_ring_rom: Running transform generation_view_transform 2017.05.23.17:58:46 Info: cra_ring_rom: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:46 Info: kernel_system_cra_ring_rom: Running transform interconnect_transform_chooser 2017.05.23.17:58:46 Info: kernel_system_cra_ring_rom: Running transform interconnect_transform_chooser took 0.008s 2017.05.23.17:58:46 Info: kernel_system_cra_ring_rom: "Naming system components in system: kernel_system_cra_ring_rom" 2017.05.23.17:58:46 Info: kernel_system_cra_ring_rom: "Processing generation queue" 2017.05.23.17:58:46 Info: kernel_system_cra_ring_rom: "Generating: kernel_system_cra_ring_rom" 2017.05.23.17:58:46 Info: kernel_system_cra_ring_rom: "Generating: cra_ring_rom" 2017.05.23.17:58:46 Info: kernel_system_cra_ring_rom: Done "kernel_system_cra_ring_rom" with 2 modules, 2 files 2017.05.23.17:58:46 Info: qsys-generate succeeded. 2017.05.23.17:58:46 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:46 Info: 2017.05.23.17:58:46 Info: Saving generation log to /root/Documents/hello_world/bin/hello_world/kernel_system/kernel_system_generation.rpt 2017.05.23.17:58:46 Info: Generated by version: 17.0 build 290 2017.05.23.17:58:46 Info: Starting: Create HDL design files for synthesis 2017.05.23.17:58:46 Info: qsys-generate /root/Documents/hello_world/bin/hello_world/kernel_system.qsys --synthesis=VERILOG --output-directory=/root/Documents/hello_world/bin/hello_world/kernel_system --family="Arria 10" --part=10AX115S2F45I1SG 2017.05.23.17:58:46 Info: Loading hello_world/kernel_system.qsys 2017.05.23.17:58:46 Info: Reading input file 2017.05.23.17:58:46 Info: Adding acl_internal_snoop [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module acl_internal_snoop 2017.05.23.17:58:46 Info: Adding avs_hello_world_cra_cra_ring [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module avs_hello_world_cra_cra_ring 2017.05.23.17:58:46 Info: Adding clk_1x [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module clk_1x 2017.05.23.17:58:46 Info: Adding clk_2x [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module clk_2x 2017.05.23.17:58:46 Info: Adding clk_snoop [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module clk_snoop 2017.05.23.17:58:46 Info: Adding cra_ring_rom [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module cra_ring_rom 2017.05.23.17:58:46 Info: Adding cra_root [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module cra_root 2017.05.23.17:58:46 Info: Adding hello_world_system [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module hello_world_system 2017.05.23.17:58:46 Info: Adding kernel_cra [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module kernel_cra 2017.05.23.17:58:46 Info: Adding kernel_irq [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module kernel_irq 2017.05.23.17:58:46 Info: Adding kernel_mem0 [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module kernel_mem0 2017.05.23.17:58:46 Info: Adding reset [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module reset 2017.05.23.17:58:46 Info: Adding sys_description_rom [altera_generic_component 1.0] 2017.05.23.17:58:46 Info: Parameterizing module sys_description_rom 2017.05.23.17:58:46 Info: Building connections 2017.05.23.17:58:46 Info: Parameterizing connections 2017.05.23.17:58:46 Info: Validating 2017.05.23.17:58:46 Info: Done reading input file 2017.05.23.17:58:47 Warning: kernel_system.acl_internal_snoop: Warnings found in IP parameterization. 2017.05.23.17:58:47 Warning: kernel_system.acl_internal_snoop.out_0: acl_internal_snoop.out_0 must be connected to an Avalon-ST sink 2017.05.23.17:58:47 Info: kernel_system: "Transforming system: kernel_system" 2017.05.23.17:58:47 Info: kernel_system: Running transform generation_view_transform 2017.05.23.17:58:47 Info: kernel_system: Running transform generation_view_transform took 0.000s 2017.05.23.17:58:47 Info: kernel_system: Running transform interconnect_transform_chooser 2017.05.23.17:58:47 Info: Interconnect is inserted between master kernel_cra.m0 and slave cra_root.cra_slave because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide. 2017.05.23.17:58:47 Info: Interconnect is inserted between master kernel_cra.m0 and slave cra_root.cra_slave because the master has address signal 30 bit wide, but the slave is 6 bit wide. 2017.05.23.17:58:47 Info: Interconnect is inserted between master kernel_cra.m0 and slave cra_root.cra_slave because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide. 2017.05.23.17:58:48 Info: kernel_system: Running transform interconnect_transform_chooser took 0.406s 2017.05.23.17:58:48 Info: mm_interconnect_0: Running transform interconnect_transform_chooser 2017.05.23.17:58:48 Info: mm_interconnect_0: Running transform interconnect_transform_chooser took 0.034s 2017.05.23.17:58:48 Info: mm_interconnect_3: Running transform interconnect_transform_chooser 2017.05.23.17:58:48 Info: mm_interconnect_3: Running transform interconnect_transform_chooser took 0.034s 2017.05.23.17:58:48 Info: kernel_system: "Naming system components in system: kernel_system" 2017.05.23.17:58:48 Info: kernel_system: "Processing generation queue" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_acl_internal_snoop" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_avs_hello_world_cra_cra_ring" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_clk_1x" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_clk_2x" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_clk_snoop" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_cra_ring_rom" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_cra_root" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_hello_world_system" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_kernel_cra" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_kernel_irq" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_kernel_mem0" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_reset" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_sys_description_rom" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_altera_mm_interconnect_170_5lbt62i" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_altera_mm_interconnect_170_rsilsxi" 2017.05.23.17:58:48 Info: kernel_system: "Generating: kernel_system_altera_irq_mapper_170_3h3lcxy" 2017.05.23.17:58:48 Info: kernel_system: "Generating: altera_reset_controller" 2017.05.23.17:58:48 Info: kernel_system: "Generating: altera_merlin_master_translator" 2017.05.23.17:58:48 Info: kernel_system: "Generating: altera_merlin_slave_translator" 2017.05.23.17:58:48 Info: kernel_system: Done "kernel_system" with 20 modules, 9 files 2017.05.23.17:58:48 Info: qsys-generate succeeded. 2017.05.23.17:58:48 Info: Finished: Create HDL design files for synthesis 2017.05.23.17:58:49 Info: Searching kernel_system.qsys for referenced ip or qsys files 2017.05.23.17:58:49 Info: Starting library initialization 2017.05.23.17:58:52 Info: Finished initializing library 2017.05.23.17:58:54 Info: Searching kernel_system for referenced ip or qsys files 2017.05.23.17:58:54 Info: Device: 10AX115S2F45I1SG Device Family: Arria 10 2017.05.23.17:58:54 Info: Found kernel_system_acl_internal_snoop.ip 2017.05.23.17:58:54 Info: Found kernel_system_avs_hello_world_cra_cra_ring.ip 2017.05.23.17:58:54 Info: Found kernel_system_clk_1x.ip 2017.05.23.17:58:54 Info: Found kernel_system_clk_2x.ip 2017.05.23.17:58:54 Info: Found kernel_system_clk_snoop.ip 2017.05.23.17:58:54 Info: Found kernel_system_cra_ring_rom.ip 2017.05.23.17:58:54 Info: Found kernel_system_cra_root.ip 2017.05.23.17:58:54 Info: Found kernel_system_hello_world_system.ip 2017.05.23.17:58:54 Info: Found kernel_system_kernel_cra.ip 2017.05.23.17:58:54 Info: Found kernel_system_kernel_irq.ip 2017.05.23.17:58:54 Info: Found kernel_system_kernel_mem0.ip 2017.05.23.17:58:54 Info: Found kernel_system_reset.ip 2017.05.23.17:58:54 Info: Found kernel_system_sys_description_rom.ip 2017.05.23.17:58:54 Info: Searching kernel_system_cra_root for referenced ip or qsys files 2017.05.23.17:58:54 Info: Searching kernel_system_sys_description_rom for referenced ip or qsys files 2017.05.23.17:58:54 Info: Searching kernel_system_clk_snoop for referenced ip or qsys files 2017.05.23.17:58:54 Info: Searching kernel_system_clk_2x for referenced ip or qsys files 2017.05.23.17:58:55 Info: Searching kernel_system_reset for referenced ip or qsys files 2017.05.23.17:58:55 Info: Searching kernel_system_hello_world_system for referenced ip or qsys files 2017.05.23.17:58:55 Info: Searching kernel_system_kernel_cra for referenced ip or qsys files 2017.05.23.17:58:55 Info: Searching kernel_system_acl_internal_snoop for referenced ip or qsys files 2017.05.23.17:58:55 Info: Searching kernel_system_kernel_mem0 for referenced ip or qsys files 2017.05.23.17:58:55 Info: Searching kernel_system_cra_ring_rom for referenced ip or qsys files 2017.05.23.17:58:56 Info: Searching kernel_system_avs_hello_world_cra_cra_ring for referenced ip or qsys files 2017.05.23.17:58:56 Info: Searching kernel_system_kernel_irq for referenced ip or qsys files 2017.05.23.17:58:56 Info: Searching kernel_system_clk_1x for referenced ip or qsys files 2017.05.23.17:58:56 Info: Search complete 2017.05.23.17:58:56 Info: Creating archive for /root/Documents/hello_world/bin/hello_world/kernel_system.qsys 2017.05.23.17:58:56 Info: Consolidating ip files and their references. 2017.05.23.17:58:56 Info: Done consolidating ip files and references. 2017.05.23.17:58:56 Info: Adding ip/kernel_system_avs_hello_world_cra_cra_ring.ip 2017.05.23.17:58:56 Info: Adding .qsys_top_level 2017.05.23.17:58:56 Info: Adding ip/kernel_system_clk_2x.ip 2017.05.23.17:58:56 Info: Adding ip/kernel_system_reset.ip 2017.05.23.17:58:56 Info: Adding ip/kernel_system_sys_description_rom.ip 2017.05.23.17:58:56 Info: Adding ip/kernel_system_kernel_irq.ip 2017.05.23.17:58:56 Info: Adding ip/kernel_system_kernel_mem0.ip 2017.05.23.17:58:56 Info: Adding ip/kernel_system_acl_internal_snoop.ip 2017.05.23.17:58:56 Info: Adding ip/kernel_system_cra_root.ip 2017.05.23.17:58:56 Info: Adding ip/kernel_system_cra_ring_rom.ip 2017.05.23.17:58:56 Info: Adding ip/kernel_system_clk_1x.ip 2017.05.23.17:58:56 Info: Adding kernel_system.qsys 2017.05.23.17:58:56 Info: Adding ip/kernel_system_clk_snoop.ip 2017.05.23.17:58:56 Info: Adding ip/kernel_system_kernel_cra.ip 2017.05.23.17:58:56 Info: Adding ip/kernel_system_hello_world_system.ip 2017.05.23.17:58:56 Info: Archiving complete. Result is stored here: /root/Documents/hello_world/bin/hello_world/kernel_system.zip 2017.05.23.17:58:56 Info: Adding all files to /root/Documents/hello_world/bin/hello_world/top revision opencl_bsp_ip. 2017.05.23.17:58:58 Info: Done adding files. Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 17.0.0 Build 290 04/26/2017 SJ Pro Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Intel and sold by Intel or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Tue May 23 17:58:26 2017 Info: Command: quartus_sh -t scripts/pre_flow_pr.tcl Info: Using INI file /root/Documents/hello_world/bin/hello_world/quartus.ini Info: Running pre-flow script Info: Project name: top Info: Revision name: top Info: Device part name is 10AX115S2F45I1SG Info: Checking for OpenCL SDK installation, environment should have ALTERAOCLSDKROOT defined Info: ALTERAOCLSDKROOT=/root/intelFPGA_pro/17.0/hld Info: Compiling top revision -> unpacking base revision compile outputs from base.qar Info: Generating kernel_system.qsys: Info: qsys-generate -syn --family="Arria 10" --part=10AX115S2F45I1SG kernel_system.qsys Info (23030): Evaluation of Tcl script scripts/pre_flow_pr.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings Info: Peak virtual memory: 968 megabytes Info: Processing ended: Tue May 23 17:58:58 2017 Info: Elapsed time: 00:00:32 Info: Total CPU time (on all processors): 00:01:21