Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Sun May 06 08:07:03 2018 Info: Command: quartus_sh --flow compile top -c top Info: Quartus(args): compile top -c top Info: Using INI file c:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/quartus.ini Info: Project Name = C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top Info: Revision Name = top Info (125068): Revision "top" was previously opened in Quartus II software version 14.1. Created Quartus Prime Default Settings File C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 14.1. Info (125069): Default assignment values were changed in the current version of the Quartus Prime software -- changes to default assignments values are contained in file c:/intelfpga_lite/17.1/quartus/bin64/assignment_defaults.qdf Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition Info: Processing started: Sun May 06 08:07:40 2018 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top Info: Using INI file C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/quartus.ini Critical Warning (138067): Current license file does not support incremental compilation. The Quartus Prime software removes all the user-specified design partitions in the design automatically. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 2 design units, including 2 entities, in source file top.v Info (12023): Found entity 1: top File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 18 Info (12023): Found entity 2: async_counter_30 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 224 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/system.v Info (12023): Found entity 1: system File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/system.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_controller.v Info (12023): Found entity 1: altera_reset_controller File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_reset_controller.v Line: 42 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_synchronizer.v Info (12023): Found entity 1: altera_reset_synchronizer File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_reset_synchronizer.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_irq_mapper.sv Info (12023): Found entity 1: system_irq_mapper File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_irq_mapper.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_3.v Info (12023): Found entity 1: system_mm_interconnect_3 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_mm_interconnect_3.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_translator.sv Info (12023): Found entity 1: altera_merlin_slave_translator File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_translator.sv Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_translator.sv Info (12023): Found entity 1: altera_merlin_master_translator File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_master_translator.sv Line: 32 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_1.v Info (12023): Found entity 1: system_mm_interconnect_1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_mm_interconnect_1.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_0.v Info (12023): Found entity 1: system_mm_interconnect_0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_shift_register.v Info (12023): Found entity 1: acl_shift_register File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_shift_register.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_work_group_dispatcher.v Info (12023): Found entity 1: acl_work_group_dispatcher File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_work_group_dispatcher.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_kernel_finish_detector.v Info (12023): Found entity 1: acl_kernel_finish_detector File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_kernel_finish_detector.v Line: 42 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_multistage_accumulator.v Info (12023): Found entity 1: acl_multistage_accumulator File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_multistage_accumulator.v Line: 21 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/acl_reset_handler.sv Info (12023): Found entity 1: acl_reset_handler File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 48 Info (12023): Found entity 2: acl_reset_fanout_pipeline_with_synchronizer_and_pulse_extender File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 124 Info (12023): Found entity 3: acl_reset_pulse_extender File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 200 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_std_synchronizer_nocut.v Info (12023): Found entity 1: acl_std_synchronizer_nocut File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_std_synchronizer_nocut.v Line: 52 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_fanout_pipeline.sv Info (12023): Found entity 1: acl_fanout_pipeline File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fanout_pipeline.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_id_iterator.v Info (12023): Found entity 1: acl_id_iterator File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_id_iterator.v Line: 39 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_work_item_iterator.v Info (12023): Found entity 1: acl_work_item_iterator File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_work_item_iterator.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_multistage_adder.v Info (12023): Found entity 1: acl_multistage_adder File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_multistage_adder.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_fifo.v Info (12023): Found entity 1: acl_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_fifo_stall_valid_lookahead.sv Info (12023): Found entity 1: acl_fifo_stall_valid_lookahead File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo_stall_valid_lookahead.sv Line: 25 Info (12021): Found 6 design units, including 6 entities, in source file system/synthesis/submodules/hello_world_system.v Info (12023): Found entity 1: hello_world_system File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 23 Info (12023): Found entity 2: hello_world_partition_wrapper File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 698 Info (12023): Found entity 3: hello_world_top_wrapper_0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 977 Info (12023): Found entity 4: hello_world_system_interconnect_0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1092 Info (12023): Found entity 5: hello_world_system_interconnect_1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1285 Info (12023): Found entity 6: hello_world_system_interconnect_2 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1481 Info (12021): Found 1 design units, including 0 entities, in source file system/synthesis/submodules/dspba_library_package.vhd Info (12022): Found design unit 1: dspba_library_package (system) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/dspba_library_package.vhd Line: 17 Info (12021): Found 6 design units, including 3 entities, in source file system/synthesis/submodules/dspba_library.vhd Info (12022): Found design unit 1: dspba_delay-delay File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/dspba_library.vhd Line: 34 Info (12022): Found design unit 2: dspba_sync_reg-sync_reg File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/dspba_library.vhd Line: 117 Info (12022): Found design unit 3: dspba_pipe-rtl File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/dspba_library.vhd Line: 356 Info (12023): Found entity 1: dspba_delay File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/dspba_library.vhd Line: 18 Info (12023): Found entity 2: dspba_sync_reg File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/dspba_library.vhd Line: 93 Info (12023): Found entity 3: dspba_pipe File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/dspba_library.vhd Line: 343 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_data_fifo.v Info (12023): Found entity 1: acl_data_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 49 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ll_fifo.v Info (12023): Found entity 1: acl_ll_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ll_fifo.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ll_ram_fifo.v Info (12023): Found entity 1: acl_ll_ram_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ll_ram_fifo.v Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_valid_fifo_counter.v Info (12023): Found entity 1: acl_valid_fifo_counter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_valid_fifo_counter.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_dspba_valid_fifo_counter.v Info (12023): Found entity 1: acl_dspba_valid_fifo_counter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_dspba_valid_fifo_counter.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_staging_reg.v Info (12023): Found entity 1: acl_staging_reg File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_staging_reg.v Line: 24 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/hld_fifo.sv Info (12023): Found entity 1: hld_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hld_fifo.sv Line: 132 Info (12023): Found entity 2: earliness_delay File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hld_fifo.sv Line: 389 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hld_fifo_zero_width.sv Info (12023): Found entity 1: hld_fifo_zero_width File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hld_fifo_zero_width.sv Line: 26 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/acl_high_speed_fifo.sv Info (12023): Found entity 1: acl_high_speed_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_high_speed_fifo.sv Line: 133 Info (12023): Found entity 2: scfifo_to_acl_high_speed_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_high_speed_fifo.sv Line: 1084 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_low_latency_fifo.sv Info (12023): Found entity 1: acl_low_latency_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_low_latency_fifo.sv Line: 80 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_zero_latency_fifo.sv Info (12023): Found entity 1: acl_zero_latency_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_zero_latency_fifo.sv Line: 97 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/acl_tessellated_incr_decr_threshold.sv Info (12023): Found entity 1: acl_tessellated_incr_decr_threshold File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_tessellated_incr_decr_threshold.sv Line: 42 Info (12023): Found entity 2: acl_tessellated_incr_decr File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_tessellated_incr_decr_threshold.sv Line: 374 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_tessellated_incr_lookahead.sv Info (12023): Found entity 1: acl_tessellated_incr_lookahead File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_tessellated_incr_lookahead.sv Line: 40 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/acl_lfsr.sv Info (12023): Found entity 1: acl_lfsr File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_lfsr.sv Line: 42 Info (12023): Found entity 2: galois_lfsr File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_lfsr.sv Line: 1622 Info (12023): Found entity 3: fibonacci_lfsr File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_lfsr.sv Line: 1670 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_dspba_buffer.v Info (12023): Found entity 1: acl_dspba_buffer File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_dspba_buffer.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_printf_buffer_address_generator.v Info (12023): Found entity 1: acl_printf_buffer_address_generator File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_printf_buffer_address_generator.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_top.v Info (12023): Found entity 1: lsu_top File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_top.v Line: 82 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_permute_address.v Info (12023): Found entity 1: lsu_permute_address File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_permute_address.v Line: 20 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_pipelined.v Info (12023): Found entity 1: lsu_pipelined_read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_pipelined.v Line: 43 Info (12023): Found entity 2: lsu_pipelined_write File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_pipelined.v Line: 458 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_enabled.v Info (12023): Found entity 1: lsu_enabled_read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_enabled.v Line: 41 Info (12023): Found entity 2: lsu_enabled_write File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_enabled.v Line: 194 Info (12021): Found 4 design units, including 4 entities, in source file system/synthesis/submodules/lsu_basic_coalescer.v Info (12023): Found entity 1: lsu_basic_coalesced_read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_basic_coalescer.v Line: 41 Info (12023): Found entity 2: lsu_basic_coalesced_write File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_basic_coalescer.v Line: 227 Info (12023): Found entity 3: lookahead_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_basic_coalescer.v Line: 482 Info (12023): Found entity 4: basic_coalescer File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_basic_coalescer.v Line: 543 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_simple.v Info (12023): Found entity 1: lsu_simple_read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_simple.v Line: 36 Info (12023): Found entity 2: lsu_simple_write File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_simple.v Line: 201 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_streaming.v Info (12023): Found entity 1: lsu_streaming_read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_streaming.v Line: 39 Info (12023): Found entity 2: lsu_streaming_write File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_streaming.v Line: 294 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_burst_master.v Info (12023): Found entity 1: lsu_burst_read_master File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_burst_master.v Line: 30 Info (12021): Found 7 design units, including 7 entities, in source file system/synthesis/submodules/lsu_bursting_load_stores.v Info (12023): Found entity 1: lsu_bursting_read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 18 Info (12023): Found entity 2: acl_io_pipeline File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 405 Info (12023): Found entity 3: lsu_bursting_pipelined_read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 432 Info (12023): Found entity 4: acl_stall_free_coalescer File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 939 Info (12023): Found entity 5: lsu_bursting_write File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1096 Info (12023): Found entity 6: lsu_bursting_write_internal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1260 Info (12023): Found entity 7: bursting_coalescer File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1675 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_non_aligned_write.v Info (12023): Found entity 1: lsu_non_aligned_write File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_non_aligned_write.v Line: 19 Info (12023): Found entity 2: lsu_non_aligned_write_internal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_non_aligned_write.v Line: 168 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_read_cache.v Info (12023): Found entity 1: lsu_read_cache File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_read_cache.v Line: 45 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_atomic.v Info (12023): Found entity 1: lsu_atomic_pipelined File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_atomic.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_prefetch_block.v Info (12023): Found entity 1: lsu_prefetch_block File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_prefetch_block.v Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_wide_wrapper.v Info (12023): Found entity 1: lsu_wide_wrapper File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_wide_wrapper.v Line: 21 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/lsu_streaming_prefetch.v Info (12023): Found entity 1: lsu_streaming_prefetch_read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_streaming_prefetch.v Line: 25 Info (12023): Found entity 2: lsu_streaming_prefetch_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_streaming_prefetch.v Line: 324 Info (12023): Found entity 3: lsu_streaming_prefetch_avalon_bust_master File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_streaming_prefetch.v Line: 542 Info (12021): Found 6 design units, including 6 entities, in source file system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Info (12023): Found entity 1: acl_aligned_burst_coalesced_lsu File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 65 Info (12023): Found entity 2: avalon_interface File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 310 Info (12023): Found entity 3: valid_generator File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 496 Info (12023): Found entity 4: acl_lsu_buffers File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 563 Info (12023): Found entity 5: acl_burst_coalescer File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 767 Info (12023): Found entity 6: acl_registered_comparison File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 1186 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_toggle_detect.v Info (12023): Found entity 1: acl_toggle_detect File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_toggle_detect.v Line: 39 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_debug_mem.v Info (12023): Found entity 1: acl_debug_mem File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_debug_mem.v Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_burst_coalesced_pipelined_write.sv Info (12023): Found entity 1: lsu_burst_coalesced_pipelined_write File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_burst_coalesced_pipelined_write.sv Line: 69 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_burst_coalesced_pipelined_read.sv Info (12023): Found entity 1: lsu_burst_coalesced_pipelined_read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_burst_coalesced_pipelined_read.sv Line: 63 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_clock2x_holder.v Info (12023): Found entity 1: acl_clock2x_holder File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_clock2x_holder.v Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/hello_world_function_wrapper.vhd Info (12022): Found design unit 1: hello_world_function_wrapper-normal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_function_wrapper.vhd Line: 100 Info (12023): Found entity 1: hello_world_function_wrapper File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_function_wrapper.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/hello_world_function.vhd Info (12022): Found design unit 1: hello_world_function-normal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_function.vhd Line: 80 Info (12023): Found entity 1: hello_world_function File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_function.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/bb_hello_world_b0.vhd Info (12022): Found design unit 1: bb_hello_world_B0-normal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/bb_hello_world_B0.vhd Line: 72 Info (12023): Found entity 1: bb_hello_world_B0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/bb_hello_world_B0.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/bb_hello_world_b0_stall_region.vhd Info (12022): Found design unit 1: bb_hello_world_B0_stall_region-normal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/bb_hello_world_B0_stall_region.vhd Line: 72 Info (12023): Found entity 1: bb_hello_world_B0_stall_region File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/bb_hello_world_B0_stall_region.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/hello_world_b0_merge_reg.vhd Info (12022): Found design unit 1: hello_world_B0_merge_reg-normal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_B0_merge_reg.vhd Line: 48 Info (12023): Found entity 1: hello_world_B0_merge_reg File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_B0_merge_reg.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_store_unnamed_hello_world0_hello_world6.vhd Info (12022): Found design unit 1: i_store_unnamed_hello_world0_hello_world6-normal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/i_store_unnamed_hello_world0_hello_world6.vhd Line: 66 Info (12023): Found entity 1: i_store_unnamed_hello_world0_hello_world6 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/i_store_unnamed_hello_world0_hello_world6.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_printf_printf_addr_hello_world3.vhd Info (12022): Found design unit 1: i_printf_printf_addr_hello_world3-normal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/i_printf_printf_addr_hello_world3.vhd Line: 61 Info (12023): Found entity 1: i_printf_printf_addr_hello_world3 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/i_printf_printf_addr_hello_world3.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_syncbuf_thread_id_from_which_to_print_a0zfer_hello_world0.vhd Info (12022): Found design unit 1: i_syncbuf_thread_id_from_which_to_print_message_sync_buffer_hello_world0-normal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/i_syncbuf_thread_id_from_which_to_print_A0Zfer_hello_world0.vhd Line: 49 Info (12023): Found entity 1: i_syncbuf_thread_id_from_which_to_print_message_sync_buffer_hello_world0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/i_syncbuf_thread_id_from_which_to_print_A0Zfer_hello_world0.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/hello_world_b0_branch.vhd Info (12022): Found design unit 1: hello_world_B0_branch-normal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_B0_branch.vhd Line: 46 Info (12023): Found entity 1: hello_world_B0_branch File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_B0_branch.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/hello_world_b0_merge.vhd Info (12022): Found design unit 1: hello_world_B0_merge-normal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_B0_merge.vhd Line: 48 Info (12023): Found entity 1: hello_world_B0_merge File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_B0_merge.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/hello_world_function_cra_slave.vhd Info (12022): Found design unit 1: hello_world_function_cra_slave-normal File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_function_cra_slave.vhd Line: 77 Info (12023): Found entity 1: hello_world_function_cra_slave File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_function_cra_slave.vhd Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_start_signal_chain_element.v Info (12023): Found entity 1: acl_start_signal_chain_element File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_start_signal_chain_element.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_avm_to_ic.v Info (12023): Found entity 1: acl_avm_to_ic File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_avm_to_ic.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_master_endpoint.v Info (12023): Found entity 1: acl_ic_master_endpoint File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_master_endpoint.v Line: 22 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/acl_arb_intf.v Info (12023): Found entity 1: acl_arb_data File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_arb_intf.v Line: 21 Info (12023): Found entity 2: acl_arb_intf File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_arb_intf.v Line: 42 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/acl_ic_intf.v Info (12023): Found entity 1: acl_ic_wrp_intf File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_intf.v Line: 19 Info (12023): Found entity 2: acl_ic_rrp_intf File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_intf.v Line: 27 Info (12023): Found entity 3: acl_ic_master_intf File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_intf.v Line: 37 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_slave_endpoint.v Info (12023): Found entity 1: acl_ic_slave_endpoint File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_slave_endpoint.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_slave_rrp.v Info (12023): Found entity 1: acl_ic_slave_rrp File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_slave_rrp.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_slave_wrp.v Info (12023): Found entity 1: acl_ic_slave_wrp File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_slave_wrp.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_mem_router_reorder.v Info (12023): Found entity 1: acl_ic_mem_router_reorder File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_mem_router_reorder.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_address_to_bankaddress.v Info (12023): Found entity 1: acl_address_to_bankaddress File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_address_to_bankaddress.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_to_avm.v Info (12023): Found entity 1: acl_ic_to_avm File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_to_avm.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_printf_counter.v Info (12023): Found entity 1: acl_printf_counter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_printf_counter.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/cra_ring_root.sv Info (12023): Found entity 1: cra_ring_root File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/cra_ring_root.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/cra_ring_node.sv Info (12023): Found entity 1: cra_ring_node File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/cra_ring_node.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface.v Info (12023): Found entity 1: system_acl_iface File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_irq_mapper_001.sv Info (12023): Found entity 1: system_acl_iface_irq_mapper_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_irq_mapper_001.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_irq_mapper.sv Info (12023): Found entity 1: system_acl_iface_irq_mapper File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_irq_mapper.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_7 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_avalon_st_adapter.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_avalon_st_adapter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_avalon_st_adapter_error_adapter_0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_7_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_7_rsp_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7_rsp_mux.sv Line: 51 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_arbitrator.sv Info (12023): Found entity 1: altera_merlin_arbitrator File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 103 Info (12023): Found entity 2: altera_merlin_arb_adder File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 228 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_7_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_7_rsp_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_7_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_7_cmd_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_7_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_7_cmd_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7_cmd_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter.sv Info (12023): Found entity 1: altera_merlin_burst_adapter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_uncompressed_only File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Line: 39 Info (12021): Found 5 design units, including 5 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 40 Info (12023): Found entity 2: altera_merlin_burst_adapter_adder File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 55 Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 77 Info (12023): Found entity 4: altera_merlin_burst_adapter_min File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 98 Info (12023): Found entity 5: altera_merlin_burst_adapter_13_1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 264 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter_new.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_new File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_new.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_incr_burst_converter.sv Info (12023): Found entity 1: altera_incr_burst_converter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_incr_burst_converter.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_wrap_burst_converter.sv Info (12023): Found entity 1: altera_wrap_burst_converter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_wrap_burst_converter.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_default_burst_converter.sv Info (12023): Found entity 1: altera_default_burst_converter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_default_burst_converter.sv Line: 30 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_address_alignment.sv Info (12023): Found entity 1: altera_merlin_address_alignment File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_address_alignment.sv Line: 26 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Info (12023): Found entity 1: altera_avalon_st_pipeline_stage File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_base.v Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_st_pipeline_base.v Line: 22 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_7_router_002.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_7_router_002_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_7_router_002 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_7_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_7_router_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_7_router File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_sc_fifo.v Info (12023): Found entity 1: altera_avalon_sc_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_sc_fifo.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_agent.sv Info (12023): Found entity 1: altera_merlin_slave_agent File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_uncompressor.sv Info (12023): Found entity 1: altera_merlin_burst_uncompressor File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_axi_master_ni.sv Info (12023): Found entity 1: altera_merlin_axi_master_ni File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_axi_master_ni.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_avalon_st_adapter_002.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_avalon_st_adapter_002 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_avalon_st_adapter_002.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_avalon_st_adapter_002_error_adapter_0.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_avalon_st_adapter_002_error_adapter_0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_avalon_st_adapter_002_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_width_adapter.sv Info (12023): Found entity 1: altera_merlin_width_adapter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_rsp_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_rsp_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_cmd_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_cmd_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_cmd_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_traffic_limiter.sv Info (12023): Found entity 1: altera_merlin_traffic_limiter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_traffic_limiter.sv Line: 49 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_reorder_memory.sv Info (12023): Found entity 1: altera_merlin_reorder_memory File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 28 Info (12023): Found entity 2: memory_pointer_controller File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 185 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_003.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_router_003_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_003.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_6_router_003 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_003.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_001.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_router_001_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_6_router_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_router_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_6_router File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_agent.sv Info (12023): Found entity 1: altera_merlin_master_agent File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_master_agent.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_avalon_st_adapter.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_avalon_st_adapter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_avalon_st_adapter_error_adapter_0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5_rsp_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5_rsp_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5_cmd_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5_cmd_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router_002.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5_router_002_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_5_router_002 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5_router_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_5_router File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4_rsp_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4_cmd_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4_cmd_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router_001.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4_router_001_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_4_router_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4_router_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_4_router File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_rsp_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_rsp_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_cmd_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_cmd_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router_002.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_router_002_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_3_router_002 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_router_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_3_router File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_rsp_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_cmd_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_cmd_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router_001.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_router_001_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_2_router_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_router_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_2_router File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_0.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_mm_bridge.v Info (12023): Found entity 1: altera_avalon_mm_bridge File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_mm_bridge.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_address_span_extender.sv Info (12023): Found entity 1: altera_address_span_extender File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_address_span_extender.sv Line: 39 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_pll.v Info (12023): Found entity 1: system_acl_iface_pll File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_pll.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface.v Info (12023): Found entity 1: system_acl_iface_kernel_interface File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_handshake_clock_crosser File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_clock_crosser File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_st_clock_crosser.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_std_synchronizer_nocut.v Info (12023): Found entity 1: altera_std_synchronizer_nocut File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_std_synchronizer_nocut.v Line: 44 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux_002.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux_002 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux_002.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_cmd_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_cmd_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_002.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_router_002_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_kernel_interface_mm_interconnect_1_router_002 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_001.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_router_001_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_kernel_interface_mm_interconnect_1_router_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_router_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_kernel_interface_mm_interconnect_1_router File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_0_rsp_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_0_cmd_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_0_cmd_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_0_router_001_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_kernel_interface_mm_interconnect_0_router_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_router.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_0_router_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_kernel_interface_mm_interconnect_0_router File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/irq_ena.v Info (12023): Found entity 1: irq_ena File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/irq_ena.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/version_id.v Info (12023): Found entity 1: version_id File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/version_id.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_irq_bridge.v Info (12023): Found entity 1: altera_irq_bridge File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_irq_bridge.v Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/mem_org_mode.v Info (12023): Found entity 1: mem_org_mode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/mem_org_mode.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sw_reset.v Info (12023): Found entity 1: sw_reset File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sw_reset.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_sys_description_rom.v Info (12023): Found entity 1: system_acl_iface_kernel_interface_sys_description_rom File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_sys_description_rom.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_hps.v Info (12023): Found entity 1: system_acl_iface_hps File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_hps.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_hps_hps_io.v Info (12023): Found entity 1: system_acl_iface_hps_hps_io File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_hps_hps_io.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram.v Info (12023): Found entity 1: hps_sdram File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Info (12023): Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv Info (12023): Found entity 1: altera_mem_if_dll_cyclonev File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Info (12023): Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v Info (12023): Found entity 1: altera_mem_if_hhp_qseq_synth_top File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv Info (12023): Found entity 1: altera_mem_if_oct_cyclonev File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0.sv Info (12023): Found entity 1: hps_sdram_p0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Info (12023): Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Info (12023): Found entity 1: hps_sdram_p0_acv_hard_io_pads File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Info (12023): Found entity 1: hps_sdram_p0_acv_hard_memphy File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Info (12023): Found entity 1: hps_sdram_p0_acv_ldc File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_altdqdqs.v Info (12023): Found entity 1: hps_sdram_p0_altdqdqs File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_altdqdqs.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Info (12023): Found entity 1: hps_sdram_p0_clock_pair_generator File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_generic_ddio.v Info (12023): Found entity 1: hps_sdram_p0_generic_ddio File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_generic_ddio.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_iss_probe.v Info (12023): Found entity 1: hps_sdram_p0_iss_probe File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_iss_probe.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_phy_csr.sv Info (12023): Found entity 1: hps_sdram_p0_phy_csr File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_phy_csr.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_reset.v Info (12023): Found entity 1: hps_sdram_p0_reset File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_reset.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_reset_sync.v Info (12023): Found entity 1: hps_sdram_p0_reset_sync File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_reset_sync.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_pll.sv Info (12023): Found entity 1: hps_sdram_pll File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_pll.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Info (12023): Found entity 1: system_acl_iface_hps_hps_io_border File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_hps_fpga_interfaces.sv Info (12023): Found entity 1: system_acl_iface_hps_fpga_interfaces File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_hps_fpga_interfaces.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 9 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Info (12023): Found entity 1: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 34 Info (12023): Found entity 2: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b_module File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 97 Info (12023): Found entity 3: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 159 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v Info (12023): Found entity 1: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv Info (12023): Found entity 1: altera_mem_if_sequencer_mem_no_ifdef_params File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_sequencer_rst.sv Info (12023): Found entity 1: altera_mem_if_sequencer_rst File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_rst.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_simple_avalon_mm_bridge.sv Info (12023): Found entity 1: altera_mem_if_simple_avalon_mm_bridge File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_simple_avalon_mm_bridge.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_reg_file.sv Info (12023): Found entity 1: sequencer_reg_file File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_reg_file.sv Line: 37 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_acv_phase_decode.v Info (12023): Found entity 1: sequencer_scc_acv_phase_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_acv_phase_decode.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_acv_wrapper.sv Info (12023): Found entity 1: sequencer_scc_acv_wrapper File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_acv_wrapper.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_mgr.sv Info (12023): Found entity 1: sequencer_scc_mgr File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_mgr.sv Line: 29 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_reg_file.v Info (12023): Found entity 1: sequencer_scc_reg_file File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_reg_file.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_siii_phase_decode.v Info (12023): Found entity 1: sequencer_scc_siii_phase_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_siii_phase_decode.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_siii_wrapper.sv Info (12023): Found entity 1: sequencer_scc_siii_wrapper File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_siii_wrapper.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_sv_phase_decode.v Info (12023): Found entity 1: sequencer_scc_sv_phase_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_sv_phase_decode.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_sv_wrapper.sv Info (12023): Found entity 1: sequencer_scc_sv_wrapper File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_sv_wrapper.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_irq_mapper.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_irq_mapper File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_irq_mapper.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux_001.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux_001.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001.sv Line: 51 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_demux_001.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_demux_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_demux_001.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux_001.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux_001.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_clock_pair_generator.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_clock_pair_generator File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_clock_pair_generator.v Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_acv_hard_memphy File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_ldc.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_acv_ldc File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_ldc.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_acv_hard_io_pads File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_generic_ddio.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_generic_ddio File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_generic_ddio.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_reset File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset_sync.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_reset_sync File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset_sync.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_phy_csr.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_phy_csr File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_phy_csr.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_iss_probe.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_iss_probe File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_iss_probe.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_altdqdqs.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_altdqdqs File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_altdqdqs.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_pll0.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_pll0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_pll0.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_memory_bank_divider.v Info (12023): Found entity 1: system_acl_iface_acl_memory_bank_divider File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_memory_bank_divider.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/snoop_adapter.v Info (12023): Found entity 1: snoop_adapter File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/snoop_adapter.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Info (12023): Found entity 1: altera_avalon_mm_clock_crossing_bridge File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 30 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_dc_fifo.v Info (12023): Found entity 1: altera_avalon_dc_fifo File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_dc_fifo.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v Info (12023): Found entity 1: altera_dcfifo_synchronizer_bundle File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v Line: 8 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux_001.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux_001.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_default_decode File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_acl_kernel_clk_mm_interconnect_0_router File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_pll_rom File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/pll_lock_avs.v Info (12023): Found entity 1: pll_lock_avs File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/pll_lock_avs.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/global_routing.v Info (12023): Found entity 1: global_routing File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/global_routing.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/timer.v Info (12023): Found entity 1: acl_timer File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/timer.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_kernel_pll.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_kernel_pll File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_kernel_pll.v Line: 2 Warning (10236): Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for "pll_dr_clk" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_pll.sv Line: 168 Info (12127): Elaborating entity "top" for the top level hierarchy Info (12128): Elaborating entity "system" for hierarchy "system:the_system" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 211 Info (12128): Elaborating entity "system_acl_iface" for hierarchy "system:the_system|system_acl_iface:acl_iface" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/system.v Line: 265 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 368 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_kernel_pll" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 78 Info (12128): Elaborating entity "altera_pll" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_kernel_pll.v Line: 242 Warning (10034): Output port "lvds_clk" at altera_pll.v(319) has no driver File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 319 Warning (10034): Output port "loaden" at altera_pll.v(320) has no driver File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 320 Warning (10034): Output port "extclk_out" at altera_pll.v(321) has no driver File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 321 Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_kernel_pll.v Line: 242 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_kernel_pll.v Line: 242 Info (12134): Parameter "fractional_vco_multiplier" = "true" Info (12134): Parameter "reference_clock_frequency" = "50.0 MHz" Info (12134): Parameter "pll_fractional_cout" = "24" Info (12134): Parameter "pll_dsm_out_sel" = "1st_order" Info (12134): Parameter "operation_mode" = "direct" Info (12134): Parameter "number_of_clocks" = "2" Info (12134): Parameter "output_clock_frequency0" = "140.000000 MHz" Info (12134): Parameter "phase_shift0" = "0 ps" Info (12134): Parameter "duty_cycle0" = "50" Info (12134): Parameter "output_clock_frequency1" = "280.000000 MHz" Info (12134): Parameter "phase_shift1" = "0 ps" Info (12134): Parameter "duty_cycle1" = "50" Info (12134): Parameter "output_clock_frequency2" = "0 MHz" Info (12134): Parameter "phase_shift2" = "0 ps" Info (12134): Parameter "duty_cycle2" = "50" Info (12134): Parameter "output_clock_frequency3" = "0 MHz" Info (12134): Parameter "phase_shift3" = "0 ps" Info (12134): Parameter "duty_cycle3" = "50" Info (12134): Parameter "output_clock_frequency4" = "0 MHz" Info (12134): Parameter "phase_shift4" = "0 ps" Info (12134): Parameter "duty_cycle4" = "50" Info (12134): Parameter "output_clock_frequency5" = "0 MHz" Info (12134): Parameter "phase_shift5" = "0 ps" Info (12134): Parameter "duty_cycle5" = "50" Info (12134): Parameter "output_clock_frequency6" = "0 MHz" Info (12134): Parameter "phase_shift6" = "0 ps" Info (12134): Parameter "duty_cycle6" = "50" Info (12134): Parameter "output_clock_frequency7" = "0 MHz" Info (12134): Parameter "phase_shift7" = "0 ps" Info (12134): Parameter "duty_cycle7" = "50" Info (12134): Parameter "output_clock_frequency8" = "0 MHz" Info (12134): Parameter "phase_shift8" = "0 ps" Info (12134): Parameter "duty_cycle8" = "50" Info (12134): Parameter "output_clock_frequency9" = "0 MHz" Info (12134): Parameter "phase_shift9" = "0 ps" Info (12134): Parameter "duty_cycle9" = "50" Info (12134): Parameter "output_clock_frequency10" = "0 MHz" Info (12134): Parameter "phase_shift10" = "0 ps" Info (12134): Parameter "duty_cycle10" = "50" Info (12134): Parameter "output_clock_frequency11" = "0 MHz" Info (12134): Parameter "phase_shift11" = "0 ps" Info (12134): Parameter "duty_cycle11" = "50" Info (12134): Parameter "output_clock_frequency12" = "0 MHz" Info (12134): Parameter "phase_shift12" = "0 ps" Info (12134): Parameter "duty_cycle12" = "50" Info (12134): Parameter "output_clock_frequency13" = "0 MHz" Info (12134): Parameter "phase_shift13" = "0 ps" Info (12134): Parameter "duty_cycle13" = "50" Info (12134): Parameter "output_clock_frequency14" = "0 MHz" Info (12134): Parameter "phase_shift14" = "0 ps" Info (12134): Parameter "duty_cycle14" = "50" Info (12134): Parameter "output_clock_frequency15" = "0 MHz" Info (12134): Parameter "phase_shift15" = "0 ps" Info (12134): Parameter "duty_cycle15" = "50" Info (12134): Parameter "output_clock_frequency16" = "0 MHz" Info (12134): Parameter "phase_shift16" = "0 ps" Info (12134): Parameter "duty_cycle16" = "50" Info (12134): Parameter "output_clock_frequency17" = "0 MHz" Info (12134): Parameter "phase_shift17" = "0 ps" Info (12134): Parameter "duty_cycle17" = "50" Info (12134): Parameter "pll_type" = "Cyclone V" Info (12134): Parameter "pll_subtype" = "Reconfigurable" Info (12134): Parameter "m_cnt_hi_div" = "6" Info (12134): Parameter "m_cnt_lo_div" = "5" Info (12134): Parameter "n_cnt_hi_div" = "256" Info (12134): Parameter "n_cnt_lo_div" = "256" Info (12134): Parameter "m_cnt_bypass_en" = "false" Info (12134): Parameter "n_cnt_bypass_en" = "true" Info (12134): Parameter "m_cnt_odd_div_duty_en" = "true" Info (12134): Parameter "n_cnt_odd_div_duty_en" = "false" Info (12134): Parameter "c_cnt_hi_div0" = "2" Info (12134): Parameter "c_cnt_lo_div0" = "2" Info (12134): Parameter "c_cnt_prst0" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst0" = "0" Info (12134): Parameter "c_cnt_in_src0" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en0" = "false" Info (12134): Parameter "c_cnt_odd_div_duty_en0" = "false" Info (12134): Parameter "c_cnt_hi_div1" = "1" Info (12134): Parameter "c_cnt_lo_div1" = "1" Info (12134): Parameter "c_cnt_prst1" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst1" = "0" Info (12134): Parameter "c_cnt_in_src1" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en1" = "false" Info (12134): Parameter "c_cnt_odd_div_duty_en1" = "false" Info (12134): Parameter "c_cnt_hi_div2" = "1" Info (12134): Parameter "c_cnt_lo_div2" = "1" Info (12134): Parameter "c_cnt_prst2" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst2" = "0" Info (12134): Parameter "c_cnt_in_src2" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en2" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en2" = "false" Info (12134): Parameter "c_cnt_hi_div3" = "1" Info (12134): Parameter "c_cnt_lo_div3" = "1" Info (12134): Parameter "c_cnt_prst3" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst3" = "0" Info (12134): Parameter "c_cnt_in_src3" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en3" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en3" = "false" Info (12134): Parameter "c_cnt_hi_div4" = "1" Info (12134): Parameter "c_cnt_lo_div4" = "1" Info (12134): Parameter "c_cnt_prst4" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst4" = "0" Info (12134): Parameter "c_cnt_in_src4" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en4" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en4" = "false" Info (12134): Parameter "c_cnt_hi_div5" = "1" Info (12134): Parameter "c_cnt_lo_div5" = "1" Info (12134): Parameter "c_cnt_prst5" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst5" = "0" Info (12134): Parameter "c_cnt_in_src5" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en5" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en5" = "false" Info (12134): Parameter "c_cnt_hi_div6" = "1" Info (12134): Parameter "c_cnt_lo_div6" = "1" Info (12134): Parameter "c_cnt_prst6" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst6" = "0" Info (12134): Parameter "c_cnt_in_src6" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en6" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en6" = "false" Info (12134): Parameter "c_cnt_hi_div7" = "1" Info (12134): Parameter "c_cnt_lo_div7" = "1" Info (12134): Parameter "c_cnt_prst7" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst7" = "0" Info (12134): Parameter "c_cnt_in_src7" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en7" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en7" = "false" Info (12134): Parameter "c_cnt_hi_div8" = "1" Info (12134): Parameter "c_cnt_lo_div8" = "1" Info (12134): Parameter "c_cnt_prst8" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst8" = "0" Info (12134): Parameter "c_cnt_in_src8" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en8" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en8" = "false" Info (12134): Parameter "c_cnt_hi_div9" = "1" Info (12134): Parameter "c_cnt_lo_div9" = "1" Info (12134): Parameter "c_cnt_prst9" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst9" = "0" Info (12134): Parameter "c_cnt_in_src9" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en9" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en9" = "false" Info (12134): Parameter "c_cnt_hi_div10" = "1" Info (12134): Parameter "c_cnt_lo_div10" = "1" Info (12134): Parameter "c_cnt_prst10" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst10" = "0" Info (12134): Parameter "c_cnt_in_src10" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en10" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en10" = "false" Info (12134): Parameter "c_cnt_hi_div11" = "1" Info (12134): Parameter "c_cnt_lo_div11" = "1" Info (12134): Parameter "c_cnt_prst11" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst11" = "0" Info (12134): Parameter "c_cnt_in_src11" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en11" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en11" = "false" Info (12134): Parameter "c_cnt_hi_div12" = "1" Info (12134): Parameter "c_cnt_lo_div12" = "1" Info (12134): Parameter "c_cnt_prst12" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst12" = "0" Info (12134): Parameter "c_cnt_in_src12" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en12" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en12" = "false" Info (12134): Parameter "c_cnt_hi_div13" = "1" Info (12134): Parameter "c_cnt_lo_div13" = "1" Info (12134): Parameter "c_cnt_prst13" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst13" = "0" Info (12134): Parameter "c_cnt_in_src13" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en13" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en13" = "false" Info (12134): Parameter "c_cnt_hi_div14" = "1" Info (12134): Parameter "c_cnt_lo_div14" = "1" Info (12134): Parameter "c_cnt_prst14" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst14" = "0" Info (12134): Parameter "c_cnt_in_src14" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en14" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en14" = "false" Info (12134): Parameter "c_cnt_hi_div15" = "1" Info (12134): Parameter "c_cnt_lo_div15" = "1" Info (12134): Parameter "c_cnt_prst15" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst15" = "0" Info (12134): Parameter "c_cnt_in_src15" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en15" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en15" = "false" Info (12134): Parameter "c_cnt_hi_div16" = "1" Info (12134): Parameter "c_cnt_lo_div16" = "1" Info (12134): Parameter "c_cnt_prst16" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst16" = "0" Info (12134): Parameter "c_cnt_in_src16" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en16" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en16" = "false" Info (12134): Parameter "c_cnt_hi_div17" = "1" Info (12134): Parameter "c_cnt_lo_div17" = "1" Info (12134): Parameter "c_cnt_prst17" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst17" = "0" Info (12134): Parameter "c_cnt_in_src17" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en17" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en17" = "false" Info (12134): Parameter "pll_vco_div" = "2" Info (12134): Parameter "pll_cp_current" = "20" Info (12134): Parameter "pll_bwctrl" = "4000" Info (12134): Parameter "pll_output_clk_frequency" = "559.999999 MHz" Info (12134): Parameter "pll_fractional_division" = "3355443" Info (12134): Parameter "mimic_fbclk_type" = "none" Info (12134): Parameter "pll_fbclk_mux_1" = "glb" Info (12134): Parameter "pll_fbclk_mux_2" = "m_cnt" Info (12134): Parameter "pll_m_cnt_in_src" = "ph_mux_clk" Info (12134): Parameter "pll_slf_rst" = "false" Info (12128): Elaborating entity "dps_extra_kick" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 768 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 768 Info (12128): Elaborating entity "dprio_init" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|dprio_init:dprio_init_inst" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 783 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|dprio_init:dprio_init_inst", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 783 Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1960 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1960 Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1971 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1971 Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1982 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1982 Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1993 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1993 Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2004 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2004 Info (12128): Elaborating entity "altera_cyclonev_pll" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2223 Warning (10034): Output port "extclk" at altera_cyclonev_pll.v(631) has no driver File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 631 Warning (10034): Output port "clkout[0]" at altera_cyclonev_pll.v(636) has no driver File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 636 Warning (10034): Output port "loaden" at altera_cyclonev_pll.v(640) has no driver File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 640 Warning (10034): Output port "lvdsclk" at altera_cyclonev_pll.v(641) has no driver File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 641 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2223 Info (12128): Elaborating entity "altera_cyclonev_pll_base" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1152 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1152 Info (12128): Elaborating entity "acl_timer" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|acl_timer:counter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 95 Info (12128): Elaborating entity "global_routing" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|global_routing:global_routing_kernel_clk" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 100 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_avalon_mm_bridge:ctrl" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 139 Info (12128): Elaborating entity "sw_reset" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|sw_reset:pll_sw_reset" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 154 Info (12128): Elaborating entity "pll_lock_avs" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|pll_lock_avs:pll_lock_avs_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 165 Info (12128): Elaborating entity "version_id" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|version_id:version_id_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 175 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_pll_rom" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 190 Info (12128): Elaborating entity "altsyncram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Line: 79 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Line: 79 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Line: 79 Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "init_file" = "pll_rom.hex" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "maximum_depth" = "256" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "operation_mode" = "SINGLE_PORT" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "read_during_write_mode_port_a" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12134): Parameter "widthad_a" = "8" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_lil1.tdf Info (12023): Found entity 1: altsyncram_lil1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_lil1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791 Critical Warning (127005): Memory depth (256) in the design file differs from memory depth (8) in the Memory Initialization File "C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/pll_rom.hex" -- setting initial value for remaining addresses to 0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Line: 79 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 233 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:ctrl_m0_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 451 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pll_rom_s1_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 515 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_s_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 579 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pll_sw_reset_s_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 643 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pll_lock_avs_0_s_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 707 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:ctrl_m0_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 852 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pll_rom_s1_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 936 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pll_rom_s1_agent|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pll_rom_s1_agent_rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 977 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_s_agent_rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1102 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_s_agent_rdata_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1143 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_router:router" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1534 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_router:router|system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router.sv Line: 188 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001:router_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1550 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001:router_001|system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001.sv Line: 173 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:ctrl_m0_limiter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1664 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux:cmd_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1705 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux:cmd_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1722 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux:rsp_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1807 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux_001:rsp_demux_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1824 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux:rsp_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1916 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux.sv Line: 358 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_avalon_dc_fifo:async_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1961 Info (12128): Elaborating entity "altera_dcfifo_synchronizer_bundle" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_avalon_dc_fifo:async_fifo|altera_dcfifo_synchronizer_bundle:write_crosser" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_dc_fifo.v Line: 373 Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_avalon_dc_fifo:async_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v Line: 33 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_avalon_st_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_mm_interconnect_3_avalon_st_adapter:avalon_st_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 2035 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_avalon_st_adapter_error_adapter_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_mm_interconnect_3_avalon_st_adapter:avalon_st_adapter|system_acl_iface_mm_interconnect_3_avalon_st_adapter_error_adapter_0:error_adapter_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_avalon_st_adapter.v Line: 200 Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_reset_controller:rst_controller" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 296 Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_reset_controller:rst_controller_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 359 Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_reset_controller.v Line: 208 Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_reset_controller.v Line: 220 Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_reset_controller:rst_controller_002" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 422 Info (12128): Elaborating entity "altera_avalon_mm_clock_crossing_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 404 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem0|altera_avalon_dc_fifo:cmd_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 149 Info (12128): Elaborating entity "altera_dcfifo_synchronizer_bundle" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem0|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_dc_fifo.v Line: 373 Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem0|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v Line: 33 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem0|altera_avalon_dc_fifo:rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 282 Info (12128): Elaborating entity "system_acl_iface_acl_memory_bank_divider" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 433 Info (12128): Elaborating entity "snoop_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_memory_bank_divider.v Line: 72 Info (12128): Elaborating entity "dcfifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/snoop_adapter.v Line: 108 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/snoop_adapter.v Line: 108 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/snoop_adapter.v Line: 108 Info (12134): Parameter "intended_device_family" = "Stratix IV" Info (12134): Parameter "lpm_numwords" = "256" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "dcfifo" Info (12134): Parameter "lpm_width" = "30" Info (12134): Parameter "lpm_widthu" = "8" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "rdsync_delaypipe" = "4" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12134): Parameter "wrsync_delaypipe" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_e8n1.tdf Info (12023): Found entity 1: dcfifo_e8n1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dcfifo_e8n1.tdf Line: 40 Info (12128): Elaborating entity "dcfifo_e8n1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/dcfifo.tdf Line: 190 Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_g9b.tdf Info (12023): Found entity 1: a_gray2bin_g9b File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_gray2bin_g9b.tdf Line: 22 Info (12128): Elaborating entity "a_gray2bin_g9b" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|a_gray2bin_g9b:rdptr_g_gray2bin" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dcfifo_e8n1.tdf Line: 54 Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_dg6.tdf Info (12023): Found entity 1: a_graycounter_dg6 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_graycounter_dg6.tdf Line: 24 Info (12128): Elaborating entity "a_graycounter_dg6" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|a_graycounter_dg6:rdptr_g1p" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dcfifo_e8n1.tdf Line: 56 Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_9ub.tdf Info (12023): Found entity 1: a_graycounter_9ub File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_graycounter_9ub.tdf Line: 24 Info (12128): Elaborating entity "a_graycounter_9ub" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|a_graycounter_9ub:wrptr_g1p" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dcfifo_e8n1.tdf Line: 57 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1b81.tdf Info (12023): Found entity 1: altsyncram_1b81 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_1b81" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dcfifo_e8n1.tdf Line: 58 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_1v8.tdf Info (12023): Found entity 1: dffpipe_1v8 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dffpipe_1v8.tdf Line: 24 Info (12128): Elaborating entity "dffpipe_1v8" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|dffpipe_1v8:rs_brp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dcfifo_e8n1.tdf Line: 65 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_h9l.tdf Info (12023): Found entity 1: alt_synch_pipe_h9l File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/alt_synch_pipe_h9l.tdf Line: 26 Info (12128): Elaborating entity "alt_synch_pipe_h9l" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|alt_synch_pipe_h9l:rs_dgwp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dcfifo_e8n1.tdf Line: 67 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_2v8.tdf Info (12023): Found entity 1: dffpipe_2v8 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dffpipe_2v8.tdf Line: 24 Info (12128): Elaborating entity "dffpipe_2v8" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|alt_synch_pipe_h9l:rs_dgwp|dffpipe_2v8:dffpipe13" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/alt_synch_pipe_h9l.tdf Line: 33 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_i9l.tdf Info (12023): Found entity 1: alt_synch_pipe_i9l File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/alt_synch_pipe_i9l.tdf Line: 26 Info (12128): Elaborating entity "alt_synch_pipe_i9l" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|alt_synch_pipe_i9l:ws_dgrp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dcfifo_e8n1.tdf Line: 68 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_3v8.tdf Info (12023): Found entity 1: dffpipe_3v8 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dffpipe_3v8.tdf Line: 24 Info (12128): Elaborating entity "dffpipe_3v8" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|alt_synch_pipe_i9l:ws_dgrp|dffpipe_3v8:dffpipe16" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/alt_synch_pipe_i9l.tdf Line: 33 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_1v5.tdf Info (12023): Found entity 1: cmpr_1v5 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/cmpr_1v5.tdf Line: 22 Info (12128): Elaborating entity "cmpr_1v5" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|cmpr_1v5:rdempty_eq_comp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dcfifo_e8n1.tdf Line: 72 Info (12128): Elaborating entity "version_id" for hierarchy "system:the_system|system_acl_iface:acl_iface|version_id:version_id" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 479 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 546 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_pll0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_pll0:pll0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 156 Info (10648): Verilog HDL Display System Task info at system_acl_iface_fpga_sdram_pll0.sv(157): Using Regular pll emif simulation models File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_pll0.sv Line: 157 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 281 Info (10648): Verilog HDL Display System Task info at system_acl_iface_fpga_sdram_p0.sv(405): Using Regular core emif simulation models File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0.sv Line: 405 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_acv_hard_memphy" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0.sv Line: 573 Warning (10036): Verilog HDL or VHDL warning at system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v(436): object "seq_calib_init_reg" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Line: 436 Warning (10230): Verilog HDL assignment warning at system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v(557): truncated value with size 4 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Line: 557 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_reset" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Line: 487 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_reset_sync" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_afi_clk" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset.v Line: 87 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_reset_sync" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_ctl_reset_clk" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset.v Line: 95 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_reset_sync" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_addr_cmd_clk" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset.v Line: 103 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_reset_sync" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_avl_clk" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset.v Line: 137 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_acv_ldc" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_ldc:memphy_ldc" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Line: 554 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_acv_hard_io_pads" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Line: 780 Warning (10034): Output port "ddio_phy_dqdin[179..140]" at system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v(192) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 192 Warning (10034): Output port "ddio_phy_dqdin[107..104]" at system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v(192) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 192 Warning (10034): Output port "ddio_phy_dqdin[71..68]" at system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v(192) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 192 Warning (10034): Output port "ddio_phy_dqdin[35..32]" at system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v(192) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 192 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 245 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|system_acl_iface_fpga_sdram_p0_generic_ddio:uaddress_pad" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 157 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|system_acl_iface_fpga_sdram_p0_generic_ddio:ubank_pad" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 166 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|system_acl_iface_fpga_sdram_p0_generic_ddio:ucmd_pad" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 189 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|system_acl_iface_fpga_sdram_p0_generic_ddio:ureset_n_pad" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 198 Info (12128): Elaborating entity "altddio_out" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 317 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 317 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 317 Info (12134): Parameter "extend_oe_disable" = "UNUSED" Info (12134): Parameter "intended_device_family" = "Cyclone V" Info (12134): Parameter "invert_output" = "OFF" Info (12134): Parameter "lpm_hint" = "UNUSED" Info (12134): Parameter "lpm_type" = "altddio_out" Info (12134): Parameter "oe_reg" = "UNUSED" Info (12134): Parameter "power_up_high" = "OFF" Info (12134): Parameter "width" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/ddio_out_uqe.tdf Info (12023): Found entity 1: ddio_out_uqe File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/ddio_out_uqe.tdf Line: 27 Info (12128): Elaborating entity "ddio_out_uqe" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad|ddio_out_uqe:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altddio_out.tdf Line: 100 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_clock_pair_generator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|system_acl_iface_fpga_sdram_p0_clock_pair_generator:clock_gen[0].uclk_generator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 337 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_altdqdqs" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 317 Info (12128): Elaborating entity "altdq_dqs2_acv_connect_to_hard_phy_cyclonev" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_altdqdqs.v Line: 143 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 303 Info (12128): Elaborating entity "altera_mem_if_sequencer_rst" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_rst:sequencer_rst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 79 Info (12128): Elaborating entity "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 99 Info (12128): Elaborating entity "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench:the_altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 803 Info (12128): Elaborating entity "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module:altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 1266 Info (12128): Elaborating entity "altsyncram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module:altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a|altsyncram:the_altsyncram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 68 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module:altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a|altsyncram:the_altsyncram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 68 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module:altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a|altsyncram:the_altsyncram" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 68 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "32" Info (12134): Parameter "numwords_b" = "32" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "widthad_a" = "5" Info (12134): Parameter "widthad_b" = "5" Info (12134): Parameter "intended_device_family" = "CYCLONEV" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_mri1.tdf Info (12023): Found entity 1: altsyncram_mri1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_mri1.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_mri1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module:altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a|altsyncram:the_altsyncram|altsyncram_mri1:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791 Info (12128): Elaborating entity "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b_module" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b_module:altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 1288 Info (12128): Elaborating entity "sequencer_scc_mgr" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 140 Info (12128): Elaborating entity "sequencer_scc_reg_file" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_mgr.sv Line: 581 Info (12128): Elaborating entity "altdpram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_reg_file.v Line: 59 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_reg_file.v Line: 59 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_reg_file.v Line: 59 Info (12134): Parameter "indata_aclr" = "OFF" Info (12134): Parameter "indata_reg" = "INCLOCK" Info (12134): Parameter "intended_device_family" = "Stratix IV" Info (12134): Parameter "lpm_type" = "altdpram" Info (12134): Parameter "outdata_aclr" = "OFF" Info (12134): Parameter "outdata_reg" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "MLAB" Info (12134): Parameter "rdaddress_aclr" = "OFF" Info (12134): Parameter "rdaddress_reg" = "UNREGISTERED" Info (12134): Parameter "rdcontrol_aclr" = "OFF" Info (12134): Parameter "rdcontrol_reg" = "UNREGISTERED" Info (12134): Parameter "width" = "19" Info (12134): Parameter "widthad" = "6" Info (12134): Parameter "width_byteena" = "1" Info (12134): Parameter "wraddress_aclr" = "OFF" Info (12134): Parameter "wraddress_reg" = "INCLOCK" Info (12134): Parameter "wrcontrol_aclr" = "OFF" Info (12134): Parameter "wrcontrol_reg" = "INCLOCK" Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_k3s1.tdf Info (12023): Found entity 1: dpram_k3s1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dpram_k3s1.tdf Line: 29 Info (12128): Elaborating entity "dpram_k3s1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altdpram.tdf Line: 202 Info (12021): Found 1 design units, including 1 entities, in source file db/decode_5la.tdf Info (12023): Found entity 1: decode_5la File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/decode_5la.tdf Line: 22 Info (12128): Elaborating entity "decode_5la" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|decode_5la:wr_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dpram_k3s1.tdf Line: 39 Info (12021): Found 1 design units, including 1 entities, in source file db/mux_7hb.tdf Info (12023): Found entity 1: mux_7hb File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/mux_7hb.tdf Line: 22 Info (12128): Elaborating entity "mux_7hb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|mux_7hb:rd_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/dpram_k3s1.tdf Line: 40 Info (12128): Elaborating entity "sequencer_scc_acv_wrapper" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_acv_wrapper:sequencer_scc_family_wrapper" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_mgr.sv Line: 680 Info (12128): Elaborating entity "sequencer_scc_acv_phase_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_acv_wrapper:sequencer_scc_family_wrapper|sequencer_scc_acv_phase_decode:sequencer_scc_phase_decode_dqe_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_scc_acv_wrapper.sv Line: 79 Info (12128): Elaborating entity "sequencer_reg_file" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 159 Info (12128): Elaborating entity "altsyncram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_reg_file.sv Line: 134 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_reg_file.sv Line: 134 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/sequencer_reg_file.sv Line: 134 Info (12134): Parameter "address_aclr_b" = "CLEAR0" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "Stratix III" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "ram_block_type" = "MLAB" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "numwords_a" = "16" Info (12134): Parameter "numwords_b" = "16" Info (12134): Parameter "widthad_a" = "4" Info (12134): Parameter "widthad_b" = "4" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12134): Parameter "width_byteena_b" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_c9v1.tdf Info (12023): Found entity 1: altsyncram_c9v1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_c9v1.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_c9v1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791 Info (12128): Elaborating entity "altera_mem_if_simple_avalon_mm_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_simple_avalon_mm_bridge:hphy_bridge" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 195 Info (12128): Elaborating entity "altera_mem_if_sequencer_mem_no_ifdef_params" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_mem_no_ifdef_params:sequencer_mem" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 215 Info (12128): Elaborating entity "altsyncram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_mem_no_ifdef_params:sequencer_mem|altsyncram:the_altsyncram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv Line: 83 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_mem_no_ifdef_params:sequencer_mem|altsyncram:the_altsyncram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv Line: 83 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_mem_no_ifdef_params:sequencer_mem|altsyncram:the_altsyncram" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv Line: 83 Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "maximum_depth" = "3584" Info (12134): Parameter "numwords_a" = "3584" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12134): Parameter "widthad_a" = "12" Info (12134): Parameter "init_file" = "system_acl_iface_fpga_sdram_s0_sequencer_mem.hex" Info (12134): Parameter "operation_mode" = "SINGLE_PORT" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_rbl1.tdf Info (12023): Found entity 1: altsyncram_rbl1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_rbl1.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_rbl1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_mem_no_ifdef_params:sequencer_mem|altsyncram:the_altsyncram|altsyncram_rbl1:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 256 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:cpu_inst_data_master_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 405 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:cpu_inst_instruction_master_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 465 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:hphy_bridge_s0_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 529 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sequencer_mem_s1_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 593 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sequencer_scc_mgr_inst_avl_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 657 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sequencer_reg_file_inst_avl_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 721 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:cpu_inst_data_master_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 802 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:cpu_inst_instruction_master_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 883 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:hphy_bridge_s0_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 967 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:hphy_bridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:hphy_bridge_s0_agent_rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1008 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router:router" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1399 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router:router|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router.sv Line: 182 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001:router_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1415 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001:router_001|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001.sv Line: 174 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002:router_002" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1431 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002:router_002|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003:router_003" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1447 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003:router_003|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003.sv Line: 178 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux:cmd_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1514 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux_001:cmd_demux_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1531 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux:cmd_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1548 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001:cmd_mux_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1571 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001:cmd_mux_001|altera_merlin_arbitrator:arb" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001.sv Line: 331 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001:cmd_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_demux_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_demux_001:rsp_demux_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1645 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux:rsp_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1714 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux.sv Line: 342 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux_001:rsp_mux_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1731 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1760 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter.v Line: 200 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_irq_mapper" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_irq_mapper:irq_mapper" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 262 Info (12128): Elaborating entity "altera_mem_if_hard_memory_controller_top_cyclonev" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|altera_mem_if_hard_memory_controller_top_cyclonev:c0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 859 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of target (256) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1166 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1167 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168): truncated value with size 320 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1168 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169): truncated value with size 320 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1169 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1170 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1171 Info (12128): Elaborating entity "altera_mem_if_oct_cyclonev" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|altera_mem_if_oct_cyclonev:oct0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 867 Info (12128): Elaborating entity "altera_mem_if_dll_cyclonev" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|altera_mem_if_dll_cyclonev:dll0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 879 Info (12128): Elaborating entity "system_acl_iface_hps" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 683 Info (12128): Elaborating entity "system_acl_iface_hps_fpga_interfaces" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_hps.v Line: 260 Info (12128): Elaborating entity "system_acl_iface_hps_hps_io" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_hps.v Line: 307 Info (12128): Elaborating entity "system_acl_iface_hps_hps_io_border" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_hps_hps_io.v Line: 101 Info (12128): Elaborating entity "hps_sdram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 254 Info (12128): Elaborating entity "hps_sdram_pll" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram.v Line: 105 Warning (10036): Verilog HDL or VHDL warning at hps_sdram_pll.sv(168): object "pll_dr_clk" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_pll.sv Line: 168 Warning (10034): Output port "pll_locked" at hps_sdram_pll.sv(91) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_pll.sv Line: 91 Info (12128): Elaborating entity "hps_sdram_p0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram.v Line: 230 Info (10648): Verilog HDL Display System Task info at hps_sdram_p0.sv(405): Using Regular core emif simulation models File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0.sv Line: 405 Info (12128): Elaborating entity "hps_sdram_p0_acv_hard_memphy" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0.sv Line: 573 Warning (10858): Verilog HDL warning at hps_sdram_p0_acv_hard_memphy.v(420): object reset_n_seq_clk used but never assigned File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 420 Warning (10230): Verilog HDL assignment warning at hps_sdram_p0_acv_hard_memphy.v(557): truncated value with size 4 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 557 Warning (10030): Net "reset_n_seq_clk" at hps_sdram_p0_acv_hard_memphy.v(420) has no driver or initial value, using a default initial value '0' File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 420 Warning (10034): Output port "ctl_reset_export_n" at hps_sdram_p0_acv_hard_memphy.v(222) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 222 Info (12128): Elaborating entity "hps_sdram_p0_acv_ldc" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 554 Warning (10036): Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(45): object "phy_clk_dq" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 45 Warning (10036): Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(47): object "phy_clk_dqs_2x" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 47 Info (12128): Elaborating entity "hps_sdram_p0_acv_hard_io_pads" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 780 Warning (10034): Output port "ddio_phy_dqdin[179..176]" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 191 Warning (10034): Output port "ddio_phy_dqdin[143..140]" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 191 Warning (10034): Output port "ddio_phy_dqdin[107..104]" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 191 Warning (10034): Output port "ddio_phy_dqdin[71..68]" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 191 Warning (10034): Output port "ddio_phy_dqdin[35..32]" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 191 Info (12128): Elaborating entity "hps_sdram_p0_acv_hard_addr_cmd_pads" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 244 Info (12128): Elaborating entity "hps_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:uaddress_pad" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 157 Info (12128): Elaborating entity "hps_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ubank_pad" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 166 Info (12128): Elaborating entity "hps_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ucmd_pad" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 189 Info (12128): Elaborating entity "hps_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ureset_n_pad" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 198 Info (12128): Elaborating entity "hps_sdram_p0_clock_pair_generator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_clock_pair_generator:clock_gen[0].uclk_generator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 337 Info (12128): Elaborating entity "hps_sdram_p0_altdqdqs" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 317 Info (12128): Elaborating entity "altdq_dqs2_acv_connect_to_hard_phy_cyclonev" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram_p0_altdqdqs.v Line: 146 Info (12128): Elaborating entity "altera_mem_if_hhp_qseq_synth_top" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hhp_qseq_synth_top:seq" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram.v Line: 238 Warning (12158): Entity "altera_mem_if_hhp_qseq_synth_top" contains only dangling pins File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram.v Line: 238 Info (12128): Elaborating entity "altera_mem_if_hard_memory_controller_top_cyclonev" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hps_sdram.v Line: 794 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1166 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1167 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168): truncated value with size 320 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1168 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169): truncated value with size 320 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1169 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1170 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1171 Info (12128): Elaborating entity "system_acl_iface_kernel_interface" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 716 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_sys_description_rom" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_sys_description_rom:sys_description_rom" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 130 Info (12128): Elaborating entity "altsyncram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_sys_description_rom:sys_description_rom|altsyncram:the_altsyncram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_sys_description_rom.v Line: 79 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_sys_description_rom:sys_description_rom|altsyncram:the_altsyncram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_sys_description_rom.v Line: 79 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_sys_description_rom:sys_description_rom|altsyncram:the_altsyncram" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_sys_description_rom.v Line: 79 Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "init_file" = "sys_description.hex" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "maximum_depth" = "512" Info (12134): Parameter "numwords_a" = "512" Info (12134): Parameter "operation_mode" = "SINGLE_PORT" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "read_during_write_mode_port_a" = "DONT_CARE" Info (12134): Parameter "width_a" = "64" Info (12134): Parameter "width_byteena_a" = "8" Info (12134): Parameter "widthad_a" = "9" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_2em1.tdf Info (12023): Found entity 1: altsyncram_2em1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_2em1.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_2em1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_sys_description_rom:sys_description_rom|altsyncram:the_altsyncram|altsyncram_2em1:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791 Critical Warning (127005): Memory depth (512) in the design file differs from memory depth (26) in the Memory Initialization File "C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/sys_description.hex" -- setting initial value for remaining addresses to 0 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_sys_description_rom.v Line: 79 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|altera_avalon_mm_bridge:kernel_cra" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 164 Info (12128): Elaborating entity "altera_address_span_extender" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|altera_address_span_extender:address_span_extender_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 203 Info (12128): Elaborating entity "sw_reset" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|sw_reset:sw_reset" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 218 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|altera_avalon_mm_bridge:kernel_cntrl" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 252 Info (12128): Elaborating entity "mem_org_mode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mem_org_mode:mem_org_mode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 266 Warning (10230): Verilog HDL assignment warning at mem_org_mode.v(30): truncated value with size 32 to match size of target (2) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/mem_org_mode.v Line: 30 Warning (10230): Verilog HDL assignment warning at mem_org_mode.v(35): truncated value with size 2 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/mem_org_mode.v Line: 35 Info (12128): Elaborating entity "altera_irq_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|altera_irq_bridge:irq_bridge_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 306 Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|altera_reset_controller:reset_controller_sw" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 379 Info (12128): Elaborating entity "irq_ena" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|irq_ena:irq_ena_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 392 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 417 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:address_span_extender_0_expanded_master_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 190 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:kernel_cra_s0_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 254 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:address_span_extender_0_expanded_master_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 335 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:kernel_cra_s0_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 419 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:kernel_cra_s0_agent|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:kernel_cra_s0_agent_rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 460 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_kernel_interface_mm_interconnect_0_router:router" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 476 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_kernel_interface_mm_interconnect_0_router:router|system_acl_iface_kernel_interface_mm_interconnect_0_router_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_router.sv Line: 174 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_kernel_interface_mm_interconnect_0_router_001:router_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 492 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_kernel_interface_mm_interconnect_0_router_001:router_001|system_acl_iface_kernel_interface_mm_interconnect_0_router_001_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_router_001.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_kernel_interface_mm_interconnect_0_cmd_demux:cmd_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 509 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_kernel_interface_mm_interconnect_0_cmd_mux:cmd_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 526 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_kernel_interface_mm_interconnect_0_rsp_mux:rsp_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 560 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:kernel_cra_s0_cmd_width_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 626 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 283 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:kernel_cra_s0_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 954 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:kernel_cra_s0_rsp_width_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 692 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_avalon_st_adapter_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_mm_interconnect_6_avalon_st_adapter_002:avalon_st_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 721 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_avalon_st_adapter_002_error_adapter_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_mm_interconnect_6_avalon_st_adapter_002:avalon_st_adapter|system_acl_iface_mm_interconnect_6_avalon_st_adapter_002_error_adapter_0:error_adapter_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_avalon_st_adapter_002.v Line: 200 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 476 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:kernel_cntrl_m0_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 632 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:address_span_extender_0_windowed_slave_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 696 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:address_span_extender_0_cntl_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 760 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:sys_description_rom_s1_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 824 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:sw_reset_s_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 888 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:mem_org_mode_s_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 952 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:version_id_0_s_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1016 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_agent:kernel_cntrl_m0_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1161 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:address_span_extender_0_windowed_slave_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1245 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:address_span_extender_0_windowed_slave_agent|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:address_span_extender_0_windowed_slave_agent_rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1286 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:address_span_extender_0_cntl_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1411 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:address_span_extender_0_cntl_agent|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:address_span_extender_0_cntl_agent_rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1452 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:address_span_extender_0_cntl_agent_rdata_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1493 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:sys_description_rom_s1_agent_rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1618 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_router:router" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2134 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_router:router|system_acl_iface_kernel_interface_mm_interconnect_1_router_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router.sv Line: 190 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_router_001:router_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2150 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_router_001:router_001|system_acl_iface_kernel_interface_mm_interconnect_1_router_001_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_001.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_router_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_router_002:router_002" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2166 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_router_002_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_router_002:router_002|system_acl_iface_kernel_interface_mm_interconnect_1_router_002_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_002.sv Line: 173 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_traffic_limiter:kernel_cntrl_m0_limiter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2296 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_cmd_demux:cmd_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2349 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_cmd_mux:cmd_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2366 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux:rsp_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2485 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux_002:rsp_demux_002" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2519 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux:rsp_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2640 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux.sv Line: 390 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_width_adapter:address_span_extender_0_cntl_cmd_width_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2706 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 283 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_width_adapter:address_span_extender_0_cntl_rsp_width_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2904 Info (12128): Elaborating entity "altera_avalon_st_handshake_clock_crosser" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_st_handshake_clock_crosser:crosser" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 3070 Info (12128): Elaborating entity "altera_avalon_st_clock_crosser" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Line: 149 Info (12128): Elaborating entity "system_irq_mapper" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_irq_mapper:irq_mapper" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 483 Info (12128): Elaborating entity "system_acl_iface_pll" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_pll:pll" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 723 Info (12128): Elaborating entity "altera_pll" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_pll:pll|altera_pll:altera_pll_i" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_pll.v Line: 85 Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_pll:pll|altera_pll:altera_pll_i" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_pll.v Line: 85 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_pll:pll|altera_pll:altera_pll_i" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_pll.v Line: 85 Info (12134): Parameter "fractional_vco_multiplier" = "false" Info (12134): Parameter "reference_clock_frequency" = "50.0 MHz" Info (12134): Parameter "operation_mode" = "normal" Info (12134): Parameter "number_of_clocks" = "1" Info (12134): Parameter "output_clock_frequency0" = "100.000000 MHz" Info (12134): Parameter "phase_shift0" = "0 ps" Info (12134): Parameter "duty_cycle0" = "50" Info (12134): Parameter "output_clock_frequency1" = "0 MHz" Info (12134): Parameter "phase_shift1" = "0 ps" Info (12134): Parameter "duty_cycle1" = "50" Info (12134): Parameter "output_clock_frequency2" = "0 MHz" Info (12134): Parameter "phase_shift2" = "0 ps" Info (12134): Parameter "duty_cycle2" = "50" Info (12134): Parameter "output_clock_frequency3" = "0 MHz" Info (12134): Parameter "phase_shift3" = "0 ps" Info (12134): Parameter "duty_cycle3" = "50" Info (12134): Parameter "output_clock_frequency4" = "0 MHz" Info (12134): Parameter "phase_shift4" = "0 ps" Info (12134): Parameter "duty_cycle4" = "50" Info (12134): Parameter "output_clock_frequency5" = "0 MHz" Info (12134): Parameter "phase_shift5" = "0 ps" Info (12134): Parameter "duty_cycle5" = "50" Info (12134): Parameter "output_clock_frequency6" = "0 MHz" Info (12134): Parameter "phase_shift6" = "0 ps" Info (12134): Parameter "duty_cycle6" = "50" Info (12134): Parameter "output_clock_frequency7" = "0 MHz" Info (12134): Parameter "phase_shift7" = "0 ps" Info (12134): Parameter "duty_cycle7" = "50" Info (12134): Parameter "output_clock_frequency8" = "0 MHz" Info (12134): Parameter "phase_shift8" = "0 ps" Info (12134): Parameter "duty_cycle8" = "50" Info (12134): Parameter "output_clock_frequency9" = "0 MHz" Info (12134): Parameter "phase_shift9" = "0 ps" Info (12134): Parameter "duty_cycle9" = "50" Info (12134): Parameter "output_clock_frequency10" = "0 MHz" Info (12134): Parameter "phase_shift10" = "0 ps" Info (12134): Parameter "duty_cycle10" = "50" Info (12134): Parameter "output_clock_frequency11" = "0 MHz" Info (12134): Parameter "phase_shift11" = "0 ps" Info (12134): Parameter "duty_cycle11" = "50" Info (12134): Parameter "output_clock_frequency12" = "0 MHz" Info (12134): Parameter "phase_shift12" = "0 ps" Info (12134): Parameter "duty_cycle12" = "50" Info (12134): Parameter "output_clock_frequency13" = "0 MHz" Info (12134): Parameter "phase_shift13" = "0 ps" Info (12134): Parameter "duty_cycle13" = "50" Info (12134): Parameter "output_clock_frequency14" = "0 MHz" Info (12134): Parameter "phase_shift14" = "0 ps" Info (12134): Parameter "duty_cycle14" = "50" Info (12134): Parameter "output_clock_frequency15" = "0 MHz" Info (12134): Parameter "phase_shift15" = "0 ps" Info (12134): Parameter "duty_cycle15" = "50" Info (12134): Parameter "output_clock_frequency16" = "0 MHz" Info (12134): Parameter "phase_shift16" = "0 ps" Info (12134): Parameter "duty_cycle16" = "50" Info (12134): Parameter "output_clock_frequency17" = "0 MHz" Info (12134): Parameter "phase_shift17" = "0 ps" Info (12134): Parameter "duty_cycle17" = "50" Info (12134): Parameter "pll_type" = "General" Info (12134): Parameter "pll_subtype" = "General" Info (12128): Elaborating entity "altera_avalon_mm_clock_crossing_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 759 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:cmd_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 149 Info (12128): Elaborating entity "altera_dcfifo_synchronizer_bundle" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_dc_fifo.v Line: 373 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 282 Info (12128): Elaborating entity "altera_dcfifo_synchronizer_bundle" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_avalon_dc_fifo.v Line: 373 Info (12128): Elaborating entity "altera_address_span_extender" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_address_span_extender:address_span_extender_kernel" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 798 Info (12128): Elaborating entity "altera_address_span_extender" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_address_span_extender:address_span_extender_axi" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 837 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_bridge:mm_bridge_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 871 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_0:mm_interconnect_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 896 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:acl_memory_bank_divider_bank1_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_0.v Line: 104 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_cross_axi_fpga_s0_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_0.v Line: 168 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 920 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:clock_cross_kernel_mem1_m0_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 103 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:address_span_extender_kernel_windowed_slave_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 167 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 944 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_master_translator:address_span_extender_kernel_expanded_master_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 177 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_translator:hps_f2h_sdram0_data_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 241 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_master_agent:address_span_extender_kernel_expanded_master_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 322 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_agent:hps_f2h_sdram0_data_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 406 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_agent:hps_f2h_sdram0_data_agent|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_avalon_sc_fifo:hps_f2h_sdram0_data_agent_rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 447 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_router:router" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 463 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_router:router|system_acl_iface_mm_interconnect_2_router_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router.sv Line: 174 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_router_001:router_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 479 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_router_001:router_001|system_acl_iface_mm_interconnect_2_router_001_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router_001.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_cmd_demux:cmd_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 496 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_cmd_mux:cmd_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 513 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_rsp_mux:rsp_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 547 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_avalon_st_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_avalon_st_adapter:avalon_st_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 576 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_avalon_st_adapter_error_adapter_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_avalon_st_adapter:avalon_st_adapter|system_acl_iface_mm_interconnect_2_avalon_st_adapter_error_adapter_0:error_adapter_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_avalon_st_adapter.v Line: 200 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 995 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:address_span_extender_axi_windowed_slave_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 235 Info (12128): Elaborating entity "altera_merlin_axi_master_ni" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_axi_master_ni:hps_h2f_axi_master_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 363 Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_axi_master_ni:hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_axi_master_ni.sv Line: 485 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:address_span_extender_axi_windowed_slave_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 447 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:address_span_extender_axi_windowed_slave_agent|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:address_span_extender_axi_windowed_slave_agent_rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 488 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:address_span_extender_axi_windowed_slave_agent_rdata_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 529 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_router:router" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 545 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_router:router|system_acl_iface_mm_interconnect_3_router_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router.sv Line: 174 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_router_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_router_002:router_002" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 577 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_router_002_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_router_002:router_002|system_acl_iface_mm_interconnect_3_router_002_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router_002.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 627 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 778 Info (12128): Elaborating entity "altera_merlin_burst_adapter_burstwrap_increment" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 979 Info (12128): Elaborating entity "altera_merlin_burst_adapter_min" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 1004 Info (12128): Elaborating entity "altera_merlin_burst_adapter_subtractor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 157 Info (12128): Elaborating entity "altera_merlin_burst_adapter_adder" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 88 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_cmd_demux:cmd_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 644 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_cmd_mux:cmd_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 684 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_rsp_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_rsp_demux:rsp_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 707 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_rsp_mux:rsp_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 724 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 1019 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_master_translator:address_span_extender_axi_expanded_master_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 192 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_slave_translator:acl_memory_bank_divider_s_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 256 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_master_agent:address_span_extender_axi_expanded_master_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 337 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_slave_agent:acl_memory_bank_divider_s_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 421 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_slave_agent:acl_memory_bank_divider_s_agent|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_avalon_sc_fifo:acl_memory_bank_divider_s_agent_rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 462 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_avalon_sc_fifo:acl_memory_bank_divider_s_agent_rdata_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 503 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_router:router" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 519 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_router:router|system_acl_iface_mm_interconnect_4_router_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router.sv Line: 174 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_router_001:router_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 535 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_router_001:router_001|system_acl_iface_mm_interconnect_4_router_001_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router_001.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_cmd_demux:cmd_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 552 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_cmd_mux:cmd_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 569 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_rsp_mux:rsp_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 603 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_width_adapter:acl_memory_bank_divider_s_cmd_width_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 669 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 283 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_width_adapter:acl_memory_bank_divider_s_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 954 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_width_adapter:acl_memory_bank_divider_s_rsp_width_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 735 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 1056 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_merlin_master_translator:clock_cross_axi_fpga_m0_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 230 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_merlin_master_translator:clock_cross_kernel_mem0_m0_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 290 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_merlin_master_agent:clock_cross_axi_fpga_m0_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 435 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_merlin_master_agent:clock_cross_kernel_mem0_m0_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 516 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_merlin_slave_agent:fpga_sdram_avl_0_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 600 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_avalon_sc_fifo:fpga_sdram_avl_0_agent_rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 641 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_router:router" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 657 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_router:router|system_acl_iface_mm_interconnect_5_router_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router.sv Line: 174 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_router_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_router_002:router_002" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 689 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_router_002_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_router_002:router_002|system_acl_iface_mm_interconnect_5_router_002_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router_002.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_cmd_demux:cmd_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 706 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_cmd_mux:cmd_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 746 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_rsp_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_rsp_demux:rsp_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 769 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_rsp_mux:rsp_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 786 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 1088 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_master_translator:mm_bridge_0_m0_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 323 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_translator:version_id_s_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 387 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_translator:kernel_interface_ctrl_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 451 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_translator:address_span_extender_axi_cntl_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 515 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_master_agent:mm_bridge_0_m0_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 596 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_agent:version_id_s_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 680 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_agent:version_id_s_agent|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_agent:address_span_extender_axi_cntl_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 930 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_agent:address_span_extender_axi_cntl_agent|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_router:router" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 987 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_router:router|system_acl_iface_mm_interconnect_6_router_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router.sv Line: 186 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_router_001:router_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1003 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_router_001:router_001|system_acl_iface_mm_interconnect_6_router_001_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_001.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_router_003" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_router_003:router_003" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1035 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_router_003_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_router_003:router_003|system_acl_iface_mm_interconnect_6_router_003_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_003.sv Line: 173 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_traffic_limiter:mm_bridge_0_m0_limiter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1085 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_cmd_demux:cmd_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1114 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_cmd_mux:cmd_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1131 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_rsp_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_rsp_demux:rsp_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1182 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_rsp_mux:rsp_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1245 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_rsp_mux.sv Line: 326 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_width_adapter:address_span_extender_axi_cntl_cmd_width_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1311 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 283 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_width_adapter:address_span_extender_axi_cntl_rsp_width_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1377 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_7" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 1140 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_merlin_slave_translator:mm_bridge_0_s0_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 236 Info (12128): Elaborating entity "altera_merlin_axi_master_ni" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_merlin_axi_master_ni:hps_h2f_lw_axi_master_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 364 Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_merlin_axi_master_ni:hps_h2f_lw_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_axi_master_ni.sv Line: 485 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_merlin_slave_agent:mm_bridge_0_s0_agent" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 448 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_merlin_slave_agent:mm_bridge_0_s0_agent|altera_merlin_burst_uncompressor:uncompressor" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_avalon_sc_fifo:mm_bridge_0_s0_agent_rsp_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 489 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_avalon_sc_fifo:mm_bridge_0_s0_agent_rdata_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 530 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_7_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|system_acl_iface_mm_interconnect_7_router:router" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 546 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_7_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|system_acl_iface_mm_interconnect_7_router:router|system_acl_iface_mm_interconnect_7_router_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7_router.sv Line: 174 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_7_router_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|system_acl_iface_mm_interconnect_7_router_002:router_002" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 578 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_7_router_002_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|system_acl_iface_mm_interconnect_7_router_002:router_002|system_acl_iface_mm_interconnect_7_router_002_default_decode:the_default_decode" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7_router_002.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_merlin_burst_adapter:mm_bridge_0_s0_burst_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 628 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_merlin_burst_adapter:mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_merlin_burst_adapter:mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 778 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_7_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|system_acl_iface_mm_interconnect_7_cmd_demux:cmd_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 645 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_7_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|system_acl_iface_mm_interconnect_7_cmd_mux:cmd_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 685 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_7_rsp_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|system_acl_iface_mm_interconnect_7_rsp_demux:rsp_demux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 708 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_7_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|system_acl_iface_mm_interconnect_7_rsp_mux:rsp_mux" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 725 Info (12128): Elaborating entity "system_acl_iface_irq_mapper" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_irq_mapper:irq_mapper" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 1147 Info (12128): Elaborating entity "system_acl_iface_irq_mapper_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_irq_mapper_001:irq_mapper_001" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface.v Line: 1153 Info (12128): Elaborating entity "cra_ring_node" for hierarchy "system:the_system|cra_ring_node:avs_hello_world_cra_cra_ring" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/system.v Line: 297 Warning (10230): Verilog HDL assignment warning at cra_ring_node.sv(29): truncated value with size 32 to match size of target (2) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/cra_ring_node.sv Line: 29 Info (12128): Elaborating entity "acl_reset_handler" for hierarchy "system:the_system|cra_ring_node:avs_hello_world_cra_cra_ring|acl_reset_handler:acl_reset_handler_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/cra_ring_node.sv Line: 77 Info (12128): Elaborating entity "acl_reset_fanout_pipeline_with_synchronizer_and_pulse_extender" for hierarchy "system:the_system|cra_ring_node:avs_hello_world_cra_cra_ring|acl_reset_handler:acl_reset_handler_inst|acl_reset_fanout_pipeline_with_synchronizer_and_pulse_extender:reset_fanout_pipeline" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 92 Info (12128): Elaborating entity "acl_reset_pulse_extender" for hierarchy "system:the_system|cra_ring_node:avs_hello_world_cra_cra_ring|acl_reset_handler:acl_reset_handler_inst|acl_reset_fanout_pipeline_with_synchronizer_and_pulse_extender:reset_fanout_pipeline|acl_reset_pulse_extender:pulse_extender" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 171 Warning (10230): Verilog HDL assignment warning at acl_reset_handler.sv(227): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 227 Warning (10230): Verilog HDL assignment warning at acl_reset_handler.sv(244): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 244 Info (12128): Elaborating entity "acl_fanout_pipeline" for hierarchy "system:the_system|cra_ring_node:avs_hello_world_cra_cra_ring|acl_reset_handler:acl_reset_handler_inst|acl_reset_fanout_pipeline_with_synchronizer_and_pulse_extender:reset_fanout_pipeline|acl_fanout_pipeline:reset_sync_fanout_pipeline_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 183 Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "pipe" into its bus Info (12128): Elaborating entity "cra_ring_root" for hierarchy "system:the_system|cra_ring_root:cra_root" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/system.v Line: 330 Info (12128): Elaborating entity "hello_world_system" for hierarchy "system:the_system|hello_world_system:hello_world_system" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/system.v Line: 362 Info (12128): Elaborating entity "hello_world_partition_wrapper" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 144 Warning (10036): Verilog HDL or VHDL warning at hello_world_system.v(750): object "hello_world_finish_chain" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 750 Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "hello_world_global_id" into its bus Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "hello_world_local_id" into its bus Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "hello_world_group_id" into its bus Info (12128): Elaborating entity "acl_work_group_dispatcher" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_work_group_dispatcher:hello_world_workgroup_dispatcher" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 806 Info (12128): Elaborating entity "acl_kernel_finish_detector" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_kernel_finish_detector:hello_world_finish_detector" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 832 Info (12128): Elaborating entity "acl_multistage_accumulator" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_kernel_finish_detector:hello_world_finish_detector|acl_multistage_accumulator:ndrange_sum" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_kernel_finish_detector.v Line: 257 Warning (10230): Verilog HDL assignment warning at acl_multistage_accumulator.v(191): truncated value with size 97 to match size of target (96) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_multistage_accumulator.v Line: 191 Info (12128): Elaborating entity "acl_multistage_accumulator" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_kernel_finish_detector:hello_world_finish_detector|acl_multistage_accumulator:ndrange_completed" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_kernel_finish_detector.v Line: 299 Warning (10230): Verilog HDL assignment warning at acl_multistage_accumulator.v(191): truncated value with size 97 to match size of target (96) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_multistage_accumulator.v Line: 191 Info (12128): Elaborating entity "hello_world_function_cra_slave" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_function_cra_slave:hello_world_cra_slave_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 874 Info (12128): Elaborating entity "acl_id_iterator" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 905 Warning (10036): Verilog HDL or VHDL warning at acl_id_iterator.v(99): object "issue_check" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_id_iterator.v Line: 99 Warning (10034): Output port "stall_out_lookahead" at acl_id_iterator.v(59) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_id_iterator.v Line: 59 Warning (10034): Output port "valid_out_lookahead" at acl_id_iterator.v(64) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_id_iterator.v Line: 64 Info (12128): Elaborating entity "acl_shift_register" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_shift_register:register_block[0].acl_gid" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_id_iterator.v Line: 119 Info (12128): Elaborating entity "acl_shift_register" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_shift_register:acl_valid" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_id_iterator.v Line: 136 Info (12128): Elaborating entity "acl_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_id_iterator.v Line: 169 Info (12128): Elaborating entity "scfifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 213 Info (12130): Elaborated megafunction instantiation "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 213 Info (12133): Instantiated megafunction "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 213 Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "intended_device_family" = "Stratix IV" Info (12134): Parameter "lpm_hint" = "unused" Info (12134): Parameter "lpm_numwords" = "4" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "192" Info (12134): Parameter "lpm_widthu" = "2" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12134): Parameter "almost_full_value" = "0" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_25d1.tdf Info (12023): Found entity 1: scfifo_25d1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/scfifo_25d1.tdf Line: 24 Info (12128): Elaborating entity "scfifo_25d1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/scfifo.tdf Line: 299 Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_s7a1.tdf Info (12023): Found entity 1: a_dpfifo_s7a1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_s7a1.tdf Line: 32 Info (12128): Elaborating entity "a_dpfifo_s7a1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/scfifo_25d1.tdf Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1hn1.tdf Info (12023): Found entity 1: altsyncram_1hn1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_1hn1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_s7a1.tdf Line: 46 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_1l8.tdf Info (12023): Found entity 1: cmpr_1l8 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/cmpr_1l8.tdf Line: 22 Info (12128): Elaborating entity "cmpr_1l8" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cmpr_1l8:almost_full_comparer" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_s7a1.tdf Line: 55 Info (12128): Elaborating entity "cmpr_1l8" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cmpr_1l8:three_comparison" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_s7a1.tdf Line: 56 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_egb.tdf Info (12023): Found entity 1: cntr_egb File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/cntr_egb.tdf Line: 25 Info (12128): Elaborating entity "cntr_egb" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_s7a1.tdf Line: 57 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_rg7.tdf Info (12023): Found entity 1: cntr_rg7 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/cntr_rg7.tdf Line: 25 Info (12128): Elaborating entity "cntr_rg7" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_s7a1.tdf Line: 58 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_fgb.tdf Info (12023): Found entity 1: cntr_fgb File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/cntr_fgb.tdf Line: 25 Info (12128): Elaborating entity "cntr_fgb" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_s7a1.tdf Line: 59 Info (12128): Elaborating entity "acl_work_item_iterator" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_work_item_iterator:work_item_iterator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_id_iterator.v Line: 194 Warning (10036): Verilog HDL or VHDL warning at acl_work_item_iterator.v(113): object "global_total" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_work_item_iterator.v Line: 113 Warning (10036): Verilog HDL or VHDL warning at acl_work_item_iterator.v(114): object "local_total" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_work_item_iterator.v Line: 114 Warning (10034): Output port "group_id" at acl_work_item_iterator.v(95) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_work_item_iterator.v Line: 95 Warning (10034): Output port "stall_out" at acl_work_item_iterator.v(83) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_work_item_iterator.v Line: 83 Warning (10034): Output port "valid_out" at acl_work_item_iterator.v(87) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_work_item_iterator.v Line: 87 Warning (10034): Output port "valid_out_lookahead" at acl_work_item_iterator.v(88) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_work_item_iterator.v Line: 88 Info (12128): Elaborating entity "hello_world_top_wrapper_0" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 952 Info (12128): Elaborating entity "hello_world_function_wrapper" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1084 Info (12128): Elaborating entity "hello_world_function" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_function_wrapper.vhd Line: 215 Info (12128): Elaborating entity "bb_hello_world_B0" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_function.vhd Line: 145 Info (12128): Elaborating entity "hello_world_B0_branch" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|hello_world_B0_branch:thehello_world_B0_branch" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/bb_hello_world_B0.vhd Line: 168 Info (12128): Elaborating entity "hello_world_B0_merge" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|hello_world_B0_merge:thehello_world_B0_merge" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/bb_hello_world_B0.vhd Line: 179 Info (12128): Elaborating entity "bb_hello_world_B0_stall_region" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/bb_hello_world_B0.vhd Line: 192 Info (12128): Elaborating entity "i_printf_printf_addr_hello_world3" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_printf_printf_addr_hello_world3:thei_printf_printf_addr_hello_world" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/bb_hello_world_B0_stall_region.vhd Line: 376 Info (12128): Elaborating entity "acl_printf_buffer_address_generator" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_printf_printf_addr_hello_world3:thei_printf_printf_addr_hello_world|acl_printf_buffer_address_generator:thei_printf_printf_addr_hello_world4" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/i_printf_printf_addr_hello_world3.vhd Line: 148 Info (12128): Elaborating entity "i_syncbuf_thread_id_from_which_to_print_message_sync_buffer_hello_world0" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_syncbuf_thread_id_from_which_to_print_message_sync_buffer_hello_world0:thei_syncbuf_thread_id_from_which_to_print_message_sync_buffer_hello_world" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/bb_hello_world_B0_stall_region.vhd Line: 499 Info (12128): Elaborating entity "acl_dspba_buffer" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_syncbuf_thread_id_from_which_to_print_message_sync_buffer_hello_world0:thei_syncbuf_thread_id_from_which_to_print_message_sync_buffer_hello_world|acl_dspba_buffer:thei_syncbuf_thread_id_from_which_to_print_message_sync_buffer_hello_world1" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/i_syncbuf_thread_id_from_which_to_print_A0Zfer_hello_world0.vhd Line: 74 Info (12128): Elaborating entity "hello_world_B0_merge_reg" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|hello_world_B0_merge_reg:thehello_world_B0_merge_reg_aunroll_x" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/bb_hello_world_B0_stall_region.vhd Line: 567 Info (12128): Elaborating entity "acl_data_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|acl_data_fifo:thebubble_out_i_printf_printf_addr_hello_world_data_reg" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/bb_hello_world_B0_stall_region.vhd Line: 710 Info (12128): Elaborating entity "acl_data_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|acl_data_fifo:thebubble_out_i_printf_printf_addr_hello_world_data_reg|acl_data_fifo:fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 465 Warning (10230): Verilog HDL assignment warning at acl_data_fifo.v(135): truncated value with size 32 to match size of target (3) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 135 Info (12128): Elaborating entity "acl_data_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|acl_data_fifo:thebubble_out_i_printf_printf_addr_hello_world_data_reg|acl_data_fifo:fifo|acl_data_fifo:fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 160 Info (12128): Elaborating entity "acl_ll_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|acl_data_fifo:thebubble_out_i_printf_printf_addr_hello_world_data_reg|acl_data_fifo:fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 310 Info (12128): Elaborating entity "acl_staging_reg" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|acl_data_fifo:thebubble_out_i_printf_printf_addr_hello_world_data_reg|acl_data_fifo:fifo|acl_staging_reg:staging_reg" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 172 Info (12128): Elaborating entity "i_store_unnamed_hello_world0_hello_world6" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/bb_hello_world_B0_stall_region.vhd Line: 804 Info (12128): Elaborating entity "lsu_top" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/i_store_unnamed_hello_world0_hello_world6.vhd Line: 266 Warning (10034): Output port "o_readdata" at lsu_top.v(224) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_top.v Line: 224 Warning (10034): Output port "o_input_fifo_depth" at lsu_top.v(243) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_top.v Line: 243 Info (12128): Elaborating entity "acl_reset_handler" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|acl_reset_handler:acl_reset_handler_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_top.v Line: 284 Info (12128): Elaborating entity "acl_reset_fanout_pipeline_with_synchronizer_and_pulse_extender" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|acl_reset_handler:acl_reset_handler_inst|acl_reset_fanout_pipeline_with_synchronizer_and_pulse_extender:reset_fanout_pipeline" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 92 Info (12128): Elaborating entity "acl_std_synchronizer_nocut" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|acl_reset_handler:acl_reset_handler_inst|acl_reset_fanout_pipeline_with_synchronizer_and_pulse_extender:reset_fanout_pipeline|acl_std_synchronizer_nocut:GEN_SYNCHRONIZER.reset_synchronizer" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 158 Info (12128): Elaborating entity "acl_reset_pulse_extender" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|acl_reset_handler:acl_reset_handler_inst|acl_reset_fanout_pipeline_with_synchronizer_and_pulse_extender:reset_fanout_pipeline|acl_reset_pulse_extender:pulse_extender" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 171 Warning (10230): Verilog HDL assignment warning at acl_reset_handler.sv(227): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 227 Warning (10230): Verilog HDL assignment warning at acl_reset_handler.sv(244): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 244 Info (12128): Elaborating entity "acl_fanout_pipeline" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|acl_reset_handler:acl_reset_handler_inst|acl_reset_fanout_pipeline_with_synchronizer_and_pulse_extender:reset_fanout_pipeline|acl_fanout_pipeline:reset_sync_fanout_pipeline_inst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_reset_handler.sv Line: 183 Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "pipe" into its bus Info (12128): Elaborating entity "lsu_permute_address" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_permute_address:u_permute_address" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_top.v Line: 437 Info (12128): Elaborating entity "lsu_non_aligned_write" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_top.v Line: 1327 Warning (10230): Verilog HDL assignment warning at lsu_non_aligned_write.v(99): truncated value with size 32 to match size of target (31) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_non_aligned_write.v Line: 99 Info (12128): Elaborating entity "lsu_non_aligned_write_internal" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_non_aligned_write.v Line: 162 Info (12128): Elaborating entity "lsu_bursting_write" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_non_aligned_write.v Line: 387 Info (12128): Elaborating entity "lsu_bursting_write_internal" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1252 Warning (10230): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1622): truncated value with size 6 to match size of target (5) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1622 Warning (10230): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1640): truncated value with size 32 to match size of target (8) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1640 Warning (10230): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1654): truncated value with size 32 to match size of target (5) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1654 Info (12128): Elaborating entity "bursting_coalescer" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1455 Warning (10230): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1799): truncated value with size 32 to match size of target (26) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1799 Warning (10230): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1801): truncated value with size 32 to match size of target (5) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1801 Warning (10230): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1802): truncated value with size 32 to match size of target (5) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1802 Warning (10230): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1811): truncated value with size 32 to match size of target (5) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1811 Warning (10230): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1812): truncated value with size 32 to match size of target (10) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1812 Info (12128): Elaborating entity "acl_data_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1562 Info (12128): Elaborating entity "acl_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 366 Info (12128): Elaborating entity "scfifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 213 Info (12130): Elaborated megafunction instantiation "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 213 Info (12133): Instantiated megafunction "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 213 Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "intended_device_family" = "Stratix IV" Info (12134): Parameter "lpm_hint" = "unused" Info (12134): Parameter "lpm_numwords" = "48" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "288" Info (12134): Parameter "lpm_widthu" = "6" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12134): Parameter "almost_full_value" = "0" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_47d1.tdf Info (12023): Found entity 1: scfifo_47d1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/scfifo_47d1.tdf Line: 24 Info (12128): Elaborating entity "scfifo_47d1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_47d1:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/scfifo.tdf Line: 299 Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_u9a1.tdf Info (12023): Found entity 1: a_dpfifo_u9a1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_u9a1.tdf Line: 32 Info (12128): Elaborating entity "a_dpfifo_u9a1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_47d1:auto_generated|a_dpfifo_u9a1:dpfifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/scfifo_47d1.tdf Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1ln1.tdf Info (12023): Found entity 1: altsyncram_1ln1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1ln1.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_1ln1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_47d1:auto_generated|a_dpfifo_u9a1:dpfifo|altsyncram_1ln1:FIFOram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_u9a1.tdf Line: 46 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_5l8.tdf Info (12023): Found entity 1: cmpr_5l8 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/cmpr_5l8.tdf Line: 22 Info (12128): Elaborating entity "cmpr_5l8" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_47d1:auto_generated|a_dpfifo_u9a1:dpfifo|cmpr_5l8:almost_full_comparer" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_u9a1.tdf Line: 55 Info (12128): Elaborating entity "cmpr_5l8" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_47d1:auto_generated|a_dpfifo_u9a1:dpfifo|cmpr_5l8:three_comparison" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_u9a1.tdf Line: 56 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_igb.tdf Info (12023): Found entity 1: cntr_igb File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/cntr_igb.tdf Line: 25 Info (12128): Elaborating entity "cntr_igb" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_47d1:auto_generated|a_dpfifo_u9a1:dpfifo|cntr_igb:rd_ptr_msb" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_u9a1.tdf Line: 57 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_vg7.tdf Info (12023): Found entity 1: cntr_vg7 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/cntr_vg7.tdf Line: 25 Info (12128): Elaborating entity "cntr_vg7" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_47d1:auto_generated|a_dpfifo_u9a1:dpfifo|cntr_vg7:usedw_counter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_u9a1.tdf Line: 58 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_jgb.tdf Info (12023): Found entity 1: cntr_jgb File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/cntr_jgb.tdf Line: 25 Info (12128): Elaborating entity "cntr_jgb" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_47d1:auto_generated|a_dpfifo_u9a1:dpfifo|cntr_jgb:wr_ptr" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_u9a1.tdf Line: 59 Info (12128): Elaborating entity "acl_data_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 381 Warning (10230): Verilog HDL assignment warning at acl_data_fifo.v(135): truncated value with size 32 to match size of target (2) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 135 Info (12128): Elaborating entity "acl_data_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 160 Warning (10230): Verilog HDL assignment warning at acl_data_fifo.v(222): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 222 Info (12128): Elaborating entity "acl_staging_reg" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 172 Info (12128): Elaborating entity "acl_data_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1579 Info (12128): Elaborating entity "acl_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 366 Info (12128): Elaborating entity "scfifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 213 Info (12130): Elaborated megafunction instantiation "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 213 Info (12133): Instantiated megafunction "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 213 Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "intended_device_family" = "Stratix IV" Info (12134): Parameter "lpm_hint" = "unused" Info (12134): Parameter "lpm_numwords" = "96" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "8" Info (12134): Parameter "lpm_widthu" = "7" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12134): Parameter "almost_full_value" = "0" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_u3d1.tdf Info (12023): Found entity 1: scfifo_u3d1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/scfifo_u3d1.tdf Line: 24 Info (12128): Elaborating entity "scfifo_u3d1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u3d1:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/scfifo.tdf Line: 299 Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_o6a1.tdf Info (12023): Found entity 1: a_dpfifo_o6a1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_o6a1.tdf Line: 32 Info (12128): Elaborating entity "a_dpfifo_o6a1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u3d1:auto_generated|a_dpfifo_o6a1:dpfifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/scfifo_u3d1.tdf Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_hhn1.tdf Info (12023): Found entity 1: altsyncram_hhn1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_hhn1.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_hhn1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u3d1:auto_generated|a_dpfifo_o6a1:dpfifo|altsyncram_hhn1:FIFOram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_o6a1.tdf Line: 46 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_6l8.tdf Info (12023): Found entity 1: cmpr_6l8 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/cmpr_6l8.tdf Line: 22 Info (12128): Elaborating entity "cmpr_6l8" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u3d1:auto_generated|a_dpfifo_o6a1:dpfifo|cmpr_6l8:almost_full_comparer" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_o6a1.tdf Line: 55 Info (12128): Elaborating entity "cmpr_6l8" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u3d1:auto_generated|a_dpfifo_o6a1:dpfifo|cmpr_6l8:three_comparison" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_o6a1.tdf Line: 56 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_0h7.tdf Info (12023): Found entity 1: cntr_0h7 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/cntr_0h7.tdf Line: 25 Info (12128): Elaborating entity "cntr_0h7" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u3d1:auto_generated|a_dpfifo_o6a1:dpfifo|cntr_0h7:usedw_counter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_o6a1.tdf Line: 58 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_kgb.tdf Info (12023): Found entity 1: cntr_kgb File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/cntr_kgb.tdf Line: 25 Info (12128): Elaborating entity "cntr_kgb" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u3d1:auto_generated|a_dpfifo_o6a1:dpfifo|cntr_kgb:wr_ptr" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_o6a1.tdf Line: 59 Info (12128): Elaborating entity "acl_data_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 381 Warning (10230): Verilog HDL assignment warning at acl_data_fifo.v(135): truncated value with size 32 to match size of target (2) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 135 Info (12128): Elaborating entity "acl_data_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 160 Warning (10230): Verilog HDL assignment warning at acl_data_fifo.v(222): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 222 Info (12128): Elaborating entity "acl_staging_reg" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 172 Info (12128): Elaborating entity "acl_data_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1600 Info (12128): Elaborating entity "acl_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 366 Info (12128): Elaborating entity "scfifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 213 Info (12130): Elaborated megafunction instantiation "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 213 Info (12133): Instantiated megafunction "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_fifo.v Line: 213 Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "intended_device_family" = "Stratix IV" Info (12134): Parameter "lpm_hint" = "unused" Info (12134): Parameter "lpm_numwords" = "48" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "31" Info (12134): Parameter "lpm_widthu" = "6" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12134): Parameter "almost_full_value" = "0" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_65d1.tdf Info (12023): Found entity 1: scfifo_65d1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/scfifo_65d1.tdf Line: 24 Info (12128): Elaborating entity "scfifo_65d1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_65d1:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/scfifo.tdf Line: 299 Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_08a1.tdf Info (12023): Found entity 1: a_dpfifo_08a1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_08a1.tdf Line: 32 Info (12128): Elaborating entity "a_dpfifo_08a1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_65d1:auto_generated|a_dpfifo_08a1:dpfifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/scfifo_65d1.tdf Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_5hn1.tdf Info (12023): Found entity 1: altsyncram_5hn1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_5hn1.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_5hn1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_65d1:auto_generated|a_dpfifo_08a1:dpfifo|altsyncram_5hn1:FIFOram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_08a1.tdf Line: 46 Info (12128): Elaborating entity "acl_data_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 381 Warning (10230): Verilog HDL assignment warning at acl_data_fifo.v(135): truncated value with size 32 to match size of target (2) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 135 Info (12128): Elaborating entity "acl_data_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 160 Warning (10230): Verilog HDL assignment warning at acl_data_fifo.v(222): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 222 Info (12128): Elaborating entity "acl_staging_reg" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|hello_world_function:thehello_world_function|bb_hello_world_B0:thebb_hello_world_B0|bb_hello_world_B0_stall_region:thebb_hello_world_B0_stall_region|i_store_unnamed_hello_world0_hello_world6:thei_store_unnamed_hello_world0_hello_world_aunroll_x|lsu_top:thei_store_unnamed_hello_world0_hello_world7|lsu_non_aligned_write:bursting_non_aligned_write|lsu_non_aligned_write_internal:non_aligned_write|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_data_fifo.v Line: 172 Info (12128): Elaborating entity "acl_clock2x_holder" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|hello_world_top_wrapper_0:hello_world_inst_0|hello_world_function_wrapper:kernel|acl_clock2x_holder:theacl_clock2x_dummy_consumer" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_function_wrapper.vhd Line: 284 Info (12128): Elaborating entity "acl_start_signal_chain_element" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_start_signal_chain_element:hello_world_start_elem_inst_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 969 Info (12128): Elaborating entity "acl_avm_to_ic" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_avm_to_ic:gmem0_.t[0].gmem0_avm_to_ic" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 261 Info (12128): Elaborating entity "hello_world_system_interconnect_0" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_0:gmem0_.global_ic_preroutegmem0_router_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 309 Warning (10230): Verilog HDL assignment warning at hello_world_system.v(1155): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1155 Info (12128): Elaborating entity "acl_ic_master_intf" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_0:gmem0_.global_ic_preroutegmem0_router_0|acl_ic_master_intf:m[0].m_intf" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1136 Warning (12158): Entity "acl_ic_master_intf" contains only dangling pins File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1136 Info (12128): Elaborating entity "acl_arb_intf" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_0:gmem0_.global_ic_preroutegmem0_router_0|acl_arb_intf:m[0].arb_intf" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1144 Warning (12158): Entity "acl_arb_intf" contains only dangling pins File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1144 Info (12128): Elaborating entity "acl_ic_wrp_intf" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_0:gmem0_.global_ic_preroutegmem0_router_0|acl_ic_wrp_intf:m[0].wrp_intf" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1148 Warning (12158): Entity "acl_ic_wrp_intf" contains only dangling pins File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1148 Info (12128): Elaborating entity "acl_ic_rrp_intf" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_0:gmem0_.global_ic_preroutegmem0_router_0|acl_ic_rrp_intf:m[0].rrp_intf" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1153 Warning (12158): Entity "acl_ic_rrp_intf" contains only dangling pins File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1153 Info (12128): Elaborating entity "acl_ic_master_endpoint" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_0:gmem0_.global_ic_preroutegmem0_router_0|acl_ic_master_endpoint:m[0].m_endp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1176 Warning (10036): Verilog HDL or VHDL warning at acl_ic_master_endpoint.v(48): object "id" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_master_endpoint.v Line: 48 Warning (10230): Verilog HDL assignment warning at acl_ic_master_endpoint.v(48): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_master_endpoint.v Line: 48 Info (12128): Elaborating entity "acl_ic_slave_endpoint" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_0:gmem0_.global_ic_preroutegmem0_router_0|acl_ic_slave_endpoint:s.s_endp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1251 Info (12128): Elaborating entity "acl_ic_slave_wrp" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_0:gmem0_.global_ic_preroutegmem0_router_0|acl_ic_slave_endpoint:s.s_endp|acl_ic_slave_wrp:wrp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_slave_endpoint.v Line: 131 Info (12128): Elaborating entity "acl_ic_slave_rrp" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_0:gmem0_.global_ic_preroutegmem0_router_0|acl_ic_slave_endpoint:s.s_endp|acl_ic_slave_rrp:rrp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_slave_endpoint.v Line: 158 Info (12128): Elaborating entity "acl_ic_mem_router_reorder" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 370 Warning (10230): Verilog HDL assignment warning at acl_ic_mem_router_reorder.v(167): truncated value with size 32 to match size of target (5) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_mem_router_reorder.v Line: 167 Warning (10230): Verilog HDL assignment warning at acl_ic_mem_router_reorder.v(227): truncated value with size 32 to match size of target (7) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_mem_router_reorder.v Line: 227 Warning (10230): Verilog HDL assignment warning at acl_ic_mem_router_reorder.v(309): truncated value with size 32 to match size of target (5) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_mem_router_reorder.v Line: 309 Warning (10230): Verilog HDL assignment warning at acl_ic_mem_router_reorder.v(320): truncated value with size 32 to match size of target (6) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_mem_router_reorder.v Line: 320 Info (12128): Elaborating entity "acl_address_to_bankaddress" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|acl_address_to_bankaddress:a2b" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_mem_router_reorder.v Line: 96 Warning (10230): Verilog HDL assignment warning at acl_address_to_bankaddress.v(43): truncated value with size 26 to match size of target (25) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_address_to_bankaddress.v Line: 43 Info (12128): Elaborating entity "acl_ll_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|acl_ll_fifo:rrp.bs_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_mem_router_reorder.v Line: 158 Info (12128): Elaborating entity "scfifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_mem_router_reorder.v Line: 204 Info (12130): Elaborated megafunction instantiation "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_mem_router_reorder.v Line: 204 Info (12133): Instantiated megafunction "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo" with the following parameter: File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_mem_router_reorder.v Line: 204 Info (12134): Parameter "lpm_width" = "256" Info (12134): Parameter "lpm_widthu" = "6" Info (12134): Parameter "lpm_numwords" = "62" Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "intended_device_family" = "stratixiv" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_o141.tdf Info (12023): Found entity 1: scfifo_o141 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/scfifo_o141.tdf Line: 24 Info (12128): Elaborating entity "scfifo_o141" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/scfifo.tdf Line: 299 Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_dm91.tdf Info (12023): Found entity 1: a_dpfifo_dm91 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_dm91.tdf Line: 32 Info (12128): Elaborating entity "a_dpfifo_dm91" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/scfifo_o141.tdf Line: 36 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_nkn1.tdf Info (12023): Found entity 1: altsyncram_nkn1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_nkn1" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_dm91.tdf Line: 45 Info (12128): Elaborating entity "cmpr_5l8" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|cmpr_5l8:almost_full_comparer" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_dm91.tdf Line: 54 Info (12128): Elaborating entity "cmpr_5l8" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|cmpr_5l8:three_comparison" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_dm91.tdf Line: 55 Info (12128): Elaborating entity "cntr_igb" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|cntr_igb:rd_ptr_msb" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_dm91.tdf Line: 56 Info (12128): Elaborating entity "cntr_vg7" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|cntr_vg7:usedw_counter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_dm91.tdf Line: 57 Info (12128): Elaborating entity "cntr_jgb" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|cntr_jgb:wr_ptr" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/a_dpfifo_dm91.tdf Line: 58 Info (12128): Elaborating entity "acl_ll_fifo" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|acl_ll_fifo:wrp.bs_fifo" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_mem_router_reorder.v Line: 300 Info (12128): Elaborating entity "hello_world_system_interconnect_1" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_1:gmem0_.global_icgmem0_port_0_0_rw" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 408 Warning (10230): Verilog HDL assignment warning at hello_world_system.v(1348): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1348 Info (12128): Elaborating entity "acl_ic_master_intf" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_1:gmem0_.global_icgmem0_port_0_0_rw|acl_ic_master_intf:m[0].m_intf" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1329 Warning (12158): Entity "acl_ic_master_intf" contains only dangling pins File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1329 Info (12128): Elaborating entity "acl_arb_intf" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_1:gmem0_.global_icgmem0_port_0_0_rw|acl_arb_intf:m[0].arb_intf" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1337 Warning (12158): Entity "acl_arb_intf" contains only dangling pins File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1337 Info (12128): Elaborating entity "acl_ic_master_endpoint" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_1:gmem0_.global_icgmem0_port_0_0_rw|acl_ic_master_endpoint:m[0].m_endp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1369 Warning (10036): Verilog HDL or VHDL warning at acl_ic_master_endpoint.v(48): object "id" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_master_endpoint.v Line: 48 Warning (10230): Verilog HDL assignment warning at acl_ic_master_endpoint.v(48): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_master_endpoint.v Line: 48 Info (12128): Elaborating entity "acl_ic_slave_endpoint" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_1:gmem0_.global_icgmem0_port_0_0_rw|acl_ic_slave_endpoint:s.s_endp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1444 Info (12128): Elaborating entity "acl_ic_slave_wrp" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_1:gmem0_.global_icgmem0_port_0_0_rw|acl_ic_slave_endpoint:s.s_endp|acl_ic_slave_wrp:wrp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_slave_endpoint.v Line: 131 Info (12128): Elaborating entity "acl_ic_slave_rrp" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_1:gmem0_.global_icgmem0_port_0_0_rw|acl_ic_slave_endpoint:s.s_endp|acl_ic_slave_rrp:rrp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_slave_endpoint.v Line: 158 Info (12128): Elaborating entity "acl_ic_to_avm" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_ic_to_avm:gmem0_.global_out_ic_to_avmgmem0_port_0_0_rw" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 466 Warning (10034): Output port "avm_enable" at acl_ic_to_avm.v(33) has no driver File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_to_avm.v Line: 33 Info (12128): Elaborating entity "acl_printf_counter" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_printf_counter:hello_world_printf_counter" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 579 Info (12128): Elaborating entity "acl_avm_to_ic" for hierarchy "system:the_system|hello_world_system:hello_world_system|acl_avm_to_ic:printf_system_hello_world.p[0].p_avm_to_ic" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 646 Info (12128): Elaborating entity "hello_world_system_interconnect_2" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_2:printf_system_hello_world.printf_ic_interconnect" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 682 Warning (10230): Verilog HDL assignment warning at hello_world_system.v(1544): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1544 Info (12128): Elaborating entity "acl_ic_master_intf" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_2:printf_system_hello_world.printf_ic_interconnect|acl_ic_master_intf:m[0].m_intf" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1525 Warning (12158): Entity "acl_ic_master_intf" contains only dangling pins File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1525 Info (12128): Elaborating entity "acl_arb_intf" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_2:printf_system_hello_world.printf_ic_interconnect|acl_arb_intf:m[0].arb_intf" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1533 Warning (12158): Entity "acl_arb_intf" contains only dangling pins File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1533 Info (12128): Elaborating entity "acl_ic_master_endpoint" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_2:printf_system_hello_world.printf_ic_interconnect|acl_ic_master_endpoint:m[0].m_endp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1565 Warning (10036): Verilog HDL or VHDL warning at acl_ic_master_endpoint.v(48): object "id" assigned a value but never read File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_master_endpoint.v Line: 48 Warning (10230): Verilog HDL assignment warning at acl_ic_master_endpoint.v(48): truncated value with size 32 to match size of target (1) File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_master_endpoint.v Line: 48 Info (12128): Elaborating entity "acl_ic_slave_endpoint" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_2:printf_system_hello_world.printf_ic_interconnect|acl_ic_slave_endpoint:s.s_endp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/hello_world_system.v Line: 1640 Info (12128): Elaborating entity "acl_ic_slave_wrp" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_2:printf_system_hello_world.printf_ic_interconnect|acl_ic_slave_endpoint:s.s_endp|acl_ic_slave_wrp:wrp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_slave_endpoint.v Line: 131 Info (12128): Elaborating entity "acl_ic_slave_rrp" for hierarchy "system:the_system|hello_world_system:hello_world_system|hello_world_system_interconnect_2:printf_system_hello_world.printf_ic_interconnect|acl_ic_slave_endpoint:s.s_endp|acl_ic_slave_rrp:rrp" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_slave_endpoint.v Line: 158 Info (12128): Elaborating entity "system_mm_interconnect_0" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/system.v Line: 388 Info (12128): Elaborating entity "system_mm_interconnect_1" for hierarchy "system:the_system|system_mm_interconnect_1:mm_interconnect_1" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/system.v Line: 414 Info (12128): Elaborating entity "system_mm_interconnect_3" for hierarchy "system:the_system|system_mm_interconnect_3:mm_interconnect_3" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/system.v Line: 439 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_translator:acl_iface_kernel_cra_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_mm_interconnect_3.v Line: 104 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:cra_root_cra_slave_translator" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_mm_interconnect_3.v Line: 168 Info (12128): Elaborating entity "async_counter_30" for hierarchy "async_counter_30:AC30" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 217 Warning (12011): Net is missing source, defaulting to GND Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[63]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[62]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[61]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[60]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[59]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[58]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[57]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[56]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[55]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[54]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[53]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[52]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[51]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[50]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[49]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[48]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[47]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[46]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[45]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[44]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[43]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[42]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[41]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[40]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[39]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[38]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[37]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[36]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[35]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[34]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[33]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[32]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[31]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[30]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[29]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[28]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[27]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[26]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[25]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[24]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[23]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[22]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[21]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[20]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[19]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[18]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[17]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[16]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[15]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[14]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[13]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[12]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[11]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[10]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[9]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[8]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[7]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[6]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[5]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[4]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[3]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[2]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[1]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[31]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[30]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[29]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[28]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[27]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[26]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[25]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[24]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[23]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[22]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[21]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[20]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[19]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[18]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[17]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[16]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[15]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[14]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[13]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[12]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[11]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[10]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[9]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[8]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[7]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[6]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[5]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[4]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[3]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[2]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[1]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12030): Port "extclk" on the entity instantiation of "cyclonev_pll" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic. File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2223 Warning (12011): Net is missing source, defaulting to GND Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[31]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[30]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[29]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[28]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[27]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[26]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[25]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[24]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[23]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[22]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[21]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[20]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[19]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[18]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[17]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[16]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[15]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[14]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[13]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[12]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[11]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[10]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[9]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[8]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[7]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[6]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[5]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[4]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[3]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[2]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[1]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 54 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[31]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[30]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[29]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[28]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[27]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[26]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[25]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[24]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[23]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[22]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[21]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[20]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[19]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[18]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[17]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[16]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[15]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[14]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[13]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[12]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[11]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[10]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[9]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[8]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[7]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[6]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[5]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[4]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[3]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[2]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[1]" is missing source, defaulting to GND File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 60 Critical Warning (138067): Current license file does not support incremental compilation. The Quartus Prime software removes all the user-specified design partitions in the design automatically. Info (12205): 1 design partition requires Analysis and Synthesis Info (12210): Partition "Top" requires synthesis because its netlist type is Source File Info (12209): No design partitions will skip synthesis in the current incremental compilation Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following LCELL buffer node(s): Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|cntsel_temp[4]" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|cntsel_temp[3]" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|cntsel_temp[2]" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|cntsel_temp[1]" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|cntsel_temp[0]" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|gnd" File: c:/intelfpga_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 426 Warning (14285): Synthesized away the following RAM node(s): Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[0]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 39 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[1]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 71 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[2]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 103 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[3]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 135 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[4]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 167 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[5]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 199 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[6]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 231 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[7]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 263 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[8]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 295 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[9]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 327 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[10]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 359 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[11]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 391 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[12]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 423 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[13]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 455 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[14]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 487 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[15]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 519 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[16]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 551 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[17]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 583 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[18]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 615 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[19]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 647 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[20]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 679 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[21]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 711 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[22]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 743 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[23]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 775 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[24]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 807 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[25]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 839 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[26]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 871 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[27]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 903 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[28]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 935 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[29]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 967 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[30]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 999 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[31]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1031 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[32]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1063 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[33]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1095 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[34]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1127 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[35]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1159 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[36]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1191 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[37]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1223 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[38]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1255 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[39]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1287 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[40]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1319 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[41]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1351 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[42]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1383 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[43]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1415 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[44]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1447 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[45]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1479 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[46]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1511 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[47]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1543 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[48]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1575 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[49]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1607 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[50]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1639 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[51]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1671 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[52]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1703 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[53]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1735 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[54]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1767 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[55]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1799 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[56]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1831 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[57]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1863 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[58]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1895 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[59]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1927 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[60]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1959 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[61]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1991 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[62]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2023 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[63]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2055 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[64]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2087 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[65]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2119 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[66]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2151 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[67]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2183 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[68]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2215 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[69]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2247 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[70]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2279 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[71]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2311 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[72]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2343 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[73]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2375 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[74]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2407 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[75]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2439 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[76]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2471 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[77]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2503 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[78]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2535 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[79]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2567 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[80]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2599 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[81]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2631 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[82]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2663 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[83]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2695 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[84]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2727 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[85]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2759 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[86]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2791 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[87]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2823 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[88]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2855 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[89]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2887 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[90]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2919 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[91]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2951 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[92]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2983 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[93]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3015 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[94]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3047 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[95]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3079 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[96]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3111 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[97]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3143 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[98]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3175 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[99]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3207 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[100]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3239 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[101]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3271 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[102]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3303 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[103]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3335 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[104]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3367 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[105]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3399 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[106]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3431 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[107]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3463 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[108]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3495 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[109]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3527 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[110]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3559 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[111]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3591 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[112]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3623 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[113]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3655 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[114]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3687 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[115]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3719 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[116]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3751 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[117]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3783 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[118]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3815 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[119]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3847 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[120]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3879 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[121]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3911 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[122]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3943 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[123]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3975 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[124]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4007 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[125]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4039 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[126]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4071 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[127]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4103 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[128]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4135 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[129]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4167 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[130]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4199 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[131]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4231 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[132]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4263 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[133]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4295 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[134]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4327 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[135]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4359 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[136]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4391 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[137]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4423 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[138]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4455 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[139]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4487 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[140]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4519 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[141]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4551 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[142]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4583 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[143]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4615 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[144]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4647 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[145]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4679 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[146]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4711 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[147]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4743 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[148]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4775 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[149]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4807 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[150]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4839 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[151]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4871 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[152]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4903 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[153]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4935 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[154]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4967 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[155]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4999 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[156]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5031 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[157]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5063 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[158]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5095 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[159]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5127 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[160]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5159 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[161]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5191 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[162]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5223 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[163]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5255 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[164]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5287 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[165]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5319 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[166]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5351 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[167]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5383 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[168]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5415 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[169]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5447 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[170]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5479 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[171]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5511 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[172]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5543 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[173]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5575 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[174]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5607 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[175]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5639 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[176]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5671 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[177]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5703 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[178]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5735 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[179]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5767 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[180]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5799 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[181]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5831 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[182]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5863 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[183]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5895 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[184]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5927 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[185]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5959 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[186]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5991 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[187]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6023 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[188]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6055 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[189]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6087 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[190]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6119 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[191]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6151 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[192]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6183 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[193]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6215 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[194]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6247 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[195]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6279 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[196]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6311 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[197]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6343 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[198]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6375 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[199]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6407 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[200]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6439 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[201]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6471 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[202]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6503 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[203]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6535 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[204]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6567 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[205]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6599 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[206]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6631 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[207]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6663 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[208]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6695 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[209]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6727 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[210]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6759 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[211]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6791 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[212]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6823 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[213]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6855 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[214]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6887 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[215]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6919 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[216]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6951 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[217]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6983 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[218]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7015 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[219]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7047 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[220]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7079 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[221]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7111 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[222]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7143 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[223]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7175 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[224]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7207 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[225]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7239 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[226]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7271 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[227]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7303 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[228]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7335 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[229]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7367 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[230]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7399 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[231]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7431 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[232]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7463 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[233]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7495 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[234]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7527 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[235]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7559 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[236]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7591 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[237]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7623 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[238]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7655 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[239]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7687 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[240]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7719 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[241]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7751 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[242]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7783 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[243]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7815 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[244]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7847 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[245]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7879 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[246]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7911 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[247]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7943 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[248]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7975 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[249]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8007 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[250]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8039 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[251]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8071 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[252]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8103 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[253]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8135 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[254]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8167 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[1].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[255]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8199 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[0]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 39 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[1]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 71 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[2]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 103 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[3]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 135 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[4]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 167 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[5]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 199 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[6]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 231 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[7]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 263 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[8]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 295 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[9]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 327 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[10]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 359 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[11]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 391 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[12]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 423 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[13]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 455 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[14]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 487 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[15]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 519 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[16]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 551 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[17]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 583 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[18]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 615 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[19]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 647 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[20]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 679 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[21]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 711 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[22]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 743 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[23]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 775 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[24]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 807 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[25]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 839 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[26]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 871 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[27]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 903 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[28]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 935 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[29]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 967 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[30]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 999 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[31]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1031 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[32]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1063 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[33]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1095 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[34]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1127 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[35]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1159 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[36]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1191 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[37]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1223 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[38]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1255 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[39]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1287 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[40]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1319 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[41]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1351 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[42]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1383 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[43]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1415 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[44]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1447 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[45]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1479 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[46]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1511 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[47]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1543 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[48]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1575 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[49]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1607 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[50]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1639 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[51]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1671 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[52]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1703 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[53]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1735 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[54]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1767 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[55]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1799 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[56]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1831 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[57]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1863 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[58]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1895 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[59]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1927 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[60]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1959 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[61]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 1991 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[62]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2023 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[63]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2055 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[64]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2087 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[65]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2119 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[66]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2151 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[67]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2183 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[68]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2215 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[69]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2247 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[70]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2279 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[71]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2311 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[72]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2343 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[73]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2375 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[74]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2407 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[75]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2439 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[76]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2471 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[77]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2503 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[78]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2535 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[79]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2567 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[80]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2599 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[81]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2631 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[82]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2663 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[83]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2695 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[84]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2727 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[85]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2759 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[86]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2791 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[87]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2823 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[88]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2855 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[89]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2887 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[90]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2919 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[91]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2951 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[92]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 2983 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[93]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3015 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[94]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3047 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[95]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3079 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[96]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3111 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[97]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3143 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[98]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3175 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[99]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3207 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[100]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3239 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[101]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3271 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[102]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3303 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[103]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3335 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[104]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3367 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[105]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3399 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[106]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3431 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[107]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3463 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[108]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3495 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[109]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3527 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[110]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3559 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[111]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3591 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[112]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3623 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[113]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3655 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[114]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3687 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[115]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3719 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[116]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3751 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[117]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3783 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[118]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3815 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[119]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3847 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[120]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3879 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[121]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3911 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[122]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3943 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[123]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 3975 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[124]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4007 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[125]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4039 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[126]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4071 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[127]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4103 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[128]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4135 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[129]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4167 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[130]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4199 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[131]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4231 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[132]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4263 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[133]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4295 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[134]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4327 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[135]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4359 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[136]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4391 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[137]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4423 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[138]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4455 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[139]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4487 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[140]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4519 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[141]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4551 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[142]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4583 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[143]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4615 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[144]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4647 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[145]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4679 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[146]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4711 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[147]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4743 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[148]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4775 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[149]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4807 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[150]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4839 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[151]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4871 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[152]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4903 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[153]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4935 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[154]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4967 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[155]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 4999 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[156]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5031 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[157]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5063 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[158]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5095 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[159]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5127 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[160]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5159 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[161]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5191 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[162]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5223 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[163]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5255 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[164]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5287 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[165]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5319 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[166]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5351 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[167]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5383 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[168]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5415 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[169]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5447 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[170]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5479 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[171]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5511 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[172]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5543 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[173]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5575 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[174]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5607 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[175]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5639 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[176]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5671 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[177]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5703 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[178]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5735 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[179]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5767 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[180]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5799 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[181]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5831 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[182]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5863 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[183]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5895 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[184]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5927 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[185]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5959 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[186]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 5991 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[187]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6023 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[188]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6055 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[189]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6087 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[190]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6119 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[191]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6151 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[192]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6183 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[193]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6215 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[194]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6247 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[195]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6279 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[196]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6311 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[197]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6343 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[198]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6375 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[199]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6407 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[200]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6439 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[201]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6471 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[202]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6503 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[203]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6535 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[204]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6567 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[205]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6599 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[206]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6631 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[207]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6663 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[208]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6695 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[209]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6727 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[210]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6759 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[211]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6791 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[212]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6823 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[213]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6855 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[214]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6887 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[215]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6919 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[216]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6951 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[217]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 6983 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[218]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7015 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[219]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7047 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[220]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7079 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[221]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7111 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[222]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7143 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[223]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7175 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[224]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7207 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[225]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7239 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[226]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7271 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[227]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7303 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[228]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7335 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[229]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7367 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[230]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7399 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[231]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7431 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[232]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7463 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[233]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7495 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[234]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7527 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[235]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7559 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[236]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7591 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[237]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7623 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[238]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7655 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[239]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7687 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[240]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7719 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[241]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7751 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[242]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7783 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[243]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7815 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[244]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7847 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[245]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7879 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[246]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7911 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[247]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7943 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[248]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 7975 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[249]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8007 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[250]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8039 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[251]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8071 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[252]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8103 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[253]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8135 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[254]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8167 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|scfifo:rrp.bank[0].data_fifo|scfifo_o141:auto_generated|a_dpfifo_dm91:dpfifo|altsyncram_nkn1:FIFOram|q_b[255]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_nkn1.tdf Line: 8199 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[32]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1063 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[33]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1095 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[34]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1127 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[35]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1159 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[36]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1191 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[37]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1223 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[38]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1255 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[39]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1287 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[40]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1319 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[41]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1351 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[42]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1383 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[43]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1415 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[44]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1447 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[45]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1479 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[46]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1511 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[47]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1543 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[48]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1575 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[49]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1607 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[50]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1639 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[51]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1671 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[52]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1703 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[53]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1735 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[54]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1767 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[55]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1799 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[56]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1831 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[57]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1863 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[58]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1895 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[59]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1927 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[60]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1959 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[61]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 1991 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[62]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2023 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[63]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2055 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[64]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2087 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[65]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2119 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[66]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2151 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[67]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2183 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[68]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2215 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[69]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2247 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[70]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2279 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[71]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2311 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[72]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2343 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[73]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2375 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[74]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2407 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[75]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2439 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[76]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2471 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[77]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2503 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[78]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2535 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[79]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2567 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[80]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2599 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[81]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2631 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[82]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2663 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[83]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2695 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[84]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2727 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[85]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2759 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[86]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2791 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[87]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2823 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[88]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2855 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[89]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2887 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[90]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2919 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[91]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2951 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[92]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 2983 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[93]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3015 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[94]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3047 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[95]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3079 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[96]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3111 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[97]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3143 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[98]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3175 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[99]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3207 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[100]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3239 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[101]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3271 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[102]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3303 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[103]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3335 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[104]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3367 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[105]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3399 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[106]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3431 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[107]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3463 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[108]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3495 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[109]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3527 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[110]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3559 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[111]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3591 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[112]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3623 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[113]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3655 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[114]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3687 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[115]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3719 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[116]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3751 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[117]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3783 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[118]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3815 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[119]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3847 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[120]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3879 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[121]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3911 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[122]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3943 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[123]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 3975 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[124]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4007 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[125]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4039 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[126]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4071 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[127]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4103 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[128]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4135 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[129]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4167 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[130]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4199 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[131]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4231 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[132]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4263 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[133]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4295 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[134]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4327 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[135]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4359 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[136]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4391 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[137]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4423 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[138]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4455 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[139]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4487 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[140]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4519 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[141]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4551 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[142]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4583 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[143]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4615 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[144]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4647 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[145]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4679 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[146]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4711 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[147]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4743 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[148]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4775 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[149]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4807 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[150]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4839 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[151]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4871 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[152]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4903 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[153]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4935 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[154]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4967 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[155]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 4999 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[156]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5031 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[157]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5063 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[158]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5095 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[159]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5127 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[160]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5159 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[161]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5191 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[162]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5223 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[163]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5255 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[164]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5287 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[165]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5319 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[166]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5351 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[167]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5383 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[168]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5415 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[169]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5447 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[170]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5479 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[171]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5511 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[172]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5543 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[173]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5575 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[174]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5607 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[175]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5639 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[176]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5671 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[177]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5703 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[178]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5735 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[179]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5767 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[180]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5799 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[181]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5831 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[182]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5863 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[183]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5895 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[184]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5927 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[185]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5959 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[186]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 5991 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[187]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 6023 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[188]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 6055 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[189]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 6087 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[190]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 6119 Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|hello_world_partition_wrapper:hello_world_inst|acl_id_iterator:hello_world_id_iter_inst_0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[191]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1hn1.tdf Line: 6151 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[0]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 39 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[1]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 69 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[2]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 99 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[3]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 129 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[4]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 159 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[5]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 189 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[6]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 219 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[7]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 249 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[8]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 279 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[9]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 309 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[10]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 339 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[11]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 369 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[12]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 399 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[13]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 429 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[14]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 459 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[15]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 489 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[16]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 519 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[17]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 549 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[18]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 579 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[19]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 609 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[20]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 639 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[21]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 669 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[22]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 699 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[23]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 729 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[24]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 759 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[25]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 789 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[26]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 819 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[27]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 849 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[28]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 879 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|q_b[29]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_1b81.tdf Line: 909 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[0]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 38 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[1]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 61 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[2]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 84 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[3]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 107 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[4]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 130 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[5]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 153 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[6]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 176 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[7]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 199 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[8]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 222 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[9]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 245 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[10]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 268 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[11]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 291 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[12]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 314 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[13]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 337 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[14]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 360 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[15]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 383 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[16]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 406 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[17]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 429 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[18]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 452 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[19]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 475 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[20]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 498 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[21]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 521 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[22]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 544 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[23]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 567 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[24]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 590 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[25]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 613 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[26]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 636 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[27]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 659 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[28]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 682 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[29]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 705 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[30]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 728 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_lil1:auto_generated|q_a[31]" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_lil1.tdf Line: 751 Warning (14285): Synthesized away the following PLL node(s): Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_pll0:pll0|afi_phy_clk" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_pll0.sv Line: 200 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_pll0:pll0|pll_mem_clk" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_pll0.sv Line: 233 Warning (14320): Synthesized away node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_pll0:pll0|pll_addr_cmd_clk" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/system_acl_iface_fpga_sdram_pll0.sv Line: 329 Warning (12241): 106 hierarchies have connectivity warnings - see the Connectivity Checks report folder Info (281037): Using 2 processors to synthesize 2 partitions in parallel Info: ******************************************************************* Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition Info: Processing started: Sun May 06 08:10:59 2018 Info: Command: quartus_map --parallel=1 --helper=2 --helper_type=user_partition --partition=system_acl_iface_hps_hps_io_border:border top -c top Info: Using INI file C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/quartus.ini Info: Running Quartus Prime Analysis & Synthesis Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition Info: Processing started: Sun May 06 08:10:59 2018 Info: Command: quartus_map --parallel=1 --helper=0 --helper_type=user_partition --partition=Top top -c top Info: Using INI file C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/quartus.ini Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following LCELL buffer node(s): Warning (14320): Synthesized away node "system:the_system|hello_world_system:hello_world_system|acl_ic_mem_router_reorder:gmem0_.router[0].router|rrp.bs_doneburst" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/system/synthesis/submodules/acl_ic_mem_router_reorder.v Line: 140 Critical Warning (140003): Current license file does not support LogicLock regions. The Quartus Prime software removes all the LogicLock regions in your design automatically. Info (19000): Inferred 7 megafunctions from design logic Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_avalon_sc_fifo:mm_bridge_0_s0_agent_rdata_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 32 Info (286033): Parameter WIDTHAD_A set to 3 Info (286033): Parameter NUMWORDS_A set to 8 Info (286033): Parameter WIDTH_B set to 32 Info (286033): Parameter WIDTHAD_B set to 3 Info (286033): Parameter NUMWORDS_B set to 8 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_avalon_sc_fifo:acl_memory_bank_divider_s_agent_rdata_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 256 Info (286033): Parameter WIDTHAD_A set to 3 Info (286033): Parameter NUMWORDS_A set to 8 Info (286033): Parameter WIDTH_B set to 256 Info (286033): Parameter WIDTHAD_B set to 3 Info (286033): Parameter NUMWORDS_B set to 8 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:address_span_extender_axi_windowed_slave_agent_rdata_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 32 Info (286033): Parameter WIDTHAD_A set to 5 Info (286033): Parameter NUMWORDS_A set to 32 Info (286033): Parameter WIDTH_B set to 32 Info (286033): Parameter WIDTHAD_B set to 5 Info (286033): Parameter NUMWORDS_B set to 32 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:rsp_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 256 Info (286033): Parameter WIDTHAD_A set to 5 Info (286033): Parameter NUMWORDS_A set to 32 Info (286033): Parameter WIDTH_B set to 256 Info (286033): Parameter WIDTHAD_B set to 5 Info (286033): Parameter NUMWORDS_B set to 32 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK1 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:cmd_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 320 Info (286033): Parameter WIDTHAD_A set to 2 Info (286033): Parameter NUMWORDS_A set to 4 Info (286033): Parameter WIDTH_B set to 320 Info (286033): Parameter WIDTHAD_B set to 2 Info (286033): Parameter NUMWORDS_B set to 4 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK1 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem1|altera_avalon_dc_fifo:cmd_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 319 Info (286033): Parameter WIDTHAD_A set to 6 Info (286033): Parameter NUMWORDS_A set to 64 Info (286033): Parameter WIDTH_B set to 319 Info (286033): Parameter WIDTHAD_B set to 6 Info (286033): Parameter NUMWORDS_B set to 64 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK1 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem0|altera_avalon_dc_fifo:cmd_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 319 Info (286033): Parameter WIDTHAD_A set to 6 Info (286033): Parameter NUMWORDS_A set to 64 Info (286033): Parameter WIDTH_B set to 319 Info (286033): Parameter WIDTHAD_B set to 6 Info (286033): Parameter NUMWORDS_B set to 64 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK1 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_avalon_sc_fifo:mm_bridge_0_s0_agent_rdata_fifo|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_avalon_sc_fifo:mm_bridge_0_s0_agent_rdata_fifo|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "32" Info (12134): Parameter "WIDTHAD_A" = "3" Info (12134): Parameter "NUMWORDS_A" = "8" Info (12134): Parameter "WIDTH_B" = "32" Info (12134): Parameter "WIDTHAD_B" = "3" Info (12134): Parameter "NUMWORDS_B" = "8" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_00n1.tdf Info (12023): Found entity 1: altsyncram_00n1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_00n1.tdf Line: 27 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_avalon_sc_fifo:acl_memory_bank_divider_s_agent_rdata_fifo|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_avalon_sc_fifo:acl_memory_bank_divider_s_agent_rdata_fifo|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "256" Info (12134): Parameter "WIDTHAD_A" = "3" Info (12134): Parameter "NUMWORDS_A" = "8" Info (12134): Parameter "WIDTH_B" = "256" Info (12134): Parameter "WIDTHAD_B" = "3" Info (12134): Parameter "NUMWORDS_B" = "8" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_g3n1.tdf Info (12023): Found entity 1: altsyncram_g3n1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_g3n1.tdf Line: 27 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:address_span_extender_axi_windowed_slave_agent_rdata_fifo|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:address_span_extender_axi_windowed_slave_agent_rdata_fifo|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "32" Info (12134): Parameter "WIDTHAD_A" = "5" Info (12134): Parameter "NUMWORDS_A" = "32" Info (12134): Parameter "WIDTH_B" = "32" Info (12134): Parameter "WIDTHAD_B" = "5" Info (12134): Parameter "NUMWORDS_B" = "32" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_u2n1.tdf Info (12023): Found entity 1: altsyncram_u2n1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_u2n1.tdf Line: 27 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:rsp_fifo|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "256" Info (12134): Parameter "WIDTHAD_A" = "5" Info (12134): Parameter "NUMWORDS_A" = "32" Info (12134): Parameter "WIDTH_B" = "256" Info (12134): Parameter "WIDTHAD_B" = "5" Info (12134): Parameter "NUMWORDS_B" = "32" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_k9j1.tdf Info (12023): Found entity 1: altsyncram_k9j1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_k9j1.tdf Line: 27 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "320" Info (12134): Parameter "WIDTHAD_A" = "2" Info (12134): Parameter "NUMWORDS_A" = "4" Info (12134): Parameter "WIDTH_B" = "320" Info (12134): Parameter "WIDTHAD_B" = "2" Info (12134): Parameter "NUMWORDS_B" = "4" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_s5j1.tdf Info (12023): Found entity 1: altsyncram_s5j1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_s5j1.tdf Line: 27 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem1|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem1|altera_avalon_dc_fifo:cmd_fifo|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "319" Info (12134): Parameter "WIDTHAD_A" = "6" Info (12134): Parameter "NUMWORDS_A" = "64" Info (12134): Parameter "WIDTH_B" = "319" Info (12134): Parameter "WIDTHAD_B" = "6" Info (12134): Parameter "NUMWORDS_B" = "64" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_0aj1.tdf Info (12023): Found entity 1: altsyncram_0aj1 File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/db/altsyncram_0aj1.tdf Line: 27 Info (281020): Starting Logic Optimization and Technology Mapping for Top Partition Warning (13009): TRI or OPNDRN buffers permanently enabled Warning (13010): Node "memory_mem_dq[0]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[1]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[2]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[3]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[4]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[5]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[6]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[7]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[8]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[9]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[10]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[11]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[12]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[13]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[14]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[15]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[16]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[17]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[18]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[19]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[20]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[21]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[22]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[23]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[24]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[25]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[26]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[27]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[28]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[29]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[30]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[31]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[32]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[33]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[34]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[35]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[36]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[37]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[38]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dq[39]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 90 Warning (13010): Node "memory_mem_dqs[0]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 91 Warning (13010): Node "memory_mem_dqs[1]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 91 Warning (13010): Node "memory_mem_dqs[2]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 91 Warning (13010): Node "memory_mem_dqs[3]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 91 Warning (13010): Node "memory_mem_dqs[4]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 91 Warning (13010): Node "memory_mem_dqs_n[0]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 92 Warning (13010): Node "memory_mem_dqs_n[1]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 92 Warning (13010): Node "memory_mem_dqs_n[2]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 92 Warning (13010): Node "memory_mem_dqs_n[3]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 92 Warning (13010): Node "memory_mem_dqs_n[4]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 92 Warning (13010): Node "emac_mdio~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 97 Warning (13010): Node "sd_cmd~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 106 Warning (13010): Node "sd_d[0]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 108 Warning (13010): Node "sd_d[1]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 108 Warning (13010): Node "sd_d[2]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 108 Warning (13010): Node "sd_d[3]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 108 Warning (13010): Node "led[0]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 111 Warning (13010): Node "led[1]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 111 Warning (13010): Node "led[2]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 111 Warning (13010): Node "led[3]~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 111 Warning (13010): Node "i2c_sda~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 113 Warning (13010): Node "i2c_scl~synth" File: C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.v Line: 112 Info (286031): Timing-Driven Synthesis is running on partition "Top" Internal Error: Sub-system: QSYN, File: /quartus/synth/qsyn/qsyn_cmd.cpp, Line: 1803 p Stack Trace: 0x17d9d: QSYN_FRAMEWORK::initialize_parallel_helper + 0x88d (quartus_map) 0x13843: QSYN_FRAMEWORK::execute + 0x233 (quartus_map) 0x11067: qexe_do_grunt + 0xa7 (comp_qexe) 0x16063: qexe_run + 0x353 (comp_qexe) 0x16e51: qexe_standard_main + 0xc1 (comp_qexe) 0x1b08b: qsyn_main + 0x51b (quartus_map) 0x12e98: msg_main_thread + 0x18 (CCL_MSG) 0x1467e: msg_thread_wrapper + 0x6e (CCL_MSG) 0x16660: mem_thread_wrapper + 0x70 (ccl_mem) 0x12761: msg_exe_main + 0xa1 (CCL_MSG) 0x29872: __tmainCRTStartup + 0x10e (quartus_map) 0x16ac: BaseThreadInitThunk + 0xc (KERNEL32) 0x74628: RtlUserThreadStart + 0x1c (ntdll) End-trace Info (17049): 3735 registers lost all their fanouts during netlist optimizations. Info (21057): Implemented 16400 device resources after synthesis - the final resource count might be different Info (21058): Implemented 11 input pins Info (21059): Implemented 76 output pins Info (21060): Implemented 102 bidirectional pins Info (21061): Implemented 13411 logic cells Info (21064): Implemented 2115 RAM segments Info (21065): Implemented 7 PLLs Info (21066): Implemented 1 delay-locked loops Info (21071): Implemented 1 partitions Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 67 warnings Info: Peak virtual memory: 992 megabytes Info: Processing ended: Sun May 06 08:13:34 2018 Info: Elapsed time: 00:02:35 Info: Total CPU time (on all processors): 00:02:22 Error (281039): Finished parallel synthesis of 1 partition(s). 1 partitions did not finish parallel synthesis because there were errors Error (281040): Partition "system_acl_iface_hps_hps_io_border:border" did not complete synthesis due to errors Info (144001): Generated suppressed messages file C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top.map.smsg Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1083 warnings Error: Peak virtual memory: 1668 megabytes Error: Processing ended: Sun May 06 08:20:08 2018 Error: Elapsed time: 00:12:28 Error: Total CPU time (on all processors): 00:12:19 Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 1083 warnings Error: Flow compile (for project C:/intelFPGA_lite/17.1/hld/bin/bin/hello_world/top) was not successful Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last. Error (23031): Evaluation of Tcl script c:/intelfpga_lite/17.1/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 11 errors, 1083 warnings Error: Peak virtual memory: 439 megabytes Error: Processing ended: Sun May 06 08:20:15 2018 Error: Elapsed time: 00:13:12 Error: Total CPU time (on all processors): 00:01:28