=========================================================================================================
                                   *** Optimization Report ***                                        
 Warning: Compile with "-g" to get line number, variable name, and additional loop information         

Kernels that do not use any work-item built-in functions, such as get_global_id(), are compiled for single
work-item execution (a task). Otherwise, a kernel is compiled as an ND-Range.

For tasks, the compiler will attempt to pipeline every loop in the kernel to allow multiple iterations of
the loop to execute concurrently. If some loops are not pipelined, or not pipelined well, you may not get
good performance.

For ND-Range kernels, the loops are not pipelined. Instead, they are built to accept multiple work-items
simultaneously. Kernel throughput is usually reduced by the largest total number of iterations of nested
loops. A large number of threads is usually required to efficiently utilize ND-Range kernels.

=========================================================================================================
Kernel: Correlator                                                                                       
=========================================================================================================
The kernel is compiled for single work-item execution.

Loop Report:

 + Loop "Block1"
 | Pipelined with successive iterations launched every 2 cycles due to: 
 |      
 |     Pipeline structure: every terminating loop with subloops has iterations launched at least 2 cycles apart.
 |     Having successive iterations launched every two cycles should still lead to good performance
 |     if the inner loop is pipelined well and has sufficiently high number of iterations.
 |  
 | Iterations executed serially across the regions listed below.
 | Only a single loop iteration will execute inside the listed regions.
 | This will cause performance degradation unless the regions are pipelined well
 | (can process an iteration every cycle).
 |      
 |     Loop "Block2"
 |     due to:
 |     Memory dependency on Store Operation from:
 |       Store Operation
 |       Store Operation
 | 
 | 
 |-+ Loop "Block2"
   | Pipelined with successive iterations launched every 2 cycles due to: 
   |      
   |     Pipeline structure: every terminating loop with subloops has iterations launched at least 2 cycles apart.
   |     Having successive iterations launched every two cycles should still lead to good performance
   |     if the inner loop is pipelined well and has sufficiently high number of iterations.
   |  
   | Additional memory dependencies:
   |      
   |     Memory dependency on Store Operation from:
   |       Store Operation
   |       Store Operation
   |       Store Operation
   |      
   |     Memory dependency on Store Operation from:
   |       Store Operation
   |       Store Operation
   |       Store Operation
   |      
   |     Memory dependency on Store Operation from:
   |       Store Operation
   |       Store Operation
   |       Store Operation
   |      
   |     Memory dependency on Store Operation from:
   |       Store Operation
   |       Store Operation
   |       Store Operation
   | 
   | 
   |-+ Loop "Block3"
       Pipelined well. Successive iterations are launched every cycle.
       
       
=========================================================================================================

+--------------------------------------------------------------------+
; Estimated Resource Usage Summary                                   ;
+----------------------------------------+---------------------------+
; Resource                               + Usage                     ;
+----------------------------------------+---------------------------+
; Logic utilization                      ;   75%                     ;
; ALUTs                                  ;   39%                     ;
; Dedicated logic registers              ;   39%                     ;
; Memory blocks                          ;   19%                     ;
; DSP blocks                             ;   29%                     ;
+----------------------------------------+---------------------------;
System name: FixedCor

2017.06.27.15:05:25 Info: Doing: <b>qsys-script --script=kernel_system.tcl --Xmx512M --XX:+UseSerialGC</b>
2017.06.27.15:05:30 Info: set_validation_property AUTOMATIC_VALIDATION false
2017.06.27.15:05:30 Info: add_instance clk_1x altera_clock_bridge 
2017.06.27.15:05:31 Info: set_instance_parameter_value clk_1x EXPLICIT_CLOCK_RATE 0
2017.06.27.15:05:31 Info: set_instance_parameter_value clk_1x NUM_CLOCK_OUTPUTS 1
2017.06.27.15:05:31 Info: add_interface clock_reset clock sink
2017.06.27.15:05:31 Info: set_interface_property clock_reset EXPORT_OF clk_1x.in_clk
2017.06.27.15:05:31 Info: add_instance clk_2x altera_clock_bridge 
2017.06.27.15:05:31 Info: set_instance_parameter_value clk_2x EXPLICIT_CLOCK_RATE 0
2017.06.27.15:05:31 Info: set_instance_parameter_value clk_2x NUM_CLOCK_OUTPUTS 1
2017.06.27.15:05:31 Info: add_interface clock_reset2x clock sink
2017.06.27.15:05:31 Info: set_interface_property clock_reset2x EXPORT_OF clk_2x.in_clk
2017.06.27.15:05:31 Info: add_instance clk_snoop altera_clock_bridge 
2017.06.27.15:05:31 Info: set_instance_parameter_value clk_snoop EXPLICIT_CLOCK_RATE 0
2017.06.27.15:05:31 Info: set_instance_parameter_value clk_snoop NUM_CLOCK_OUTPUTS 1
2017.06.27.15:05:31 Info: add_interface cc_snoop_clk clock sink
2017.06.27.15:05:31 Info: set_interface_property cc_snoop_clk EXPORT_OF clk_snoop.in_clk
2017.06.27.15:05:31 Info: add_instance reset altera_reset_bridge 
2017.06.27.15:05:31 Info: set_instance_parameter_value reset ACTIVE_LOW_RESET 1
2017.06.27.15:05:31 Info: set_instance_parameter_value reset SYNCHRONOUS_EDGES deassert
2017.06.27.15:05:31 Info: set_instance_parameter_value reset NUM_RESET_OUTPUTS 1
2017.06.27.15:05:31 Info: add_interface clock_reset_reset reset sink
2017.06.27.15:05:31 Info: set_interface_property clock_reset_reset EXPORT_OF reset.in_reset
2017.06.27.15:05:31 Info: add_connection clk_1x.out_clk reset.clk
2017.06.27.15:05:31 Info: add_instance FixedCor_system FixedCor_system 
2017.06.27.15:05:32 Info: add_connection clk_1x.out_clk FixedCor_system.clock_reset
2017.06.27.15:05:32 Info: add_connection clk_2x.out_clk FixedCor_system.clock_reset2x
2017.06.27.15:05:32 Info: add_connection reset.out_reset FixedCor_system.clock_reset_reset
2017.06.27.15:05:32 Info: add_interface kernel_mem0 avalon slave
2017.06.27.15:05:32 Info: set_interface_property kernel_mem0 EXPORT_OF FixedCor_system.avm_memgmem0_DDR_port_0_0_rw
2017.06.27.15:05:32 Info: add_interface kernel_mem1 avalon slave
2017.06.27.15:05:32 Info: set_interface_property kernel_mem1 EXPORT_OF FixedCor_system.avm_memgmem0_DDR_port_1_0_rw
2017.06.27.15:05:32 Info: add_instance kernel_irq altera_irq_bridge 
2017.06.27.15:05:32 Info: set_instance_parameter_value kernel_irq IRQ_WIDTH 1
2017.06.27.15:05:32 Info: set_instance_parameter_value kernel_irq IRQ_N 0
2017.06.27.15:05:32 Info: add_interface kernel_irq irq sender
2017.06.27.15:05:32 Info: set_interface_property kernel_irq EXPORT_OF kernel_irq.sender0_irq
2017.06.27.15:05:32 Info: add_connection clk_1x.out_clk kernel_irq.clk
2017.06.27.15:05:32 Info: add_connection reset.out_reset kernel_irq.clk_reset
2017.06.27.15:05:32 Info: add_connection kernel_irq.receiver_irq FixedCor_system.kernel_irq
2017.06.27.15:05:32 Info: add_instance kernel_cra altera_avalon_mm_bridge 
2017.06.27.15:05:32 Info: set_instance_parameter_value kernel_cra DATA_WIDTH 64
2017.06.27.15:05:32 Info: set_instance_parameter_value kernel_cra SYMBOL_WIDTH 8
2017.06.27.15:05:32 Info: set_instance_parameter_value kernel_cra ADDRESS_WIDTH 30
2017.06.27.15:05:32 Info: set_instance_parameter_value kernel_cra USE_AUTO_ADDRESS_WIDTH 0
2017.06.27.15:05:32 Info: set_instance_parameter_value kernel_cra ADDRESS_UNITS SYMBOLS
2017.06.27.15:05:32 Info: set_instance_parameter_value kernel_cra MAX_BURST_SIZE 1
2017.06.27.15:05:32 Info: set_instance_parameter_value kernel_cra MAX_PENDING_RESPONSES 1
2017.06.27.15:05:32 Info: set_instance_parameter_value kernel_cra LINEWRAPBURSTS 0
2017.06.27.15:05:32 Info: set_instance_parameter_value kernel_cra PIPELINE_COMMAND 0
2017.06.27.15:05:32 Info: set_instance_parameter_value kernel_cra PIPELINE_RESPONSE 0
2017.06.27.15:05:32 Info: add_connection clk_1x.out_clk kernel_cra.clk
2017.06.27.15:05:32 Info: add_connection reset.out_reset kernel_cra.reset
2017.06.27.15:05:32 Info: add_interface avs_kernel_cra avalon slave
2017.06.27.15:05:32 Info: set_interface_property kernel_cra EXPORT_OF kernel_cra.s0
2017.06.27.15:05:32 Info: add_instance cra_root cra_ring_root 
2017.06.27.15:05:32 Info: set_instance_parameter_value cra_root DATA_W 64
2017.06.27.15:05:32 Info: set_instance_parameter_value cra_root ADDR_W 4
2017.06.27.15:05:32 Info: set_instance_parameter_value cra_root ID_W 0
2017.06.27.15:05:32 Info: add_connection clk_1x.out_clk cra_root.clock
2017.06.27.15:05:32 Info: add_connection reset.out_reset cra_root.reset
2017.06.27.15:05:32 Info: add_connection kernel_cra.m0 cra_root.cra_slave
2017.06.27.15:05:32 Info: set_connection_parameter_value kernel_cra.m0/cra_root.cra_slave baseAddress 0x0
2017.06.27.15:05:32 Info: add_instance avs_Correlator_cra_cra_ring cra_ring_node 
2017.06.27.15:05:32 Info: set_instance_parameter_value avs_Correlator_cra_cra_ring DATA_W 64
2017.06.27.15:05:32 Info: set_instance_parameter_value avs_Correlator_cra_cra_ring RING_ADDR_W 4
2017.06.27.15:05:32 Info: set_instance_parameter_value avs_Correlator_cra_cra_ring CRA_ADDR_W 4
2017.06.27.15:05:32 Info: set_instance_parameter_value avs_Correlator_cra_cra_ring ID_W 0
2017.06.27.15:05:32 Info: set_instance_parameter_value avs_Correlator_cra_cra_ring ID 0
2017.06.27.15:05:32 Info: add_connection clk_1x.out_clk avs_Correlator_cra_cra_ring.clock
2017.06.27.15:05:32 Info: add_connection reset.out_reset avs_Correlator_cra_cra_ring.reset
2017.06.27.15:05:32 Info: add_connection cra_root.ring_out avs_Correlator_cra_cra_ring.ring_in
2017.06.27.15:05:32 Info: add_connection avs_Correlator_cra_cra_ring.cra_master FixedCor_system.avs_Correlator_cra
2017.06.27.15:05:32 Info: set_connection_parameter_value avs_Correlator_cra_cra_ring.cra_master/FixedCor_system.avs_Correlator_cra baseAddress 0x0
2017.06.27.15:05:32 Info: add_connection avs_Correlator_cra_cra_ring.ring_out cra_root.ring_in
2017.06.27.15:05:32 Info: add_instance acl_internal_snoop altera_avalon_st_adapter 
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop inBitsPerSymbol 33
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop inUsePackets 0
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop inDataWidth 33
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop inMaxChannel 0
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop inChannelWidth 0
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop inErrorWidth 0
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop inErrorDescriptor 
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop inUseEmptyPort 0
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop inUseValid 1
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop inUseReady 1
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop inReadyLatency 0
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop outDataWidth 33
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop outMaxChannel 0
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop outChannelWidth 0
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop outErrorWidth 0
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop outErrorDescriptor 
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop outUseEmptyPort 0
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop outUseValid 1
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop outUseReady 1
2017.06.27.15:05:33 Info: set_instance_parameter_value acl_internal_snoop outReadyLatency 0
2017.06.27.15:05:33 Info: add_connection clk_snoop.out_clk acl_internal_snoop.in_clk_0
2017.06.27.15:05:33 Info: add_connection reset.out_reset acl_internal_snoop.in_rst_0
2017.06.27.15:05:33 Info: add_interface cc_snoop avalon_streaming sink
2017.06.27.15:05:33 Info: set_interface_property cc_snoop EXPORT_OF acl_internal_snoop.in_0
2017.06.27.15:05:33 Info: save_system kernel_system.qsys
2017.06.27.15:05:33 Info: Doing: <b>qsys-script --script=system.tcl --Xmx512M --XX:+UseSerialGC --system-file=system.qsys</b>
2017.06.27.15:05:58 Info: set_validation_property AUTOMATIC_VALIDATION false
2017.06.27.15:05:58 Info: add_instance kernel_system kernel_system 
2017.06.27.15:05:58 Info: add_connection board.kernel_clk kernel_system.clock_reset
2017.06.27.15:05:58 Info: add_connection board.kernel_clk2x kernel_system.clock_reset2x
2017.06.27.15:05:58 Info: add_connection board.kernel_reset kernel_system.clock_reset_reset
2017.06.27.15:05:58 Info: add_connection kernel_system.kernel_mem0 board.kernel_mem0
2017.06.27.15:05:58 Info: add_connection kernel_system.kernel_mem1 board.kernel_mem1
2017.06.27.15:05:58 Info: add_connection board.kernel_irq kernel_system.kernel_irq
2017.06.27.15:05:58 Info: add_connection board.kernel_cra kernel_system.kernel_cra
2017.06.27.15:05:58 Info: add_connection board.acl_internal_snoop kernel_system.cc_snoop
2017.06.27.15:05:58 Info: add_connection board.kernel_clk kernel_system.cc_snoop_clk
2017.06.27.15:05:58 Info: save_system 
2017.06.27.15:06:24 Info: Saving generation log to /var/scratch/avdploeg/FixedCor/system/system_generation.rpt
2017.06.27.15:06:24 Info: Starting: <b>Create HDL design files for synthesis</b>
2017.06.27.15:06:24 Info: qsys-generate /var/scratch/avdploeg/FixedCor/system.qsys --synthesis=VERILOG --output-directory=/var/scratch/avdploeg/FixedCor/system/synthesis --family="Stratix V" --part=Unknown
2017.06.27.15:06:24 Info: Loading FixedCor/system.qsys
2017.06.27.15:06:24 Info: Reading input file
2017.06.27.15:06:24 Info: Adding board [board 1.0]
2017.06.27.15:06:25 Info: Parameterizing module board
2017.06.27.15:06:25 Info: Adding global_reset [altera_reset_bridge 16.0]
2017.06.27.15:06:25 Info: Parameterizing module global_reset
2017.06.27.15:06:25 Info: Adding kernel_system [kernel_system 1.0]
2017.06.27.15:06:25 Info: Parameterizing module kernel_system
2017.06.27.15:06:25 Info: Building connections
2017.06.27.15:06:25 Info: Parameterizing connections
2017.06.27.15:06:25 Info: Validating
2017.06.27.15:06:28 Info: Done reading input file
2017.06.27.15:06:34 Info: system.board.pcie: CVP support for this design is enabled.
2017.06.27.15:06:34 Info: system.board.pcie: The application clock frequency (pld_clk) is 250 Mhz
2017.06.27.15:06:34 Info: system.board.pcie: Family: Stratix V
2017.06.27.15:06:34 Info: system.board.pcie: 10 reconfiguration interfaces are required for connection to the external reconfiguration controller and the reconfig driver
2017.06.27.15:06:34 Info: system.board.pcie: Hard Reset Controller enabled
2017.06.27.15:06:34 Info: system.board.pcie: Credit allocation in the 16 KBytes receive buffer:
2017.06.27.15:06:34 Info: system.board.pcie: Posted    : header=16  data=16
2017.06.27.15:06:34 Info: system.board.pcie: Non posted: header=16  data=0
2017.06.27.15:06:34 Info: system.board.pcie: Completion: header=195 data=781
2017.06.27.15:06:34 Info: system.board.pcie: TXS ADDRESS WIDTH is 32
2017.06.27.15:06:34 Warning: system.board.ddr3a: Timing closure may not be achievable at maximum frequency for 'Command Queue Look-Ahead Depth' value greater than 4.
2017.06.27.15:06:34 Warning: system.board.ddr3a: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
2017.06.27.15:06:34 Warning: system.board.ddr3a.oct_bridge: <b>oct_bridge.oct_sharing</b> cannot be both connected and exported
2017.06.27.15:06:34 Warning: system.board.ddr3a.pll_bridge: <b>pll_bridge.pll_sharing</b> cannot be both connected and exported
2017.06.27.15:06:34 Warning: system.board.ddr3b: DLL slave mode selected, DLL inputs must be connected to a Master Memory Controller or user generated DLL
2017.06.27.15:06:34 Warning: system.board.ddr3b: OCT slave mode selected, OCT termination control inputs must be connected to an OCT control block and Termination Control Block assignments must be updated for the new OCT control block location
2017.06.27.15:06:34 Warning: system.board.ddr3b: Timing closure may not be achievable at maximum frequency for 'Command Queue Look-Ahead Depth' value greater than 4.
2017.06.27.15:06:34 Warning: system.board.ddr3b: PLL slave mode selected, PLL inputs must be connected to a Master Memory Controller or user generated PLL
2017.06.27.15:06:34 Warning: system.board.ddr3b: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
2017.06.27.15:06:34 Info: system.board.temperature_pll: The legal reference clock frequency is 5.0 MHz..800.0 MHz
2017.06.27.15:06:34 Info: system.board.temperature_pll: Able to implement PLL with user settings
2017.06.27.15:06:34 Warning: system.board.kernel_clk_gen.kernel_clk: The input clock frequency must be known or set by the parent if this is a subsystem.
2017.06.27.15:06:34 Info: system.board.kernel_clk_gen.kernel_pll: The legal reference clock frequency is 50.0 MHz..800.0 MHz
2017.06.27.15:06:34 Warning: system.board.kernel_clk_gen.kernel_pll: Able to implement PLL - Actual settings differ from Requested settings
2017.06.27.15:06:34 Warning: system.board.kernel_interface: <b>add_instance</b>: Component <b>altera_avalon_mm_bridge</b> version <b>13.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.kernel_interface: <b>add_instance</b>: Component <b>altera_address_span_extender</b> version <b>15.0</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.kernel_interface: <b>add_instance</b>: Component <b>altera_avalon_mm_bridge</b> version <b>13.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.kernel_interface: <b>add_instance</b>: Component <b>clock_source</b> version <b>13.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.kernel_interface: <b>add_instance</b>: Component <b>altera_irq_bridge</b> version <b>13.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.kernel_interface: <b>add_instance</b>: Component <b>altera_reset_bridge</b> version <b>13.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.kernel_interface: <b>add_instance</b>: Component <b>altera_reset_controller</b> version <b>13.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.kernel_interface: <b>add_instance</b>: Component <b>altera_clock_bridge</b> version <b>13.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.kernel_interface: <b>add_instance</b>: Component <b>altera_reset_bridge</b> version <b>13.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.kernel_interface: <b>add_instance</b>: Component <b>altera_reset_bridge</b> version <b>13.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.kernel_interface: <b>add_instance</b>: Component <b>altera_avalon_onchip_memory2</b> version <b>13.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.kernel_interface.mem_org_mode0: <b>mem_org_mode0.mem_organization_kernel</b> must be exported, or connected to a matching conduit.
2017.06.27.15:06:34 Warning: system.board.kernel_clk: The input clock frequency must be known or set by the parent if this is a subsystem.
2017.06.27.15:06:34 Warning: system.board.memory_bank_divider_0: <b>add_instance</b>: Component <b>altera_avalon_mm_bridge</b> version <b>12.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.acl_memory_bank_divider: <b>add_instance</b>: Component <b>clock_source</b> version <b>12.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.acl_memory_bank_divider: <b>add_instance</b>: Component <b>clock_source</b> version <b>12.1</b> is not installed - loaded latest installed version <b>16.0</b> instead.  Please check for parameter mismatches 
2017.06.27.15:06:34 Warning: system.board.config_clk.out_clk/kernel_clk_gen.clk: <b>kernel_clk_gen.clk</b> requires 50000000Hz, but source has frequency of 0Hz
2017.06.27.15:06:34 Warning: system.board.pcie.coreclkout/kernel_interface.clk: <b>kernel_interface.clk</b> requires 100000000Hz, but source has frequency of 250000000Hz
2017.06.27.15:06:34 Warning: system.board.kernel_clk_gen.kernel_clk/memory_bank_divider_0.kernel_clk: <b>memory_bank_divider_0.kernel_clk</b> requires 100000000Hz, but source has frequency of 0Hz
2017.06.27.15:06:34 Warning: system.board.pcie: <b>pcie.reconfig_clk_locked</b> must be exported, or connected to a matching conduit.
2017.06.27.15:06:34 Warning: system.board.pcie: <b>pcie.hip_pipe</b> must be exported, or connected to a matching conduit.
2017.06.27.15:06:34 Warning: system.board.temperature_pll: <b>temperature_pll.locked</b> must be exported, or connected to a matching conduit.
2017.06.27.15:06:34 Warning: system.board.kernel_clk_gen: <b>kernel_clk_gen.kernel_pll_locked</b> must be exported, or connected to a matching conduit.
2017.06.27.15:06:34 Warning: system.board.uniphy_status_0: <b>uniphy_status_0.status_export</b> must be exported, or connected to a matching conduit.
2017.06.27.15:06:34 Warning: system.board.pcie: Interrupt sender <b>pcie.CraIrq</b> is not connected to an interrupt receiver
2017.06.27.15:06:34 Warning: system.board.cpld_bridge_0: Interrupt sender <b>cpld_bridge_0.csr_irq</b> is not connected to an interrupt receiver
2017.06.27.15:06:34 Warning: system.board.por_reset_counter: <b>por_reset_counter.s</b> must be connected to an Avalon-MM master
2017.06.27.15:06:34 Warning: system.board.pipe_stage_qdr_host_0: <b>pipe_stage_qdr_host_0.m0</b> must be connected to an Avalon-MM slave
2017.06.27.15:06:34 Warning: system.board.cpld_bridge_0: <b>cpld_bridge_0.master</b> must be connected to an Avalon-MM slave
2017.06.27.15:06:34 Warning: system.kernel_system.acl_internal_snoop: No adaptation is needed; a pass through bridge is inserted
2017.06.27.15:06:34 Info: system.kernel_system.acl_internal_snoop: Inserting channel_adapter: pass_through_0
2017.06.27.15:06:34 Warning: system.kernel_system.acl_internal_snoop.out_0: <b>acl_internal_snoop.out_0</b> must be connected to an Avalon-ST sink
2017.06.27.15:06:34 Warning: system.board: <b>board.pcie_hip_ctrl</b> must be exported, or connected to a matching conduit.
2017.06.27.15:06:36 Info: system: Generating <b>system</b> "<b>system</b>" for QUARTUS_SYNTH
2017.06.27.15:06:45 Info: Interconnect is inserted between master pipe_stage_ddr3a_dimm.m0 and slave ddr3a.avl because the master has address signal 32 bit wide, but the slave is 26 bit wide.
2017.06.27.15:06:45 Info: Interconnect is inserted between master pipe_stage_ddr3a_dimm.m0 and slave ddr3a.avl because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2017.06.27.15:06:46 Info: Interconnect is inserted between master pipe_stage_ddr3b_dimm.m0 and slave ddr3b.avl because the master has address signal 32 bit wide, but the slave is 26 bit wide.
2017.06.27.15:06:46 Info: Interconnect is inserted between master pipe_stage_ddr3b_dimm.m0 and slave ddr3b.avl because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2017.06.27.15:06:47 Info: Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0
2017.06.27.15:06:47 Info: Inserting clock-crossing logic between cmd_demux.src1 and cmd_mux_001.sink0
2017.06.27.15:06:47 Info: Inserting clock-crossing logic between cmd_demux.src9 and cmd_mux_009.sink0
2017.06.27.15:06:47 Info: Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0
2017.06.27.15:06:47 Info: Inserting clock-crossing logic between rsp_demux_001.src0 and rsp_mux.sink1
2017.06.27.15:06:47 Info: Inserting clock-crossing logic between rsp_demux_009.src0 and rsp_mux.sink9
2017.06.27.15:06:48 Info: Interconnect is inserted between master pcie.Rxm_BAR0 and slave pipe_stage_host_ctrl.s0 because the master has address signal 32 bit wide, but the slave is 18 bit wide.
2017.06.27.15:06:48 Info: Interconnect is inserted between master pcie.Rxm_BAR0 and slave pipe_stage_host_ctrl.s0 because the master has readdata signal 128 bit wide, but the slave is 32 bit wide.
2017.06.27.15:06:48 Info: Interconnect is inserted between master pcie.Rxm_BAR0 and slave pipe_stage_host_ctrl.s0 because the master has writedata signal 128 bit wide, but the slave is 32 bit wide.
2017.06.27.15:06:48 Info: Interconnect is inserted between master pcie.Rxm_BAR0 and slave pipe_stage_host_ctrl.s0 because the master has burstcount signal 6 bit wide, but the slave is 1 bit wide.
2017.06.27.15:06:48 Info: Interconnect is inserted between master pcie.Rxm_BAR0 and slave pipe_stage_host_ctrl.s0 because the master has byteenable signal 16 bit wide, but the slave is 4 bit wide.
2017.06.27.15:06:48 Info: Interconnect is inserted between master clock_cross_dma_to_pcie.m0 and slave pcie.Txs because the master has readdata signal 512 bit wide, but the slave is 128 bit wide.
2017.06.27.15:06:48 Info: Interconnect is inserted between master clock_cross_dma_to_pcie.m0 and slave pcie.Txs because the master has burstcount signal 5 bit wide, but the slave is 6 bit wide.
2017.06.27.15:06:48 Info: Interconnect is inserted between master clock_cross_dma_to_pcie.m0 and slave pcie.Txs because the master has writedata signal 512 bit wide, but the slave is 128 bit wide.
2017.06.27.15:06:48 Info: Interconnect is inserted between master clock_cross_dma_to_pcie.m0 and slave pcie.Txs because the master has byteenable signal 64 bit wide, but the slave is 16 bit wide.
2017.06.27.15:06:48 Info: Interconnect is inserted between master clock_cross_dma_to_pcie.m0 and slave pcie.Txs because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master pipe_stage_qdr_host.m0 and slave pipe_stage_qdr_host_0.s0 because the master has readdata signal 512 bit wide, but the slave is 128 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master pipe_stage_qdr_host.m0 and slave pipe_stage_qdr_host_0.s0 because the master has writedata signal 512 bit wide, but the slave is 128 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master pipe_stage_qdr_host.m0 and slave pipe_stage_qdr_host_0.s0 because the master has byteenable signal 64 bit wide, but the slave is 16 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_1.m0 and slave dma_0.s_nondma because the master has readdata signal 32 bit wide, but the slave is 512 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_1.m0 and slave dma_0.s_nondma because the master has burstcount signal 1 bit wide, but the slave is 5 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_1.m0 and slave dma_0.s_nondma because the master has writedata signal 32 bit wide, but the slave is 512 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_1.m0 and slave dma_0.s_nondma because the master has address signal 16 bit wide, but the slave is 10 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_1.m0 and slave dma_0.s_nondma because the master has byteenable signal 4 bit wide, but the slave is 64 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_1.m0 and slave dma_0.s_nondma because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_0.m0 and slave dma_0.csr because the master has readdata signal 32 bit wide, but the slave is 64 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_0.m0 and slave dma_0.csr because the master has writedata signal 32 bit wide, but the slave is 64 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_0.m0 and slave dma_0.csr because the master has byteenable signal 4 bit wide, but the slave is 8 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_cpld.m0 and slave cpld_bridge_0.cpld_mm_in because the master has readdata signal 32 bit wide, but the slave is 16 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_cpld.m0 and slave cpld_bridge_0.cpld_mm_in because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_cpld.m0 and slave cpld_bridge_0.cpld_mm_in because the master has writedata signal 32 bit wide, but the slave is 16 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_cpld.m0 and slave cpld_bridge_0.cpld_mm_in because the master has address signal 3 bit wide, but the slave is 0 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_cpld.m0 and slave cpld_bridge_0.cpld_mm_in because the master has byteenable signal 4 bit wide, but the slave is 0 bit wide.
2017.06.27.15:06:49 Info: Interconnect is inserted between master clock_cross_pcie_to_cpld.m0 and slave cpld_bridge_0.cpld_mm_in because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2017.06.27.15:06:55 Info: board: "<b>system</b>" instantiated <b>board</b> "<b>board</b>"
2017.06.27.15:06:55 Info: Interconnect is inserted between master kernel_cra.m0 and slave cra_root.cra_slave because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide.
2017.06.27.15:06:55 Info: Interconnect is inserted between master kernel_cra.m0 and slave cra_root.cra_slave because the master has address signal 30 bit wide, but the slave is 4 bit wide.
2017.06.27.15:06:55 Info: Interconnect is inserted between master kernel_cra.m0 and slave cra_root.cra_slave because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2017.06.27.15:06:55 Info: kernel_system: "<b>system</b>" instantiated <b>kernel_system</b> "<b>kernel_system</b>"
2017.06.27.15:06:55 Info: mm_interconnect_1: "<b>system</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>"
2017.06.27.15:06:55 Info: mm_interconnect_2: "<b>system</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_2</b>"
2017.06.27.15:06:55 Info: irq_mapper: "<b>system</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"
2017.06.27.15:06:55 Info: rst_controller: "<b>system</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"
2017.06.27.15:06:55 Info: pipe_stage_ddr3b_dimm: "<b>board</b>" instantiated <b>altera_avalon_mm_bridge</b> "<b>pipe_stage_ddr3b_dimm</b>"
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_pcs.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_pcs.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_pcs_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_pcs_ch.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_pma.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_xcvr.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_reconfig_bundle_to_ip.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_ip.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_reconfig_bundle_merger.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_merger.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_rx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_rx_pma.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_tx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_tx_pma.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_tx_pma_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_tx_pma_ch.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_h.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_xcvr_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_avmm_csr.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_xcvr_avmm_dcd.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_avmm_dcd.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_xcvr_avmm.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_avmm.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_xcvr_data_adapter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_data_adapter.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_xcvr_native.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_native.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_xcvr_plls.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_plls.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_10g_rx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_10g_rx_pcs_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_10g_tx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_10g_tx_pcs_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_8g_rx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_8g_rx_pcs_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_8g_tx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_8g_tx_pcs_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_8g_pcs_aggregate_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_8g_pcs_aggregate_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_common_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_common_pcs_pma_interface_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_common_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_common_pld_pcs_interface_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_pipe_gen1_2_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_pipe_gen1_2_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_pipe_gen3_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_pipe_gen3_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_rx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_rx_pcs_pma_interface_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_rx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_rx_pld_pcs_interface_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_tx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_tx_pcs_pma_interface_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_hssi_tx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_tx_pld_pcs_interface_rbc.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_xcvr_emsip_adapter.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/sv/sv_xcvr_emsip_adapter.sv
2017.06.27.15:06:55 Info: pcie: add_fileset_file ./sv_xcvr_pipe_native.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/sv/sv_xcvr_pipe_native.sv
2017.06.27.15:06:55 Info: pcie: "<b>board</b>" instantiated <b>altera_pcie_sv_hip_avmm</b> "<b>pcie</b>"
2017.06.27.15:06:56 Info: ddr3a: "<b>board</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>ddr3a</b>"
2017.06.27.15:06:56 Info: ddr3b: "<b>board</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>ddr3b</b>"
2017.06.27.15:06:56 Info: clock_cross_dma_to_pcie: "<b>board</b>" instantiated <b>altera_avalon_mm_clock_crossing_bridge</b> "<b>clock_cross_dma_to_pcie</b>"
2017.06.27.15:06:56 Info: temperature_pll: "<b>board</b>" instantiated <b>altera_pll</b> "<b>temperature_pll</b>"
2017.06.27.15:06:56 Info: temperature_0: "<b>board</b>" instantiated <b>temperature</b> "<b>temperature_0</b>"
2017.06.27.15:06:57 Info: Inserting clock-crossing logic between cmd_demux.src2 and cmd_mux_002.sink0
2017.06.27.15:06:57 Info: Inserting clock-crossing logic between rsp_demux_002.src0 and rsp_mux.sink2
2017.06.27.15:06:58 Info: kernel_clk_gen: "<b>board</b>" instantiated <b>acl_kernel_clk</b> "<b>kernel_clk_gen</b>"
2017.06.27.15:06:58 Info: Interconnect is inserted between master address_span_extender_0.expanded_master and slave kernel_cra.s0 because they have different clock source.
2017.06.27.15:06:58 Info: Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0
2017.06.27.15:06:58 Info: Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0
2017.06.27.15:07:00 Info: kernel_interface: "<b>board</b>" instantiated <b>kernel_interface</b> "<b>kernel_interface</b>"
2017.06.27.15:07:02 Info: dma_0: "<b>board</b>" instantiated <b>acl_dma</b> "<b>dma_0</b>"
2017.06.27.15:07:02 Info: Interconnect is inserted between master pipe_stage_presplitter.m0 and slave mem_splitter_0.s because the master has address signal 33 bit wide, but the slave is 27 bit wide.
2017.06.27.15:07:02 Info: Interconnect is inserted between master pipe_stage_presplitter.m0 and slave mem_splitter_0.s because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2017.06.27.15:07:02 Info: memory_bank_divider_0: "<b>board</b>" instantiated <b>acl_memory_bank_divider</b> "<b>memory_bank_divider_0</b>"
2017.06.27.15:07:02 Info: por_reset_counter: "<b>board</b>" instantiated <b>sw_reset</b> "<b>por_reset_counter</b>"
2017.06.27.15:07:02 Info: uniphy_status_0: "<b>board</b>" instantiated <b>uniphy_status</b> "<b>uniphy_status_0</b>"
2017.06.27.15:07:02 Info: version_id_0: "<b>board</b>" instantiated <b>version_id</b> "<b>version_id_0</b>"
2017.06.27.15:07:02 Info: no_reset_for_uniphy: "<b>board</b>" instantiated <b>no_reset</b> "<b>no_reset_for_uniphy</b>"
2017.06.27.15:07:02 Info: onchip_ram: Starting RTL generation for module 'system_board_onchip_ram'
2017.06.27.15:07:02 Info: onchip_ram:   Generation command is [exec /var/tmp/atze/quartus/linux64/perl/bin/perl -I /var/tmp/atze/quartus/linux64/perl/lib -I /var/tmp/atze/quartus/sopc_builder/bin/europa -I /var/tmp/atze/quartus/sopc_builder/bin/perl_lib -I /var/tmp/atze/quartus/sopc_builder/bin -I /var/tmp/atze/quartus/../ip/altera/sopc_builder_ip/common -I /var/tmp/atze/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /var/tmp/atze/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=system_board_onchip_ram --dir=/tmp/alt7344_5980828811768715281.dir/0008_onchip_ram_gen/ --quartus_dir=/var/tmp/atze/quartus --verilog --config=/tmp/alt7344_5980828811768715281.dir/0008_onchip_ram_gen//system_board_onchip_ram_component_configuration.pl  --do_build_sim=0  ]
2017.06.27.15:07:02 Info: onchip_ram: Done RTL generation for module 'system_board_onchip_ram'
2017.06.27.15:07:02 Info: onchip_ram: "<b>board</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>onchip_ram</b>"
2017.06.27.15:07:02 Info: cpld_bridge_0: "<b>board</b>" instantiated <b>cpld_bridge</b> "<b>cpld_bridge_0</b>"
2017.06.27.15:07:02 Info: mm_interconnect_0: "<b>board</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"
2017.06.27.15:07:02 Info: mm_interconnect_1: "<b>board</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>"
2017.06.27.15:07:03 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:03 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:03 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:03 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:03 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:03 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:03 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:03 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:03 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:03 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:03 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:04 Info: mm_interconnect_2: "<b>board</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_2</b>"
2017.06.27.15:07:04 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:04 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:04 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:05 Info: mm_interconnect_3: "<b>board</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_3</b>"
2017.06.27.15:07:05 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:05 Info: mm_interconnect_4: "<b>board</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_4</b>"
2017.06.27.15:07:05 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:05 Info: mm_interconnect_5: "<b>board</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_5</b>"
2017.06.27.15:07:05 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:06 Info: mm_interconnect_6: "<b>board</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_6</b>"
2017.06.27.15:07:06 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:06 Info: mm_interconnect_7: "<b>board</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_7</b>"
2017.06.27.15:07:06 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:06 Info: mm_interconnect_8: "<b>board</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_8</b>"
2017.06.27.15:07:06 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:06 Info: mm_interconnect_9: "<b>board</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_9</b>"
2017.06.27.15:07:06 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:07 Info: mm_interconnect_10: "<b>board</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_10</b>"
2017.06.27.15:07:07 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2017.06.27.15:07:07 Info: mm_interconnect_11: "<b>board</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_11</b>"
2017.06.27.15:07:07 Info: irq_mapper: "<b>board</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"
2017.06.27.15:07:07 Info: irq_mapper_001: "<b>board</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper_001</b>"
2017.06.27.15:07:07 Info: irq_synchronizer: "<b>board</b>" instantiated <b>altera_irq_clock_crosser</b> "<b>irq_synchronizer</b>"
2017.06.27.15:07:07 Info: FixedCor_system: "<b>kernel_system</b>" instantiated <b>FixedCor_system</b> "<b>FixedCor_system</b>"
2017.06.27.15:07:07 Info: acl_internal_snoop: "<b>kernel_system</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>acl_internal_snoop</b>"
2017.06.27.15:07:07 Info: avs_Correlator_cra_cra_ring: "<b>kernel_system</b>" instantiated <b>cra_ring_node</b> "<b>avs_Correlator_cra_cra_ring</b>"
2017.06.27.15:07:07 Info: cra_root: "<b>kernel_system</b>" instantiated <b>cra_ring_root</b> "<b>cra_root</b>"
2017.06.27.15:07:07 Info: kernel_irq: "<b>kernel_system</b>" instantiated <b>altera_irq_bridge</b> "<b>kernel_irq</b>"
2017.06.27.15:07:07 Info: mm_interconnect_1: "<b>kernel_system</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_1</b>"
2017.06.27.15:07:07 Info: kernel_system_kernel_mem0_translator: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_master_translator</b> "<b>kernel_system_kernel_mem0_translator</b>"
2017.06.27.15:07:07 Info: board_kernel_mem0_translator: "<b>mm_interconnect_1</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>board_kernel_mem0_translator</b>"
2017.06.27.15:07:07 Info: pll0: "<b>ddr3a</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"
2017.06.27.15:07:07 Info: p0: Generating clock pair generator
2017.06.27.15:07:10 Info: p0: Generating system_board_ddr3a_p0_altdqdqs
2017.06.27.15:07:17 Info: p0: 
2017.06.27.15:07:17 Info: p0: *****************************
2017.06.27.15:07:17 Info: p0: 
2017.06.27.15:07:17 Info: p0: Remember to run the system_board_ddr3a_p0_pin_assignments.tcl
2017.06.27.15:07:17 Info: p0: script after running Synthesis and before Fitting.
2017.06.27.15:07:17 Info: p0: 
2017.06.27.15:07:17 Info: p0: *****************************
2017.06.27.15:07:17 Info: p0: 
2017.06.27.15:07:17 Info: p0: "<b>ddr3a</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"
2017.06.27.15:07:17 Info: m0: "<b>ddr3a</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"
ERROR: Cannot find sequencer/sequencer.elf
2017.06.27.15:07:17 Error: s0: Cannot find sequencer/sequencer.elf
2017.06.27.15:07:17 Error: s0: An error occurred
    while executing
"error "An error occurred""
    (procedure "_error" line 8)
    invoked from within
"_error "Cannot find $seq_file""
    ("if" then script line 2)
    invoked from within
"if {[file exists $seq_file] == 0} {
		_error "Cannot find $seq_file"
	}"
    (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
    invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
    invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
    ("if" then script line 2)
    invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
		set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
    (procedure "generate_qsys_sequencer_sw" line 924)
    invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name $ac_rom_init_file_name ..."
    invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name ..."
    ("if" else script line 2)
    invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
		set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
    (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)
    invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
    invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
    (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
    invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
    invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
		set file_name [file tail $genera..."
    (procedure "generate_synth" line 8)
    invoked from within
"generate_synth system_board_ddr3a_s0"
2017.06.27.15:07:17 Info: s0: "<b>ddr3a</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"
2017.06.27.15:07:17 Error: Generation stopped, 303 or more modules remaining
2017.06.27.15:07:17 Info: system: Done "<b>system</b>" with 140 modules, 241 files
2017.06.27.15:07:19 Error: qsys-generate failed with exit code 1: 3 Errors, 43 Warnings
2017.06.27.15:07:19 Info: Finished: <b>Create HDL design files for synthesis</b>