========================================================================================================================
| *** Optimization Report *** |
+--------------------------------------------------------------------+
; Estimated Resource Usage Summary ;
+----------------------------------------+---------------------------+
; Resource + Usage ;
+----------------------------------------+---------------------------+
; Logic utilization ; 60% ;
; Dedicated logic registers ; 28% ;
; Memory blocks ; 87% ;
; DSP blocks ; 0% ;
+----------------------------------------+---------------------------;
System name: kernel_gpu_opencl_altera_v2
2015.07.07.23:26:17 Info: Doing: qsys-script --script=kernel_system.tcl --Xmx512M --XX:+UseSerialGC
2015.07.07.23:26:23 Info: set_validation_property AUTOMATIC_VALIDATION false
2015.07.07.23:26:23 Info: add_instance clk_1x altera_clock_bridge
2015.07.07.23:26:24 Info: set_instance_parameter_value clk_1x EXPLICIT_CLOCK_RATE 0
2015.07.07.23:26:24 Info: set_instance_parameter_value clk_1x NUM_CLOCK_OUTPUTS 1
2015.07.07.23:26:24 Info: add_interface clock_reset clock sink
2015.07.07.23:26:24 Info: set_interface_property clock_reset EXPORT_OF clk_1x.in_clk
2015.07.07.23:26:24 Info: add_instance clk_2x altera_clock_bridge
2015.07.07.23:26:24 Info: set_instance_parameter_value clk_2x EXPLICIT_CLOCK_RATE 0
2015.07.07.23:26:24 Info: set_instance_parameter_value clk_2x NUM_CLOCK_OUTPUTS 1
2015.07.07.23:26:24 Info: add_interface clock_reset2x clock sink
2015.07.07.23:26:24 Info: set_interface_property clock_reset2x EXPORT_OF clk_2x.in_clk
2015.07.07.23:26:24 Info: add_instance clk_snoop altera_clock_bridge
2015.07.07.23:26:24 Info: set_instance_parameter_value clk_snoop EXPLICIT_CLOCK_RATE 0
2015.07.07.23:26:24 Info: set_instance_parameter_value clk_snoop NUM_CLOCK_OUTPUTS 1
2015.07.07.23:26:24 Info: add_interface cc_snoop_clk clock sink
2015.07.07.23:26:24 Info: set_interface_property cc_snoop_clk EXPORT_OF clk_snoop.in_clk
2015.07.07.23:26:24 Info: add_instance reset altera_reset_bridge
2015.07.07.23:26:24 Info: set_instance_parameter_value reset ACTIVE_LOW_RESET 1
2015.07.07.23:26:24 Info: set_instance_parameter_value reset SYNCHRONOUS_EDGES deassert
2015.07.07.23:26:24 Info: set_instance_parameter_value reset NUM_RESET_OUTPUTS 1
2015.07.07.23:26:24 Info: add_interface clock_reset_reset reset sink
2015.07.07.23:26:24 Info: set_interface_property clock_reset_reset EXPORT_OF reset.in_reset
2015.07.07.23:26:24 Info: add_connection clk_1x.out_clk reset.clk
2015.07.07.23:26:24 Info: add_instance kernel_gpu_opencl_altera_v2_system kernel_gpu_opencl_altera_v2_system
2015.07.07.23:26:24 Info: add_connection clk_1x.out_clk kernel_gpu_opencl_altera_v2_system.clock_reset
2015.07.07.23:26:24 Info: add_connection clk_2x.out_clk kernel_gpu_opencl_altera_v2_system.clock_reset2x
2015.07.07.23:26:24 Info: add_connection reset.out_reset kernel_gpu_opencl_altera_v2_system.clock_reset_reset
2015.07.07.23:26:24 Info: add_interface kernel_mem0 avalon slave
2015.07.07.23:26:24 Info: set_interface_property kernel_mem0 EXPORT_OF kernel_gpu_opencl_altera_v2_system.avm_memgmem0_DDR_port_0_0_rw
2015.07.07.23:26:24 Info: add_interface kernel_mem1 avalon slave
2015.07.07.23:26:24 Info: set_interface_property kernel_mem1 EXPORT_OF kernel_gpu_opencl_altera_v2_system.avm_memgmem0_DDR_port_1_0_rw
2015.07.07.23:26:24 Info: add_instance kernel_irq altera_irq_bridge
2015.07.07.23:26:25 Info: set_instance_parameter_value kernel_irq IRQ_WIDTH 1
2015.07.07.23:26:25 Info: set_instance_parameter_value kernel_irq IRQ_N 0
2015.07.07.23:26:25 Info: add_interface kernel_irq irq sender
2015.07.07.23:26:25 Info: set_interface_property kernel_irq EXPORT_OF kernel_irq.sender0_irq
2015.07.07.23:26:25 Info: add_connection clk_1x.out_clk kernel_irq.clk
2015.07.07.23:26:25 Info: add_connection reset.out_reset kernel_irq.clk_reset
2015.07.07.23:26:25 Info: add_connection kernel_irq.receiver_irq kernel_gpu_opencl_altera_v2_system.kernel_irq
2015.07.07.23:26:25 Info: add_instance kernel_cra altera_avalon_mm_bridge
2015.07.07.23:26:25 Info: set_instance_parameter_value kernel_cra DATA_WIDTH 64
2015.07.07.23:26:25 Info: set_instance_parameter_value kernel_cra SYMBOL_WIDTH 8
2015.07.07.23:26:25 Info: set_instance_parameter_value kernel_cra ADDRESS_WIDTH 30
2015.07.07.23:26:25 Info: set_instance_parameter_value kernel_cra USE_AUTO_ADDRESS_WIDTH 0
2015.07.07.23:26:25 Info: set_instance_parameter_value kernel_cra ADDRESS_UNITS SYMBOLS
2015.07.07.23:26:25 Info: set_instance_parameter_value kernel_cra MAX_BURST_SIZE 1
2015.07.07.23:26:25 Info: set_instance_parameter_value kernel_cra MAX_PENDING_RESPONSES 1
2015.07.07.23:26:25 Info: set_instance_parameter_value kernel_cra LINEWRAPBURSTS 0
2015.07.07.23:26:25 Info: set_instance_parameter_value kernel_cra PIPELINE_COMMAND 0
2015.07.07.23:26:25 Info: set_instance_parameter_value kernel_cra PIPELINE_RESPONSE 0
2015.07.07.23:26:25 Info: add_connection clk_1x.out_clk kernel_cra.clk
2015.07.07.23:26:25 Info: add_connection reset.out_reset kernel_cra.reset
2015.07.07.23:26:25 Info: add_interface avs_kernel_cra avalon slave
2015.07.07.23:26:25 Info: set_interface_property kernel_cra EXPORT_OF kernel_cra.s0
2015.07.07.23:26:25 Info: add_instance cra_root cra_ring_root
2015.07.07.23:26:25 Info: set_instance_parameter_value cra_root DATA_W 64
2015.07.07.23:26:25 Info: set_instance_parameter_value cra_root ADDR_W 5
2015.07.07.23:26:25 Info: set_instance_parameter_value cra_root ID_W 1
2015.07.07.23:26:25 Info: add_connection clk_1x.out_clk cra_root.clock
2015.07.07.23:26:25 Info: add_connection reset.out_reset cra_root.reset
2015.07.07.23:26:25 Info: add_connection kernel_cra.m0 cra_root.cra_slave
2015.07.07.23:26:25 Info: set_connection_parameter_value kernel_cra.m0/cra_root.cra_slave baseAddress 0x0
2015.07.07.23:26:25 Info: add_instance avs_findK_cra_cra_ring cra_ring_node
2015.07.07.23:26:25 Info: set_instance_parameter_value avs_findK_cra_cra_ring DATA_W 64
2015.07.07.23:26:25 Info: set_instance_parameter_value avs_findK_cra_cra_ring RING_ADDR_W 5
2015.07.07.23:26:25 Info: set_instance_parameter_value avs_findK_cra_cra_ring CRA_ADDR_W 5
2015.07.07.23:26:25 Info: set_instance_parameter_value avs_findK_cra_cra_ring ID_W 1
2015.07.07.23:26:25 Info: set_instance_parameter_value avs_findK_cra_cra_ring ID 0
2015.07.07.23:26:25 Info: add_connection clk_1x.out_clk avs_findK_cra_cra_ring.clock
2015.07.07.23:26:25 Info: add_connection reset.out_reset avs_findK_cra_cra_ring.reset
2015.07.07.23:26:25 Info: add_connection cra_root.ring_out avs_findK_cra_cra_ring.ring_in
2015.07.07.23:26:25 Info: add_connection avs_findK_cra_cra_ring.cra_master kernel_gpu_opencl_altera_v2_system.avs_findK_cra
2015.07.07.23:26:25 Info: set_connection_parameter_value avs_findK_cra_cra_ring.cra_master/kernel_gpu_opencl_altera_v2_system.avs_findK_cra baseAddress 0x0
2015.07.07.23:26:25 Info: add_instance avs_findRangeK_cra_cra_ring cra_ring_node
2015.07.07.23:26:25 Info: set_instance_parameter_value avs_findRangeK_cra_cra_ring DATA_W 64
2015.07.07.23:26:25 Info: set_instance_parameter_value avs_findRangeK_cra_cra_ring RING_ADDR_W 5
2015.07.07.23:26:25 Info: set_instance_parameter_value avs_findRangeK_cra_cra_ring CRA_ADDR_W 5
2015.07.07.23:26:25 Info: set_instance_parameter_value avs_findRangeK_cra_cra_ring ID_W 1
2015.07.07.23:26:25 Info: set_instance_parameter_value avs_findRangeK_cra_cra_ring ID 1
2015.07.07.23:26:25 Info: add_connection clk_1x.out_clk avs_findRangeK_cra_cra_ring.clock
2015.07.07.23:26:25 Info: add_connection reset.out_reset avs_findRangeK_cra_cra_ring.reset
2015.07.07.23:26:25 Info: add_connection avs_findK_cra_cra_ring.ring_out avs_findRangeK_cra_cra_ring.ring_in
2015.07.07.23:26:25 Info: add_connection avs_findRangeK_cra_cra_ring.cra_master kernel_gpu_opencl_altera_v2_system.avs_findRangeK_cra
2015.07.07.23:26:25 Info: set_connection_parameter_value avs_findRangeK_cra_cra_ring.cra_master/kernel_gpu_opencl_altera_v2_system.avs_findRangeK_cra baseAddress 0x0
2015.07.07.23:26:25 Info: add_connection avs_findRangeK_cra_cra_ring.ring_out cra_root.ring_in
2015.07.07.23:26:25 Info: add_instance acl_internal_snoop altera_avalon_st_adapter
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop inBitsPerSymbol 33
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop inUsePackets 0
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop inDataWidth 33
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop inMaxChannel 0
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop inChannelWidth 0
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop inErrorWidth 0
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop inErrorDescriptor
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop inUseEmptyPort 0
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop inUseValid 1
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop inUseReady 1
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop inReadyLatency 0
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop outDataWidth 33
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop outMaxChannel 0
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop outChannelWidth 0
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop outErrorWidth 0
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop outErrorDescriptor
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop outUseEmptyPort 0
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop outUseValid 1
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop outUseReady 1
2015.07.07.23:26:26 Info: set_instance_parameter_value acl_internal_snoop outReadyLatency 0
2015.07.07.23:26:26 Info: add_connection clk_snoop.out_clk acl_internal_snoop.in_clk_0
2015.07.07.23:26:26 Info: add_connection reset.out_reset acl_internal_snoop.in_rst_0
2015.07.07.23:26:26 Info: add_interface cc_snoop avalon_streaming sink
2015.07.07.23:26:26 Info: set_interface_property cc_snoop EXPORT_OF acl_internal_snoop.in_0
2015.07.07.23:26:26 Info: save_system kernel_system.qsys
2015.07.07.23:26:26 Info: Doing: qsys-script --script=system.tcl --Xmx512M --XX:+UseSerialGC --system-file=system.qsys
2015.07.07.23:27:02 Info: set_validation_property AUTOMATIC_VALIDATION false
2015.07.07.23:27:02 Info: add_instance kernel_system kernel_system
2015.07.07.23:27:03 Info: add_connection board.kernel_clk kernel_system.clock_reset
2015.07.07.23:27:03 Info: add_connection board.kernel_clk2x kernel_system.clock_reset2x
2015.07.07.23:27:03 Info: add_connection board.kernel_reset kernel_system.clock_reset_reset
2015.07.07.23:27:03 Info: add_connection kernel_system.kernel_mem0 board.kernel_mem0
2015.07.07.23:27:03 Info: add_connection kernel_system.kernel_mem1 board.kernel_mem1
2015.07.07.23:27:03 Info: add_connection board.kernel_irq kernel_system.kernel_irq
2015.07.07.23:27:03 Info: add_connection board.kernel_cra kernel_system.kernel_cra
2015.07.07.23:27:03 Info: add_connection board.acl_internal_snoop kernel_system.cc_snoop
2015.07.07.23:27:03 Info: add_connection board.kernel_clk kernel_system.cc_snoop_clk
2015.07.07.23:27:03 Info: save_system
2015.07.07.23:27:04 Info:
********************************************************************************************************************
Use qsys-generate for a simpler command-line interface for generating IP.
Run ip-generate with switch --remove-qsys-generate-warning to prevent this notice from appearing in subsequent runs.
********************************************************************************************************************
2015.07.07.23:27:09 Progress: Loading kernel_gpu_opencl_altera_v2/system.qsys
2015.07.07.23:27:10 Progress: Reading input file
2015.07.07.23:27:10 Progress: Adding board [board 1.0]
2015.07.07.23:27:10 Progress: Reading input file
2015.07.07.23:27:10 Progress: Adding global_reset_in [altera_reset_bridge 14.0]
2015.07.07.23:27:11 Warning: global_reset_in: Used altera_reset_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:11 Progress: Parameterizing module global_reset_in
2015.07.07.23:27:11 Progress: Adding pipe_stage_ddr3b_dimm [altera_avalon_mm_bridge 14.0]
2015.07.07.23:27:12 Warning: pipe_stage_ddr3b_dimm: Used altera_avalon_mm_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:12 Progress: Parameterizing module pipe_stage_ddr3b_dimm
2015.07.07.23:27:12 Progress: Adding pcie [altera_pcie_sv_hip_avmm 14.0]
2015.07.07.23:27:12 Warning: pcie: Used altera_pcie_sv_hip_avmm 15.0 (instead of 14.0)
2015.07.07.23:27:12 Progress: Parameterizing module pcie
2015.07.07.23:27:12 Progress: Adding ddr3a [altera_mem_if_ddr3_emif 14.0]
2015.07.07.23:27:12 Warning: ddr3a: Used altera_mem_if_ddr3_emif 15.0 (instead of 14.0)
2015.07.07.23:27:12 Progress: Parameterizing module ddr3a
2015.07.07.23:27:12 Progress: Adding ddr3b [altera_mem_if_ddr3_emif 14.0]
2015.07.07.23:27:12 Warning: ddr3b: Used altera_mem_if_ddr3_emif 15.0 (instead of 14.0)
2015.07.07.23:27:12 Progress: Parameterizing module ddr3b
2015.07.07.23:27:13 Progress: Adding pipe_stage_ddr3a_dimm [altera_avalon_mm_bridge 14.0]
2015.07.07.23:27:13 Warning: pipe_stage_ddr3a_dimm: Used altera_avalon_mm_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:13 Progress: Parameterizing module pipe_stage_ddr3a_dimm
2015.07.07.23:27:13 Progress: Adding config_clk [altera_clock_bridge 14.0]
2015.07.07.23:27:13 Warning: config_clk: Used altera_clock_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:13 Progress: Parameterizing module config_clk
2015.07.07.23:27:13 Progress: Adding clock_cross_dma_to_pcie [altera_avalon_mm_clock_crossing_bridge 14.0]
2015.07.07.23:27:13 Warning: clock_cross_dma_to_pcie: Used altera_avalon_mm_clock_crossing_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:13 Progress: Parameterizing module clock_cross_dma_to_pcie
2015.07.07.23:27:13 Progress: Adding temperature_pll [altera_pll 14.0]
2015.07.07.23:27:15 Warning: temperature_pll: Used altera_pll 15.0 (instead of 14.0)
2015.07.07.23:27:15 Progress: Parameterizing module temperature_pll
2015.07.07.23:27:15 Progress: Adding temperature_0 [temperature 10.0]
2015.07.07.23:27:15 Progress: Parameterizing module temperature_0
2015.07.07.23:27:15 Progress: Adding kernel_clk_gen [acl_kernel_clk 1.0]
2015.07.07.23:27:20 Progress: Parameterizing module kernel_clk_gen
2015.07.07.23:27:20 Progress: Adding kernel_interface [kernel_interface 1.0]
2015.07.07.23:27:20 Warning: kernel_interface: Catalog mismatch; expected v1.0 but found v15.0
2015.07.07.23:27:20 Warning: kernel_interface: Used kernel_interface 15.0 (instead of 1.0)
2015.07.07.23:27:20 Progress: Parameterizing module kernel_interface
2015.07.07.23:27:20 Progress: Adding dma_0 [acl_dma 1.0]
2015.07.07.23:27:25 Progress: Parameterizing module dma_0
2015.07.07.23:27:25 Progress: Adding pipe_stage_host_ctrl [altera_avalon_mm_bridge 14.0]
2015.07.07.23:27:25 Warning: pipe_stage_host_ctrl: Used altera_avalon_mm_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module pipe_stage_host_ctrl
2015.07.07.23:27:25 Progress: Adding clock_cross_kernel_mem_0 [altera_avalon_mm_clock_crossing_bridge 14.0]
2015.07.07.23:27:25 Warning: clock_cross_kernel_mem_0: Used altera_avalon_mm_clock_crossing_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module clock_cross_kernel_mem_0
2015.07.07.23:27:25 Progress: Adding clock_cross_kernel_mem_1 [altera_avalon_mm_clock_crossing_bridge 14.0]
2015.07.07.23:27:25 Warning: clock_cross_kernel_mem_1: Used altera_avalon_mm_clock_crossing_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module clock_cross_kernel_mem_1
2015.07.07.23:27:25 Progress: Adding kernel_clk [clock_source 14.0]
2015.07.07.23:27:25 Warning: kernel_clk: Used clock_source 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module kernel_clk
2015.07.07.23:27:25 Progress: Adding memory_bank_divider_0 [acl_memory_bank_divider 1.0]
2015.07.07.23:27:25 Warning: acl_memory_bank_divider: add_instance: Component clock_source version 12.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:25 Warning: acl_memory_bank_divider: add_instance: Component clock_source version 12.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:25 Progress: Parameterizing module memory_bank_divider_0
2015.07.07.23:27:25 Progress: Adding por_reset_counter [sw_reset 10.0]
2015.07.07.23:27:25 Progress: Parameterizing module por_reset_counter
2015.07.07.23:27:25 Progress: Adding reset_controller_pcie [altera_reset_controller 14.0]
2015.07.07.23:27:25 Warning: reset_controller_pcie: Used altera_reset_controller 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module reset_controller_pcie
2015.07.07.23:27:25 Progress: Adding reset_controller_ddr3a [altera_reset_controller 14.0]
2015.07.07.23:27:25 Warning: reset_controller_ddr3a: Used altera_reset_controller 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module reset_controller_ddr3a
2015.07.07.23:27:25 Progress: Adding npor_export [altera_reset_bridge 14.0]
2015.07.07.23:27:25 Warning: npor_export: Used altera_reset_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module npor_export
2015.07.07.23:27:25 Progress: Adding global_reset [altera_reset_bridge 14.0]
2015.07.07.23:27:25 Warning: global_reset: Used altera_reset_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module global_reset
2015.07.07.23:27:25 Progress: Adding reset_controller_global [altera_reset_controller 14.0]
2015.07.07.23:27:25 Warning: reset_controller_global: Used altera_reset_controller 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module reset_controller_global
2015.07.07.23:27:25 Progress: Adding uniphy_status_0 [uniphy_status 10.0]
2015.07.07.23:27:25 Progress: Parameterizing module uniphy_status_0
2015.07.07.23:27:25 Progress: Adding version_id_0 [version_id 10.0]
2015.07.07.23:27:25 Progress: Parameterizing module version_id_0
2015.07.07.23:27:25 Progress: Adding pipe_stage_qdr_host [altera_avalon_mm_bridge 14.0]
2015.07.07.23:27:25 Warning: pipe_stage_qdr_host: Used altera_avalon_mm_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module pipe_stage_qdr_host
2015.07.07.23:27:25 Progress: Adding pipe_stage_qdr_host_0 [altera_avalon_mm_bridge 14.0]
2015.07.07.23:27:25 Warning: pipe_stage_qdr_host_0: Used altera_avalon_mm_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module pipe_stage_qdr_host_0
2015.07.07.23:27:25 Progress: Adding no_reset_for_uniphy [no_reset 10.0]
2015.07.07.23:27:25 Progress: Parameterizing module no_reset_for_uniphy
2015.07.07.23:27:25 Progress: Adding clock_cross_pcie_to_dma_0 [altera_avalon_mm_clock_crossing_bridge 14.0]
2015.07.07.23:27:25 Warning: clock_cross_pcie_to_dma_0: Used altera_avalon_mm_clock_crossing_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module clock_cross_pcie_to_dma_0
2015.07.07.23:27:25 Progress: Adding clock_cross_pcie_to_dma_1 [altera_avalon_mm_clock_crossing_bridge 14.0]
2015.07.07.23:27:25 Warning: clock_cross_pcie_to_dma_1: Used altera_avalon_mm_clock_crossing_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module clock_cross_pcie_to_dma_1
2015.07.07.23:27:25 Progress: Adding onchip_ram [altera_avalon_onchip_memory2 14.0]
2015.07.07.23:27:25 Warning: onchip_ram: Used altera_avalon_onchip_memory2 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module onchip_ram
2015.07.07.23:27:25 Progress: Adding cpld_bridge_0 [cpld_bridge 1.0]
2015.07.07.23:27:25 Progress: Parameterizing module cpld_bridge_0
2015.07.07.23:27:25 Progress: Adding clock_cross_pcie_to_cpld [altera_avalon_mm_clock_crossing_bridge 14.0]
2015.07.07.23:27:25 Warning: clock_cross_pcie_to_cpld: Used altera_avalon_mm_clock_crossing_bridge 15.0 (instead of 14.0)
2015.07.07.23:27:25 Progress: Parameterizing module clock_cross_pcie_to_cpld
2015.07.07.23:27:25 Progress: Building connections
2015.07.07.23:27:25 Progress: Parameterizing connections
2015.07.07.23:27:25 Progress: Validating
2015.07.07.23:27:35 Progress: Done reading input file
2015.07.07.23:27:37 Progress: Parameterizing module board
2015.07.07.23:27:37 Progress: Adding global_reset [altera_reset_bridge 15.0]
2015.07.07.23:27:37 Progress: Parameterizing module global_reset
2015.07.07.23:27:37 Progress: Adding kernel_system [kernel_system 1.0]
2015.07.07.23:27:37 Progress: Reading input file
2015.07.07.23:27:37 Progress: Adding acl_internal_snoop [altera_avalon_st_adapter 15.0]
2015.07.07.23:27:37 Progress: Parameterizing module acl_internal_snoop
2015.07.07.23:27:37 Progress: Adding avs_findK_cra_cra_ring [cra_ring_node 1.0]
2015.07.07.23:27:37 Progress: Parameterizing module avs_findK_cra_cra_ring
2015.07.07.23:27:37 Progress: Adding avs_findRangeK_cra_cra_ring [cra_ring_node 1.0]
2015.07.07.23:27:37 Progress: Parameterizing module avs_findRangeK_cra_cra_ring
2015.07.07.23:27:37 Progress: Adding clk_1x [altera_clock_bridge 15.0]
2015.07.07.23:27:37 Progress: Parameterizing module clk_1x
2015.07.07.23:27:37 Progress: Adding clk_2x [altera_clock_bridge 15.0]
2015.07.07.23:27:37 Progress: Parameterizing module clk_2x
2015.07.07.23:27:37 Progress: Adding clk_snoop [altera_clock_bridge 15.0]
2015.07.07.23:27:37 Progress: Parameterizing module clk_snoop
2015.07.07.23:27:37 Progress: Adding cra_root [cra_ring_root 1.0]
2015.07.07.23:27:37 Progress: Parameterizing module cra_root
2015.07.07.23:27:37 Progress: Adding kernel_cra [altera_avalon_mm_bridge 15.0]
2015.07.07.23:27:37 Progress: Parameterizing module kernel_cra
2015.07.07.23:27:37 Progress: Adding kernel_gpu_opencl_altera_v2_system [kernel_gpu_opencl_altera_v2_system 14.0]
2015.07.07.23:27:37 Progress: Parameterizing module kernel_gpu_opencl_altera_v2_system
2015.07.07.23:27:37 Progress: Adding kernel_irq [altera_irq_bridge 15.0]
2015.07.07.23:27:37 Progress: Parameterizing module kernel_irq
2015.07.07.23:27:37 Progress: Adding reset [altera_reset_bridge 15.0]
2015.07.07.23:27:37 Progress: Parameterizing module reset
2015.07.07.23:27:37 Progress: Building connections
2015.07.07.23:27:37 Progress: Parameterizing connections
2015.07.07.23:27:37 Progress: Validating
2015.07.07.23:27:37 Progress: Done reading input file
2015.07.07.23:27:37 Progress: Parameterizing module kernel_system
2015.07.07.23:27:37 Progress: Building connections
2015.07.07.23:27:37 Progress: Parameterizing connections
2015.07.07.23:27:37 Progress: Validating
2015.07.07.23:27:40 Progress: Done reading input file
2015.07.07.23:27:46 Info: system.board.pcie: CVP support for this design is enabled.
2015.07.07.23:27:46 Info: system.board.pcie: The application clock frequency (pld_clk) is 250 Mhz
2015.07.07.23:27:46 Info: system.board.pcie: Family: Stratix V
2015.07.07.23:27:46 Info: system.board.pcie: 10 reconfiguration interfaces are required for connection to the external reconfiguration controller and the reconfig driver
2015.07.07.23:27:46 Info: system.board.pcie: Hard Reset Controller enabled
2015.07.07.23:27:46 Info: system.board.pcie: Credit allocation in the 16 KBytes receive buffer:
2015.07.07.23:27:46 Info: system.board.pcie: Posted : header=16 data=16
2015.07.07.23:27:46 Info: system.board.pcie: Non posted: header=16 data=0
2015.07.07.23:27:46 Info: system.board.pcie: Completion: header=195 data=781
2015.07.07.23:27:46 Info: system.board.pcie: TXS ADDRESS WIDTH is 32
2015.07.07.23:27:46 Warning: system.board.ddr3a: Timing closure may not be achievable at maximum frequency for 'Command Queue Look-Ahead Depth' value greater than 4.
2015.07.07.23:27:46 Warning: system.board.ddr3a: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
2015.07.07.23:27:46 Warning: system.board.ddr3a.oct_bridge: oct_bridge.oct_sharing cannot be both connected and exported
2015.07.07.23:27:46 Warning: system.board.ddr3a.pll_bridge: pll_bridge.pll_sharing cannot be both connected and exported
2015.07.07.23:27:46 Warning: system.board.ddr3b: DLL slave mode selected, DLL inputs must be connected to a Master Memory Controller or user generated DLL
2015.07.07.23:27:46 Warning: system.board.ddr3b: OCT slave mode selected, OCT termination control inputs must be connected to an OCT control block and Termination Control Block assignments must be updated for the new OCT control block location
2015.07.07.23:27:46 Warning: system.board.ddr3b: Timing closure may not be achievable at maximum frequency for 'Command Queue Look-Ahead Depth' value greater than 4.
2015.07.07.23:27:46 Warning: system.board.ddr3b: PLL slave mode selected, PLL inputs must be connected to a Master Memory Controller or user generated PLL
2015.07.07.23:27:46 Warning: system.board.ddr3b: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
2015.07.07.23:27:46 Info: system.board.temperature_pll: The legal reference clock frequency is 5.0 MHz..800.0 MHz
2015.07.07.23:27:46 Info: system.board.temperature_pll: Able to implement PLL with user settings
2015.07.07.23:27:46 Warning: system.board.kernel_clk_gen.kernel_clk: The input clock frequency must be known or set by the parent if this is a subsystem.
2015.07.07.23:27:46 Info: system.board.kernel_clk_gen.kernel_pll: The legal reference clock frequency is 50.0 MHz..800.0 MHz
2015.07.07.23:27:46 Warning: system.board.kernel_clk_gen.kernel_pll: Able to implement PLL - Actual settings differ from Requested settings
2015.07.07.23:27:46 Warning: system.board.kernel_interface: add_instance: Component altera_avalon_mm_bridge version 13.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.kernel_interface: add_instance: Component altera_avalon_mm_bridge version 13.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.kernel_interface: add_instance: Component clock_source version 13.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.kernel_interface: add_instance: Component altera_irq_bridge version 13.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.kernel_interface: add_instance: Component altera_reset_bridge version 13.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.kernel_interface: add_instance: Component altera_reset_controller version 13.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.kernel_interface: add_instance: Component altera_clock_bridge version 13.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.kernel_interface: add_instance: Component altera_reset_bridge version 13.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.kernel_interface: add_instance: Component altera_reset_bridge version 13.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.kernel_interface: add_instance: Component altera_avalon_onchip_memory2 version 13.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.kernel_interface.mem_org_mode0: mem_org_mode0.mem_organization_kernel must be exported, or connected to a matching conduit.
2015.07.07.23:27:46 Warning: system.board.kernel_clk: The input clock frequency must be known or set by the parent if this is a subsystem.
2015.07.07.23:27:46 Warning: system.board.memory_bank_divider_0: add_instance: Component altera_avalon_mm_bridge version 12.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.acl_memory_bank_divider: add_instance: Component clock_source version 12.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.acl_memory_bank_divider: add_instance: Component clock_source version 12.1 is not installed - loaded latest installed version 15.0 instead. Please check for parameter mismatches
2015.07.07.23:27:46 Warning: system.board.config_clk.out_clk/kernel_clk_gen.clk: kernel_clk_gen.clk requires 50000000Hz, but source has frequency of 0Hz
2015.07.07.23:27:46 Warning: system.board.pcie.coreclkout/kernel_interface.clk: kernel_interface.clk requires 100000000Hz, but source has frequency of 250000000Hz
2015.07.07.23:27:46 Warning: system.board.kernel_clk_gen.kernel_clk/memory_bank_divider_0.kernel_clk: memory_bank_divider_0.kernel_clk requires 100000000Hz, but source has frequency of 0Hz
2015.07.07.23:27:46 Warning: system.board.pcie: pcie.reconfig_clk_locked must be exported, or connected to a matching conduit.
2015.07.07.23:27:46 Warning: system.board.pcie: pcie.hip_pipe must be exported, or connected to a matching conduit.
2015.07.07.23:27:46 Warning: system.board.temperature_pll: temperature_pll.locked must be exported, or connected to a matching conduit.
2015.07.07.23:27:46 Warning: system.board.kernel_clk_gen: kernel_clk_gen.kernel_pll_locked must be exported, or connected to a matching conduit.
2015.07.07.23:27:46 Warning: system.board.uniphy_status_0: uniphy_status_0.status_export must be exported, or connected to a matching conduit.
2015.07.07.23:27:46 Warning: system.board.pcie: Interrupt sender pcie.CraIrq is not connected to an interrupt receiver
2015.07.07.23:27:46 Warning: system.board.cpld_bridge_0: Interrupt sender cpld_bridge_0.csr_irq is not connected to an interrupt receiver
2015.07.07.23:27:46 Warning: system.board.por_reset_counter: por_reset_counter.s must be connected to an Avalon-MM master
2015.07.07.23:27:46 Warning: system.board.pipe_stage_qdr_host_0: pipe_stage_qdr_host_0.m0 must be connected to an Avalon-MM slave
2015.07.07.23:27:46 Warning: system.board.cpld_bridge_0: cpld_bridge_0.master must be connected to an Avalon-MM slave
2015.07.07.23:27:46 Warning: system.kernel_system.acl_internal_snoop: No adaptation is needed; a pass through bridge is inserted
2015.07.07.23:27:46 Info: system.kernel_system.acl_internal_snoop: Inserting channel_adapter: pass_through_0
2015.07.07.23:27:46 Warning: system.kernel_system.acl_internal_snoop.out_0: acl_internal_snoop.out_0 must be connected to an Avalon-ST sink
2015.07.07.23:27:46 Warning: system.board: board.pcie_hip_ctrl must be exported, or connected to a matching conduit.
2015.07.07.23:27:46 Info: system: Generating system "system" for QUARTUS_SYNTH
2015.07.07.23:27:56 Info: Interconnect is inserted between master pipe_stage_ddr3a_dimm.m0 and slave ddr3a.avl because the master has address signal 32 bit wide, but the slave is 26 bit wide.
2015.07.07.23:27:56 Info: Interconnect is inserted between master pipe_stage_ddr3a_dimm.m0 and slave ddr3a.avl because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2015.07.07.23:27:56 Info: Interconnect is inserted between master pipe_stage_ddr3b_dimm.m0 and slave ddr3b.avl because the master has address signal 32 bit wide, but the slave is 26 bit wide.
2015.07.07.23:27:56 Info: Interconnect is inserted between master pipe_stage_ddr3b_dimm.m0 and slave ddr3b.avl because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2015.07.07.23:27:57 Info: Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0
2015.07.07.23:27:57 Info: Inserting clock-crossing logic between cmd_demux.src1 and cmd_mux_001.sink0
2015.07.07.23:27:57 Info: Inserting clock-crossing logic between cmd_demux.src9 and cmd_mux_009.sink0
2015.07.07.23:27:57 Info: Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0
2015.07.07.23:27:57 Info: Inserting clock-crossing logic between rsp_demux_001.src0 and rsp_mux.sink1
2015.07.07.23:27:57 Info: Inserting clock-crossing logic between rsp_demux_009.src0 and rsp_mux.sink9
2015.07.07.23:27:58 Info: Interconnect is inserted between master pcie.Rxm_BAR0 and slave pipe_stage_host_ctrl.s0 because the master has address signal 32 bit wide, but the slave is 18 bit wide.
2015.07.07.23:27:58 Info: Interconnect is inserted between master pcie.Rxm_BAR0 and slave pipe_stage_host_ctrl.s0 because the master has readdata signal 128 bit wide, but the slave is 32 bit wide.
2015.07.07.23:27:58 Info: Interconnect is inserted between master pcie.Rxm_BAR0 and slave pipe_stage_host_ctrl.s0 because the master has writedata signal 128 bit wide, but the slave is 32 bit wide.
2015.07.07.23:27:58 Info: Interconnect is inserted between master pcie.Rxm_BAR0 and slave pipe_stage_host_ctrl.s0 because the master has burstcount signal 6 bit wide, but the slave is 1 bit wide.
2015.07.07.23:27:58 Info: Interconnect is inserted between master pcie.Rxm_BAR0 and slave pipe_stage_host_ctrl.s0 because the master has byteenable signal 16 bit wide, but the slave is 4 bit wide.
2015.07.07.23:27:59 Info: Interconnect is inserted between master clock_cross_dma_to_pcie.m0 and slave pcie.Txs because the master has readdata signal 512 bit wide, but the slave is 128 bit wide.
2015.07.07.23:27:59 Info: Interconnect is inserted between master clock_cross_dma_to_pcie.m0 and slave pcie.Txs because the master has burstcount signal 5 bit wide, but the slave is 6 bit wide.
2015.07.07.23:27:59 Info: Interconnect is inserted between master clock_cross_dma_to_pcie.m0 and slave pcie.Txs because the master has writedata signal 512 bit wide, but the slave is 128 bit wide.
2015.07.07.23:27:59 Info: Interconnect is inserted between master clock_cross_dma_to_pcie.m0 and slave pcie.Txs because the master has byteenable signal 64 bit wide, but the slave is 16 bit wide.
2015.07.07.23:27:59 Info: Interconnect is inserted between master clock_cross_dma_to_pcie.m0 and slave pcie.Txs because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2015.07.07.23:28:00 Info: Interconnect is inserted between master pipe_stage_qdr_host.m0 and slave pipe_stage_qdr_host_0.s0 because the master has readdata signal 512 bit wide, but the slave is 128 bit wide.
2015.07.07.23:28:00 Info: Interconnect is inserted between master pipe_stage_qdr_host.m0 and slave pipe_stage_qdr_host_0.s0 because the master has writedata signal 512 bit wide, but the slave is 128 bit wide.
2015.07.07.23:28:00 Info: Interconnect is inserted between master pipe_stage_qdr_host.m0 and slave pipe_stage_qdr_host_0.s0 because the master has byteenable signal 64 bit wide, but the slave is 16 bit wide.
2015.07.07.23:28:00 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_1.m0 and slave dma_0.s_nondma because the master has readdata signal 32 bit wide, but the slave is 512 bit wide.
2015.07.07.23:28:00 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_1.m0 and slave dma_0.s_nondma because the master has burstcount signal 1 bit wide, but the slave is 5 bit wide.
2015.07.07.23:28:00 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_1.m0 and slave dma_0.s_nondma because the master has writedata signal 32 bit wide, but the slave is 512 bit wide.
2015.07.07.23:28:00 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_1.m0 and slave dma_0.s_nondma because the master has address signal 16 bit wide, but the slave is 10 bit wide.
2015.07.07.23:28:00 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_1.m0 and slave dma_0.s_nondma because the master has byteenable signal 4 bit wide, but the slave is 64 bit wide.
2015.07.07.23:28:00 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_1.m0 and slave dma_0.s_nondma because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2015.07.07.23:28:00 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_0.m0 and slave dma_0.csr because the master has readdata signal 32 bit wide, but the slave is 64 bit wide.
2015.07.07.23:28:00 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_0.m0 and slave dma_0.csr because the master has writedata signal 32 bit wide, but the slave is 64 bit wide.
2015.07.07.23:28:00 Info: Interconnect is inserted between master clock_cross_pcie_to_dma_0.m0 and slave dma_0.csr because the master has byteenable signal 4 bit wide, but the slave is 8 bit wide.
2015.07.07.23:28:01 Info: Interconnect is inserted between master clock_cross_pcie_to_cpld.m0 and slave cpld_bridge_0.cpld_mm_in because the master has readdata signal 32 bit wide, but the slave is 16 bit wide.
2015.07.07.23:28:01 Info: Interconnect is inserted between master clock_cross_pcie_to_cpld.m0 and slave cpld_bridge_0.cpld_mm_in because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide.
2015.07.07.23:28:01 Info: Interconnect is inserted between master clock_cross_pcie_to_cpld.m0 and slave cpld_bridge_0.cpld_mm_in because the master has writedata signal 32 bit wide, but the slave is 16 bit wide.
2015.07.07.23:28:01 Info: Interconnect is inserted between master clock_cross_pcie_to_cpld.m0 and slave cpld_bridge_0.cpld_mm_in because the master has address signal 3 bit wide, but the slave is 0 bit wide.
2015.07.07.23:28:01 Info: Interconnect is inserted between master clock_cross_pcie_to_cpld.m0 and slave cpld_bridge_0.cpld_mm_in because the master has byteenable signal 4 bit wide, but the slave is 0 bit wide.
2015.07.07.23:28:01 Info: Interconnect is inserted between master clock_cross_pcie_to_cpld.m0 and slave cpld_bridge_0.cpld_mm_in because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2015.07.07.23:28:06 Info: board: "system" instantiated board "board"
2015.07.07.23:28:06 Info: Interconnect is inserted between master kernel_cra.m0 and slave cra_root.cra_slave because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide.
2015.07.07.23:28:06 Info: Interconnect is inserted between master kernel_cra.m0 and slave cra_root.cra_slave because the master has address signal 30 bit wide, but the slave is 6 bit wide.
2015.07.07.23:28:06 Info: Interconnect is inserted between master kernel_cra.m0 and slave cra_root.cra_slave because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2015.07.07.23:28:06 Info: kernel_system: "system" instantiated kernel_system "kernel_system"
2015.07.07.23:28:06 Info: mm_interconnect_1: "system" instantiated altera_mm_interconnect "mm_interconnect_1"
2015.07.07.23:28:06 Info: mm_interconnect_2: "system" instantiated altera_mm_interconnect "mm_interconnect_2"
2015.07.07.23:28:06 Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper"
2015.07.07.23:28:06 Info: rst_controller: "system" instantiated altera_reset_controller "rst_controller"
2015.07.07.23:28:06 Info: pipe_stage_ddr3b_dimm: "board" instantiated altera_avalon_mm_bridge "pipe_stage_ddr3b_dimm"
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_pcs.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_pcs.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_pcs_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_pcs_ch.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_pma.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_xcvr.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_reconfig_bundle_to_ip.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_ip.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_reconfig_bundle_merger.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_merger.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_rx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_rx_pma.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_tx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_tx_pma.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_tx_pma_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_tx_pma_ch.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_h.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_xcvr_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_avmm_csr.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_xcvr_avmm_dcd.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_avmm_dcd.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_xcvr_avmm.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_avmm.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_xcvr_data_adapter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_data_adapter.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_xcvr_native.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_native.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_xcvr_plls.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_xcvr_plls.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_10g_rx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_10g_rx_pcs_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_10g_tx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_10g_tx_pcs_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_8g_rx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_8g_rx_pcs_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_8g_tx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_8g_tx_pcs_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_8g_pcs_aggregate_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_8g_pcs_aggregate_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_common_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_common_pcs_pma_interface_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_common_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_common_pld_pcs_interface_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_pipe_gen1_2_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_pipe_gen1_2_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_pipe_gen3_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_pipe_gen3_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_rx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_rx_pcs_pma_interface_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_rx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_rx_pld_pcs_interface_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_tx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_tx_pcs_pma_interface_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_hssi_tx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/rbc/sv_hssi_tx_pld_pcs_interface_rbc.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_xcvr_emsip_adapter.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/sv/sv_xcvr_emsip_adapter.sv
2015.07.07.23:28:06 Info: pcie: add_fileset_file ./sv_xcvr_pipe_native.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/sv/sv_xcvr_pipe_native.sv
2015.07.07.23:28:06 Info: pcie: "board" instantiated altera_pcie_sv_hip_avmm "pcie"
2015.07.07.23:28:07 Info: ddr3a: "board" instantiated altera_mem_if_ddr3_emif "ddr3a"
2015.07.07.23:28:07 Info: ddr3b: "board" instantiated altera_mem_if_ddr3_emif "ddr3b"
2015.07.07.23:28:07 Info: clock_cross_dma_to_pcie: "board" instantiated altera_avalon_mm_clock_crossing_bridge "clock_cross_dma_to_pcie"
2015.07.07.23:28:07 Info: temperature_pll: "board" instantiated altera_pll "temperature_pll"
2015.07.07.23:28:07 Info: temperature_0: "board" instantiated temperature "temperature_0"
2015.07.07.23:28:08 Info: Inserting clock-crossing logic between cmd_demux.src2 and cmd_mux_002.sink0
2015.07.07.23:28:08 Info: Inserting clock-crossing logic between rsp_demux_002.src0 and rsp_mux.sink2
2015.07.07.23:28:09 Info: kernel_clk_gen: "board" instantiated acl_kernel_clk "kernel_clk_gen"
2015.07.07.23:28:09 Info: Interconnect is inserted between master address_span_extender_0.expanded_master and slave kernel_cra.s0 because they have different clock source.
2015.07.07.23:28:09 Info: Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0
2015.07.07.23:28:09 Info: Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0
2015.07.07.23:28:11 Info: kernel_interface: "board" instantiated kernel_interface "kernel_interface"
2015.07.07.23:28:13 Info: dma_0: "board" instantiated acl_dma "dma_0"
2015.07.07.23:28:13 Info: Interconnect is inserted between master pipe_stage_presplitter.m0 and slave mem_splitter_0.s because the master has address signal 33 bit wide, but the slave is 27 bit wide.
2015.07.07.23:28:13 Info: Interconnect is inserted between master pipe_stage_presplitter.m0 and slave mem_splitter_0.s because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
2015.07.07.23:28:13 Info: memory_bank_divider_0: "board" instantiated acl_memory_bank_divider "memory_bank_divider_0"
2015.07.07.23:28:13 Info: por_reset_counter: "board" instantiated sw_reset "por_reset_counter"
2015.07.07.23:28:13 Info: uniphy_status_0: "board" instantiated uniphy_status "uniphy_status_0"
2015.07.07.23:28:13 Info: version_id_0: "board" instantiated version_id "version_id_0"
2015.07.07.23:28:13 Info: no_reset_for_uniphy: "board" instantiated no_reset "no_reset_for_uniphy"
2015.07.07.23:28:13 Info: onchip_ram: Starting RTL generation for module 'system_board_onchip_ram'
2015.07.07.23:28:13 Info: onchip_ram: Generation command is [exec /root/altera/15.0/quartus/linux64/perl/bin/perl -I /root/altera/15.0/quartus/linux64/perl/lib -I /root/altera/15.0/quartus/sopc_builder/bin/europa -I /root/altera/15.0/quartus/sopc_builder/bin/perl_lib -I /root/altera/15.0/quartus/sopc_builder/bin -I /root/altera/15.0/quartus/../ip/altera/sopc_builder_ip/common -I /root/altera/15.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /root/altera/15.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=system_board_onchip_ram --dir=/tmp/alt6623_6609210147268013060.dir/0006_onchip_ram_gen/ --quartus_dir=/root/altera/15.0/quartus --verilog --config=/tmp/alt6623_6609210147268013060.dir/0006_onchip_ram_gen//system_board_onchip_ram_component_configuration.pl --do_build_sim=0 ]
2015.07.07.23:28:13 Info: onchip_ram: Done RTL generation for module 'system_board_onchip_ram'
2015.07.07.23:28:13 Info: onchip_ram: "board" instantiated altera_avalon_onchip_memory2 "onchip_ram"
2015.07.07.23:28:13 Info: cpld_bridge_0: "board" instantiated cpld_bridge "cpld_bridge_0"
2015.07.07.23:28:13 Info: mm_interconnect_0: "board" instantiated altera_mm_interconnect "mm_interconnect_0"
2015.07.07.23:28:13 Info: mm_interconnect_1: "board" instantiated altera_mm_interconnect "mm_interconnect_1"
2015.07.07.23:28:14 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:14 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:14 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:14 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:14 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:14 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:14 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:15 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:15 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:15 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:15 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:15 Info: mm_interconnect_2: "board" instantiated altera_mm_interconnect "mm_interconnect_2"
2015.07.07.23:28:16 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:16 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:16 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:16 Info: mm_interconnect_3: "board" instantiated altera_mm_interconnect "mm_interconnect_3"
2015.07.07.23:28:16 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:16 Info: mm_interconnect_4: "board" instantiated altera_mm_interconnect "mm_interconnect_4"
2015.07.07.23:28:16 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:17 Info: mm_interconnect_5: "board" instantiated altera_mm_interconnect "mm_interconnect_5"
2015.07.07.23:28:17 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:17 Info: mm_interconnect_6: "board" instantiated altera_mm_interconnect "mm_interconnect_6"
2015.07.07.23:28:17 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:17 Info: mm_interconnect_7: "board" instantiated altera_mm_interconnect "mm_interconnect_7"
2015.07.07.23:28:17 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:17 Info: mm_interconnect_8: "board" instantiated altera_mm_interconnect "mm_interconnect_8"
2015.07.07.23:28:17 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:18 Info: mm_interconnect_9: "board" instantiated altera_mm_interconnect "mm_interconnect_9"
2015.07.07.23:28:18 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:18 Info: mm_interconnect_10: "board" instantiated altera_mm_interconnect "mm_interconnect_10"
2015.07.07.23:28:18 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
2015.07.07.23:28:18 Info: mm_interconnect_11: "board" instantiated altera_mm_interconnect "mm_interconnect_11"
2015.07.07.23:28:18 Info: irq_mapper: "board" instantiated altera_irq_mapper "irq_mapper"
2015.07.07.23:28:18 Info: irq_mapper_001: "board" instantiated altera_irq_mapper "irq_mapper_001"
2015.07.07.23:28:18 Info: irq_synchronizer: "board" instantiated altera_irq_clock_crosser "irq_synchronizer"
2015.07.07.23:28:18 Info: acl_internal_snoop: "kernel_system" instantiated altera_avalon_st_adapter "acl_internal_snoop"
2015.07.07.23:28:18 Info: avs_findK_cra_cra_ring: "kernel_system" instantiated cra_ring_node "avs_findK_cra_cra_ring"
2015.07.07.23:28:18 Info: cra_root: "kernel_system" instantiated cra_ring_root "cra_root"
2015.07.07.23:28:18 Info: kernel_gpu_opencl_altera_v2_system: "kernel_system" instantiated kernel_gpu_opencl_altera_v2_system "kernel_gpu_opencl_altera_v2_system"
2015.07.07.23:28:18 Info: kernel_irq: "kernel_system" instantiated altera_irq_bridge "kernel_irq"
2015.07.07.23:28:18 Info: mm_interconnect_2: "kernel_system" instantiated altera_mm_interconnect "mm_interconnect_2"
2015.07.07.23:28:18 Info: kernel_system_kernel_mem0_translator: "mm_interconnect_1" instantiated altera_merlin_master_translator "kernel_system_kernel_mem0_translator"
2015.07.07.23:28:18 Info: board_kernel_mem0_translator: "mm_interconnect_1" instantiated altera_merlin_slave_translator "board_kernel_mem0_translator"
2015.07.07.23:28:19 Info: pll0: "ddr3a" instantiated altera_mem_if_ddr3_pll "pll0"
2015.07.07.23:28:19 Info: p0: Generating clock pair generator
2015.07.07.23:28:24 Info: p0: Generating system_board_ddr3a_p0_altdqdqs
2015.07.07.23:28:36 Info: p0:
2015.07.07.23:28:36 Info: p0: *****************************
2015.07.07.23:28:36 Info: p0:
2015.07.07.23:28:36 Info: p0: Remember to run the system_board_ddr3a_p0_pin_assignments.tcl
2015.07.07.23:28:36 Info: p0: script after running Synthesis and before Fitting.
2015.07.07.23:28:36 Info: p0:
2015.07.07.23:28:36 Info: p0: *****************************
2015.07.07.23:28:36 Info: p0:
2015.07.07.23:28:36 Info: p0: "ddr3a" instantiated altera_mem_if_ddr3_phy_core "p0"
2015.07.07.23:28:36 Info: m0: "ddr3a" instantiated altera_mem_if_ddr3_afi_mux "m0"
ERROR: Cannot find sequencer/sequencer.elf
2015.07.07.23:28:41 Error: s0: Cannot find sequencer/sequencer.elf
2015.07.07.23:28:41 Error: s0: An error occurred
while executing
"error "An error occurred""
(procedure "_error" line 8)
invoked from within
"_error "Cannot find $seq_file""
("if" then script line 2)
invoked from within
"if {[file exists $seq_file] == 0} {
_error "Cannot find $seq_file"
}"
(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
("if" then script line 2)
invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
(procedure "generate_qsys_sequencer_sw" line 904)
invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."
invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."
("if" else script line 2)
invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
(procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
set file_name [file tail $genera..."
(procedure "generate_synth" line 8)
invoked from within
"generate_synth system_board_ddr3a_s0"
2015.07.07.23:28:41 Info: s0: "ddr3a" instantiated altera_mem_if_ddr3_qseq "s0"
2015.07.07.23:28:41 Error: Generation stopped, 303 or more modules remaining
2015.07.07.23:28:41 Info: system: Done "system" with 140 modules, 236 files