LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;


ENTITY merg_hw_module IS
    PORT (
        -- SYSTEM PORT
        mhm_clk            : IN STD_LOGIC := '0';
        mhm_SendToSortDATA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
        -- from merg_state_machine_module PORT
        mhm_start_en : IN STD_LOGIC;
        mhm_bound_en : IN STD_LOGIC;
        mhm_pair_ubound : IN INTEGER;
        mhm_rd1_ubound : IN INTEGER;
        mhm_rd2_ubound : IN INTEGER;
        mhm_rd2_initval : IN INTEGER;
        mhm_SendDataStart  : IN STD_LOGIC := '0';
        -- to merg_state_machine_module PORT
        mhm_bound_done : OUT STD_LOGIC;
        mhm_state_done : OUT STD_LOGIC;
        -- ports to mem1
        ToM1AdrA : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
        ToM1AdrB : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
        ToM1DataA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
        ToM1DataB : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
        ToM1RdenA : OUT STD_LOGIC := '0';
        ToM1RdenB : OUT STD_LOGIC := '0';
        ToM1WrenA : OUT STD_LOGIC := '0';
        ToM1WrenB : OUT STD_LOGIC := '0';
        FromM1QA : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        FromM1QB : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        -- ports to mem2
        ToM2AdrA : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
        ToM2AdrB : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
        ToM2DataA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
        ToM2DataB : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
        ToM2RdenA : OUT STD_LOGIC := '0';
        ToM2RdenB : OUT STD_LOGIC := '0';
        ToM2WrenA : OUT STD_LOGIC := '0';
        ToM2WrenB : OUT STD_LOGIC := '0';
        FromM2QA : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        FromM2QB : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
    );
END ENTITY;


ARCHITECTURE rt OF merg_hw_module IS


BEGIN
merg: PROCESS (mhm_clk) 
VARIABLE rd1 : INTEGER := 0;
VARIABLE rd2 : INTEGER := 0;
VARIABLE ele_num : INTEGER;
VARIABLE full_rd1 : INTEGER;
VARIABLE full_rd2 : INTEGER; 
VARIABLE wr : INTEGER := 0;
VARIABLE wr2 : INTEGER := 0;
VARIABLE pair : INTEGER := 0;
BEGIN
    IF (RISING_EDGE(mhm_clk)) THEN
        ------------------------------------------------
        -- assign the parameter value
        ------------------------------------------------
        IF (mhm_bound_en = '1') THEN
            rd1 := 0;
            rd2 := mhm_rd2_initval;
            wr  := 0;
            wr2 := 0;
            rd_delay := 0;
            pair := 0;
            mhm_bound_done <= '1';
        ELSE
            mhm_bound_done <= '0';
        END IF;
        ------------------------------------------------
        -- Mrg sort from RAM1 to RAM 2
        --
        ------------------------------------------------
        IF (mhm_start_en = '1') THEN
            IF (pair < mhm_pair_ubound) THEN
                IF (rd1 < mhm_rd1_ubound) AND (rd2 < mhm_rd2_ubound) THEN
                    full_rd1 := rd1 + ele_num * pair;
                    full_rd2 := rd2 + ele_num * pair;
                    ToM1RdenA <= '1';
                    ToM1RdenB <= '1';
                    ToM1AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(full_rd1, 7));
                    ToM1AdrB <= STD_LOGIC_VECTOR (TO_UNSIGNED(full_rd2, 7));
                    IF (rd_delay < 3) THEN
                        rd_delay := rd_delay + 1;
                    ELSE
                        IF (FromM1QA = FromM1QB) THEN
                            ToM2WrenA <= '1';
                            ToM2AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(wr, 7));
                            ToM2DataA <= FromM1QA;
                            rd1 := rd1 + 1;
                            wr := wr + 1;
                            rd_delay := 0;
                        ELSIF (FromM1QA < FromM1QB) THEN
                            ToM2WrenA <= '1';
                            ToM2AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(wr, 7));
                            ToM2DataA <= FromM1QA;
                            rd1 := rd1 + 1;
                            wr := wr + 1;
                            rd_delay := 0;
                        ELSIF (FromM1QA > FromM1QB) THEN
                            ToM2WrenA <= '1';
                            ToM2AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(wr, 7));
                            ToM2DataA <= FromM1QB;
                            rd2 := rd2 + 1;
                            wr := wr + 1;
                            rd_delay := 0;
                        END IF; -- end for if elsif
                    END IF; -- end for rd_delay
                ELSIF (rd1 < mhm_rd1_ubound) OR (rd2 < mhm_rd2_ubound) THEN
                    full_rd1 := rd1 + ele_num * pair;
                    full_rd2 := rd2 + ele_num * pair;
                    ToM1RdenA <= '1';
                    ToM1RdenB <= '1';
                    ToM1AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(full_rd1, 7));
                    ToM1AdrB <= STD_LOGIC_VECTOR (TO_UNSIGNED(full_rd2, 7));
                    IF (rd_delay < 3) THEN
                        rd_delay := rd_delay + 1;
                    ELSE
                        IF (FromM1QA = FromM1QB) THEN
                            ToM2WrenA <= '1';
                            ToM2AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(wr, 7));
                            ToM2DataA <= FromM1QA;
                            rd1 := rd1 + 1;
                            wr := wr + 1;
                            rd_delay := 0;
                        ELSIF (FromM1QA < FromM1QB) THEN
                            ToM2WrenA <= '1';
                            ToM2AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(wr, 7));
                            ToM2DataA <= FromM1QB;
                            rd2 := rd2 + 1;
                            wr := wr + 1;
                            rd_delay := 0;
                        ELSIF (FromM1QA > FromM1QB) THEN
                            ToM2WrenA <= '1';
                            ToM2AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(wr, 7));
                            ToM2DataA <= FromM1QA;
                            rd1 := rd1 + 1;
                            wr := wr + 1;
                            rd_delay := 0;
                        END IF; -- end for if elsif
                    END IF; -- end for rd_delay
                ELSE
                    pair := pair + 1;
                    rd1 := 0;
                    rd2 := mhm_rd2_initval;
                END IF;
            ELSE -- current finish the sort, send data back to m1
                IF (rd1 < 128) THEN
                    ToM2RdenB <= '1';
                    ToM2AdrB <= STD_LOGIC_VECTOR (TO_UNSIGNED(rd1, 7));
                    rd1 := rd1 + 1;
                END IF; -- end for rd1
                IF (rd_delay < 3) THEN
                    rd_delay := rd_delay + 1;
                ELSE
                    IF (wr2 < 128) THEN
                        ToM1WrenA <= '1';
                        ToM1RdenA <= '0';
                        ToM1AdrA <= STD_LOGIC_VECTOR(TO_UNSIGNED(wr2, 7));
                        ToM1DataA <= FromM2QA;
                    ELSE
                        rd_delay := 0;
                        rd1 := 0;
                        ToM1WrenA <= '0';
                        mhm_state_done <= '1';
                    END IF;
                END IF;
            END IF;
        ELSE
            mhm_state_done <= '0';
        END IF;
        ---------------------------------------------
        --         send data to srt
        --  currently, sorted data is stored at m2
        ---------------------------------------------
        IF (mhm_SendDataStart = '1') THEN
            IF (rd1 < 128) THEN
                ToM1RdenB <= '1';
                ToM1AdrB <= STD_LOGIC_VECTOR (TO_UNSIGNED(rd1, 7));
            END IF; -- end for rd1
            IF (rd_delay < 3) THEN
                rd_delay := rd_delay + 1;
            ELSE
                mhm_SendToSortData <= FromM1QB;
            END IF; -- end for rd_delay
        END IF; -- end for mc_SendToSortEn
    END IF;
END PROCESS;
END ARCHITECTURE;