module alarm_clock( 
	input  clock,
  	input  [3:0]  KEY,
  	output  reg [6:0]  HEX0, HEX1, HEX2,HEX3,
  	output  reg [10:0]  LEDR, 
  	input [1:0] SW,
  	output reg dot);

//min1=0; min2=0; hr1=0; hr2=1;
reg [3:0]min1=0;
reg [3:0]min2=0;
reg [3:0]hr1=0;
reg [3:0]hr2=1;
reg [1:0]reset;
reg [6:0]number;
reg[3:0] cnt1=0;
reg[3:0] cnt2=0;
reg[3:0] cnt3=0;
reg[3:0] cnt4=1;
reg[3:0] store1;
reg[3:0] store2;
reg[3:0] store3;
reg[3:0] store4;
reg[5:0] sec;
reg stat=0;

reg [24:0] counter;
reg clk_out;
initial begin
clk_out=0;
end

always @(posedge clock)
begin
		if(counter==27000000)
		begin
			counter<=0;
		end
		else
		begin
			clk_out<=counter[24];
			dot=clk_out;
			counter=counter+1;
		end
	end

always @(posedge clk_out)
begin
			if(sec<59) sec=sec+1;
			else
			begin
			sec=0;
			if (min1 < 9) //minute1 < 9
			begin 
				min1 = min1 + 1; 
			end
			else
			begin
				min1 = 0;
				if ( min2 < 5 )//minute2 < 5
				begin	
					min2 = min2 + 1; 
				end
				else 	
				begin 	min2 = 0;
					if ( hr2 == 2 & hr1 == 3 ) //hour2==2 & hour1==3
					begin	
						hr1 = 0;	hr2 = 0;	
					end
					else 
					if ( hr1 < 9 )//hour1 < 9
					begin	
						hr1 = hr1 + 1; 
					end
						else	
							begin	
								hr1 = 0;
								if ( hr2 < 2 )//hour2 < 2
									begin 
									hr2 = hr2 + 1; 
									end
								else 
									begin 
									hr2 = 0; 
									end
							end
				end
			end
			end
end

always@(posedge clock)
begin
if(SW[0]==1)
	begin

	HEX0<=display(cnt1);
	HEX1<=display(cnt2);
	HEX2<=display(cnt3);
	HEX3<=display(cnt4);
	
	if(KEY[0]==0&&stat==1)
	begin
		stat=0;	
			if(cnt1<9)
			begin
				cnt1=cnt1+1;
			end
			else //if(cnt1==9)
			begin
				cnt1=0;
			end
		end
	else if(KEY[1]==0&&stat==1)
	begin
		stat=0;
		if(cnt2<5)
		begin
		cnt2=cnt2+1;
		end
		else //if(cnt2==9)
		begin
		cnt2=0;
		end
	end
	else if(KEY[2]==0&&stat==1)
	begin	
		stat=0;
		if(cnt3<9)
		begin
		cnt3=cnt3+1;
		if(cnt4==2)
		begin
		 if(cnt3>3) cnt3=0;
		 else cnt3=cnt3;
		end
		end
		else// if(cnt3==9)
		begin
		cnt3=0;
		end
	end
	else if(KEY[3]==0&&stat==1)
	begin	
		stat=0;
		if(cnt4<2)
		begin
		cnt4=cnt4+1;
		end
		else //if(cnt4==9)
		begin
		cnt4=0;
		end
	end
	else if(KEY[0]==1&&KEY[1]==1&&KEY[2]==1&&KEY[3]==1)
	begin
		cnt1=cnt1;
		cnt2=cnt2;
		cnt3=cnt3;
		cnt4=cnt4;
		stat=1;
	end
end

else
begin

HEX0<=display(min1);
HEX1<=display(min2);
HEX2<=display(hr1);
HEX3<=display(hr2);
if(SW[1]==1)
begin
	if(min1==cnt1&&min2==cnt2&&hr1==cnt3&&hr2==cnt4)
	LEDR<=10'b1111111111;
	else
	LEDR<=10'b0000000000;
end
else
	LEDR<=10'b0000000000;
end
end


function [6:0]display;
input [3:0]key;
case(key)   //gfedcba
0: display=7'b1000000;
1: display=7'b1111001;
2: display=7'b0100100;
3: display=7'b0110000;
4: display=7'b0011001;
5: display=7'b0010010;
6: display=7'b0000010;
7: display=7'b1111000;
8: display=7'b0000000;
9: display=7'b0010000;
10: display=7'b1111110;
default: display=7'b0000001;
endcase
endfunction	

endmodule