Code: VGA_Controller u1 ( // Host Side .iCursor_RGB_EN(4'b0111), .oAddress(mVGA_ADDR), .oCoord_X(Coord_X), .oCoord_Y(Coord_Y), .iRed(mVGA_R), .iGreen(mVGA_G), .iBlue(mVGA_B), // VGA Side .oVGA_R(VGA_R), .oVGA_G(VGA_G), .oVGA_B(VGA_B), .oVGA_H_SYNC(VGA_HS), .oVGA_V_SYNC(VGA_VS), .oVGA_SYNC(VGA_SYNC), .oVGA_BLANK(VGA_BLANK), // Control Signal .iCLK(VGA_CTRL_CLK), .iRST_N(DLY_RST_0) ); Reset_Delay u2 ( .iCLK(CLOCK_50), .iRST(KEY[0]), .oRST_0(DLY_RST_0), .oRST_1(DLY_RST_1), .oRST_2(DLY_RST_2) ); //camera module CCD_Capture u3 ( .oDATA(mCCD_DATA), .oDVAL(mCCD_DVAL), .oX_Cont(X_Cont), .oY_Cont(Y_Cont), .oFrame_Cont(Frame_Cont), .iDATA(rCCD_DATA), .iFVAL(rCCD_FVAL), .iLVAL(rCCD_LVAL), .iSTART(startCAM), .iEND(stopCAM), .iCLK(CCD_PIXCLK), .iRST(DLY_RST_1)); //convert raw data to RGB RAW2RGB u4 ( .oRed(mCCD_R), .oGreen(mCCD_G), .oBlue(mCCD_B), .oDVAL(mCCD_DVAL_d), .iX_Cont(X_Cont), .iY_Cont(Y_Cont), .iDATA(mCCD_DATA), .iDVAL(mCCD_DVAL), .iCLK(CCD_PIXCLK), .iRST(DLY_RST_1)); SEG7_LUT_8 u5 ( .oSEG0(HEX0),.oSEG1(HEX1), .oSEG2(HEX2),.oSEG3(HEX3), .oSEG4(HEX4),.oSEG5(HEX5), .oSEG6(HEX6),.oSEG7(HEX7), .iDIG({16'h0000,SADTemp}) ); //.iDIG({Frame_Cont}) ); // //this is completely differnet now // the ram is partitioned between two images //specifically, image 1 is in the first 640*512 block // image 2 is offset by h100000 (~the offset required // for the blanking pixel clock cycles) reg [31:0] pixcnt; reg FRMA; always @(posedge CCD_PIXCLK) begin if (~DLY_RST_1) begin pixcnt<=0; FRMA<=0; end else if (sCCD_DVAL) begin if (pixcnt < ((640*512)-1)) pixcnt<=pixcnt+1; else begin pixcnt<=0; FRMA<=~FRMA; end end end Sdram_Control_4Port u6 ( // HOST Side .REF_CLK(CLOCK_50), .RESET_N(1'b1), //never reset // FIFO Write Side 1 (image 1) .WR1_DATA({6'b000000,sCCD_BW[9:0]}), .WR1(sCCD_DVAL & FRMA), //.WR1(sCCD_DVAL), .WR1_ADDR(0), .WR1_MAX_ADDR(640*512), .WR1_LENGTH(9'h100), //256 .WR1_LOAD(!DLY_RST_0), .WR1_CLK(CCD_PIXCLK), // FIFO Write Side 2 (image 2) .WR2_DATA({6'h0,sCCD_BW[9:0]}), .WR2(sCCD_DVAL & ~FRMA), .WR2_ADDR(22'h100000), .WR2_MAX_ADDR(22'h100000+640*512), .WR2_LENGTH(9'h100), .WR2_LOAD(!DLY_RST_0), .WR2_CLK(CCD_PIXCLK), // FIFO Read Side 1 .RD1_DATA(Read_DATA1), .RD1(SDRAM_READ_LOGIC), //.RD1(Read), //.RD1() .RD1_ADDR(640*16), //16 bit offset is for the differing resolutions .RD1_MAX_ADDR(640*496), .RD1_LENGTH(9'h100), .RD1_LOAD(!DLY_RST_0), .RD1_CLK(SDRAM_READ_CLOCK), //.RD1_CLK(VGA_CTRL_CLK) //.RD1_CLK() // FIFO Read Side 2 .RD2_DATA(Read_DATA2), .RD2(SDRAM_READ_LOGIC), .RD2_ADDR(22'h100000+640*16), .RD2_MAX_ADDR(22'h100000+640*496), .RD2_LENGTH(9'h100), .RD2_LOAD(!DLY_RST_0), .RD2_CLK(SDRAM_READ_CLOCK), // SDRAM Side .SA(DRAM_ADDR), .BA({DRAM_BA_1,DRAM_BA_0}), .CS_N(DRAM_CS_N), .CKE(DRAM_CKE), .RAS_N(DRAM_RAS_N), .CAS_N(DRAM_CAS_N), .WE_N(DRAM_WE_N), .DQ(DRAM_DQ), .DQM({DRAM_UDQM,DRAM_LDQM}), .SDR_CLK(DRAM_CLK) ); //configures the I2C registers on the camera (gain, etc.) //modified explosure to higher value I2C_CCD_Config u7 ( // Host Side .iCLK(CLOCK_50), .iRST_N(KEY[1]), .iExposure(SW[9:0]), // I2C Side .I2C_SCLK(CCD_SCLK), .I2C_SDAT(CCD_SDAT) ); //modified to convert to black and white Mirror_Col u8 ( // Input Side .iCCD_R(mCCD_R), .iCCD_G(mCCD_G), .iCCD_B(mCCD_B), .iCCD_DVAL(mCCD_DVAL_d), .iCCD_PIXCLK(CCD_PIXCLK), .iRST_N(DLY_RST_1), // Output Side .oCCD_BW(sCCD_BW), .oCCD_DVAL(sCCD_DVAL), //.oLED(LEDR) ); wire [17:0] VGASRAM_ADDR; wire [15:0] VGASRAM_DATA; //performs block correlation and generates edges sobel u9 ( .iReset(reset), .iClock(CLOCK_50), .oLED(LEDR), //the images from the SDRAM .oSDRAM_READ_CLOCK(SDRAM_READ_CLOCK), //data clock on the sdram (each cycle gets a new word) .oSDRAM_READ_LOGIC(SDRAM_READ_LOGIC), //set high when data is wanted .iSDRAM_IMAGE1(Read_DATA1), //data from image 1 .iSDRAM_IMAGE2(Read_DATA2), //data from image 2 //the output to the VGA .oVGASRAM_ADDR(VGASRAM_ADDR), //address of VGA output SRAM (320x240) .oVGASRAM_DATA(VGASRAM_DATA), //data for " " .iVGA_OK_TO_WRITE(VGA_OK_TO_WRITE), //signal indicating it is OK to write to the SRAM .iVGA_CTRL_CLK(VGA_CTRL_CLK), .oStartEdgeDetect(startEdgeDetect), //ready signal for VGA .isw(SW[9:0]) //threshold values ); wire VGA_OK_TO_WRITE; assign VGA_OK_TO_WRITE = (~VGA_VS | ~VGA_HS) & (~reset); //this will go high during blanking reg lock; always @ (posedge VGA_CTRL_CLK) begin if (reset) //synch reset assumes KEY0 is held down 1/60 second begin //clear the screen addr_reg <= {Coord_X[9:1],Coord_Y[9:1]} ; // [19:0] we <= 1'b0; //write some memory data_reg <= 16'h0000; //write all zeros (black) led <= 8'b11111111; end //modify display during sync and edge calculation is active //data from sobel edge detection else if (VGA_OK_TO_WRITE & startEdgeDetect) begin addr_reg <= VGASRAM_ADDR; lock <= 1'b1; data_reg <= VGASRAM_DATA; we <= 1'b0; led <= 8'b00001111; end //show display when not blanking, //which implies we=1 (not enabled); and use VGA module address else if (~VGA_OK_TO_WRITE) begin we <= 1'b1; addr_reg <= {Coord_X[9:1],Coord_Y[9:1]} ; lock <= 1'b0; end end endmodule