// Copyright (C) 2016  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Intel and sold by Intel or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "04/11/2018 10:00:32"
                                                                                
// Verilog Test Bench template for design : imuc_v3
// 
// Simulation tool : ModelSim-Altera (Verilog)
// 

`timescale 1ns/100ps
module imuc_v3_vlg_tst();
// constants                                           
// general purpose registers
parameter SYSCLK_PERIOD = 40.690104; // 24,576MHz
//parameter SYSCLK_PERIOD = 4
reg eachvec;
// test vector input registers
reg clk_clk;
reg epcs_fc_data0 = 0;
reg extsync_syncin = 0;
reg [13:0] gyro_3axis_adc_x = 0;
reg [13:0] gyro_3axis_adc_y = 0;
reg [13:0] gyro_3axis_adc_z = 0;
reg reset_reset_n = 0;
reg sled_din = 0;
reg uart0_rxd = 1'b1;
// wires                                               
wire de;
wire epcs_fc_dclk;
wire epcs_fc_sce;
wire epcs_fc_sdo;
wire gyro_3axis_clk_adc_x;
wire gyro_3axis_clk_adc_y;
wire gyro_3axis_clk_adc_z;
wire gyro_3axis_clk_dac_x;
wire gyro_3axis_clk_dac_y;
wire gyro_3axis_clk_dac_z;
wire [13:0]  gyro_3axis_dac_x;
wire [13:0]  gyro_3axis_dac_y;
wire [13:0]  gyro_3axis_dac_z;
wire gyro_3axis_p_sync1;
wire gyro_3axis_p_sync2;
wire gyro_3axis_p_sync3;
wire re;
wire sled_cs_adc;
wire sled_cs_dac;
wire sled_cs_pot;
wire sled_dout;
wire sled_sclk_o;
wire uart0_txd;
wire wdog;


// assign statements (if any)                          

imuc_v3 i1 (
// port map - connection between master ports and signals/registers   
    .clk_clk(clk_clk),
    .de(de),
    .epcs_fc_data0(epcs_fc_data0),
    .epcs_fc_dclk(epcs_fc_dclk),
    .epcs_fc_sce(epcs_fc_sce),
    .epcs_fc_sdo(epcs_fc_sdo),
    .extsync_syncin(extsync_syncin),
    .gyro_3axis_adc_x(gyro_3axis_adc_x),
    .gyro_3axis_adc_y(gyro_3axis_adc_y),
    .gyro_3axis_adc_z(gyro_3axis_adc_z),
    .gyro_3axis_clk_adc_x(gyro_3axis_clk_adc_x),
    .gyro_3axis_clk_adc_y(gyro_3axis_clk_adc_y),
    .gyro_3axis_clk_adc_z(gyro_3axis_clk_adc_z),
    .gyro_3axis_clk_dac_x(gyro_3axis_clk_dac_x),
    .gyro_3axis_clk_dac_y(gyro_3axis_clk_dac_y),
    .gyro_3axis_clk_dac_z(gyro_3axis_clk_dac_z),
    .gyro_3axis_dac_x(gyro_3axis_dac_x),
    .gyro_3axis_dac_y(gyro_3axis_dac_y),
    .gyro_3axis_dac_z(gyro_3axis_dac_z),
    .gyro_3axis_p_sync1(gyro_3axis_p_sync1),
    .gyro_3axis_p_sync2(gyro_3axis_p_sync2),
    .gyro_3axis_p_sync3(gyro_3axis_p_sync3),
    .re(re),
    .reset_reset_n(reset_reset_n),
    .sled_cs_adc(sled_cs_adc),
    .sled_cs_dac(sled_cs_dac),
    .sled_cs_pot(sled_cs_pot),
    .sled_din(sled_din),
    .sled_dout(sled_dout),
    .sled_sclk_o(sled_sclk_o),
    .uart0_rxd(uart0_rxd),
    .uart0_txd(uart0_txd),
    .wdog(wdog)
);                                       
             
initial
begin
  #(SYSCLK_PERIOD * 20 ) reset_reset_n = 1'b1;
    clk_clk = 0;
end  
always #(SYSCLK_PERIOD / 2) clk_clk = ~clk_clk;

always @(posedge clk_clk) begin
#5 reset_reset_n = 1;
#50 reset_reset_n = 0;
#100 reset_reset_n = 1;
#25 reset_reset_n = 0;
#55 reset_reset_n = 1;

// just provide input stimus like #55 reset_reset_n = 1; shown above
/* epcs_fc_data0;
 extsync_syncin;
 [13:0] gyro_3axis_adc_x;
 [13:0] gyro_3axis_adc_y;
 [13:0] gyro_3axis_adc_z;
 sled_din;
 uart0_rxd ;
*/
end

                                      
endmodule