Info: ******************************************************************* Info: Running Quartus Prime IP Generation Tool Info: Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition Info: Processing started: Fri Nov 2 11:54:57 2018 Info: Command: quartus_ipgenerate pcie_example_design -c pcie_example_design --run_default_mode_op Info: Found 5 IP file(s) in the project. Info: IP file E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/pcie_example_design.qsys was found in the project. Info: IP file E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT.ip was found in the project. Info: IP file E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DK.ip was found in the project. Info: IP file E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS.ip was found in the project. Info: IP file E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_MEM.ip was found in the project. Info: Finished generating IP file(s) in the project. Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT). Info: Skipped generation of synthesis files for the Platform Designer IP file E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DK). Info: Skipped generation of synthesis files for the Platform Designer IP file E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DK.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS). Info: Skipped generation of synthesis files for the Platform Designer IP file E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_MEM). Info: Skipped generation of synthesis files for the Platform Designer IP file E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_MEM.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/pcie_example_design). Info: Skipped generation of synthesis files for the Platform Designer IP file E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/pcie_example_design.qsys based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Quartus Prime IP Generation Tool was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4750 megabytes Info: Processing ended: Fri Nov 2 11:55:09 2018 Info: Elapsed time: 00:00:12 Info: ******************************************************************* Info: Running Quartus Prime Synthesis Info: Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition Info: Processing started: Fri Nov 2 11:55:13 2018 Info: Command: quartus_syn --read_settings_files=on --write_settings_files=off pcie_example_design -c pcie_example_design Info: qis_default_flow_script.tcl version: #1 Info: Initializing Synthesis... Info: Project = "pcie_example_design" Info: Revision = "pcie_example_design" Info: Analyzing source files Warning (16124): Can't analyze file ip/pcie_example_design/pcie_example_design_DUT/altera_xcvr_native_a10_181/synth/rcfg_timing_db/pcie_example_design_DUT_hssi_common_pcs_pma_interface_rcfg_settings_wkfaq3y.json - no such file exists Warning (16124): Can't analyze file ip/pcie_example_design/pcie_example_design_DUT/altera_xcvr_native_a10_181/synth/rcfg_timing_db/pcie_example_design_DUT_hssi_common_pld_pcs_interface_rcfg_settings_wkfaq3y.json - no such file exists Warning (16124): Can't analyze file ip/pcie_example_design/pcie_example_design_DUT/altera_xcvr_native_a10_181/synth/rcfg_timing_db/pcie_example_design_DUT_hssi_rx_pcs_pma_interface_rcfg_settings_wkfaq3y.json - no such file exists Warning (16124): Can't analyze file ip/pcie_example_design/pcie_example_design_DUT/altera_xcvr_native_a10_181/synth/rcfg_timing_db/pcie_example_design_DUT_hssi_rx_pld_pcs_interface_rcfg_settings_wkfaq3y.json - no such file exists Warning (16124): Can't analyze file ip/pcie_example_design/pcie_example_design_DUT/altera_xcvr_native_a10_181/synth/rcfg_timing_db/pcie_example_design_DUT_hssi_tx_pcs_pma_interface_rcfg_settings_wkfaq3y.json - no such file exists Warning (16124): Can't analyze file ip/pcie_example_design/pcie_example_design_DUT/altera_xcvr_native_a10_181/synth/rcfg_timing_db/pcie_example_design_DUT_hssi_tx_pld_pcs_interface_rcfg_settings_wkfaq3y.json - no such file exists Warning (13228): Verilog HDL or VHDL warning at altpcie_tlp_inspector_monitor_a10.sv(368): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_tlp_inspector_monitor_a10.sv Line: 368 Warning (13228): Verilog HDL or VHDL warning at altpcie_tlp_inspector_monitor_a10.sv(426): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_tlp_inspector_monitor_a10.sv Line: 426 Warning (13228): Verilog HDL or VHDL warning at altpcie_tlp_inspector_monitor_a10.sv(608): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_tlp_inspector_monitor_a10.sv Line: 608 Warning (13228): Verilog HDL or VHDL warning at altpcie_tlp_inspector_monitor_a10.sv(684): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_tlp_inspector_monitor_a10.sv Line: 684 Warning (13228): Verilog HDL or VHDL warning at altpcie_tlp_inspector_monitor_a10.sv(813): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_tlp_inspector_monitor_a10.sv Line: 813 Warning (13228): Verilog HDL or VHDL warning at altpcieav_256_rp_app.sv(304): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_app.sv Line: 304 Warning (13228): Verilog HDL or VHDL warning at altpcieav_256_rp_app.sv(508): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_app.sv Line: 508 Warning (13228): Verilog HDL or VHDL warning at altpcieav_256_rp_app.sv(592): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_app.sv Line: 592 Warning (13228): Verilog HDL or VHDL warning at altpcieav_256_rp_hip_interface.sv(544): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_hip_interface.sv Line: 544 Warning (13228): Verilog HDL or VHDL warning at altpcieav_256_rp_txs.sv(252): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_txs.sv Line: 252 Warning (13468): Verilog HDL Expression warning at altpcieav_256_rp_rxm_rdwr.sv(553): truncated literal to match 16 bits File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_rxm_rdwr.sv Line: 553 Warning (13228): Verilog HDL or VHDL warning at altpcieav_256_rp_rxm.sv(265): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_rxm.sv Line: 265 Warning (13228): Verilog HDL or VHDL warning at ast2avmm_bridge_256_hwtcl.sv(436): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/ast2avmm_bridge_256_hwtcl.sv Line: 436 Info: Elaborating from top-level entity "pcie_example_design" Info (18235): Library search order is as follows: "altera_xcvr_native_a10_181; altera_pcie_a10_hip_181; altera_xcvr_fpll_a10_181; altera_xcvr_atx_pll_a10_181; pcie_example_design_DUT; altpcie_devkit_181; pcie_example_design_DK; ast2avmm_bridge_256_181; pcie_example_design_APPS; altera_avalon_onchip_memory2_181; pcie_example_design_MEM; altera_merlin_master_translator_181; altera_merlin_slave_translator_181; altera_merlin_master_agent_181; altera_merlin_slave_agent_181; altera_avalon_sc_fifo_181; altera_merlin_router_181; altera_merlin_burst_adapter_181; altera_merlin_demultiplexer_181; altera_merlin_multiplexer_181; altera_mm_interconnect_181; altera_irq_mapper_181; altera_reset_controller_181; pcie_example_design; ctp". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER. Warning (16735): Verilog HDL warning at altpcieav_256_rp_rxm.sv(150): actual bit length 5 differs from formal bit length 4 for port "CmdFifoUsedw_i" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_rxm.sv Line: 150 Warning (16735): Verilog HDL warning at altpcieav_256_rp_hip_interface.sv(316): actual bit length 4 differs from formal bit length 5 for port "fifo_count" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_hip_interface.sv Line: 316 Warning (16735): Verilog HDL warning at altpcieav_256_rp_hip_interface.sv(427): actual bit length 4 differs from formal bit length 5 for port "fifo_count" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_hip_interface.sv Line: 427 Warning (16735): Verilog HDL warning at altpcieav_256_rp_hip_interface.sv(456): actual bit length 4 differs from formal bit length 5 for port "fifo_count" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_hip_interface.sv Line: 456 Warning (16735): Verilog HDL warning at altpcieav_256_rp_app.sv(366): actual bit length 32 differs from formal bit length 2 for port "bus_master_en_vf_i" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_app.sv Line: 366 Warning (16735): Verilog HDL warning at altpcieav_256_rp_app.sv(589): actual bit length 4 differs from formal bit length 5 for port "fifo_count" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_APPS/ast2avmm_bridge_256_181/synth/altpcieav_256_rp_app.sv Line: 589 Warning (16753): Verilog HDL warning at pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v(2591): left shift count is greater than or equal to the width of the value File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v Line: 2591 Warning (16753): Verilog HDL warning at pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v(2589): left shift count is greater than or equal to the width of the value File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v Line: 2589 Warning (16753): Verilog HDL warning at pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v(2590): left shift count is greater than or equal to the width of the value File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v Line: 2590 Warning (16753): Verilog HDL warning at pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v(2601): left shift count is greater than or equal to the width of the value File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v Line: 2601 Warning (16788): Net "clk500_out" does not have a driver at altpcie_a10_hip_pipen1b.v(1338) File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_a10_hip_pipen1b.v Line: 1338 Warning (16735): Verilog HDL warning at pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v(4353): actual bit length 33 differs from formal bit length 32 for port "csebaddr" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v Line: 4353 Warning (16735): Verilog HDL warning at pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v(4354): actual bit length 5 differs from formal bit length 4 for port "csebaddrparity" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v Line: 4354 Warning (13469): Verilog HDL assignment warning at pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v(4551): truncated value with size 4 to match size of target (1) File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v Line: 4551 Warning (13469): Verilog HDL assignment warning at pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v(4552): truncated value with size 4 to match size of target (1) File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/pcie_example_design_DUT_altera_pcie_a10_hip_181_utnlmty.v Line: 4552 Info: Found 175 design entities Info: There are 300 partitions after elaboration. Info: Creating instance-specific data models and dissolving soft partitions Info (18299): Expanding entity and wildcard assignments. Info (18300): Expanded entity and wildcard assignments. Elapsed time: 00:00:00 Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following LCELL buffer node(s): Warning (14320): Synthesized away node "dut|dut|altpcie_a10_hip_pipen1b|skp_pat_det_g3_ps[7]" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_a10_hip_pipen1b.v Line: 3393 Warning (14320): Synthesized away node "dut|dut|altpcie_a10_hip_pipen1b|skp_pat_det_g3_ps[6]" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_a10_hip_pipen1b.v Line: 3393 Warning (14320): Synthesized away node "dut|dut|altpcie_a10_hip_pipen1b|skp_pat_det_g3_ps[5]" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_a10_hip_pipen1b.v Line: 3393 Warning (14320): Synthesized away node "dut|dut|altpcie_a10_hip_pipen1b|skp_pat_det_g3_ps[4]" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_a10_hip_pipen1b.v Line: 3393 Warning (14320): Synthesized away node "dut|dut|altpcie_a10_hip_pipen1b|skp_pat_det_g3_ps[3]" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_a10_hip_pipen1b.v Line: 3393 Warning (14320): Synthesized away node "dut|dut|altpcie_a10_hip_pipen1b|skp_pat_det_g3_ps[2]" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_a10_hip_pipen1b.v Line: 3393 Warning (14320): Synthesized away node "dut|dut|altpcie_a10_hip_pipen1b|skp_pat_det_g3_ps[1]" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_a10_hip_pipen1b.v Line: 3393 Warning (14320): Synthesized away node "dut|dut|altpcie_a10_hip_pipen1b|skp_pat_det_g3_ps[0]" File: E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_a10_hip_181/synth/altpcie_a10_hip_pipen1b.v Line: 3393 Info: found pre-synthesis snapshots for 1 partition(s) Info: Synthesizing partition "root_partition" Info (286030): Timing-Driven Synthesis is running Info (17049): 2954 registers lost all their fanouts during netlist optimizations. Info (21057): Implemented 13148 device resources after synthesis - the final resource count might be different Info (21058): Implemented 416 input pins Info (21059): Implemented 640 output pins Info (21061): Implemented 10730 logic cells Info (21064): Implemented 1114 RAM segments Error (19436): Unable to create project database files because the source file "./pcie_example_design_DUT/altera_xcvr_native_a10_181/synth/rcfg_timing_db/pcie_example_design_DUT_hssi_rx_pld_pcs_interface_rcfg_settings_wkfaq3y.json" cannot be located. Error: Failed to synthesize partition Info (144001): Generated suppressed messages file E:/FPGA_PRJ/pcietest/pcie_gen3/pcie_a10_hip_0_example_design/pcie_example_design.syn.smsg Info: Saving post-synthesis snapshots for 1 partition(s) Error: Quartus Prime Synthesis was unsuccessful. 2 errors, 44 warnings Error: Peak virtual memory: 5616 megabytes Error: Processing ended: Fri Nov 2 11:56:56 2018 Error: Elapsed time: 00:01:43 Info (19538): Reading SDC files took 00:00:04 cumulatively in this process.