Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Tue Jun 12 19:07:05 2018 Info: Command: quartus_sh --flow compile top -c top Info: Quartus(args): compile top -c top Info: Using INI file e:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/quartus.ini Info: Project Name = E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/top Info: Revision Name = top Info (125068): Revision "top" was previously opened in Quartus II software version 16.0.2. Created Quartus Prime Default Settings File E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/top_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 16.0.2. Info (125069): Default assignment values were changed in the current version of the Quartus Prime software -- changes to default assignments values are contained in file e:/intelfpga/17.1/quartus/bin64/assignment_defaults.qdf Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition Info: Processing started: Tue Jun 12 19:07:13 2018 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top Info: Using INI file E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/quartus.ini Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (12021): Found 2 design units, including 2 entities, in source file top.v Info (12023): Found entity 1: top File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/top.v Line: 1 Info (12023): Found entity 2: async_counter_30 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/top.v Line: 180 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/system.v Info (12023): Found entity 1: system File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/system.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_controller.v Info (12023): Found entity 1: altera_reset_controller File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_reset_controller.v Line: 42 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_synchronizer.v Info (12023): Found entity 1: altera_reset_synchronizer File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_reset_synchronizer.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_irq_mapper.sv Info (12023): Found entity 1: system_irq_mapper File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_irq_mapper.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_6.v Info (12023): Found entity 1: system_mm_interconnect_6 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_mm_interconnect_6.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_translator.sv Info (12023): Found entity 1: altera_merlin_slave_translator File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_slave_translator.sv Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_translator.sv Info (12023): Found entity 1: altera_merlin_master_translator File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_master_translator.sv Line: 32 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_0.v Info (12023): Found entity 1: system_mm_interconnect_0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/cra_ring_root.sv Info (12023): Found entity 1: cra_ring_root File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/cra_ring_root.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_shift_register.v Info (12023): Found entity 1: acl_shift_register File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_shift_register.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_work_group_dispatcher.v Info (12023): Found entity 1: acl_work_group_dispatcher File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_work_group_dispatcher.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_kernel_finish_detector.v Info (12023): Found entity 1: acl_kernel_finish_detector File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_kernel_finish_detector.v Line: 42 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_multistage_accumulator.v Info (12023): Found entity 1: acl_multistage_accumulator File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_multistage_accumulator.v Line: 21 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/acl_reset_handler.sv Info (12023): Found entity 1: acl_reset_handler File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_reset_handler.sv Line: 48 Info (12023): Found entity 2: acl_reset_fanout_pipeline_with_synchronizer_and_pulse_extender File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_reset_handler.sv Line: 124 Info (12023): Found entity 3: acl_reset_pulse_extender File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_reset_handler.sv Line: 200 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_std_synchronizer_nocut.v Info (12023): Found entity 1: acl_std_synchronizer_nocut File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_std_synchronizer_nocut.v Line: 52 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_fanout_pipeline.sv Info (12023): Found entity 1: acl_fanout_pipeline File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_fanout_pipeline.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_id_iterator.v Info (12023): Found entity 1: acl_id_iterator File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_id_iterator.v Line: 39 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_work_item_iterator.v Info (12023): Found entity 1: acl_work_item_iterator File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_work_item_iterator.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_multistage_adder.v Info (12023): Found entity 1: acl_multistage_adder File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_multistage_adder.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_fifo.v Info (12023): Found entity 1: acl_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_fifo.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_fifo_stall_valid_lookahead.sv Info (12023): Found entity 1: acl_fifo_stall_valid_lookahead File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_fifo_stall_valid_lookahead.sv Line: 25 Error (10759): Verilog HDL error at boardtest_system.v(510): object kclk_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 510 Error (10112): Ignored design unit "kclk_partition_wrapper" at boardtest_system.v(488) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 488 Error (10759): Verilog HDL error at boardtest_system.v(757): object mem_burstcoalesced_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 757 Error (10112): Ignored design unit "mem_burstcoalesced_partition_wrapper" at boardtest_system.v(711) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 711 Error (10759): Verilog HDL error at boardtest_system.v(1028): object mem_stream_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1028 Error (10112): Ignored design unit "mem_stream_partition_wrapper" at boardtest_system.v(982) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 982 Error (10759): Verilog HDL error at boardtest_system.v(1299): object mem_writestream_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1299 Error (10112): Ignored design unit "mem_writestream_partition_wrapper" at boardtest_system.v(1253) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1253 Error (10759): Verilog HDL error at boardtest_system.v(1581): object reorder_const_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1581 Error (10112): Ignored design unit "reorder_const_partition_wrapper" at boardtest_system.v(1524) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1524 Error (10112): Ignored design unit "kclk_top_wrapper_0" at boardtest_system.v(1817) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1817 Error (10112): Ignored design unit "mem_burstcoalesced_top_wrapper_0" at boardtest_system.v(1886) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1886 Error (10112): Ignored design unit "mem_stream_top_wrapper_0" at boardtest_system.v(2003) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2003 Error (10112): Ignored design unit "mem_writestream_top_wrapper_0" at boardtest_system.v(2120) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2120 Error (10112): Ignored design unit "reorder_const_top_wrapper_0" at boardtest_system.v(2237) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2237 Info (12021): Found 0 design units, including 0 entities, in source file system/synthesis/submodules/boardtest_system.v Info (12021): Found 1 design units, including 0 entities, in source file system/synthesis/submodules/dspba_library_package.vhd Info (12022): Found design unit 1: dspba_library_package (system) File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/dspba_library_package.vhd Line: 17 Info (12021): Found 6 design units, including 3 entities, in source file system/synthesis/submodules/dspba_library.vhd Info (12022): Found design unit 1: dspba_delay-delay File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/dspba_library.vhd Line: 34 Info (12022): Found design unit 2: dspba_sync_reg-sync_reg File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/dspba_library.vhd Line: 117 Info (12022): Found design unit 3: dspba_pipe-rtl File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/dspba_library.vhd Line: 356 Info (12023): Found entity 1: dspba_delay File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/dspba_library.vhd Line: 18 Info (12023): Found entity 2: dspba_sync_reg File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/dspba_library.vhd Line: 93 Info (12023): Found entity 3: dspba_pipe File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/dspba_library.vhd Line: 343 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_data_fifo.v Info (12023): Found entity 1: acl_data_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_data_fifo.v Line: 49 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ll_fifo.v Info (12023): Found entity 1: acl_ll_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_ll_fifo.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ll_ram_fifo.v Info (12023): Found entity 1: acl_ll_ram_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_ll_ram_fifo.v Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_valid_fifo_counter.v Info (12023): Found entity 1: acl_valid_fifo_counter File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_valid_fifo_counter.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_dspba_valid_fifo_counter.v Info (12023): Found entity 1: acl_dspba_valid_fifo_counter File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_dspba_valid_fifo_counter.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_staging_reg.v Info (12023): Found entity 1: acl_staging_reg File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_staging_reg.v Line: 24 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/hld_fifo.sv Info (12023): Found entity 1: hld_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hld_fifo.sv Line: 132 Info (12023): Found entity 2: earliness_delay File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hld_fifo.sv Line: 389 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hld_fifo_zero_width.sv Info (12023): Found entity 1: hld_fifo_zero_width File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hld_fifo_zero_width.sv Line: 26 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/acl_high_speed_fifo.sv Info (12023): Found entity 1: acl_high_speed_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_high_speed_fifo.sv Line: 133 Info (12023): Found entity 2: scfifo_to_acl_high_speed_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_high_speed_fifo.sv Line: 1084 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_low_latency_fifo.sv Info (12023): Found entity 1: acl_low_latency_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_low_latency_fifo.sv Line: 80 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_zero_latency_fifo.sv Info (12023): Found entity 1: acl_zero_latency_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_zero_latency_fifo.sv Line: 97 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/acl_tessellated_incr_decr_threshold.sv Info (12023): Found entity 1: acl_tessellated_incr_decr_threshold File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_tessellated_incr_decr_threshold.sv Line: 42 Info (12023): Found entity 2: acl_tessellated_incr_decr File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_tessellated_incr_decr_threshold.sv Line: 374 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_tessellated_incr_lookahead.sv Info (12023): Found entity 1: acl_tessellated_incr_lookahead File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_tessellated_incr_lookahead.sv Line: 40 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/acl_lfsr.sv Info (12023): Found entity 1: acl_lfsr File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_lfsr.sv Line: 42 Info (12023): Found entity 2: galois_lfsr File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_lfsr.sv Line: 1622 Info (12023): Found entity 3: fibonacci_lfsr File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_lfsr.sv Line: 1670 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_clock2x_holder.v Info (12023): Found entity 1: acl_clock2x_holder File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_clock2x_holder.v Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/kclk_function_wrapper.vhd Info (12022): Found design unit 1: kclk_function_wrapper-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/kclk_function_wrapper.vhd Line: 78 Info (12023): Found entity 1: kclk_function_wrapper File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/kclk_function_wrapper.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/kclk_function.vhd Info (12022): Found design unit 1: kclk_function-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/kclk_function.vhd Line: 56 Info (12023): Found entity 1: kclk_function File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/kclk_function.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/bb_kclk_b0.vhd Info (12022): Found design unit 1: bb_kclk_B0-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_kclk_B0.vhd Line: 46 Info (12023): Found entity 1: bb_kclk_B0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_kclk_B0.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/bb_kclk_b0_stall_region.vhd Info (12022): Found design unit 1: bb_kclk_B0_stall_region-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_kclk_B0_stall_region.vhd Line: 46 Info (12023): Found entity 1: bb_kclk_B0_stall_region File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_kclk_B0_stall_region.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/kclk_b0_merge_reg.vhd Info (12022): Found design unit 1: kclk_B0_merge_reg-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/kclk_B0_merge_reg.vhd Line: 48 Info (12023): Found entity 1: kclk_B0_merge_reg File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/kclk_B0_merge_reg.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/kclk_b0_branch.vhd Info (12022): Found design unit 1: kclk_B0_branch-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/kclk_B0_branch.vhd Line: 46 Info (12023): Found entity 1: kclk_B0_branch File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/kclk_B0_branch.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/kclk_b0_merge.vhd Info (12022): Found design unit 1: kclk_B0_merge-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/kclk_B0_merge.vhd Line: 46 Info (12023): Found entity 1: kclk_B0_merge File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/kclk_B0_merge.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/kclk_function_cra_slave.vhd Info (12022): Found design unit 1: kclk_function_cra_slave-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/kclk_function_cra_slave.vhd Line: 75 Info (12023): Found entity 1: kclk_function_cra_slave File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/kclk_function_cra_slave.vhd Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_start_signal_chain_element.v Info (12023): Found entity 1: acl_start_signal_chain_element File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_start_signal_chain_element.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_dspba_buffer.v Info (12023): Found entity 1: acl_dspba_buffer File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_dspba_buffer.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_full_detector.v Info (12023): Found entity 1: acl_full_detector File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_full_detector.v Line: 42 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_top.v Info (12023): Found entity 1: lsu_top File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_top.v Line: 82 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_permute_address.v Info (12023): Found entity 1: lsu_permute_address File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_permute_address.v Line: 20 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_pipelined.v Info (12023): Found entity 1: lsu_pipelined_read File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_pipelined.v Line: 43 Info (12023): Found entity 2: lsu_pipelined_write File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_pipelined.v Line: 458 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_enabled.v Info (12023): Found entity 1: lsu_enabled_read File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_enabled.v Line: 41 Info (12023): Found entity 2: lsu_enabled_write File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_enabled.v Line: 194 Info (12021): Found 4 design units, including 4 entities, in source file system/synthesis/submodules/lsu_basic_coalescer.v Info (12023): Found entity 1: lsu_basic_coalesced_read File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_basic_coalescer.v Line: 41 Info (12023): Found entity 2: lsu_basic_coalesced_write File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_basic_coalescer.v Line: 227 Info (12023): Found entity 3: lookahead_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_basic_coalescer.v Line: 482 Info (12023): Found entity 4: basic_coalescer File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_basic_coalescer.v Line: 543 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_simple.v Info (12023): Found entity 1: lsu_simple_read File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_simple.v Line: 36 Info (12023): Found entity 2: lsu_simple_write File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_simple.v Line: 201 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_streaming.v Info (12023): Found entity 1: lsu_streaming_read File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_streaming.v Line: 39 Info (12023): Found entity 2: lsu_streaming_write File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_streaming.v Line: 294 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_burst_master.v Info (12023): Found entity 1: lsu_burst_read_master File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_burst_master.v Line: 30 Info (12021): Found 7 design units, including 7 entities, in source file system/synthesis/submodules/lsu_bursting_load_stores.v Info (12023): Found entity 1: lsu_bursting_read File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 18 Info (12023): Found entity 2: acl_io_pipeline File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 405 Info (12023): Found entity 3: lsu_bursting_pipelined_read File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 432 Info (12023): Found entity 4: acl_stall_free_coalescer File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 939 Info (12023): Found entity 5: lsu_bursting_write File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1096 Info (12023): Found entity 6: lsu_bursting_write_internal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1260 Info (12023): Found entity 7: bursting_coalescer File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1675 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_non_aligned_write.v Info (12023): Found entity 1: lsu_non_aligned_write File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_non_aligned_write.v Line: 19 Info (12023): Found entity 2: lsu_non_aligned_write_internal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_non_aligned_write.v Line: 168 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_read_cache.v Info (12023): Found entity 1: lsu_read_cache File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_read_cache.v Line: 45 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_atomic.v Info (12023): Found entity 1: lsu_atomic_pipelined File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_atomic.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_prefetch_block.v Info (12023): Found entity 1: lsu_prefetch_block File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_prefetch_block.v Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_wide_wrapper.v Info (12023): Found entity 1: lsu_wide_wrapper File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_wide_wrapper.v Line: 21 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/lsu_streaming_prefetch.v Info (12023): Found entity 1: lsu_streaming_prefetch_read File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_streaming_prefetch.v Line: 25 Info (12023): Found entity 2: lsu_streaming_prefetch_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_streaming_prefetch.v Line: 324 Info (12023): Found entity 3: lsu_streaming_prefetch_avalon_bust_master File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_streaming_prefetch.v Line: 542 Info (12021): Found 6 design units, including 6 entities, in source file system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Info (12023): Found entity 1: acl_aligned_burst_coalesced_lsu File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 65 Info (12023): Found entity 2: avalon_interface File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 310 Info (12023): Found entity 3: valid_generator File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 496 Info (12023): Found entity 4: acl_lsu_buffers File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 563 Info (12023): Found entity 5: acl_burst_coalescer File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 767 Info (12023): Found entity 6: acl_registered_comparison File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 1186 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_toggle_detect.v Info (12023): Found entity 1: acl_toggle_detect File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_toggle_detect.v Line: 39 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_debug_mem.v Info (12023): Found entity 1: acl_debug_mem File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_debug_mem.v Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_burst_coalesced_pipelined_write.sv Info (12023): Found entity 1: lsu_burst_coalesced_pipelined_write File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_burst_coalesced_pipelined_write.sv Line: 69 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_burst_coalesced_pipelined_read.sv Info (12023): Found entity 1: lsu_burst_coalesced_pipelined_read File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_burst_coalesced_pipelined_read.sv Line: 63 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_burstcoalesced_function_wrapper.vhd Info (12022): Found design unit 1: mem_burstcoalesced_function_wrapper-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_burstcoalesced_function_wrapper.vhd Line: 100 Info (12023): Found entity 1: mem_burstcoalesced_function_wrapper File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_burstcoalesced_function_wrapper.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_burstcoalesced_function.vhd Info (12022): Found design unit 1: mem_burstcoalesced_function-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_burstcoalesced_function.vhd Line: 81 Info (12023): Found entity 1: mem_burstcoalesced_function File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_burstcoalesced_function.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/bb_mem_burstcoalesced_b0.vhd Info (12022): Found design unit 1: bb_mem_burstcoalesced_B0-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_mem_burstcoalesced_B0.vhd Line: 75 Info (12023): Found entity 1: bb_mem_burstcoalesced_B0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_mem_burstcoalesced_B0.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/bb_mem_burstcoalesced_b0_stall_region.vhd Info (12022): Found design unit 1: bb_mem_burstcoalesced_B0_stall_region-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_mem_burstcoalesced_B0_stall_region.vhd Line: 75 Info (12023): Found entity 1: bb_mem_burstcoalesced_B0_stall_region File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_mem_burstcoalesced_B0_stall_region.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_load_memcoalesce_src_load_0_mem_burstcoalesced15.vhd Info (12022): Found design unit 1: i_load_memcoalesce_src_load_0_mem_burstcoalesced15-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_load_memcoalesce_src_load_0_mem_burstcoalesced15.vhd Line: 76 Info (12023): Found entity 1: i_load_memcoalesce_src_load_0_mem_burstcoalesced15 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_load_memcoalesce_src_load_0_mem_burstcoalesced15.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/readdata_reg_memcoalesce_src_load_0_mem_burstcoalesced0.vhd Info (12022): Found design unit 1: readdata_reg_memcoalesce_src_load_0_mem_burstcoalesced0-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/readdata_reg_memcoalesce_src_load_0_mem_burstcoalesced0.vhd Line: 78 Info (12023): Found entity 1: readdata_reg_memcoalesce_src_load_0_mem_burstcoalesced0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/readdata_reg_memcoalesce_src_load_0_mem_burstcoalesced0.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_sfc_c0_entry_mem_burstcoalesced_c0_enta0zm_burstcoalesced.vhd Info (12022): Found design unit 1: i_sfc_c0_entry_mem_burstcoalesced_c0_enter_mem_burstcoalesced-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_sfc_c0_entry_mem_burstcoalesced_c0_entA0Zm_burstcoalesced.vhd Line: 55 Info (12023): Found entity 1: i_sfc_c0_entry_mem_burstcoalesced_c0_enter_mem_burstcoalesced File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_sfc_c0_entry_mem_burstcoalesced_c0_entA0Zm_burstcoalesced.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_acl_sfc_exit_c0_entry_mem_burstcoalesca0zburstcoalesced14.vhd Info (12022): Found design unit 1: i_acl_sfc_exit_c0_entry_mem_burstcoalesced_c0_exit_mem_burstcoalesced14-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_acl_sfc_exit_c0_entry_mem_burstcoalescA0Zburstcoalesced14.vhd Line: 53 Info (12023): Found entity 1: i_acl_sfc_exit_c0_entry_mem_burstcoalesced_c0_exit_mem_burstcoalesced14 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_acl_sfc_exit_c0_entry_mem_burstcoalescA0Zburstcoalesced14.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_acl_sfc_exit_c0_entry_mem_burstcoalesca0zsced19_data_fifo.vhd Info (12022): Found design unit 1: i_acl_sfc_exit_c0_entry_mem_burstcoalesced_c0_exit_mem_burstcoalesced19_data_fifo-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_acl_sfc_exit_c0_entry_mem_burstcoalescA0Zsced19_data_fifo.vhd Line: 52 Info (12023): Found entity 1: i_acl_sfc_exit_c0_entry_mem_burstcoalesced_c0_exit_mem_burstcoalesced19_data_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_acl_sfc_exit_c0_entry_mem_burstcoalescA0Zsced19_data_fifo.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_acl_sfc_exit_c0_entry_mem_burstcoalesca0zed_full_detector.vhd Info (12022): Found design unit 1: i_acl_sfc_exit_c0_entry_mem_burstcoalesced_c0_exit_mem_burstcoalesced_full_detector-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_acl_sfc_exit_c0_entry_mem_burstcoalescA0Zed_full_detector.vhd Line: 48 Info (12023): Found entity 1: i_acl_sfc_exit_c0_entry_mem_burstcoalesced_c0_exit_mem_burstcoalesced_full_detector File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_acl_sfc_exit_c0_entry_mem_burstcoalescA0Zed_full_detector.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_sfc_logic_c0_entry_mem_burstcoalesced_a0z_burstcoalesced0.vhd Info (12022): Found design unit 1: i_sfc_logic_c0_entry_mem_burstcoalesced_c0_enter_mem_burstcoalesced0-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_sfc_logic_c0_entry_mem_burstcoalesced_A0Z_burstcoalesced0.vhd Line: 53 Info (12023): Found entity 1: i_sfc_logic_c0_entry_mem_burstcoalesced_c0_enter_mem_burstcoalesced0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_sfc_logic_c0_entry_mem_burstcoalesced_A0Z_burstcoalesced0.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_syncbuf_arg2_sync_buffer_mem_burstcoalesced6.vhd Info (12022): Found design unit 1: i_syncbuf_arg2_sync_buffer_mem_burstcoalesced6-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_arg2_sync_buffer_mem_burstcoalesced6.vhd Line: 49 Info (12023): Found entity 1: i_syncbuf_arg2_sync_buffer_mem_burstcoalesced6 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_arg2_sync_buffer_mem_burstcoalesced6.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_syncbuf_arg_sync_buffer_mem_burstcoalesced4.vhd Info (12022): Found design unit 1: i_syncbuf_arg_sync_buffer_mem_burstcoalesced4-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_arg_sync_buffer_mem_burstcoalesced4.vhd Line: 49 Info (12023): Found entity 1: i_syncbuf_arg_sync_buffer_mem_burstcoalesced4 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_arg_sync_buffer_mem_burstcoalesced4.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_syncbuf_dst_sync_buffer_mem_burstcoalesced11.vhd Info (12022): Found design unit 1: i_syncbuf_dst_sync_buffer_mem_burstcoalesced11-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_dst_sync_buffer_mem_burstcoalesced11.vhd Line: 49 Info (12023): Found entity 1: i_syncbuf_dst_sync_buffer_mem_burstcoalesced11 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_dst_sync_buffer_mem_burstcoalesced11.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_syncbuf_src_sync_buffer_mem_burstcoalesced8.vhd Info (12022): Found design unit 1: i_syncbuf_src_sync_buffer_mem_burstcoalesced8-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_src_sync_buffer_mem_burstcoalesced8.vhd Line: 49 Info (12023): Found entity 1: i_syncbuf_src_sync_buffer_mem_burstcoalesced8 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_src_sync_buffer_mem_burstcoalesced8.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_store_unnamed_mem_burstcoalesced0_mem_a0zburstcoalesced17.vhd Info (12022): Found design unit 1: i_store_unnamed_mem_burstcoalesced0_mem_burstcoalesced17-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_store_unnamed_mem_burstcoalesced0_mem_A0Zburstcoalesced17.vhd Line: 77 Info (12023): Found entity 1: i_store_unnamed_mem_burstcoalesced0_mem_burstcoalesced17 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_store_unnamed_mem_burstcoalesced0_mem_A0Zburstcoalesced17.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_burstcoalesced_b0_merge_reg.vhd Info (12022): Found design unit 1: mem_burstcoalesced_B0_merge_reg-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_burstcoalesced_B0_merge_reg.vhd Line: 48 Info (12023): Found entity 1: mem_burstcoalesced_B0_merge_reg File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_burstcoalesced_B0_merge_reg.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_burstcoalesced_b0_branch.vhd Info (12022): Found design unit 1: mem_burstcoalesced_B0_branch-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_burstcoalesced_B0_branch.vhd Line: 46 Info (12023): Found entity 1: mem_burstcoalesced_B0_branch File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_burstcoalesced_B0_branch.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_burstcoalesced_b0_merge.vhd Info (12022): Found design unit 1: mem_burstcoalesced_B0_merge-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_burstcoalesced_B0_merge.vhd Line: 48 Info (12023): Found entity 1: mem_burstcoalesced_B0_merge File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_burstcoalesced_B0_merge.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_burstcoalesced_function_cra_slave.vhd Info (12022): Found design unit 1: mem_burstcoalesced_function_cra_slave-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_burstcoalesced_function_cra_slave.vhd Line: 75 Info (12023): Found entity 1: mem_burstcoalesced_function_cra_slave File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_burstcoalesced_function_cra_slave.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_stream_function_wrapper.vhd Info (12022): Found design unit 1: mem_stream_function_wrapper-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_stream_function_wrapper.vhd Line: 100 Info (12023): Found entity 1: mem_stream_function_wrapper File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_stream_function_wrapper.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_stream_function.vhd Info (12022): Found design unit 1: mem_stream_function-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_stream_function.vhd Line: 81 Info (12023): Found entity 1: mem_stream_function File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_stream_function.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/bb_mem_stream_b0.vhd Info (12022): Found design unit 1: bb_mem_stream_B0-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_mem_stream_B0.vhd Line: 76 Info (12023): Found entity 1: bb_mem_stream_B0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_mem_stream_B0.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/bb_mem_stream_b0_stall_region.vhd Info (12022): Found design unit 1: bb_mem_stream_B0_stall_region-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_mem_stream_B0_stall_region.vhd Line: 77 Info (12023): Found entity 1: bb_mem_stream_B0_stall_region File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_mem_stream_B0_stall_region.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_load_memcoalesce_src_load_0_mem_stream5.vhd Info (12022): Found design unit 1: i_load_memcoalesce_src_load_0_mem_stream5-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_load_memcoalesce_src_load_0_mem_stream5.vhd Line: 79 Info (12023): Found entity 1: i_load_memcoalesce_src_load_0_mem_stream5 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_load_memcoalesce_src_load_0_mem_stream5.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/readdata_reg_memcoalesce_src_load_0_mem_stream0.vhd Info (12022): Found design unit 1: readdata_reg_memcoalesce_src_load_0_mem_stream0-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/readdata_reg_memcoalesce_src_load_0_mem_stream0.vhd Line: 78 Info (12023): Found entity 1: readdata_reg_memcoalesce_src_load_0_mem_stream0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/readdata_reg_memcoalesce_src_load_0_mem_stream0.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_store_unnamed_mem_stream0_mem_stream10.vhd Info (12022): Found design unit 1: i_store_unnamed_mem_stream0_mem_stream10-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_store_unnamed_mem_stream0_mem_stream10.vhd Line: 80 Info (12023): Found entity 1: i_store_unnamed_mem_stream0_mem_stream10 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_store_unnamed_mem_stream0_mem_stream10.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_stream_b0_merge_reg.vhd Info (12022): Found design unit 1: mem_stream_B0_merge_reg-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_stream_B0_merge_reg.vhd Line: 48 Info (12023): Found entity 1: mem_stream_B0_merge_reg File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_stream_B0_merge_reg.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_syncbuf_dst_sync_buffer_mem_stream7.vhd Info (12022): Found design unit 1: i_syncbuf_dst_sync_buffer_mem_stream7-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_dst_sync_buffer_mem_stream7.vhd Line: 49 Info (12023): Found entity 1: i_syncbuf_dst_sync_buffer_mem_stream7 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_dst_sync_buffer_mem_stream7.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_syncbuf_src_sync_buffer_mem_stream2.vhd Info (12022): Found design unit 1: i_syncbuf_src_sync_buffer_mem_stream2-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_src_sync_buffer_mem_stream2.vhd Line: 49 Info (12023): Found entity 1: i_syncbuf_src_sync_buffer_mem_stream2 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_src_sync_buffer_mem_stream2.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_stream_b0_branch.vhd Info (12022): Found design unit 1: mem_stream_B0_branch-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_stream_B0_branch.vhd Line: 46 Info (12023): Found entity 1: mem_stream_B0_branch File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_stream_B0_branch.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_stream_b0_merge.vhd Info (12022): Found design unit 1: mem_stream_B0_merge-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_stream_B0_merge.vhd Line: 48 Info (12023): Found entity 1: mem_stream_B0_merge File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_stream_B0_merge.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_stream_function_cra_slave.vhd Info (12022): Found design unit 1: mem_stream_function_cra_slave-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_stream_function_cra_slave.vhd Line: 75 Info (12023): Found entity 1: mem_stream_function_cra_slave File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_stream_function_cra_slave.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_writestream_function_wrapper.vhd Info (12022): Found design unit 1: mem_writestream_function_wrapper-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_writestream_function_wrapper.vhd Line: 100 Info (12023): Found entity 1: mem_writestream_function_wrapper File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_writestream_function_wrapper.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_writestream_function.vhd Info (12022): Found design unit 1: mem_writestream_function-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_writestream_function.vhd Line: 82 Info (12023): Found entity 1: mem_writestream_function File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_writestream_function.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/bb_mem_writestream_b0.vhd Info (12022): Found design unit 1: bb_mem_writestream_B0-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_mem_writestream_B0.vhd Line: 76 Info (12023): Found entity 1: bb_mem_writestream_B0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_mem_writestream_B0.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/bb_mem_writestream_b0_stall_region.vhd Info (12022): Found design unit 1: bb_mem_writestream_B0_stall_region-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_mem_writestream_B0_stall_region.vhd Line: 76 Info (12023): Found entity 1: bb_mem_writestream_B0_stall_region File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_mem_writestream_B0_stall_region.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_store_memdep_mem_writestream20.vhd Info (12022): Found design unit 1: i_store_memdep_mem_writestream20-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_store_memdep_mem_writestream20.vhd Line: 78 Info (12023): Found entity 1: i_store_memdep_mem_writestream20 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_store_memdep_mem_writestream20.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_store_unnamed_mem_writestream0_mem_writestream25.vhd Info (12022): Found design unit 1: i_store_unnamed_mem_writestream0_mem_writestream25-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_store_unnamed_mem_writestream0_mem_writestream25.vhd Line: 81 Info (12023): Found entity 1: i_store_unnamed_mem_writestream0_mem_writestream25 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_store_unnamed_mem_writestream0_mem_writestream25.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_writestream_b0_merge_reg.vhd Info (12022): Found design unit 1: mem_writestream_B0_merge_reg-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_writestream_B0_merge_reg.vhd Line: 48 Info (12023): Found entity 1: mem_writestream_B0_merge_reg File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_writestream_B0_merge_reg.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_syncbuf_dst_sync_buffer_mem_writestream17.vhd Info (12022): Found design unit 1: i_syncbuf_dst_sync_buffer_mem_writestream17-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_dst_sync_buffer_mem_writestream17.vhd Line: 49 Info (12023): Found entity 1: i_syncbuf_dst_sync_buffer_mem_writestream17 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_dst_sync_buffer_mem_writestream17.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_syncbuf_src_sync_buffer_mem_writestream22.vhd Info (12022): Found design unit 1: i_syncbuf_src_sync_buffer_mem_writestream22-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_src_sync_buffer_mem_writestream22.vhd Line: 49 Info (12023): Found entity 1: i_syncbuf_src_sync_buffer_mem_writestream22 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_src_sync_buffer_mem_writestream22.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_writestream_b0_branch.vhd Info (12022): Found design unit 1: mem_writestream_B0_branch-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_writestream_B0_branch.vhd Line: 46 Info (12023): Found entity 1: mem_writestream_B0_branch File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_writestream_B0_branch.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_writestream_b0_merge.vhd Info (12022): Found design unit 1: mem_writestream_B0_merge-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_writestream_B0_merge.vhd Line: 48 Info (12023): Found entity 1: mem_writestream_B0_merge File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_writestream_B0_merge.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/mem_writestream_function_cra_slave.vhd Info (12022): Found design unit 1: mem_writestream_function_cra_slave-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_writestream_function_cra_slave.vhd Line: 75 Info (12023): Found entity 1: mem_writestream_function_cra_slave File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_writestream_function_cra_slave.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/reorder_const_function_wrapper.vhd Info (12022): Found design unit 1: reorder_const_function_wrapper-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/reorder_const_function_wrapper.vhd Line: 111 Info (12023): Found entity 1: reorder_const_function_wrapper File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/reorder_const_function_wrapper.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/reorder_const_function.vhd Info (12022): Found design unit 1: reorder_const_function-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/reorder_const_function.vhd Line: 91 Info (12023): Found entity 1: reorder_const_function File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/reorder_const_function.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/bb_reorder_const_b0.vhd Info (12022): Found design unit 1: bb_reorder_const_B0-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_reorder_const_B0.vhd Line: 88 Info (12023): Found entity 1: bb_reorder_const_B0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_reorder_const_B0.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/bb_reorder_const_b0_stall_region.vhd Info (12022): Found design unit 1: bb_reorder_const_B0_stall_region-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_reorder_const_B0_stall_region.vhd Line: 89 Info (12023): Found entity 1: bb_reorder_const_B0_stall_region File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/bb_reorder_const_B0_stall_region.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/reorder_const_b0_merge_reg.vhd Info (12022): Found design unit 1: reorder_const_B0_merge_reg-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/reorder_const_B0_merge_reg.vhd Line: 48 Info (12023): Found entity 1: reorder_const_B0_merge_reg File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/reorder_const_B0_merge_reg.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_load_unnamed_reorder_const0_reorder_const3.vhd Info (12022): Found design unit 1: i_load_unnamed_reorder_const0_reorder_const3-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_load_unnamed_reorder_const0_reorder_const3.vhd Line: 64 Info (12023): Found entity 1: i_load_unnamed_reorder_const0_reorder_const3 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_load_unnamed_reorder_const0_reorder_const3.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/readdata_reg_unnamed_reorder_const0_reorder_const0.vhd Info (12022): Found design unit 1: readdata_reg_unnamed_reorder_const0_reorder_const0-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/readdata_reg_unnamed_reorder_const0_reorder_const0.vhd Line: 48 Info (12023): Found entity 1: readdata_reg_unnamed_reorder_const0_reorder_const0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/readdata_reg_unnamed_reorder_const0_reorder_const0.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_load_unnamed_reorder_const1_reorder_const8.vhd Info (12022): Found design unit 1: i_load_unnamed_reorder_const1_reorder_const8-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_load_unnamed_reorder_const1_reorder_const8.vhd Line: 61 Info (12023): Found entity 1: i_load_unnamed_reorder_const1_reorder_const8 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_load_unnamed_reorder_const1_reorder_const8.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/readdata_reg_unnamed_reorder_const1_reorder_const1.vhd Info (12022): Found design unit 1: readdata_reg_unnamed_reorder_const1_reorder_const1-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/readdata_reg_unnamed_reorder_const1_reorder_const1.vhd Line: 48 Info (12023): Found entity 1: readdata_reg_unnamed_reorder_const1_reorder_const1 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/readdata_reg_unnamed_reorder_const1_reorder_const1.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_store_unnamed_reorder_const2_reorder_const13.vhd Info (12022): Found design unit 1: i_store_unnamed_reorder_const2_reorder_const13-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_store_unnamed_reorder_const2_reorder_const13.vhd Line: 65 Info (12023): Found entity 1: i_store_unnamed_reorder_const2_reorder_const13 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_store_unnamed_reorder_const2_reorder_const13.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_syncbuf_dst_sync_buffer_reorder_const10.vhd Info (12022): Found design unit 1: i_syncbuf_dst_sync_buffer_reorder_const10-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_dst_sync_buffer_reorder_const10.vhd Line: 49 Info (12023): Found entity 1: i_syncbuf_dst_sync_buffer_reorder_const10 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_dst_sync_buffer_reorder_const10.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_syncbuf_index_sync_buffer_reorder_const0.vhd Info (12022): Found design unit 1: i_syncbuf_index_sync_buffer_reorder_const0-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_index_sync_buffer_reorder_const0.vhd Line: 49 Info (12023): Found entity 1: i_syncbuf_index_sync_buffer_reorder_const0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_index_sync_buffer_reorder_const0.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/i_syncbuf_src_sync_buffer_reorder_const5.vhd Info (12022): Found design unit 1: i_syncbuf_src_sync_buffer_reorder_const5-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_src_sync_buffer_reorder_const5.vhd Line: 49 Info (12023): Found entity 1: i_syncbuf_src_sync_buffer_reorder_const5 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/i_syncbuf_src_sync_buffer_reorder_const5.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/reorder_const_b0_branch.vhd Info (12022): Found design unit 1: reorder_const_B0_branch-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/reorder_const_B0_branch.vhd Line: 46 Info (12023): Found entity 1: reorder_const_B0_branch File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/reorder_const_B0_branch.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/reorder_const_b0_merge.vhd Info (12022): Found design unit 1: reorder_const_B0_merge-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/reorder_const_B0_merge.vhd Line: 48 Info (12023): Found entity 1: reorder_const_B0_merge File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/reorder_const_B0_merge.vhd Line: 35 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/reorder_const_function_cra_slave.vhd Info (12022): Found design unit 1: reorder_const_function_cra_slave-normal File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/reorder_const_function_cra_slave.vhd Line: 75 Info (12023): Found entity 1: reorder_const_function_cra_slave File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/reorder_const_function_cra_slave.vhd Line: 35 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/acl_const_cache.v Info (12023): Found entity 1: acl_const_cache File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_const_cache.v Line: 101 Info (12023): Found entity 2: cachefill_arbiter File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_const_cache.v Line: 632 Info (12023): Found entity 3: pipe File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_const_cache.v Line: 694 Info (12021): Found 4 design units, including 4 entities, in source file system/synthesis/submodules/acl_multireadport_mem.v Info (12023): Found entity 1: acl_multireadport_mem File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_multireadport_mem.v Line: 21 Info (12023): Found entity 2: memory_block File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_multireadport_mem.v Line: 241 Info (12023): Found entity 3: memory_block2x File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_multireadport_mem.v Line: 333 Info (12023): Found entity 4: shiftreg File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_multireadport_mem.v Line: 554 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_snoop.v Info (12023): Found entity 1: acl_snoop File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_snoop.v Line: 29 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_ic_top.sv Info (12023): Found entity 1: lsu_ic_top File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_ic_top.sv Line: 22 Info (12023): Found entity 2: debug_io_cnt File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_ic_top.sv Line: 355 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_ic_hybrid.sv Info (12023): Found entity 1: lsu_ic_hybrid File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_ic_hybrid.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_ic_token.sv Info (12023): Found entity 1: lsu_ic_token File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_ic_token.sv Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_ic_unbalance.sv Info (12023): Found entity 1: lsu_ic_unbalance File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_ic_unbalance.sv Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_n_fast.sv Info (12023): Found entity 1: lsu_n_fast File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_n_fast.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_n_token.sv Info (12023): Found entity 1: lsu_n_token File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_n_token.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_rd_back.sv Info (12023): Found entity 1: lsu_rd_back File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_rd_back.sv Line: 33 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_rd_back_n.sv Info (12023): Found entity 1: lsu_rd_back_n File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_rd_back_n.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_swdimm_token_ring.sv Info (12023): Found entity 1: lsu_swdimm_token_ring File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_swdimm_token_ring.sv Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_token_ring.sv Info (12023): Found entity 1: lsu_token_ring File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/lsu_token_ring.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_skid_buffer.sv Info (12023): Found entity 1: acl_skid_buffer File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/acl_skid_buffer.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/cra_ring_node.sv Info (12023): Found entity 1: cra_ring_node File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/cra_ring_node.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface.v Info (12023): Found entity 1: system_acl_iface File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_irq_mapper_001.sv Info (12023): Found entity 1: system_acl_iface_irq_mapper_001 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_irq_mapper_001.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_irq_mapper.sv Info (12023): Found entity 1: system_acl_iface_irq_mapper File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_irq_mapper.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_avalon_st_adapter.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_avalon_st_adapter File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_avalon_st_adapter_error_adapter_0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_rsp_mux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_rsp_mux.sv Line: 51 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_arbitrator.sv Info (12023): Found entity 1: altera_merlin_arbitrator File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 103 Info (12023): Found entity 2: altera_merlin_arb_adder File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 228 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_rsp_demux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_cmd_mux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_cmd_demux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_cmd_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_traffic_limiter.sv Info (12023): Found entity 1: altera_merlin_traffic_limiter File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_traffic_limiter.sv Line: 49 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_reorder_memory.sv Info (12023): Found entity 1: altera_merlin_reorder_memory File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 28 Info (12023): Found entity 2: memory_pointer_controller File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 185 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_sc_fifo.v Info (12023): Found entity 1: altera_avalon_sc_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_avalon_sc_fifo.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_base.v Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_avalon_st_pipeline_base.v Line: 22 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router_001.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_router_001_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_2_router_001 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_router_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_2_router File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_agent.sv Info (12023): Found entity 1: altera_merlin_slave_agent File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_uncompressor.sv Info (12023): Found entity 1: altera_merlin_burst_uncompressor File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_agent.sv Info (12023): Found entity 1: altera_merlin_master_agent File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_master_agent.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_rsp_mux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_rsp_demux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_cmd_mux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_cmd_demux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_cmd_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter.sv Info (12023): Found entity 1: altera_merlin_burst_adapter File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_uncompressed_only File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Line: 39 Info (12021): Found 5 design units, including 5 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 40 Info (12023): Found entity 2: altera_merlin_burst_adapter_adder File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 55 Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 77 Info (12023): Found entity 4: altera_merlin_burst_adapter_min File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 98 Info (12023): Found entity 5: altera_merlin_burst_adapter_13_1 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 264 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter_new.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_new File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_burst_adapter_new.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_incr_burst_converter.sv Info (12023): Found entity 1: altera_incr_burst_converter File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_incr_burst_converter.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_wrap_burst_converter.sv Info (12023): Found entity 1: altera_wrap_burst_converter File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_wrap_burst_converter.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_default_burst_converter.sv Info (12023): Found entity 1: altera_default_burst_converter File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_default_burst_converter.sv Line: 30 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_address_alignment.sv Info (12023): Found entity 1: altera_merlin_address_alignment File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_address_alignment.sv Line: 26 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Info (12023): Found entity 1: altera_avalon_st_pipeline_stage File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Line: 22 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router_002.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_router_002_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_1_router_002 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_router_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_1_router File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_axi_master_ni.sv Info (12023): Found entity 1: altera_merlin_axi_master_ni File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_axi_master_ni.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_0.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_0_avalon_st_adapter.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_0_avalon_st_adapter File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_0_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_0_avalon_st_adapter_error_adapter_0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_0_rsp_mux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_0_cmd_mux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_0_cmd_demux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_0_router_001_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_0_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_0_router_001 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_0_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_0_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_0_router_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_0_router File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/version_id.v Info (12023): Found entity 1: version_id File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/version_id.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_pll.v Info (12023): Found entity 1: system_acl_iface_pll File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_pll.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_mm_bridge.v Info (12023): Found entity 1: altera_avalon_mm_bridge File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_avalon_mm_bridge.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_hps.v Info (12023): Found entity 1: system_acl_iface_hps File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_hps.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_hps_hps_io.v Info (12023): Found entity 1: system_acl_iface_hps_hps_io File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_hps_hps_io.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram.v Info (12023): Found entity 1: hps_sdram File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Info (12023): Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv Info (12023): Found entity 1: altera_mem_if_dll_cyclonev File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Info (12023): Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v Info (12023): Found entity 1: altera_mem_if_hhp_qseq_synth_top File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv Info (12023): Found entity 1: altera_mem_if_oct_cyclonev File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0.sv Info (12023): Found entity 1: hps_sdram_p0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_p0.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Info (12023): Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Info (12023): Found entity 1: hps_sdram_p0_acv_hard_io_pads File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Info (12023): Found entity 1: hps_sdram_p0_acv_hard_memphy File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Info (12023): Found entity 1: hps_sdram_p0_acv_ldc File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_altdqdqs.v Info (12023): Found entity 1: hps_sdram_p0_altdqdqs File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_p0_altdqdqs.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Info (12023): Found entity 1: hps_sdram_p0_clock_pair_generator File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_generic_ddio.v Info (12023): Found entity 1: hps_sdram_p0_generic_ddio File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_p0_generic_ddio.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_iss_probe.v Info (12023): Found entity 1: hps_sdram_p0_iss_probe File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_p0_iss_probe.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_phy_csr.sv Info (12023): Found entity 1: hps_sdram_p0_phy_csr File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_p0_phy_csr.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_reset.v Info (12023): Found entity 1: hps_sdram_p0_reset File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_p0_reset.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_reset_sync.v Info (12023): Found entity 1: hps_sdram_p0_reset_sync File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_p0_reset_sync.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_pll.sv Info (12023): Found entity 1: hps_sdram_pll File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/hps_sdram_pll.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Info (12023): Found entity 1: system_acl_iface_hps_hps_io_border File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_hps_fpga_interfaces.sv Info (12023): Found entity 1: system_acl_iface_hps_fpga_interfaces File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_hps_fpga_interfaces.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Info (12023): Found entity 1: altera_avalon_mm_clock_crossing_bridge File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 30 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_dc_fifo.v Info (12023): Found entity 1: altera_avalon_dc_fifo File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_avalon_dc_fifo.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v Info (12023): Found entity 1: altera_dcfifo_synchronizer_bundle File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v Line: 8 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_std_synchronizer_nocut.v Info (12023): Found entity 1: altera_std_synchronizer_nocut File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_std_synchronizer_nocut.v Line: 44 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_address_span_extender.sv Info (12023): Found entity 1: altera_address_span_extender File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_address_span_extender.sv Line: 39 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_1 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter_error_adapter_0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_handshake_clock_crosser File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_clock_crosser File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_avalon_st_clock_crosser.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_width_adapter.sv Info (12023): Found entity 1: altera_merlin_width_adapter File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_mux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_demux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_router.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_acl_kernel_interface_mm_interconnect_1_router File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_1_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_0_rsp_mux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_mux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_router.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_acl_kernel_interface_mm_interconnect_0_router File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/irq_ena.v Info (12023): Found entity 1: irq_ena File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/irq_ena.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_irq_bridge.v Info (12023): Found entity 1: altera_irq_bridge File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/altera_irq_bridge.v Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/mem_org_mode.v Info (12023): Found entity 1: mem_org_mode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/mem_org_mode.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sw_reset.v Info (12023): Found entity 1: sw_reset File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/sw_reset.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_interface_sys_description_rom.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_interface_sys_description_rom File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_sys_description_rom.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux_001.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux_001 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux_001.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_default_decode File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_acl_kernel_clk_mm_interconnect_0_router File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_pll_rom File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/pll_lock_avs.v Info (12023): Found entity 1: pll_lock_avs File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/pll_lock_avs.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/global_routing.v Info (12023): Found entity 1: global_routing File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/global_routing.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/timer.v Info (12023): Found entity 1: acl_timer File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/timer.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_kernel_pll.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_kernel_pll File: E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_kernel_pll.v Line: 2 Info (144001): Generated suppressed messages file E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/top.map.smsg Error: Quartus Prime Analysis & Synthesis was unsuccessful. 15 errors, 1 warning Error: Peak virtual memory: 754 megabytes Error: Processing ended: Tue Jun 12 19:10:54 2018 Error: Elapsed time: 00:03:41 Error: Total CPU time (on all processors): 00:03:54 Error (293001): Quartus Prime Full Compilation was unsuccessful. 17 errors, 1 warning Error: Flow compile (for project E:/intelFPGA/17.1/hld/board/terasic/de1soc/examples/boardtest/bin/boardtest/top) was not successful Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last. Error (23031): Evaluation of Tcl script e:/intelfpga/17.1/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 24 errors, 1 warning Error: Peak virtual memory: 454 megabytes Error: Processing ended: Tue Jun 12 19:10:55 2018 Error: Elapsed time: 00:03:50 Error: Total CPU time (on all processors): 00:00:07