//`default_nettype none //`default_nettype wire //======================================================= // This code is generated by Terasic System Builder //======================================================= // Synthesizer `define _CycloneV `define _Synth module DE10_Nano_FB_DB25 ( //////////// ADC //////////// output wire ADC_CONVST, output wire ADC_SCK, output wire ADC_SDI, input wire ADC_SDO, //////////// ARDUINO //////////// inout wire [15:0] ARDUINO_IO, inout wire ARDUINO_RESET_N, //////////// CLOCK ////////// input wire FPGA_CLK1_50, input wire FPGA_CLK2_50, input wire FPGA_CLK3_50, //////////// GPIO //////////// inout wire [35:0] GPIO_0, inout wire [35:0] GPIO_1, //////////// HDMI //////////// inout wire HDMI_I2C_SCL, inout wire HDMI_I2C_SDA, inout wire HDMI_I2S, inout wire HDMI_LRCLK, inout wire HDMI_MCLK, inout wire HDMI_SCLK, output wire HDMI_TX_CLK, output wire [23:0] HDMI_TX_D, output wire HDMI_TX_DE, output wire HDMI_TX_HS, input wire HDMI_TX_INT, output wire HDMI_TX_VS, //////////// HPS //////////// inout wire HPS_CONV_USB_N, output wire [14:0] HPS_DDR3_ADDR, output wire [2:0] HPS_DDR3_BA, output wire HPS_DDR3_CAS_N, output wire HPS_DDR3_CKE, output wire HPS_DDR3_CK_N, output wire HPS_DDR3_CK_P, output wire HPS_DDR3_CS_N, output wire [3:0] HPS_DDR3_DM, inout wire [31:0] HPS_DDR3_DQ, inout wire [3:0] HPS_DDR3_DQS_N, inout wire [3:0] HPS_DDR3_DQS_P, output wire HPS_DDR3_ODT, output wire HPS_DDR3_RAS_N, output wire HPS_DDR3_RESET_N, input wire HPS_DDR3_RZQ, output wire HPS_DDR3_WE_N, output wire HPS_ENET_GTX_CLK, inout wire HPS_ENET_INT_N, output wire HPS_ENET_MDC, inout wire HPS_ENET_MDIO, input wire HPS_ENET_RX_CLK, input wire [3:0] HPS_ENET_RX_DATA, input wire HPS_ENET_RX_DV, output wire [3:0] HPS_ENET_TX_DATA, output wire HPS_ENET_TX_EN, inout wire HPS_GSENSOR_INT, inout wire HPS_I2C0_SCLK, inout wire HPS_I2C0_SDAT, inout wire HPS_I2C1_SCLK, inout wire HPS_I2C1_SDAT, inout wire HPS_KEY, inout wire HPS_LED, inout wire HPS_LTC_GPIO, output wire HPS_SD_CLK, inout wire HPS_SD_CMD, inout wire [3:0] HPS_SD_DATA, output wire HPS_SPIM_CLK, input wire HPS_SPIM_MISO, output wire HPS_SPIM_MOSI, inout wire HPS_SPIM_SS, input wire HPS_UART_RX, output wire HPS_UART_TX, input wire HPS_USB_CLKOUT, inout wire [7:0] HPS_USB_DATA, input wire HPS_USB_DIR, input wire HPS_USB_NXT, output wire HPS_USB_STP, //////////// KEY //////////// input wire [1:0] KEY, //////////// LED //////////// output wire [7:0] LED, //////////// SW //////////// input wire [3:0] SW ); //======================================================= // REG/WIRE declarations //======================================================= // DE10-Nano Dev kit and I/O adaptors specific info // import boardtype::*; parameter NumIOAddrReg = 6; parameter LEDCount = 8; parameter NumGPIO = 35; parameter MuxGPIOIOWidth = 35; parameter buswidth = 32; parameter KEY_WIDTH = 2; // REG/WIRE declarations wire hps_fpga_reset_n; wire [1:0] fpga_debounced_buttons; wire [3:0] buttons; wire [LEDCount-1:0] fpga_led_internal; wire [2:0] hps_reset_req; wire hps_cold_reset; wire hps_warm_reset; wire hps_debug_reset; wire fpga_clk_50; //hm2 wire clk_75; // connection of internal logics assign fpga_clk_50 = FPGA_CLK1_50; assign LED[LEDCount-1:1]= fpga_led_internal[LEDCount-2:0]; // hm2 parameter AddrWidth = 16; parameter IOWidth = 68; wire [AddrWidth - 3:0] hm_address; wire [31:0] hm_busdata_out; wire [31:0] hm_datao; wire [31:0] hm_datai; wire hm_read; wire hm_write; wire [3:0] hm_chipsel; wire hm_clk_low; wire hm_clk_med; wire hm_clk_high; wire clklow_sig; wire clkhigh_sig; // wire counter[25:0]; // wire led_level; // Mesa I/O Signals: wire [LEDCount-1:0] hm2_leds_sig; wire [IOWidth-1:0] hm2_bitsout_sig; wire [IOWidth-1:0] hm2_bitsin_sig; wire [MuxLedWidth-1:0] io_leds_sig[NumGPIO-1:0]; wire [MuxGPIOIOWidth-1:0] io_bitsout_sig[NumGPIO-1:0]; wire [MuxGPIOIOWidth-1:0] io_bitsin_sig[NumGPIO-1:0]; // connection of internal logics assign fpga_clk_50 = FPGA_CLK1_50; assign LED[7:1] = fpga_led_internal[6:0]; // irq: wire irq; assign ARDUINO_IO[15] = irq; //======================================================= // Structural coding //======================================================= // HDMI Config ------------------------------------------------------ I2C_HDMI_Config u_I2C_HDMI_Config ( .iCLK(FPGA_CLK1_50), .iRST_N( 1'b1), .I2C_SCLK(HDMI_I2C_SCL), .I2C_SDAT(HDMI_I2C_SDA), .HDMI_TX_INT(HDMI_TX_INT) ); assign HDMI_TX_CLK = clk_75; soc_system u0 ( //Clock&Reset .clk_clk (FPGA_CLK1_50 ), // clk.clk .reset_reset_n (hps_fpga_reset_n ),// reset.reset_n .alt_vip_itc_0_clocked_video_vid_clk (clk_75), // alt_vip_itc_0_clocked_video.vid_clk .alt_vip_itc_0_clocked_video_vid_data (HDMI_TX_D ), // .vid_data .alt_vip_itc_0_clocked_video_underflow ( ), // .underflow .alt_vip_itc_0_clocked_video_vid_datavalid (HDMI_TX_DE), // .vid_datavalid .alt_vip_itc_0_clocked_video_vid_v_sync (HDMI_TX_VS ), // .vid_v_sync .alt_vip_itc_0_clocked_video_vid_h_sync (HDMI_TX_HS ), // .vid_h_sync .alt_vip_itc_0_clocked_video_vid_f ( ), // .vid_f .alt_vip_itc_0_clocked_video_vid_h ( ), // .vid_h .alt_vip_itc_0_clocked_video_vid_v ( ), // .vid_v .lcd_clk_clk (clk_75), // lcd_clk.clk .pll_stream_locked_export (), // pll_stream_locked.export //HPS ddr3 .memory_mem_a ( HPS_DDR3_ADDR), // memory.mem_a .memory_mem_ba ( HPS_DDR3_BA), // .mem_ba .memory_mem_ck ( HPS_DDR3_CK_P), // .mem_ck .memory_mem_ck_n ( HPS_DDR3_CK_N), // .mem_ck_n .memory_mem_cke ( HPS_DDR3_CKE), // .mem_cke .memory_mem_cs_n ( HPS_DDR3_CS_N), // .mem_cs_n .memory_mem_ras_n ( HPS_DDR3_RAS_N), // .mem_ras_n .memory_mem_cas_n ( HPS_DDR3_CAS_N), // .mem_cas_n .memory_mem_we_n ( HPS_DDR3_WE_N), // .mem_we_n .memory_mem_reset_n ( HPS_DDR3_RESET_N), // .mem_reset_n .memory_mem_dq ( HPS_DDR3_DQ), // .mem_dq .memory_mem_dqs ( HPS_DDR3_DQS_P), // .mem_dqs .memory_mem_dqs_n ( HPS_DDR3_DQS_N), // .mem_dqs_n .memory_mem_odt ( HPS_DDR3_ODT), // .mem_odt .memory_mem_dm ( HPS_DDR3_DM), // .mem_dm .memory_oct_rzqin ( HPS_DDR3_RZQ), // .oct_rzqin //HPS ethernet .hps_0_hps_io_hps_io_emac1_inst_TX_CLK(HPS_ENET_GTX_CLK), // hps_0_hps_io.hps_io_emac1_inst_TX_CLK .hps_0_hps_io_hps_io_emac1_inst_TXD0(HPS_ENET_TX_DATA[0]), // .hps_io_emac1_inst_TXD0 .hps_0_hps_io_hps_io_emac1_inst_TXD1(HPS_ENET_TX_DATA[1]), // .hps_io_emac1_inst_TXD1 .hps_0_hps_io_hps_io_emac1_inst_TXD2(HPS_ENET_TX_DATA[2]), // .hps_io_emac1_inst_TXD2 .hps_0_hps_io_hps_io_emac1_inst_TXD3(HPS_ENET_TX_DATA[3]), // .hps_io_emac1_inst_TXD3 .hps_0_hps_io_hps_io_emac1_inst_RXD0(HPS_ENET_RX_DATA[0]), // .hps_io_emac1_inst_RXD0 .hps_0_hps_io_hps_io_emac1_inst_MDIO(HPS_ENET_MDIO), // .hps_io_emac1_inst_MDIO .hps_0_hps_io_hps_io_emac1_inst_MDC(HPS_ENET_MDC), // .hps_io_emac1_inst_MDC .hps_0_hps_io_hps_io_emac1_inst_RX_CTL(HPS_ENET_RX_DV), // .hps_io_emac1_inst_RX_CTL .hps_0_hps_io_hps_io_emac1_inst_TX_CTL(HPS_ENET_TX_EN), // .hps_io_emac1_inst_TX_CTL .hps_0_hps_io_hps_io_emac1_inst_RX_CLK(HPS_ENET_RX_CLK), // .hps_io_emac1_inst_RX_CLK .hps_0_hps_io_hps_io_emac1_inst_RXD1(HPS_ENET_RX_DATA[1]), // .hps_io_emac1_inst_RXD1 .hps_0_hps_io_hps_io_emac1_inst_RXD2(HPS_ENET_RX_DATA[2]), // .hps_io_emac1_inst_RXD2 .hps_0_hps_io_hps_io_emac1_inst_RXD3(HPS_ENET_RX_DATA[3]), // .hps_io_emac1_inst_RXD3 //HPS SD card .hps_0_hps_io_hps_io_sdio_inst_CMD(HPS_SD_CMD), // .hps_io_sdio_inst_CMD .hps_0_hps_io_hps_io_sdio_inst_D0(HPS_SD_DATA[0]), // .hps_io_sdio_inst_D0 .hps_0_hps_io_hps_io_sdio_inst_D1(HPS_SD_DATA[1]), // .hps_io_sdio_inst_D1 .hps_0_hps_io_hps_io_sdio_inst_CLK(HPS_SD_CLK), // .hps_io_sdio_inst_CLK .hps_0_hps_io_hps_io_sdio_inst_D2(HPS_SD_DATA[2]), // .hps_io_sdio_inst_D2 .hps_0_hps_io_hps_io_sdio_inst_D3(HPS_SD_DATA[3]), // .hps_io_sdio_inst_D3 //HPS USB .hps_0_hps_io_hps_io_usb1_inst_D0(HPS_USB_DATA[0]), // .hps_io_usb1_inst_D0 .hps_0_hps_io_hps_io_usb1_inst_D1(HPS_USB_DATA[1]), // .hps_io_usb1_inst_D1 .hps_0_hps_io_hps_io_usb1_inst_D2(HPS_USB_DATA[2]), // .hps_io_usb1_inst_D2 .hps_0_hps_io_hps_io_usb1_inst_D3(HPS_USB_DATA[3]), // .hps_io_usb1_inst_D3 .hps_0_hps_io_hps_io_usb1_inst_D4(HPS_USB_DATA[4]), // .hps_io_usb1_inst_D4 .hps_0_hps_io_hps_io_usb1_inst_D5(HPS_USB_DATA[5]), // .hps_io_usb1_inst_D5 .hps_0_hps_io_hps_io_usb1_inst_D6(HPS_USB_DATA[6]), // .hps_io_usb1_inst_D6 .hps_0_hps_io_hps_io_usb1_inst_D7(HPS_USB_DATA[7]), // .hps_io_usb1_inst_D7 .hps_0_hps_io_hps_io_usb1_inst_CLK(HPS_USB_CLKOUT), // .hps_io_usb1_inst_CLK .hps_0_hps_io_hps_io_usb1_inst_STP(HPS_USB_STP), // .hps_io_usb1_inst_STP .hps_0_hps_io_hps_io_usb1_inst_DIR(HPS_USB_DIR), // .hps_io_usb1_inst_DIR .hps_0_hps_io_hps_io_usb1_inst_NXT(HPS_USB_NXT), // .hps_io_usb1_inst_NXT //HPS SPI .hps_0_hps_io_hps_io_spim1_inst_CLK(HPS_SPIM_CLK), // .hps_io_spim1_inst_CLK .hps_0_hps_io_hps_io_spim1_inst_MOSI(HPS_SPIM_MOSI), // .hps_io_spim1_inst_MOSI .hps_0_hps_io_hps_io_spim1_inst_MISO(HPS_SPIM_MISO), // .hps_io_spim1_inst_MISO .hps_0_hps_io_hps_io_spim1_inst_SS0(HPS_SPIM_SS), // .hps_io_spim1_inst_SS0 //HPS UART .hps_0_hps_io_hps_io_uart0_inst_RX(HPS_UART_RX), // .hps_io_uart0_inst_RX .hps_0_hps_io_hps_io_uart0_inst_TX(HPS_UART_TX), // .hps_io_uart0_inst_TX //HPS I2C1 .hps_0_hps_io_hps_io_i2c0_inst_SDA(HPS_I2C0_SDAT), // .hps_io_i2c0_inst_SDA .hps_0_hps_io_hps_io_i2c0_inst_SCL(HPS_I2C0_SCLK), // .hps_io_i2c0_inst_SCL //HPS I2C2 .hps_0_hps_io_hps_io_i2c1_inst_SDA(HPS_I2C1_SDAT), // .hps_io_i2c1_inst_SDA .hps_0_hps_io_hps_io_i2c1_inst_SCL(HPS_I2C1_SCLK), // .hps_io_i2c1_inst_SCL //GPIO .hps_0_hps_io_hps_io_gpio_inst_GPIO09(HPS_CONV_USB_N), // .hps_io_gpio_inst_GPIO09 .hps_0_hps_io_hps_io_gpio_inst_GPIO35(HPS_ENET_INT_N), // .hps_io_gpio_inst_GPIO35 .hps_0_hps_io_hps_io_gpio_inst_GPIO40(HPS_LTC_GPIO), // .hps_io_gpio_inst_GPIO40 .hps_0_hps_io_hps_io_gpio_inst_GPIO53(HPS_LED), // .hps_io_gpio_inst_GPIO53 .hps_0_hps_io_hps_io_gpio_inst_GPIO54(HPS_KEY), // .hps_io_gpio_inst_GPIO54 .hps_0_hps_io_hps_io_gpio_inst_GPIO61(HPS_GSENSOR_INT), // .hps_io_gpio_inst_GPIO61 //FPGA Partion .led_pio_export(fpga_led_internal[6:0]), // led_pio_external_connection.export .dipsw_pio_export(SW), // dipsw_pio_external_connection.export .button_pio_export(fpga_debounced_buttons), // button_pio_external_connection.export .hps_0_h2f_reset_reset_n(hps_fpga_reset_n), // hps_0_h2f_reset.reset_n // hm2reg_io_0_conduit .mk_io_hm2_dataout(hm_datai), // hm2reg.hm2_dataout .mk_io_hm2_datain(hm_datao), // .hm2_datain .mk_io_hm2_address(hm_address), // .hm2_address // mk_io_hm2_addrout => hm_addri, -- .hm2_address // mk_io_hm2_addrin => hm_addro, -- .hm2_address .mk_io_hm2_write(hm_write), // .hm2_write .mk_io_hm2_read(hm_read), // .hm2_read // mk_io_hm2_chipsel => hm_chipsel, -- .hm2_chipsel // mk_io_hm2_we => hm_chipsel, -- .hm2_chipsel .mk_io_hm2_int_in(irq), // .hm2_int_in .clk_100mhz_out_clk(hm_clk_med), // clk_100mhz_out.clk .clk_200mhz_out_clk(hm_clk_high), // clk_100mhz_out.clk .adc_clk_40mhz_clk(adc_clk_40) ); top_io_modules top_io_modules_inst ( .clk(fpga_clk_50), // input clk_sig .reset_n(hps_fpga_reset_n), // input reset_n_sig .button_in(KEY), // input [KEY_WIDTH-1:0] button_in_sig .button_out(fpga_debounced_buttons), // output [KEY_WIDTH-1:0] button_out_sig .LED(LED[0]) // output LED_sig ); reg [25:0] counter; reg led_level; assign LED[0] = led_level; // Mesa code -------------------------------------------------------- assign clkhigh_sig = hm_clk_high; assign clkmed_sig = hm_clk_med; HostMot2_cfg HostMot2_inst( .ibus(hm_datai), // input [buswidth-1:0] ibus_sig .obus(hm_datao), // output [buswidth-1:0] obus_sig .addr(hm_address), // input [addrwidth-1:2] addr_sig -- addr => A(AddrWidth-1 downto 2), .readstb(hm_read), // input readstb_sig .writestb(hm_write), // input writestb_sig .clklow(fpga_clk_50), // input clklow_sig -- PCI clock --> all .clkmed(hm_clk_med), // input clkmed_sig -- Processor clock --> sserialwa, twiddle .clkhigh(hm_clk_high), // input clkhigh_sig -- High speed clock --> most .irq(irq), // output irq -- int => LINT, ---> PCI ? .dreq(/* open */), // output dreq_sig .demandmode(/* open */), // output demandmode_sig // iobits => -- inout [IOWidth-1:0] -- iobits => IOBITS,-- external I/O bits // GPIO_0 -- DB25-P2 // .iobits[ 0](GPIO_0[16]), // PIN 1 // .iobits[ 1](GPIO_0[17]), // PIN 14 // .iobits[ 2](GPIO_0[14]), // PIN 2 // .iobits[ 3](GPIO_0[15]), // PIN 15 // .iobits[ 4](GPIO_0[12]), // PIN 3 // .iobits[ 5](GPIO_0[13]), // PIN 16 // .iobits[ 6](GPIO_0[10]), // PIN 4 // .iobits[ 7](GPIO_0[11]), // PIN 17 // .iobits[ 8](GPIO_0[08]), // PIN 5 // .iobits[ 9](GPIO_0[09]), // PIN 6 // .iobits[10](GPIO_0[06]), // PIN 7 // .iobits[11](GPIO_0[07]), // PIN 8 // .iobits[12](GPIO_0[04]), // PIN 9 // .iobits[13](GPIO_0[05]), // PIN 10 // .iobits[14](GPIO_0[02]), // PIN 11 // .iobits[15](GPIO_0[03]), // PIN 12 // .iobits[16](GPIO_0[00]), // PIN 13 // GPIO_0 -- DB25-P3 // .iobits[17](GPIO_0[34]), // PIN 1 // .iobits[18](GPIO_0[35]), // PIN 14 // .iobits[19](GPIO_0[32]), // PIN 2 // .iobits[20](GPIO_0[33]), // PIN 15 // .iobits[21](GPIO_0[30]), // PIN 3 // .iobits[22](GPIO_0[31]), // PIN 16 // .iobits[23](GPIO_0[28]), // PIN 4 // .iobits[24](GPIO_0[29]), // PIN 17 // .iobits[25](GPIO_0[26]), // PIN 5 // .iobits[26](GPIO_0[27]), // PIN 6 // .iobits[27](GPIO_0[24]), // PIN 7 // .iobits[28](GPIO_0[25]), // PIN 8 // .iobits[29](GPIO_0[22]), // PIN 9 // .iobits[30](GPIO_0[23]), // PIN 10 // .iobits[31](GPIO_0[20]), // PIN 11 // .iobits[32](GPIO_0[21]), // PIN 12 // .iobits[33](GPIO_0[18]), // PIN 13 // GPIO_1 -- DB25-P2 // .iobits[34](GPIO_1[16]), // PIN 1 // .iobits[35](GPIO_1[17]), // PIN 14 // .iobits[36](GPIO_1[14]), // PIN 2 // .iobits[37](GPIO_1[15]), // PIN 15 // .iobits[38](GPIO_1[12]), // PIN 3 // .iobits[39](GPIO_1[13]), // PIN 16 // .iobits[40](GPIO_1[10]), // PIN 4 // .iobits[41](GPIO_1[11]), // PIN 17 // .iobits[42](GPIO_1[08]), // PIN 5 // .iobits[43](GPIO_1[09]), // PIN 6 // .iobits[44](GPIO_1[06]), // PIN 7 // .iobits[45](GPIO_1[07]), // PIN 8 // .iobits[46](GPIO_1[04]), // PIN 9 // .iobits[47](GPIO_1[05]), // PIN 10 // .iobits[48](GPIO_1[02]), // PIN 11 // .iobits[49](GPIO_1[03]), // PIN 12 // .iobits[50](GPIO_1[00]), // PIN 13 // GPIO_1 -- DB25-P3 // .iobits[51](GPIO_1[34]), // PIN 1 // .iobits[52](GPIO_1[35]), // PIN 14 // .iobits[53](GPIO_1[32]), // PIN 2 // .iobits[54](GPIO_1[33]), // PIN 15 // .iobits[55](GPIO_1[30]), // PIN 3 // .iobits[56](GPIO_1[31]), // PIN 16 // .iobits[57](GPIO_1[28]), // PIN 4 // .iobits[58](GPIO_1[29]), // PIN 17 // .iobits[59](GPIO_1[26]), // PIN 5 // .iobits[60](GPIO_1[27]), // PIN 6 // .iobits[61](GPIO_1[24]), // PIN 7 // .iobits[62](GPIO_1[25]), // PIN 8 // .iobits[63](GPIO_1[22]), // PIN 9 // .iobits[64](GPIO_1[23]), // PIN 10 // .iobits[65](GPIO_1[20]), // PIN 11 // .iobits[66](GPIO_1[21]), // PIN 12 // .iobits[67](GPIO_1[18]), // PIN 13 .iobits( { // GPIO_0 -- DB25-P2 GPIO_0(17), // PIN 14 GPIO_0(14), // PIN 2 GPIO_0(15), // PIN 15 GPIO_0(12), // PIN 3 GPIO_0(13), // PIN 16 GPIO_0(10), // PIN 4 GPIO_0(11), // PIN 17 GPIO_0(08), // PIN 5 GPIO_0(09), // PIN 6 GPIO_0(06), // PIN 7 GPIO_0(07), // PIN 8 GPIO_0(04), // PIN 9 GPIO_0(05), // PIN 10 GPIO_0(02), // PIN 11 GPIO_0(03), // PIN 12 GPIO_0(00), // PIN 13 // GPIO_0 -- DB25-P3 GPIO_0(34), // PIN 1 GPIO_0(35), // PIN 14 GPIO_0(32), // PIN 2 GPIO_0(33), // PIN 15 GPIO_0(30), // PIN 3 GPIO_0(31), // PIN 16 GPIO_0(28), // PIN 4 GPIO_0(29), // PIN 17 GPIO_0(26), // PIN 5 GPIO_0(27), // PIN 6 GPIO_0(24), // PIN 7 GPIO_0(25), // PIN 8 GPIO_0(22), // PIN 9 GPIO_0(23), // PIN 10 GPIO_0(20), // PIN 11 GPIO_0(21), // PIN 12 GPIO_0(18), // PIN 13 // GPIO_1 -- DB25-P2 GPIO_1(16), // PIN 1 GPIO_1(17), // PIN 14 GPIO_1(14), // PIN 2 GPIO_1(15), // PIN 15 GPIO_1(12), // PIN 3 GPIO_1(13), // PIN 16 GPIO_1(10), // PIN 4 GPIO_1(11), // PIN 17 GPIO_1(08), // PIN 5 GPIO_1(09), // PIN 6 GPIO_1(06), // PIN 7 GPIO_1(07), // PIN 8 GPIO_1(04), // PIN 9 GPIO_1(05), // PIN 10 GPIO_1(02), // PIN 11 GPIO_1(03), // PIN 12 GPIO_1(00), // PIN 13 // GPIO_1 -- DB25-P3 GPIO_1(34), // PIN 1 GPIO_1(35), // PIN 14 GPIO_1(32), // PIN 2 GPIO_1(33), // PIN 15 GPIO_1(30), // PIN 3 GPIO_1(31), // PIN 16 GPIO_1(28), // PIN 4 GPIO_1(29), // PIN 17 GPIO_1(26), // PIN 5 GPIO_1(27), // PIN 6 GPIO_1(24), // PIN 7 GPIO_1(25), // PIN 8 GPIO_1(22), // PIN 9 GPIO_1(23), // PIN 10 GPIO_1(20), // PIN 11 GPIO_1(21), // PIN 12 GPIO_1(18) // PIN 13 } ), // .leds[0](GPIO_0[01]), // output [ledcount-1:0] leds_sig -- leds => LEDS // .leds[1](GPIO_0[19]), // .leds[2](GPIO_1[01]), // .leds[3](GPIO_1[19]), .leds( { GPIO_0(01), // output [ledcount-1:0] leds_sig -- leds => LEDS GPIO_0(19), GPIO_1(01), GPIO_1(19) } ), .liobits(/* open */), // inout [lIOWidth-1:0] -- lhm2_iobits .rates(/* open */) // output [4:0] rates_sig ); endmodule