Info: *******************************************************************
Info: Running Quartus Prime Compiler Database Interface
    Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Feb 14 17:50:39 2018
Info: Command: quartus_cdb top -c base --import_design --file base.qdb --overwrite
Info: Quartus(args): --project top -c base --file base.qdb --overwrite
Info: Using INI file /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/quartus.ini
Info: Running design::import_design -file base.qdb -overwrite 
Critical Warning (18639): Skipping database version check for import of database files from  'Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition'. The imported database might be incompatible with current version of the software.
Critical Warning (18639): Skipping database version check for import of database files from  'Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition'. The imported database might be incompatible with current version of the software.
Critical Warning (18639): Skipping database version check for import of database files from  'Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition'. The imported database might be incompatible with current version of the software.
Critical Warning (18639): Skipping database version check for import of database files from  'Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition'. The imported database might be incompatible with current version of the software.
Info (16677): Loading final database
Info (16734): Loading "final" snapshot for partition "root_partition".
Info (16734): Loading "final" snapshot for partition "auto_fab_0".
Info (16734): Loading "final" snapshot for partition "kernel".
Info (16678): Successfully loaded final database: elapsed time is 00:17:21
Info (18230): Checking the imported netlist for invalid settings in the current version of the software.
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Info (23030): Evaluation of Tcl script /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/internal/qatm_import_design.tcl was successful
Info: Quartus Prime Compiler Database Interface was successful. 0 errors, 5 warnings
    Info: Peak virtual memory: 3437 megabytes
    Info: Processing ended: Wed Feb 14 18:16:38 2018
    Info: Elapsed time: 00:25:59
    Info: Total CPU time (on all processors): 00:26:00
Info: *******************************************************************
Info: Running Quartus Prime Fitter
    Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Feb 14 18:16:39 2018
Info: Command: quartus_fit top -c base
Info: Using INI file /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/quartus.ini
Info: qfit2_default_script.tcl version: #1
Info: Project  = top
Info: Revision = base
Info (16677): Loading synthesized database
Info (16734): Loading "final" snapshot for partition "root_partition".
Info (16734): Loading "final" snapshot for partition "auto_fab_0".
Info (16734): Loading "final" snapshot for partition "kernel".
Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:08
Info (19078): Instance assignments in read-only partitions are ignored:
    Info (19079): Ignored assignment "LOCATION PIN_AM21 -to config_clk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AP26 -to kernel_pll_refclk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AL9 -to ddr0_pll_ref_clk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_E5 -to ddr1_pll_ref_clk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AP24 -to one_pps" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AL29 -to pcie_refclk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AW16 -to perstl0_n" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AN33 -to hip_serial_rx_in[0]" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AM31 -to hip_serial_rx_in[1]" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AM35 -to hip_serial_rx_in[2]" because target belongs to a read-only partition "|"
    Info (19080): Additional 362 ignored instance assignments are not displayed.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_pipe_stage_host_sch/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/flash/flash_clock_cross_flash/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_clock_cross_kernel_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_clock_cross_pcie_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_clock_cross_pcie_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "board/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_clk_gen/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_interface/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "board/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_clk_gen/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_interface/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_memory_bank_divider/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_reset_controller_global/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_reset_controller_pcie/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/ddr3a/ddr3a_ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/ddr3b/dd3rb_ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/flash/flash_reset_controller/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr3a_pipe/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr3b_pipe/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "mem/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/dd3rb_ddr3b_altera_emif_arch_nf_171_lfxywli.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/ddr3a_ddr3a_altera_emif_arch_nf_171_kvxwm2y.sdc". Evaluation of this SDC file will be skipped.
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (119006): Selected device 10AX115N3F40E2SG for design "base"
Info (21077): Core supply voltage is 0.95V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 100 degrees C
Warning (18550): Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example.
    Info (119043): Atom "board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|cal_slave_component|ioaux_soft_ram|the_altsyncram|auto_generated|ram_block1a0" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning (176050): Can't implement Global Signal option for node "ddr1_pll_ref_clk~input" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected
Warning (176050): Can't implement Global Signal option for node "ddr0_pll_ref_clk~input" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected
Info (12262): Starting Fitter periphery placement operations
Info (12290): Loading the periphery placement data.
Info (12291): Periphery placement data loaded: elapsed time is 00:00:20
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (12789): Real-time CRC ERROR_CHECK_FREQUENCY_DIVISOR value (1) in design does not match value (2) in the Quartus Prime Settings File
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Info (16210): Plan updated with currently enabled project assignments.
Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:00:00
Info (11178): Promoted 16 clocks (12 global, 2 regional, 2 periphery)
    Info (13173): board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|outclk[0]~CLKENA0 (67091 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2J_G_I5
    Info (13173): board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|outclk[1]~CLKENA0 (9 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2J_G_I2
    Info (13173): freeze_wrapper_inst|kernel_system_clock_reset_reset_reset_n~CLKENA0 (20574 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2I_G_I0
    Info (13173): board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_c_counters[3]~CLKENA0 (184 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3B_G_I16
    Info (13173): ddr0_pll_ref_clk~inputCLKENA0 (21 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3B_G_I23
    Info (13173): board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|non_hps.core_clks_rsts_inst|clk_gen_hmc.hr_qr.clk_gen_master.emif_usr_clk_buf (13760 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3G_G_I26
    Info (13173): board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|non_hps.core_clks_rsts_inst|clk_gen_hmc.hr_qr.clk_gen_master.emif_usr_clk_buf (10282 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3B_G_I28
    Info (13173): board_inst|kernel_interface|kernel_interface|reset_controller_sw|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 (4137 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1G_G_I10
    Info (13173): board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys~CORE_CLK_OUTCLKENA0 (43210 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1D_G_I15
    Info (13173): board_inst|flash|config_iopll|config_iopll|altera_iopll_i|twentynm_pll|outclk[0]~CLKENA0 (1511 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2G_G_I4
    Info (13173): config_clk~inputCLKENA0 (1890 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2I_G_I6
    Info (13173): ddr1_pll_ref_clk~inputCLKENA0 (21 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3G_G_I22
    Info (13173): board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0 (1005 fanout) drives Regional Clock Region 2, with the buffer placed at CLKCTRL_1H_R2_I2
    Info (13173): board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0 (1389 fanout) drives Regional Clock Region 2, with the buffer placed at CLKCTRL_1H_R2_I1
    Info (13173): board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0 (992 fanout) drives Periphery Clock Region 2, with the buffer placed at CLKCTRL_1H_P2_I11
    Info (13173): board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0 (1393 fanout) drives Periphery Clock Region 2, with the buffer placed at CLKCTRL_1H_P2_I8
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176219): No registers were packed into other blocks
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity alt_xcvr_resync
        Info (332166): set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}
    Info (332165): Entity altera_std_synchronizer
        Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
    Info (332165): Entity altpcie_reset_delay_sync
        Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]]
    Info (332165): Entity altpcie_sc_bitsync
        Info (332166): set_multicycle_path -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3
        Info (332166): set_false_path -hold -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]]
        Info (332166): set_multicycle_path -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3
        Info (332166): set_false_path -hold -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]]
    Info (332165): Entity dcfifo_6ei1
        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_3v8:dffpipe16|dffe17a* 
        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_2v8:dffpipe13|dffe14a* 
    Info (332165): Entity alt_sld_fab_0_altera_a10_xcvr_reset_sequencer_171_2ufaxda
        Info (332166): if { [get_collection_size [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o]] > 0 } { create_clock -name ~ALTERA_CLKUSR~ -period 8 [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o] }
Warning (332174): Ignored filter at qfit2_default_fitter_flow.tcl(340): *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*] could not be matched with a keeper File: /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
Warning (332049): Ignored set_multicycle_path at qfit2_default_fitter_flow.tcl(340): Argument <to> is an empty collection File: /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
    Info (332050): eval "fit_plan $create_fitter_netlist_args" File: /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
Warning (332049): Ignored set_false_path at qfit2_default_fitter_flow.tcl(340): Argument <to> is an empty collection File: /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
    Info (332050): eval "fit_plan $create_fitter_netlist_args" File: /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:02.
Info (332104): Reading SDC File: 'top.sdc'
Info (332104): Reading SDC File: 'kernel_system/altera_reset_controller_171/synth/altera_reset_controller.sdc'
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'board/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'board/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/altera_xcvr_native_a10_false_paths.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_pcie/altera_xcvr_native_a10_171/synth/altera_xcvr_native_a10_false_paths.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_pcie/altera_pcie_a10_hip_171/synth/altera_pci_express.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/flash/flash_clock_cross_flash/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_reset_controller_pcie/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_memory_bank_divider/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_kernel_clk_gen/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_kernel_clk_gen/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/flash/flash_reset_controller/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_pipe_stage_host_sch/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_clock_cross_kernel_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_clock_cross_pcie_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_reset_controller_ddr3b_pipe/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_clock_cross_pcie_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_kernel_interface/mem_org_mode_100/synth/mem_org_mode.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_kernel_interface/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_kernel_interface/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_reset_controller_global/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_reset_controller_ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/flash/flash_pll_locked_to_reset/nalla_locked_to_reset_11/synth/nalla_locked_to_reset.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_temperature/acl_temperature_a10_151/synth/temp_sense_a10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_reset_controller_ddr3a_pipe/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'mem/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_reset_controller_ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/ddr3a_ddr3a_altera_emif_arch_nf_171_kvxwm2y.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/ddr3a/ddr3a_ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_alt_pr/alt_pr_171/synth/rtl/alt_pr.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/dd3rb_ddr3b_altera_emif_arch_nf_171_lfxywli.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/ddr3b/dd3rb_ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/mem/mem_uniphy_status_20nm/uniphy_status_20nm_141/synth/uniphy_status_20nm.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332104): Reading SDC File: 'top_post.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|rx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|rx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|rx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|rx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|rx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|rx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys|pll_fixed_clk_central} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|wys~CORE_CLK_OUT} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys|core_clk_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys~CORE_CLK_OUTCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|pcie|pld_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys|pld_clk}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -duty_cycle 50.00 -name {board_inst|pcie|hip_cmn_clk[0]} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pld_pcs_interface.inst_twentynm_hssi_common_pld_pcs_interface|hip_cmn_clk[0]}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|avmmclk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|avmmclk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|avmmclk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|avmmclk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|avmmclk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|avmmclk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|avmmclk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|avmmclk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_refclk_select_inst|refclk} -multiply_by 25 -duty_cycle 50.00 -name {board_inst|pcie|tx_serial_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_inst|clk0}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_refclk_select_inst|refclk} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|pll_pcie_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_inst|hclk_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_lc_refclk_select_mux_inst|lvpecl_in} -multiply_by 40 -duty_cycle 50.00 -name {board_inst|pcie|twentynm_atx_pll_inst~O_CLK0_8G} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst|clk0_8g}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pld_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|tx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|tx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|tx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|tx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|tx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|tx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|tx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[2]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[2]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[2]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|rx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[2]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|rx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|tx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|rx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|rx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|tx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|rx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|rx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|tx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|tx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|tx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|tx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|tx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|tx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|tx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|rx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|rx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|tx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|rx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|rx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|tx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|rx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|rx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|tx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|clk_fpll_b} -divide_by 16 -duty_cycle 50.00 -name {board_inst|pcie|tx_bonding_clocks[0]} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u0|xcvr_fpll_a10_0|fpll_refclk_select_inst|ref_iqclk[2]} -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch0|mcgb_serial_clk} {board_inst|sl2_ch0|sl2_ch0|u0|xcvr_fpll_a10_0|twentynm_hssi_pma_cgb_master_inst|cpulse_out_bus[5]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u0|xcvr_fpll_a10_0|fpll_refclk_select_inst|refclk} -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch1|mcgb_serial_clk} {board_inst|sl2_ch1|sl2_ch1|u0|xcvr_fpll_a10_0|twentynm_hssi_pma_cgb_master_inst|cpulse_out_bus[5]}
    Info (332110): create_generated_clock -source {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]} -divide_by 4 -multiply_by 6 -duty_cycle 50.00 -name {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|outclk0} {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|iopll_inst|outclk[0]}
    Info (332110): create_generated_clock -source {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]} -divide_by 2 -multiply_by 6 -duty_cycle 50.00 -name {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|outclk1} {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|iopll_inst|outclk[1]}
    Info (332110): create_generated_clock -source {board_inst|flash|config_iopll|config_iopll|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]} -divide_by 24 -multiply_by 6 -duty_cycle 50.00 -name {board_inst|flash|config_iopll|config_iopll|outclk0} {board_inst|flash|config_iopll|config_iopll|altera_iopll_i|twentynm_pll|iopll_inst|outclk[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst|pll_cascade_in} -divide_by 2 -multiply_by 4 -phase 22.50 -duty_cycle 50.00 -name {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|phy_clk[0]} {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst|loaden[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst|pll_cascade_in} -divide_by 4 -multiply_by 4 -phase 11.25 -duty_cycle 50.00 -name {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|phy_clk[1]} {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst|lvds_clk[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst|pll_cascade_in} -divide_by 7 -multiply_by 4 -duty_cycle 50.00 -name {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_c_counters[3]} {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst|outclk[3]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst|pll_cascade_in} -divide_by 2 -multiply_by 4 -phase 22.50 -duty_cycle 50.00 -name {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|phy_clk[0]} {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst|loaden[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst|pll_cascade_in} -divide_by 4 -multiply_by 4 -phase 11.25 -duty_cycle 50.00 -name {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|phy_clk[1]} {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst|lvds_clk[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate|pll_cascade_in} -divide_by 2 -multiply_by 4 -phase 22.50 -duty_cycle 50.00 -name {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_DuplicateLOADEN0} {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate|loaden[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate|pll_cascade_in} -divide_by 4 -multiply_by 4 -phase 11.25 -duty_cycle 50.00 -name {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_DuplicateLVDS_CLK0} {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate|lvds_clk[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|pll_cascade_in} -divide_by 2 -multiply_by 4 -phase 22.50 -duty_cycle 50.00 -name {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LOADEN0} {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|loaden[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|pll_cascade_in} -divide_by 4 -multiply_by 4 -phase 11.25 -duty_cycle 50.00 -name {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LVDS_CLK0} {board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|lvds_clk[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate|pll_cascade_in} -divide_by 2 -multiply_by 4 -phase 22.50 -duty_cycle 50.00 -name {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_DuplicateLOADEN0} {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate|loaden[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate|pll_cascade_in} -divide_by 4 -multiply_by 4 -phase 11.25 -duty_cycle 50.00 -name {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_DuplicateLVDS_CLK0} {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate|lvds_clk[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|pll_cascade_in} -divide_by 2 -multiply_by 4 -phase 22.50 -duty_cycle 50.00 -name {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LOADEN0} {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|loaden[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|pll_cascade_in} -divide_by 4 -multiply_by 4 -phase 11.25 -duty_cycle 50.00 -name {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LVDS_CLK0} {board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|lvds_clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at top_post.sdc(53): acl_hmcc_wrapper_inst|* could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 53
Warning (332174): Ignored filter at top_post.sdc(57): ddr0_mem_dqs[0]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 57
Warning (332174): Ignored filter at top_post.sdc(57): ddr0_mem_dqs[1]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 57
Warning (332174): Ignored filter at top_post.sdc(57): ddr0_mem_dqs[2]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 57
Warning (332174): Ignored filter at top_post.sdc(57): ddr0_mem_dqs[3]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 57
Warning (332174): Ignored filter at top_post.sdc(57): ddr0_mem_dqs[4]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 57
Warning (332174): Ignored filter at top_post.sdc(57): ddr0_mem_dqs[5]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 57
Warning (332174): Ignored filter at top_post.sdc(57): ddr0_mem_dqs[6]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 57
Warning (332174): Ignored filter at top_post.sdc(57): ddr0_mem_dqs[7]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 57
Warning (332174): Ignored filter at top_post.sdc(67): ddr1_mem_dqs[0]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 67
Warning (332174): Ignored filter at top_post.sdc(67): ddr1_mem_dqs[1]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 67
Warning (332174): Ignored filter at top_post.sdc(67): ddr1_mem_dqs[2]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 67
Warning (332174): Ignored filter at top_post.sdc(67): ddr1_mem_dqs[3]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 67
Warning (332174): Ignored filter at top_post.sdc(67): ddr1_mem_dqs[4]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 67
Warning (332174): Ignored filter at top_post.sdc(67): ddr1_mem_dqs[5]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 67
Warning (332174): Ignored filter at top_post.sdc(67): ddr1_mem_dqs[6]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 67
Warning (332174): Ignored filter at top_post.sdc(67): ddr1_mem_dqs[7]_IN could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 67
Warning (332174): Ignored filter at top_post.sdc(33): a10_internal_oscillator_clock0 could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 33
Warning (332174): Ignored filter at top_post.sdc(33): altera_ts_clk could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 33
Warning (332054): Assignment set_clock_groups is accepted but has some problems at top_post.sdc(33): Argument -group with value   a10_internal_oscillator_clock0   could not match any element of the following types: ( clk ) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 33
    Info (332050): set_clock_groups -asynchronous \
-group { \
   config_clk \
} -group { \
   a10_internal_oscillator_clock0 \
} -group { \
   altera_ts_clk \
} -group { \
   ddr0_pll_ref_clk \
} -group { \
   ddr1_pll_ref_clk \
} -group { \
   qsfp0_refclk0 \
} -group { \
   kernel_pll_refclk \
} -group [get_clocks { \
   pcie_refclk \
   board_inst|pcie|* \
}] -group [get_clocks { \
   board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|* \
}] -group [get_clocks { \
   acl_hmcc_wrapper_inst|* \
}] -group { \
   altera_reserved_tck \
} -group [get_clocks { \
   ddr0_mem_dqs[0]_IN \
   ddr0_mem_dqs[1]_IN \
   ddr0_mem_dqs[2]_IN \
   ddr0_mem_dqs[3]_IN \
   ddr0_mem_dqs[4]_IN \
   ddr0_mem_dqs[5]_IN \
   ddr0_mem_dqs[6]_IN \
   ddr0_mem_dqs[7]_IN \
   board_inst|mem|ddr3a|ddr3a|* \
}] -group [get_clocks { \
   ddr1_mem_dqs[0]_IN \
   ddr1_mem_dqs[1]_IN \
   ddr1_mem_dqs[2]_IN \
   ddr1_mem_dqs[3]_IN \
   ddr1_mem_dqs[4]_IN \
   ddr1_mem_dqs[5]_IN \
   ddr1_mem_dqs[6]_IN \
   ddr1_mem_dqs[7]_IN \
   board_inst|mem|ddr3b|ddr3b|* \
}] -group { \
   board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_pma_div_clk \
} -group { \
   board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_pma_div_clk \
} -group { \
   board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_pma_div_clk \
} -group { \
   board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_pma_div_clk \
} File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 33
Warning (332054): Assignment set_clock_groups is accepted but has some problems at top_post.sdc(33): Argument -group with value   altera_ts_clk   could not match any element of the following types: ( clk ) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 33
Warning (332054): Assignment set_clock_groups is accepted but has some problems at top_post.sdc(33): Argument -group with value [get_clocks {  acl_hmcc_wrapper_inst|*  }] contains zero elements File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/top_post.sdc Line: 33
Critical Warning: Compiling with slowed OpenCL Kernel clock.  This is to help achieve timing closure for board bringup.
Info (332104): Reading SDC File: '/home/rdnode/intelFPGA_pro/17.1/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc'
Info (19449): Reading SDC files elapsed 00:00:01.
Warning (332060): Node: ddr0_mem_dqs[0] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~low_dff_a is being clocked by ddr0_mem_dqs[0]
Warning (332060): Node: ddr0_mem_dqs[1] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~low_dff_a is being clocked by ddr0_mem_dqs[1]
Warning (332060): Node: ddr0_mem_dqs[2] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~low_dff_a is being clocked by ddr0_mem_dqs[2]
Warning (332060): Node: ddr0_mem_dqs[3] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[3].lane_inst~low_dff_a is being clocked by ddr0_mem_dqs[3]
Warning (332060): Node: ddr0_mem_dqs[4] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~low_dff_a is being clocked by ddr0_mem_dqs[4]
Warning (332060): Node: ddr0_mem_dqs[5] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst~low_dff_a is being clocked by ddr0_mem_dqs[5]
Warning (332060): Node: ddr0_mem_dqs[6] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[1].lane_inst~low_dff_a is being clocked by ddr0_mem_dqs[6]
Warning (332060): Node: ddr0_mem_dqs[7] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst~low_dff_a is being clocked by ddr0_mem_dqs[7]
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: ddr1_mem_dqs[0] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~low_dff_a is being clocked by ddr1_mem_dqs[0]
Warning (332060): Node: ddr1_mem_dqs[1] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~low_dff_a is being clocked by ddr1_mem_dqs[1]
Warning (332060): Node: ddr1_mem_dqs[2] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~low_dff_a is being clocked by ddr1_mem_dqs[2]
Warning (332060): Node: ddr1_mem_dqs[3] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[3].lane_inst~low_dff_a is being clocked by ddr1_mem_dqs[3]
Warning (332060): Node: ddr1_mem_dqs[4] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~low_dff_a is being clocked by ddr1_mem_dqs[4]
Warning (332060): Node: ddr1_mem_dqs[5] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst~low_dff_a is being clocked by ddr1_mem_dqs[5]
Warning (332060): Node: ddr1_mem_dqs[6] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[1].lane_inst~low_dff_a is being clocked by ddr1_mem_dqs[6]
Warning (332060): Node: ddr1_mem_dqs[7] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst~low_dff_a is being clocked by ddr1_mem_dqs[7]
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 138 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):   66.667 altera_reserved_tck
    Info (332111):   40.000 board_inst|flash|config_iopll|config_iopll|outclk0
    Info (332111):    2.500 board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|outclk0
    Info (332111):    1.250 board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|outclk1
    Info (332111):    1.875 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|phy_clk[0]
    Info (332111):    3.750 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|phy_clk[1]
    Info (332111):    6.562 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_c_counters[3]
    Info (332111):    1.875 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LOADEN0
    Info (332111):    3.750 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LVDS_CLK0
    Info (332111):    1.875 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_DuplicateLOADEN0
    Info (332111):    3.750 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_DuplicateLVDS_CLK0
    Info (332111):    1.875 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|phy_clk[0]
    Info (332111):    3.750 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|phy_clk[1]
    Info (332111):    1.875 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LOADEN0
    Info (332111):    3.750 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LVDS_CLK0
    Info (332111):    1.875 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_DuplicateLOADEN0
    Info (332111):    3.750 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_DuplicateLVDS_CLK0
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[0]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[0]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[0]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[0]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[0]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[0]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[1]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[1]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[1]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[1]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[1]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[1]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[2]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[2]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[2]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[2]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[2]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[2]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[3]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[3]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[3]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[3]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[3]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[3]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[4]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[4]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[4]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[4]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[4]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[4]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[5]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[5]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[5]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[5]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[5]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[5]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[6]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[6]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[6]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[6]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[6]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[6]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[7]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[7]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[7]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[7]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[7]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[7]|tx_clk
    Info (332111):    2.000 board_inst|pcie|hip_cmn_clk[0]
    Info (332111):    4.000 board_inst|pcie|pld_clk
    Info (332111):    2.000 board_inst|pcie|pll_pcie_clk
    Info (332111):    0.250 board_inst|pcie|twentynm_atx_pll_inst~O_CLK0_8G
    Info (332111):    6.400 board_inst|pcie|tx_bonding_clocks[0]
    Info (332111):   25.600 board_inst|pcie|tx_clkout
    Info (332111):    0.400 board_inst|pcie|tx_serial_clk
    Info (332111):    4.000 board_inst|pcie|wys~CORE_CLK_OUT
    Info (332111):   10.000 board_inst|sl2_ch0|g_xcvr_native_insts[0]|avmmclk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_pma_div_clk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_pma_div_clk
    Info (332111):   10.000 board_inst|sl2_ch0|g_xcvr_native_insts[1]|avmmclk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[1]|rx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch0|g_xcvr_native_insts[1]|rx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[1]|rx_pma_div_clk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[1]|tx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch0|g_xcvr_native_insts[1]|tx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[1]|tx_pma_div_clk
    Info (332111):   10.000 board_inst|sl2_ch0|g_xcvr_native_insts[2]|avmmclk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[2]|rx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch0|g_xcvr_native_insts[2]|rx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[2]|rx_pma_div_clk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[2]|tx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch0|g_xcvr_native_insts[2]|tx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[2]|tx_pma_div_clk
    Info (332111):   10.000 board_inst|sl2_ch0|g_xcvr_native_insts[3]|avmmclk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[3]|rx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch0|g_xcvr_native_insts[3]|rx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[3]|rx_pma_div_clk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[3]|tx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch0|g_xcvr_native_insts[3]|tx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch0|g_xcvr_native_insts[3]|tx_pma_div_clk
    Info (332111):    0.193 board_inst|sl2_ch0|mcgb_serial_clk
    Info (332111):   10.000 board_inst|sl2_ch1|g_xcvr_native_insts[0]|avmmclk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_pma_div_clk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_pma_div_clk
    Info (332111):   10.000 board_inst|sl2_ch1|g_xcvr_native_insts[1]|avmmclk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[1]|rx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch1|g_xcvr_native_insts[1]|rx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[1]|rx_pma_div_clk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[1]|tx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch1|g_xcvr_native_insts[1]|tx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[1]|tx_pma_div_clk
    Info (332111):   10.000 board_inst|sl2_ch1|g_xcvr_native_insts[2]|avmmclk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[2]|rx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch1|g_xcvr_native_insts[2]|rx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[2]|rx_pma_div_clk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[2]|tx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch1|g_xcvr_native_insts[2]|tx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[2]|tx_pma_div_clk
    Info (332111):   10.000 board_inst|sl2_ch1|g_xcvr_native_insts[3]|avmmclk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[3]|rx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch1|g_xcvr_native_insts[3]|rx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[3]|rx_pma_div_clk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[3]|tx_coreclkin
    Info (332111):    6.206 board_inst|sl2_ch1|g_xcvr_native_insts[3]|tx_pma_clk
    Info (332111):    6.400 board_inst|sl2_ch1|g_xcvr_native_insts[3]|tx_pma_div_clk
    Info (332111):    0.193 board_inst|sl2_ch1|mcgb_serial_clk
    Info (332111):   10.000   config_clk
    Info (332111):    3.750 ddr0_pll_ref_clk
    Info (332111):    3.750 ddr1_pll_ref_clk
    Info (332111):    3.750 kernel_pll_refclk
    Info (332111):   10.000  pcie_refclk
    Info (332111):    1.551 qsfp0_refclk0
    Info (332111):    8.000 ~ALTERA_CLKUSR~
Info (12263): Fitter periphery placement operations ending: elapsed time is 00:03:07
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Info (11165): Fitter preparation operations ending: elapsed time is 00:02:54
Info (170189): Fitter placement preparation operations beginning
Critical Warning: Compiling with slowed OpenCL Kernel clock.  This is to help achieve timing closure for board bringup.
Info (14951): The Fitter is using Advanced Physical Optimization.
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:02:37
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:17
Critical Warning: Compiling with slowed OpenCL Kernel clock.  This is to help achieve timing closure for board bringup.
Info (11888): Total time spent on timing analysis during Placement is 85.13 seconds.
Info (170193): Fitter routing operations beginning
Info (170239): Router is attempting to preserve 100.00 percent of routes from an earlier compilation, a user specified Routing Constraints File, or internal routing requirements.
Info (170195): Router estimated average interconnect usage is 8% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 56% of the available device resources in the region that extends from location X11_Y71 to location X22_Y81
Critical Warning: Compiling with slowed OpenCL Kernel clock.  This is to help achieve timing closure for board bringup.
Info (11888): Total time spent on timing analysis during Routing is 9.04 seconds.
Info (16607): Fitter routing operations ending: elapsed time is 00:03:33
Info (11888): Total time spent on timing analysis during Post-Routing is 4.68 seconds.
Info (16557): Fitter post-fit operations ending: elapsed time is 00:04:50
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Info: Quartus Prime Fitter was successful. 0 errors, 136 warnings
    Info: Peak virtual memory: 12675 megabytes
    Info: Processing ended: Wed Feb 14 18:36:01 2018
    Info: Elapsed time: 00:19:22
    Info: Total CPU time (on all processors): 00:57:13
Info (19538): Reading SDC files took 00:00:04 cumulatively in this process.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
    Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Feb 14 18:36:03 2018
Info: Command: quartus_asm top -c base
Info: Using INI file /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/quartus.ini
Info (16677): Loading final database
Info (16734): Loading "final" snapshot for partition "root_partition".
Info (16734): Loading "final" snapshot for partition "auto_fab_0".
Info (16734): Loading "final" snapshot for partition "kernel".
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[0]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[1]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[2]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[3]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[4]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[5]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_debugaccess~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_address[0]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_address[1]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_address[2]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_address[3]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_address[4]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_address[5]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_debugaccess~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Info (16678): Successfully loaded final database: elapsed time is 00:00:09
Warning (18890): The CRC error detection clock divisor has been changed to 2, because the previous divisor 1 is not supported by the current device.
Warning (18890): The CRC error detection clock divisor has been changed to 2, because the previous divisor 1 is not supported by the current device.
Warning (18890): The CRC error detection clock divisor has been changed to 2, because the previous divisor 1 is not supported by the current device.
Info: Quartus Prime Assembler was successful. 0 errors, 17 warnings
    Info: Peak virtual memory: 9680 megabytes
    Info: Processing ended: Wed Feb 14 18:37:26 2018
    Info: Elapsed time: 00:01:23
    Info: Total CPU time (on all processors): 00:01:34
Info: *******************************************************************
Info: Running Quartus Prime Compiler Database Interface
    Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Feb 14 18:37:27 2018
Info: Command: quartus_cdb top -c base --export_pr_static_block root_partition --snapshot final --file root_partition.qdb
Info: Quartus(args): --exclude_pr_subblocks --project top -c base --block_name root_partition --snapshot final --file root_partition.qdb
Info: Using INI file /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/quartus.ini
Info: Running design::export_block root_partition -snapshot final -file root_partition.qdb  -exclude_pr_subblocks   
Info (16677): Loading final database
Info (16734): Loading "final" snapshot for partition "root_partition".
Info (16734): Loading "final" snapshot for partition "auto_fab_0".
Info (16734): Loading "final" snapshot for partition "kernel".
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[0]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[1]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[2]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[3]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[4]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[5]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_debugaccess~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_address[0]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_address[1]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_address[2]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_address[3]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_address[4]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_address[5]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem1_debugaccess~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Info (16678): Successfully loaded final database: elapsed time is 00:00:09
Info (23030): Evaluation of Tcl script /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/internal/qatm_export_block.tcl was successful
Info: Quartus Prime Compiler Database Interface was successful. 0 errors, 14 warnings
    Info: Peak virtual memory: 2225 megabytes
    Info: Processing ended: Wed Feb 14 18:37:44 2018
    Info: Elapsed time: 00:00:17
    Info: Total CPU time (on all processors): 00:00:17
Info: *******************************************************************
Info: Running Quartus Prime Shell
    Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Feb 14 18:37:44 2018
Info: Command: quartus_sh --archive -input tmp_list_base_bak -output base_bak.qar
Info: Quartus(args): -qar -input tmp_list_base_bak -output base_bak.qar
Info: Using INI file /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/quartus.ini
Info: qar.tcl version #1
Info: Archive will store files relative to the closest common parent directory
Info (13213): Using common directory /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/
Info: ----------------------------------------------------------
Info: ----------------------------------------------------------
Info: Generated archive 'base_bak.qar'
Info: ----------------------------------------------------------
Info: ----------------------------------------------------------
Info (23030): Evaluation of Tcl script /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/apps/qpm/qar.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 802 megabytes
    Info: Processing ended: Wed Feb 14 18:37:46 2018
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01
Info: *******************************************************************
Info: Running Quartus Prime Shell
    Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Feb 14 18:37:46 2018
Info: Command: quartus_sh --archive -input bak_list.txt -output qdb.qar
Info: Quartus(args): -qar -input bak_list.txt -output qdb.qar
Info: Using INI file /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/quartus.ini
Info: qar.tcl version #1
Info: Archive will store files relative to the closest common parent directory
Info (13213): Using common directory /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/qdb/
Info: ----------------------------------------------------------
Info: ----------------------------------------------------------
Info: Generated archive 'qdb.qar'
Info: ----------------------------------------------------------
Info: ----------------------------------------------------------
Info (23030): Evaluation of Tcl script /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/apps/qpm/qar.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 803 megabytes
    Info: Processing ended: Wed Feb 14 18:37:51 2018
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:05
Info (125061): Changed top-level design entity name to "top"
Info (125061): Changed top-level design entity name to "kernel_system"
Info: *******************************************************************
Info: Running Quartus Prime Synthesis
    Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Feb 14 18:37:52 2018
Info: Command: quartus_syn top -c top_synth
Info: Using INI file /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/quartus.ini
Info: qis_default_flow_script.tcl version: #1
Info: Initializing Synthesis...
Info: Project = "top"
Info: Revision = "top_synth"
Info: Analyzing source files
Warning (16124): Can't analyze file ip/kernel_system/kernel_system_boardtest_sch_system.ip - no such file exists
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem1/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_cra/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_kernel_receiver_cra_cra_ring.ip - no such file exists
Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_kernel_sender_cra_cra_ring.ip - no such file exists
Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_mem_read_writestream_cra_cra_ring.ip - no such file exists
Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_mem_readstream_cra_cra_ring.ip - no such file exists
Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_mem_writestream_cra_cra_ring.ip - no such file exists
Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_nop_cra_cra_ring.ip - no such file exists
Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_reorder_const_cra_cra_ring.ip - no such file exists
Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_sch_loopback0_cra_cra_ring.ip - no such file exists
Warning (16124): Can't analyze file ip/kernel_system/kernel_system_avs_sch_loopback1_cra_cra_ring.ip - no such file exists
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Warning (16124): Can't analyze file .qsys_top_level - no such file exists
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_reset_tx/altera_xcvr_reset_control_171/synth/altera_xcvr_functions.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_reset_rx/altera_xcvr_reset_control_171/synth/altera_xcvr_functions.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_reset_tx/altera_xcvr_reset_control_171/synth/alt_xcvr_resync.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_reset_rx/altera_xcvr_reset_control_171/synth/alt_xcvr_resync.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_reset_tx/altera_xcvr_reset_control_171/synth/altera_xcvr_reset_control.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_reset_rx/altera_xcvr_reset_control_171/synth/altera_xcvr_reset_control.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_reset_tx/altera_xcvr_reset_control_171/synth/alt_xcvr_reset_counter.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_reset_rx/altera_xcvr_reset_control_171/synth/alt_xcvr_reset_counter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_reset_tx/altera_xcvr_reset_control_171/synth/plain_files.txt" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_reset_rx/altera_xcvr_reset_control_171/synth/plain_files.txt" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Warning (16124): Can't analyze file ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/altera_xcvr_native_a10_false_paths.sdc - no such file exists
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/alt_xcvr_resync.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/alt_xcvr_resync.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/alt_xcvr_arbiter.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/alt_xcvr_arbiter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/twentynm_pcs.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/twentynm_pcs.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/twentynm_pma.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/twentynm_pma.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/twentynm_xcvr_avmm.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/twentynm_xcvr_avmm.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/twentynm_xcvr_native.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/twentynm_xcvr_native.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/altera_xcvr_native_a10_functions_h.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/altera_xcvr_native_a10_functions_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/a10_avmm_h.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/a10_avmm_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/alt_xcvr_native_pipe_retry.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/alt_xcvr_native_pipe_retry.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/alt_xcvr_native_avmm_csr.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/alt_xcvr_native_avmm_csr.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/alt_xcvr_native_prbs_accum.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/alt_xcvr_native_prbs_accum.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/alt_xcvr_native_odi_accel.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/alt_xcvr_native_odi_accel.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/alt_xcvr_native_rcfg_arb.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/alt_xcvr_native_rcfg_arb.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Warning (16124): Can't analyze file ip/board/board_pcie/altera_xcvr_native_a10_171/synth/altera_xcvr_native_a10_false_paths.sdc - no such file exists
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/altera_xcvr_native_pcie_dfe_params_h.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/altera_xcvr_native_pcie_dfe_params_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/pcie_mgmt_commands_h.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/pcie_mgmt_commands_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/pcie_mgmt_functions_h.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/pcie_mgmt_functions_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/pcie_mgmt_program.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/pcie_mgmt_program.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/pcie_mgmt_cpu.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/pcie_mgmt_cpu.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/pcie_mgmt_master.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/pcie_mgmt_master.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/altera_xcvr_native_pcie_dfe_ip.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/altera_xcvr_native_pcie_dfe_ip.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_native_a10_171/synth/plain_files.txt" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/plain_files.txt" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_fpll_a10_171/synth/twentynm_xcvr_avmm.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_pll/altera_xcvr_fpll_a10_171/synth/twentynm_xcvr_avmm.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_fpll_a10_171/synth/alt_xcvr_resync.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_pll/altera_xcvr_fpll_a10_171/synth/alt_xcvr_resync.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_fpll_a10_171/synth/altera_xcvr_fpll_a10.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_pll/altera_xcvr_fpll_a10_171/synth/altera_xcvr_fpll_a10.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_fpll_a10_171/synth/a10_avmm_h.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_pll/altera_xcvr_fpll_a10_171/synth/a10_avmm_h.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_fpll_a10_171/synth/alt_xcvr_native_avmm_nf.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_pll/altera_xcvr_fpll_a10_171/synth/alt_xcvr_native_avmm_nf.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_fpll_a10_171/synth/alt_xcvr_pll_embedded_debug.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_pll/altera_xcvr_fpll_a10_171/synth/alt_xcvr_pll_embedded_debug.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_fpll_a10_171/synth/alt_xcvr_pll_avmm_csr.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_pll/altera_xcvr_fpll_a10_171/synth/alt_xcvr_pll_avmm_csr.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_xcvr_fpll_a10_171/synth/plain_files.txt" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/a10_sl2_txrx/xcvr_pll/altera_xcvr_fpll_a10_171/synth/plain_files.txt" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Warning (16124): Can't analyze file ip/board/board_pcie/altera_pcie_a10_hip_171/synth/altera_pci_express.sdc - no such file exists
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pipe_stage_dma_rd_master/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_clock_cross_flash/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_mm_clock_crossing_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_mm_clock_crossing_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_clock_cross_flash/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_clock_cross_flash/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_dcfifo_synchronizer_bundle.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_dcfifo_synchronizer_bundle.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_clock_cross_flash/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_std_synchronizer_nocut.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_std_synchronizer_nocut.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_reset_controller_pcie/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_reset_controller_pcie/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_pipe_stage_ddr3b_dimm_post_0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_pipe_stage_ddr3b_dimm_post_3/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_pipe_stage_ddr3a_dimm_post_final/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_memory_bank_divider/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_memory_bank_divider/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_memory_bank_divider/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_memory_bank_divider/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_memory_bank_divider/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_ddr3b_bridge/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_ddr_calibrate/sw_reset_100/synth/sw_reset.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_sw_reset/sw_reset_100/synth/sw_reset.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/sw_reset_100/synth/sw_reset.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_sw_reset/sw_reset_100/synth/sw_reset.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_merlin_slave_agent_171/synth/altera_merlin_slave_agent.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_agent_171/synth/altera_merlin_slave_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_merlin_slave_agent_171/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_agent_171/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_merlin_traffic_limiter_171/synth/altera_merlin_traffic_limiter.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_traffic_limiter_171/synth/altera_merlin_traffic_limiter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_merlin_traffic_limiter_171/synth/altera_merlin_reorder_memory.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_traffic_limiter_171/synth/altera_merlin_reorder_memory.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_merlin_traffic_limiter_171/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_traffic_limiter_171/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_merlin_traffic_limiter_171/synth/altera_avalon_st_pipeline_base.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_traffic_limiter_171/synth/altera_avalon_st_pipeline_base.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_clock_crosser.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_clock_crosser.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_pipeline_base.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_pipeline_base.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_avalon_st_handshake_clock_crosser_171/synth/altera_std_synchronizer_nocut.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_st_handshake_clock_crosser_171/synth/altera_std_synchronizer_nocut.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_reset_controller/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_reset_controller/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pipe_stage_host_sch/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_mm_clock_crossing_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_mm_clock_crossing_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pipe_stage_host_sch/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pipe_stage_host_sch/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_dcfifo_synchronizer_bundle.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_dcfifo_synchronizer_bundle.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pipe_stage_host_sch/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_std_synchronizer_nocut.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_std_synchronizer_nocut.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_mm_clock_crossing_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_mm_clock_crossing_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_dcfifo_synchronizer_bundle.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_dcfifo_synchronizer_bundle.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_std_synchronizer_nocut.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_std_synchronizer_nocut.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pipe_stage_dma_rdwr_master_512/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_pcie_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_mm_clock_crossing_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_mm_clock_crossing_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_pcie_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_pcie_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_dcfifo_synchronizer_bundle.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_dcfifo_synchronizer_bundle.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_pcie_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_std_synchronizer_nocut.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_std_synchronizer_nocut.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_pipe_stage_ddr3b_dimm_post_1/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_version_id_0/version_id_100/synth/version_id.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/version_id_100/synth/version_id.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pr_base_id/version_id_100/synth/version_id.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/version_id_100/synth/version_id.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_pipe_stage_ddr3b_dimm/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/ddr3b_pipe_stage_ddr3b_dimm_post_final/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_version_id/version_id_100/synth/version_id.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/version_id_100/synth/version_id.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_pipe_stage_ddr3a_dimm_post_1/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_reset_controller_ddr3b_pipe/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_reset_controller_ddr3b_pipe/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pipe_stage_host_ctrl/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3b/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3b/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3b/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3b/altera_merlin_slave_agent_171/synth/altera_merlin_slave_agent.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_agent_171/synth/altera_merlin_slave_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3b/altera_merlin_slave_agent_171/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_agent_171/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3b/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3b/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3b/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3b/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_pcie_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_mm_clock_crossing_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_mm_clock_crossing_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_pcie_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_pcie_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_dcfifo_synchronizer_bundle.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_dcfifo_synchronizer_bundle.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_pcie_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_std_synchronizer_nocut.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_std_synchronizer_nocut.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_pipe_stage_ddr3b_dimm_post_2/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_address_span_extender_171/synth/altera_address_span_extender.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_flash_address_span_extender/altera_address_span_extender_171/synth/altera_address_span_extender.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/sw_reset_100/synth/sw_reset.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_sw_reset/sw_reset_100/synth/sw_reset.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Warning (16124): Can't analyze file ip/board/board_kernel_interface/mem_org_mode_100/synth/mem_org_mode.sdc - no such file exists
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_irq_bridge_171/synth/altera_irq_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_irq/altera_irq_bridge_171/synth/altera_irq_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/version_id_100/synth/version_id.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_clk_gen/version_id_100/synth/version_id.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_slave_agent_171/synth/altera_merlin_slave_agent.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_agent_171/synth/altera_merlin_slave_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_slave_agent_171/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_agent_171/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_clock_crosser.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_clock_crosser.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_pipeline_base.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_pipeline_base.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_avalon_st_handshake_clock_crosser_171/synth/altera_std_synchronizer_nocut.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_st_handshake_clock_crosser_171/synth/altera_std_synchronizer_nocut.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_traffic_limiter_171/synth/altera_merlin_traffic_limiter.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_traffic_limiter_171/synth/altera_merlin_traffic_limiter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_traffic_limiter_171/synth/altera_merlin_reorder_memory.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_traffic_limiter_171/synth/altera_merlin_reorder_memory.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_traffic_limiter_171/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_traffic_limiter_171/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_traffic_limiter_171/synth/altera_avalon_st_pipeline_base.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_traffic_limiter_171/synth/altera_avalon_st_pipeline_base.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_width_adapter_171/synth/altera_merlin_width_adapter.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_width_adapter_171/synth/altera_merlin_width_adapter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_width_adapter_171/synth/altera_merlin_address_alignment.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_width_adapter_171/synth/altera_merlin_address_alignment.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_interface/altera_merlin_width_adapter_171/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_width_adapter_171/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_prom_tmp/i2c_opencores_120/synth/i2c_opencores.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_opencores.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_prom_tmp/i2c_opencores_120/synth/i2c_master_top.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_top.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_prom_tmp/i2c_opencores_120/synth/i2c_master_defines.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_defines.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_prom_tmp/i2c_opencores_120/synth/i2c_master_byte_ctrl.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_byte_ctrl.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_prom_tmp/i2c_opencores_120/synth/i2c_master_bit_ctrl.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_bit_ctrl.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pipe_stage_pcie_to_memwindow_ctrl/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_reset_controller_global/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_reset_controller_global/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_reset_controller_ddr3b/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_reset_controller_ddr3b/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3a/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3a/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3a/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3a/altera_merlin_slave_agent_171/synth/altera_merlin_slave_agent.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_agent_171/synth/altera_merlin_slave_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3a/altera_merlin_slave_agent_171/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_agent_171/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3a/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3a/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3a/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ddr3a/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_pipe_stage_ddr3a_dimm_post_0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Warning (16124): Can't analyze file ip/flash/flash_pll_locked_to_reset/nalla_locked_to_reset_11/synth/nalla_locked_to_reset.sdc - no such file exists
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pipe_stage_dma_rdwr_master/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Warning (16124): Can't analyze file ip/board/board_temperature/acl_temperature_a10_151/synth/temp_sense_a10.sdc - no such file exists
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_reset_controller_ddr3a_pipe/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_reset_controller_ddr3a_pipe/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_slave_agent_171/synth/altera_merlin_slave_agent.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_agent_171/synth/altera_merlin_slave_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_slave_agent_171/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_agent_171/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_traffic_limiter_171/synth/altera_merlin_traffic_limiter.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_traffic_limiter_171/synth/altera_merlin_traffic_limiter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_traffic_limiter_171/synth/altera_merlin_reorder_memory.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_traffic_limiter_171/synth/altera_merlin_reorder_memory.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_traffic_limiter_171/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_traffic_limiter_171/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_traffic_limiter_171/synth/altera_avalon_st_pipeline_base.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_traffic_limiter_171/synth/altera_avalon_st_pipeline_base.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_width_adapter_171/synth/altera_merlin_width_adapter.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_width_adapter_171/synth/altera_merlin_width_adapter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_width_adapter_171/synth/altera_merlin_address_alignment.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_width_adapter_171/synth/altera_merlin_address_alignment.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/flash/altera_merlin_width_adapter_171/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_width_adapter_171/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_memwindow/altera_address_span_extender_171/synth/altera_address_span_extender.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_flash_address_span_extender/altera_address_span_extender_171/synth/altera_address_span_extender.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/mem/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/mem/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/mem/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_master_agent_171/synth/altera_merlin_master_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/mem/altera_merlin_slave_agent_171/synth/altera_merlin_slave_agent.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_agent_171/synth/altera_merlin_slave_agent.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/mem/altera_merlin_slave_agent_171/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_slave_agent_171/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/mem/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_avalon_sc_fifo_171/synth/altera_avalon_sc_fifo.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/mem/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/board/altera_merlin_multiplexer_171/synth/altera_merlin_arbitrator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/mem/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/mem/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pipe_stage_pcie_to_memwindow_mem/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch1/A10_SuperLite_II_txrx_10/synth/scrambler.vhd" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/scrambler.vhd" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch1/A10_SuperLite_II_txrx_10/synth/encoder_64b66b.vhd" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/encoder_64b66b.vhd" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch1/A10_SuperLite_II_txrx_10/synth/reset_synchro.vhd" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/reset_synchro.vhd" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch1/A10_SuperLite_II_txrx_10/synth/synchro.vhd" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/synchro.vhd" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch1/A10_SuperLite_II_txrx_10/synth/tx_serial_chan_if.vhd" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/tx_serial_chan_if.vhd" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch1/A10_SuperLite_II_txrx_10/synth/descrambler.vhd" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/descrambler.vhd" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch1/A10_SuperLite_II_txrx_10/synth/decoder_66b64b.vhd" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/decoder_66b64b.vhd" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch1/A10_SuperLite_II_txrx_10/synth/rx_path_deskew.vhd" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/rx_path_deskew.vhd" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch1/A10_SuperLite_II_txrx_10/synth/general_fifo.vhd" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/general_fifo.vhd" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch1/A10_SuperLite_II_txrx_10/synth/a10_sl2_txrx.vhd" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/a10_sl2_txrx.vhd" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_reset_controller_ddr3a/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_reset_controller_ddr3a/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/mem/mem_pipe_stage_ddr3a_dimm/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Warning (16124): Can't analyze file ip/board/board_alt_pr/alt_pr_171/synth/rtl/alt_pr.sdc - no such file exists
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_oct.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_oct.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_df_o.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_df_o.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_bdir_df.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_bdir_df.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_bdir_se.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_bdir_se.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_cp_i.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_cp_i.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_df_i.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_df_i.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_se_i.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_se_i.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_se_o.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_udir_se_o.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_core_clks_rsts.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_core_clks_rsts.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_io_tiles.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_io_tiles.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_io_tiles_abphy.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_io_tiles_abphy.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_pll.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_pll.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/twentynm_io_12_lane_abphy.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/twentynm_io_12_lane_abphy.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/twentynm_io_12_lane_encrypted_abphy.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/twentynm_io_12_lane_encrypted_abphy.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_bufs.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_bufs.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_unused.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_buf_unused.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_cal_counter.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_cal_counter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_pll_fast_sim.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_pll_fast_sim.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_pll_extra_clks.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_pll_extra_clks.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hps_clks_rsts.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hps_clks_rsts.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_io_tiles_wrap.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_io_tiles_wrap.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_abphy_mux.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_abphy_mux.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_avl_if.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_avl_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_sideband_if.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_sideband_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_mmr_if.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_mmr_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_amm_data_if.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_amm_data_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_ast_data_if.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_hmc_ast_data_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_afi_if.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_afi_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_seq_if.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_seq_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_regs.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_emif_arch_nf_regs.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_oct.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_oct.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_oct_um_fsm.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_oct_um_fsm.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/altera_std_synchronizer_nocut.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/altera_std_synchronizer_nocut.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_avalon_onchip_memory2_171/synth/seq_cal_soft_m20k.hex" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3a/ddr3a_ddr3a/altera_avalon_onchip_memory2_171/synth/seq_cal_soft_m20k.hex" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_master_translator_171/synth/altera_merlin_master_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_merlin_slave_translator_171/synth/altera_merlin_slave_translator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_reset_controller_171/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/ddr3b/dd3rb_ddr3b/altera_reset_controller_171/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/altera_reset_controller_171/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_kernel_ddr3a_bridge/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_kernel_mem0/altera_avalon_mm_bridge_171/synth/altera_avalon_mm_bridge.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_por_reset_counter/sw_reset_100/synth/sw_reset.v" is a duplicate of already analyzed file "/home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_sw_reset/sw_reset_100/synth/sw_reset.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Warning (16124): Can't analyze file ip/mem/mem_uniphy_status_20nm/uniphy_status_20nm_141/synth/uniphy_status_20nm.sdc - no such file exists
Warning (13468): Verilog HDL Expression warning at altpcieav128_dma_wr_wdalign.sv(317): truncated literal to match 7 bits File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_pcie/altera_pcie_a10_hip_171/synth/altpcieav128_dma_wr_wdalign.sv Line: 317
Info (16884): Verilog HDL info at i2c_opencores.v(7): analyzing included file ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_defines.v File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_opencores.v Line: 7
Info (13230): Verilog HDL or VHDL information at i2c_opencores.v(7): back to file ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_opencores.v File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_opencores.v Line: 7
Info (16884): Verilog HDL info at i2c_master_top.v(73): analyzing included file ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_defines.v File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_top.v Line: 73
Info (13230): Verilog HDL or VHDL information at i2c_master_top.v(73): back to file ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_top.v File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_top.v Line: 73
Info (16884): Verilog HDL info at i2c_master_byte_ctrl.v(73): analyzing included file ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_defines.v File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_byte_ctrl.v Line: 73
Info (13230): Verilog HDL or VHDL information at i2c_master_byte_ctrl.v(73): back to file ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_byte_ctrl.v File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_byte_ctrl.v Line: 73
Info (16884): Verilog HDL info at i2c_master_bit_ctrl.v(127): analyzing included file ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_defines.v File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_bit_ctrl.v Line: 127
Info (13230): Verilog HDL or VHDL information at i2c_master_bit_ctrl.v(127): back to file ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_bit_ctrl.v File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/flash/flash_i2c_ucd/i2c_opencores_120/synth/i2c_master_bit_ctrl.v Line: 127
Warning (16792): VHDL Association List warning at a10_sl2_txrx.vhd(535): formal rx_pma_div_clkout that is associated individually cannot be associated with actual of OPEN File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/a10_sl2_txrx.vhd Line: 535
Warning (16792): VHDL Association List warning at a10_sl2_txrx.vhd(536): formal rx_pma_div_clkout that is associated individually cannot be associated with actual of OPEN File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/a10_sl2_txrx.vhd Line: 536
Warning (16792): VHDL Association List warning at a10_sl2_txrx.vhd(537): formal rx_pma_div_clkout that is associated individually cannot be associated with actual of OPEN File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/a10_sl2_txrx.vhd Line: 537
Warning (16792): VHDL Association List warning at a10_sl2_txrx.vhd(553): formal tx_pma_div_clkout that is associated individually cannot be associated with actual of OPEN File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/a10_sl2_txrx.vhd Line: 553
Warning (16792): VHDL Association List warning at a10_sl2_txrx.vhd(554): formal tx_pma_div_clkout that is associated individually cannot be associated with actual of OPEN File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/a10_sl2_txrx.vhd Line: 554
Warning (16792): VHDL Association List warning at a10_sl2_txrx.vhd(555): formal tx_pma_div_clkout that is associated individually cannot be associated with actual of OPEN File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/board/board_sl2_ch0/A10_SuperLite_II_txrx_10/synth/a10_sl2_txrx.vhd Line: 555
Warning (13228): Verilog HDL or VHDL warning at acl_embedded_workgroup_issuer_dspba.v(30): 2147483648 as 32-bit signed integer overflows, using -2147483648 instead File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_embedded_workgroup_issuer_dspba.v Line: 30
Warning (13228): Verilog HDL or VHDL warning at acl_embedded_workgroup_issuer.v(21): 2147483648 as 32-bit signed integer overflows, using -2147483648 instead File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_embedded_workgroup_issuer.v Line: 21
Warning (13228): Verilog HDL or VHDL warning at acl_embedded_workgroup_issuer_complex.v(57): 2147483648 as 32-bit signed integer overflows, using -2147483648 instead File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_embedded_workgroup_issuer_complex.v Line: 57
Warning (13228): Verilog HDL or VHDL warning at acl_embedded_workgroup_issuer_fifo.v(21): 2147483648 as 32-bit signed integer overflows, using -2147483648 instead File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_embedded_workgroup_issuer_fifo.v Line: 21
Info: Elaborating from top-level entity "kernel_system"
Info (18235): Library search order is as follows: "kernel_system_clk_1x; kernel_system_clk_2x; kernel_system_clk_snoop; kernel_system_reset; altera_avalon_mm_bridge_171; kernel_system_kernel_mem0; kernel_system_kernel_mem1; channel_adapter_171; altera_avalon_st_adapter_171; kernel_system_kernel_input_ch0; kernel_system_kernel_output_ch0; kernel_system_kernel_input_ch1; kernel_system_kernel_output_ch1; altera_irq_bridge_171; kernel_system_kernel_irq; kernel_system_kernel_cra; cra_ring_root_10; kernel_system_cra_root; cra_ring_rom_10; kernel_system_cra_ring_rom; kernel_system_acl_internal_snoop; acl_rom_module_10; kernel_system_sys_description_rom; altera_merlin_master_translator_171; altera_merlin_slave_translator_171; altera_mm_interconnect_171; altera_irq_mapper_171; altera_reset_controller_171; kernel_system; altera_merlin_master_agent_171; altera_merlin_slave_agent_171; altera_avalon_sc_fifo_171; altera_merlin_router_171; altera_merlin_demultiplexer_171; altera_merlin_multiplexer_171; error_adapter_171; altera_merlin_traffic_limiter_171; altera_merlin_width_adapter_171; altera_avalon_st_handshake_clock_crosser_171; altera_irq_clock_crosser_171; board; altera_xcvr_fpll_a10_171; xcvr_pll; altera_xcvr_reset_control_171; xcvr_reset_rx; xcvr_reset_tx; altera_xcvr_native_a10_171; xcvr_sl2_txrx; altera_pcie_a10_hip_171; altera_xcvr_atx_pll_a10_171; board_pcie; cade_id_10; board_cade_id; board_pipe_stage_dma_rd_master; altera_avalon_mm_clock_crossing_bridge_171; mem_clock_cross_kernel_to_ddr3a; flash_clock_cross_flash; board_global_reset_in; board_reset_controller_pcie; mem_pipe_stage_ddr3b_dimm_post_0; mem_pipe_stage_ddr3b_dimm_post_3; ddr3a_pipe_stage_ddr3a_dimm_post_final; acl_snoop_adapter_110; burst_boundary_splitter_10; mem_splitter_100; acl_memory_bank_divider_10; board_memory_bank_divider; altera_in_system_sources_probes_171; board_in_system_sources_probes_cade_id; ddr3a_reset_bridge_ddr3a; sw_reset_100; flash_sw_reset; altera_address_span_extender_171; flash_flash_address_span_extender; altera_avalon_onchip_memory2_171; board_onchip_memory2_1; mem_global_reset_in; board_kernel_ddr3b_bridge; altera_asmi_parallel_171; altera_epcq_controller_200; altera_epcq_controller_core_200; flash_epcq_controller; mem_ddr_calibrate; mem_pcie_clk_in; acl_timer_100; altera_iopll_171; pll_lock_avs_100; altera_pll_reconfig_171; version_id_100; acl_kernel_clk_a10_161; board_kernel_clk_gen; flash_reset_controller; board_pipe_stage_host_sch; ddr3a_clock_bridge_ddr3a; mem_clock_cross_kernel_to_ddr3b; board_pipe_stage_dma_rdwr_master_512; i2c_opencores_120; flash_i2c_ucd; mem_clock_cross_pcie_to_ddr3a; mem_pipe_stage_ddr3b_dimm_post_1; flash_por_bridge; ddr3b_reset_bridge_dd3b; board_version_id_0; board_pr_base_id; board_a10_status_leds; mem_pipe_stage_ddr3b_dimm; ddr3b_pipe_stage_ddr3b_dimm_post_final; altera_remote_update_core_171; altera_avalon_remote_update_controller_171; altera_remote_update_171; flash_flash_remote_update; board_version_id; mem_pipe_stage_ddr3a_dimm_post_1; mem_reset_controller_ddr3b_pipe; board_pipe_stage_host_ctrl; board_pcie_refclk; ddr3b; mem_clock_cross_pcie_to_ddr3b; mem_pipe_stage_ddr3b_dimm_post_2; global_routing_reset_100; mem_org_mode_100; kernel_interface_151; board_kernel_interface; flash_i2c_prom_tmp; board_pipe_stage_pcie_to_memwindow_ctrl; board_sl2_ch0; flash_pcie_reset_bridge; ddr3b_clock_bridge_ddr3b; board_reset_controller_global; mem_reset_controller_ddr3b; flash_config_iopll; ddr3a; flash_ucd_csr; mem_pipe_stage_ddr3a_dimm_post_0; nalla_locked_to_reset_11; flash_pll_locked_to_reset; board_pipe_stage_dma_rdwr_master; acl_temperature_a10_151; board_temperature; mem_reset_controller_ddr3a_pipe; flash_pcie_clk; flash; board_memwindow; flash_config_clk_bridge; mem; board_pipe_stage_pcie_to_memwindow_mem; board_sl2_ch1; mem_reset_controller_ddr3a; altera_emif_arch_nf_171; altera_emif_cal_slave_nf_171; altera_emif_171; ddr3a_ddr3a; mem_pipe_stage_ddr3a_dimm; board_npor_export; alt_pr_171; board_alt_pr; dd3rb_ddr3b; board_kernel_ddr3a_bridge; pcie_irq_10; board_pcie_irq; board_por_reset_counter; board_kernel_clk; uniphy_status_20nm_141; mem_uniphy_status_20nm; mem_kernel_clk_in; board_config_clk; matrix_mult_system_140; kernel_system_matrix_mult_system; cra_ring_node_10; kernel_system_avs_matrixMult_cra_cra_ring; a10_status_leds_10; a10_superlite_ii_txrx_10; pwr_controlstatus_10". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER.
Warning (13469): Verilog HDL assignment warning at acl_multistage_accumulator.v(196): truncated value with size 115 to match size of target (96) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_multistage_accumulator.v Line: 196
Warning (13469): Verilog HDL assignment warning at acl_multistage_accumulator.v(196): truncated value with size 115 to match size of target (96) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_multistage_accumulator.v Line: 196
Info (16821): Verilog HDL info at matrix_mult_system.v(844): going to vhdl side to elaborate module matrixMult_function_cra_slave File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 844
Info (19337): VHDL info at matrixMult_function_cra_slave.vhd(38): executing entity "matrixMult_function_cra_slave" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_function_cra_slave.vhd Line: 38
Info (16822): Verilog HDL info at matrix_mult_system.v(844): back to verilog to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 844
Warning (13469): Verilog HDL assignment warning at acl_work_item_iterator.v(161): truncated value with size 32 to match size of target (6) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_work_item_iterator.v Line: 161
Warning (13469): Verilog HDL assignment warning at acl_work_item_iterator.v(162): truncated value with size 32 to match size of target (6) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_work_item_iterator.v Line: 162
Warning (13469): Verilog HDL assignment warning at acl_work_item_iterator.v(163): truncated value with size 32 to match size of target (1) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_work_item_iterator.v Line: 163
Warning (13469): Verilog HDL assignment warning at acl_work_item_iterator.v(167): truncated value with size 7 to match size of target (6) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_work_item_iterator.v Line: 167
Warning (13469): Verilog HDL assignment warning at acl_work_item_iterator.v(168): truncated value with size 7 to match size of target (6) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_work_item_iterator.v Line: 168
Warning (13469): Verilog HDL assignment warning at acl_work_item_iterator.v(169): truncated value with size 2 to match size of target (1) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_work_item_iterator.v Line: 169
Warning (16735): Verilog HDL warning at acl_work_item_iterator.v(217): actual bit length 1 differs from formal bit length 32 for port "Q" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_work_item_iterator.v Line: 217
Warning (13469): Verilog HDL assignment warning at acl_multistage_adder.v(140): truncated value with size 19 to match size of target (14) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_multistage_adder.v Line: 140
Info (16821): Verilog HDL info at matrix_mult_system.v(1238): going to vhdl side to elaborate module matrixMult_function_wrapper File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1238
Info (19337): VHDL info at matrixMult_function_wrapper.vhd(38): executing entity "matrixMult_function_wrapper" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_function_wrapper.vhd Line: 38
Info (17560): VHDL info at matrixMult_function_wrapper.vhd(657): going to verilog side to elaborate module acl_embedded_workgroup_issuer_dspba File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_function_wrapper.vhd Line: 657
Warning (13469): Verilog HDL assignment warning at acl_embedded_workgroup_issuer_complex.v(141): truncated value with size 3 to match size of target (2) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_embedded_workgroup_issuer_complex.v Line: 141
Info (17561): VHDL info at matrixMult_function_wrapper.vhd(657): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_function_wrapper.vhd Line: 657
Info (19337): VHDL info at matrixMult_function.vhd(38): executing entity "matrixMult_function" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_function.vhd Line: 38
Info (19337): VHDL info at loop_limiter_matrixMult0.vhd(38): executing entity "loop_limiter_matrixMult0" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/loop_limiter_matrixMult0.vhd Line: 38
Info (17560): VHDL info at loop_limiter_matrixMult0.vhd(119): going to verilog side to elaborate module acl_loop_limiter File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/loop_limiter_matrixMult0.vhd Line: 119
Info (17561): VHDL info at loop_limiter_matrixMult0.vhd(119): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/loop_limiter_matrixMult0.vhd Line: 119
Info (19337): VHDL info at bb_matrixMult_B0.vhd(38): executing entity "bb_matrixMult_B0" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0.vhd Line: 38
Info (19337): VHDL info at matrixMult_B0_merge.vhd(38): executing entity "matrixMult_B0_merge" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_B0_merge.vhd Line: 38
Info (19337): VHDL info at bb_matrixMult_B0_stall_region.vhd(38): executing entity "bb_matrixMult_B0_stall_region" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 38
Info (19337): VHDL info at dspba_library.vhd(18): executing entity "dspba_delay(width=34,depth=0,reset_high='0')(1,5)" with architecture "delay" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dspba_library.vhd Line: 18
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(1244): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1244
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(1244): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1244
Info (19337): VHDL info at dspba_library.vhd(18): executing entity "dspba_delay(width=28,depth=0,reset_high='0')(1,5)" with architecture "delay" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dspba_library.vhd Line: 18
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(1326): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1326
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(1326): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1326
Info (19337): VHDL info at dspba_library.vhd(18): executing entity "dspba_delay(width=36,depth=0,reset_high='0')(1,5)" with architecture "delay" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dspba_library.vhd Line: 18
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(1409): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1409
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(1409): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1409
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(1609): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1609
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(1609): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1609
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(1691): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1691
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(1691): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1691
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(1774): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1774
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(1774): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1774
Info (19337): VHDL info at i_syncbuf_a_width_sync_buffer1_matrixmult5.vhd(38): executing entity "i_syncbuf_a_width_sync_buffer1_matrixmult5" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_a_width_sync_buffer1_matrixmult5.vhd Line: 38
Info (17560): VHDL info at i_syncbuf_a_width_sync_buffer1_matrixmult5.vhd(84): going to verilog side to elaborate module acl_dspba_buffer File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_a_width_sync_buffer1_matrixmult5.vhd Line: 84
Info (17561): VHDL info at i_syncbuf_a_width_sync_buffer1_matrixmult5.vhd(84): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_a_width_sync_buffer1_matrixmult5.vhd Line: 84
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(1915): going to verilog side to elaborate module acl_valid_fifo_counter File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1915
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(1915): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 1915
Info (19337): VHDL info at i_syncbuf_b_width_sync_buffer3_matrixmult11.vhd(38): executing entity "i_syncbuf_b_width_sync_buffer3_matrixmult11" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_b_width_sync_buffer3_matrixmult11.vhd Line: 38
Info (17560): VHDL info at i_syncbuf_b_width_sync_buffer3_matrixmult11.vhd(84): going to verilog side to elaborate module acl_dspba_buffer File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_b_width_sync_buffer3_matrixmult11.vhd Line: 84
Info (17561): VHDL info at i_syncbuf_b_width_sync_buffer3_matrixmult11.vhd(84): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_b_width_sync_buffer3_matrixmult11.vhd Line: 84
Info (19337): VHDL info at i_syncbuf_a_width_sync_buffer_matrixmult9.vhd(38): executing entity "i_syncbuf_a_width_sync_buffer_matrixmult9" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_a_width_sync_buffer_matrixmult9.vhd Line: 38
Info (17560): VHDL info at i_syncbuf_a_width_sync_buffer_matrixmult9.vhd(84): going to verilog side to elaborate module acl_dspba_buffer File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_a_width_sync_buffer_matrixmult9.vhd Line: 84
Info (17561): VHDL info at i_syncbuf_a_width_sync_buffer_matrixmult9.vhd(84): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_a_width_sync_buffer_matrixmult9.vhd Line: 84
Info (19337): VHDL info at i_syncbuf_a_width_sync_buffer2_matrixmult2.vhd(38): executing entity "i_syncbuf_a_width_sync_buffer2_matrixmult2" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_a_width_sync_buffer2_matrixmult2.vhd Line: 38
Info (17560): VHDL info at i_syncbuf_a_width_sync_buffer2_matrixmult2.vhd(84): going to verilog side to elaborate module acl_dspba_buffer File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_a_width_sync_buffer2_matrixmult2.vhd Line: 84
Info (17561): VHDL info at i_syncbuf_a_width_sync_buffer2_matrixmult2.vhd(84): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_a_width_sync_buffer2_matrixmult2.vhd Line: 84
Info (19337): VHDL info at matrixMult_B0_merge_reg.vhd(38): executing entity "matrixMult_B0_merge_reg" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_B0_merge_reg.vhd Line: 38
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(2279): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 2279
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(2279): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 2279
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(2361): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 2361
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(2361): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 2361
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(2456): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 2456
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(2456): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 2456
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(2614): going to verilog side to elaborate module acl_valid_fifo_counter File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 2614
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(2614): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 2614
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(2637): going to verilog side to elaborate module acl_valid_fifo_counter File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 2637
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(2637): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 2637
Info (17560): VHDL info at bb_matrixMult_B0_stall_region.vhd(2660): going to verilog side to elaborate module acl_valid_fifo_counter File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 2660
Info (17561): VHDL info at bb_matrixMult_B0_stall_region.vhd(2660): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B0_stall_region.vhd Line: 2660
Info (19337): VHDL info at matrixMult_B0_branch.vhd(38): executing entity "matrixMult_B0_branch" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_B0_branch.vhd Line: 38
Info (19337): VHDL info at bb_matrixMult_B1_sr_1.vhd(38): executing entity "bb_matrixMult_B1_sr_1" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_sr_1.vhd Line: 38
Info (19337): VHDL info at bb_matrixMult_B1_sr_0.vhd(38): executing entity "bb_matrixMult_B1_sr_0" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_sr_0.vhd Line: 38
Info (19337): VHDL info at bb_matrixMult_B1.vhd(38): executing entity "bb_matrixMult_B1" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1.vhd Line: 38
Info (19337): VHDL info at matrixMult_B1_merge.vhd(38): executing entity "matrixMult_B1_merge" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_B1_merge.vhd Line: 38
Info (19337): VHDL info at priority_encoder.vhd(38): executing entity "priority_encoder" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/priority_encoder.vhd Line: 38
Info (19337): VHDL info at loop_capacity_FIFO.vhd(38): executing entity "loop_capacity_FIFO" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/loop_capacity_FIFO.vhd Line: 38
Info (17560): VHDL info at loop_capacity_FIFO.vhd(112): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/loop_capacity_FIFO.vhd Line: 112
Info (17561): VHDL info at loop_capacity_FIFO.vhd(112): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/loop_capacity_FIFO.vhd Line: 112
Info (19337): VHDL info at bb_matrixMult_B1_stall_region.vhd(38): executing entity "bb_matrixMult_B1_stall_region" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 38
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(3041): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 3041
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(3041): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 3041
Info (19337): VHDL info at i_syncbuf_b_sync_buffer_matrixmult17.vhd(38): executing entity "i_syncbuf_b_sync_buffer_matrixmult17" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_b_sync_buffer_matrixmult17.vhd Line: 38
Info (17560): VHDL info at i_syncbuf_b_sync_buffer_matrixmult17.vhd(84): going to verilog side to elaborate module acl_dspba_buffer File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_b_sync_buffer_matrixmult17.vhd Line: 84
Info (17561): VHDL info at i_syncbuf_b_sync_buffer_matrixmult17.vhd(84): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_b_sync_buffer_matrixmult17.vhd Line: 84
Info (19337): VHDL info at i_load_memcoalesce_b_load_0_matrixmult46.vhd(38): executing entity "i_load_memcoalesce_b_load_0_matrixmult46" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_b_load_0_matrixmult46.vhd Line: 38
Info (17560): VHDL info at i_load_memcoalesce_b_load_0_matrixmult46.vhd(358): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_b_load_0_matrixmult46.vhd Line: 358
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(249): truncated value with size 32 to match size of target (2) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 249
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(250): truncated value with size 3 to match size of target (2) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 250
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1038): truncated value with size 5 to match size of target (4) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 1038
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1041): truncated value with size 8 to match size of target (7) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 1041
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1044): truncated value with size 5 to match size of target (4) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 1044
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1051): truncated value with size 6 to match size of target (5) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 1051
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(680): truncated value with size 27 to match size of target (21) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 680
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(710): truncated value with size 512 to match size of target (128) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 710
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(711): truncated value with size 512 to match size of target (128) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 711
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(712): truncated value with size 11 to match size of target (10) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 712
Info (17561): VHDL info at i_load_memcoalesce_b_load_0_matrixmult46.vhd(358): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_b_load_0_matrixmult46.vhd Line: 358
Info (19337): VHDL info at readdata_reg_memcoalesce_B_load_0_matrixMult0.vhd(38): executing entity "readdata_reg_memcoalesce_B_load_0_matrixMult0" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/readdata_reg_memcoalesce_B_load_0_matrixMult0.vhd Line: 38
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(3253): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 3253
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(3253): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 3253
Info (19337): VHDL info at i_sbar_unnamed_matrixmult2_matrixmult60.vhd(38): executing entity "i_sbar_unnamed_matrixmult2_matrixmult60" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_sbar_unnamed_matrixmult2_matrixmult60.vhd Line: 38
Info (17560): VHDL info at i_sbar_unnamed_matrixmult2_matrixmult60.vhd(133): going to verilog side to elaborate module acl_barrier_simple_with_stallout File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_sbar_unnamed_matrixmult2_matrixmult60.vhd Line: 133
Warning (13469): Verilog HDL assignment warning at acl_barrier_simple.v(167): truncated value with size 12 to match size of target (11) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_barrier_simple.v Line: 167
Warning (13469): Verilog HDL assignment warning at acl_barrier_simple.v(169): truncated value with size 32 to match size of target (13) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_barrier_simple.v Line: 169
Warning (13469): Verilog HDL assignment warning at acl_barrier_simple.v(172): truncated value with size 32 to match size of target (11) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_barrier_simple.v Line: 172
Info (17561): VHDL info at i_sbar_unnamed_matrixmult2_matrixmult60.vhd(133): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_sbar_unnamed_matrixmult2_matrixmult60.vhd Line: 133
Info (19337): VHDL info at i_acl_wg_limiter_enter_l_grpid_3_matrixmult25.vhd(38): executing entity "i_acl_wg_limiter_enter_l_grpid_3_matrixmult25" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_3_matrixmult25.vhd Line: 38
Info (17560): VHDL info at i_acl_wg_limiter_enter_l_grpid_3_matrixmult25.vhd(145): going to verilog side to elaborate module acl_work_group_limiter_dspba File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_3_matrixmult25.vhd Line: 145
Warning (13469): Verilog HDL assignment warning at acl_work_group_limiter.v(103): truncated value with size 32 to match size of target (11) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_work_group_limiter.v Line: 103
Warning (13469): Verilog HDL assignment warning at acl_work_group_limiter.v(163): truncated value with size 3 to match size of target (2) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_work_group_limiter.v Line: 163
Warning (13469): Verilog HDL assignment warning at acl_work_group_limiter.v(167): truncated value with size 11 to match size of target (10) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_work_group_limiter.v Line: 167
Warning (13469): Verilog HDL assignment warning at acl_work_group_limiter.v(208): truncated value with size 11 to match size of target (10) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_work_group_limiter.v Line: 208
Info (17561): VHDL info at i_acl_wg_limiter_enter_l_grpid_3_matrixmult25.vhd(145): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_3_matrixmult25.vhd Line: 145
Info (19337): VHDL info at i_store_memdep_18_matrixmult54.vhd(38): executing entity "i_store_memdep_18_matrixmult54" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_18_matrixmult54.vhd Line: 38
Info (17560): VHDL info at i_store_memdep_18_matrixmult54.vhd(326): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_18_matrixmult54.vhd Line: 326
Info (17561): VHDL info at i_store_memdep_18_matrixmult54.vhd(326): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_18_matrixmult54.vhd Line: 326
Info (19337): VHDL info at i_acl_wg_limiter_enter_l_grpid_0_matrixmult15.vhd(38): executing entity "i_acl_wg_limiter_enter_l_grpid_0_matrixmult15" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_0_matrixmult15.vhd Line: 38
Info (17560): VHDL info at i_acl_wg_limiter_enter_l_grpid_0_matrixmult15.vhd(145): going to verilog side to elaborate module acl_work_group_limiter_dspba File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_0_matrixmult15.vhd Line: 145
Info (17561): VHDL info at i_acl_wg_limiter_enter_l_grpid_0_matrixmult15.vhd(145): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_0_matrixmult15.vhd Line: 145
Info (19337): VHDL info at i_syncbuf_a_sync_buffer_matrixmult13.vhd(38): executing entity "i_syncbuf_a_sync_buffer_matrixmult13" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_a_sync_buffer_matrixmult13.vhd Line: 38
Info (17560): VHDL info at i_syncbuf_a_sync_buffer_matrixmult13.vhd(84): going to verilog side to elaborate module acl_dspba_buffer File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_a_sync_buffer_matrixmult13.vhd Line: 84
Info (17561): VHDL info at i_syncbuf_a_sync_buffer_matrixmult13.vhd(84): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_a_sync_buffer_matrixmult13.vhd Line: 84
Info (19337): VHDL info at i_load_memcoalesce_a_load_0_matrixmult48.vhd(38): executing entity "i_load_memcoalesce_a_load_0_matrixmult48" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_a_load_0_matrixmult48.vhd Line: 38
Info (17560): VHDL info at i_load_memcoalesce_a_load_0_matrixmult48.vhd(358): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_a_load_0_matrixmult48.vhd Line: 358
Info (17561): VHDL info at i_load_memcoalesce_a_load_0_matrixmult48.vhd(358): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_a_load_0_matrixmult48.vhd Line: 358
Info (19337): VHDL info at readdata_reg_memcoalesce_A_load_0_matrixMult1.vhd(38): executing entity "readdata_reg_memcoalesce_A_load_0_matrixMult1" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/readdata_reg_memcoalesce_A_load_0_matrixMult1.vhd Line: 38
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(4177): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 4177
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(4177): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 4177
Info (19337): VHDL info at i_store_memdep_matrixmult58.vhd(38): executing entity "i_store_memdep_matrixmult58" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_matrixmult58.vhd Line: 38
Info (17560): VHDL info at i_store_memdep_matrixmult58.vhd(365): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_matrixmult58.vhd Line: 365
Info (17561): VHDL info at i_store_memdep_matrixmult58.vhd(365): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_matrixmult58.vhd Line: 365
Info (19337): VHDL info at i_acl_wg_limiter_enter_l_grpid_4_matrixmult28.vhd(38): executing entity "i_acl_wg_limiter_enter_l_grpid_4_matrixmult28" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_4_matrixmult28.vhd Line: 38
Info (17560): VHDL info at i_acl_wg_limiter_enter_l_grpid_4_matrixmult28.vhd(145): going to verilog side to elaborate module acl_work_group_limiter_dspba File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_4_matrixmult28.vhd Line: 145
Info (17561): VHDL info at i_acl_wg_limiter_enter_l_grpid_4_matrixmult28.vhd(145): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_4_matrixmult28.vhd Line: 145
Info (19337): VHDL info at i_store_memdep_17_matrixmult56.vhd(38): executing entity "i_store_memdep_17_matrixmult56" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_17_matrixmult56.vhd Line: 38
Info (17560): VHDL info at i_store_memdep_17_matrixmult56.vhd(326): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_17_matrixmult56.vhd Line: 326
Info (17561): VHDL info at i_store_memdep_17_matrixmult56.vhd(326): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_17_matrixmult56.vhd Line: 326
Info (19337): VHDL info at i_acl_wg_limiter_enter_l_grpid_2_matrixmult22.vhd(38): executing entity "i_acl_wg_limiter_enter_l_grpid_2_matrixmult22" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_2_matrixmult22.vhd Line: 38
Info (17560): VHDL info at i_acl_wg_limiter_enter_l_grpid_2_matrixmult22.vhd(145): going to verilog side to elaborate module acl_work_group_limiter_dspba File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_2_matrixmult22.vhd Line: 145
Info (17561): VHDL info at i_acl_wg_limiter_enter_l_grpid_2_matrixmult22.vhd(145): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_2_matrixmult22.vhd Line: 145
Info (19337): VHDL info at i_store_memdep_19_matrixmult52.vhd(38): executing entity "i_store_memdep_19_matrixmult52" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_19_matrixmult52.vhd Line: 38
Info (17560): VHDL info at i_store_memdep_19_matrixmult52.vhd(326): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_19_matrixmult52.vhd Line: 326
Info (17561): VHDL info at i_store_memdep_19_matrixmult52.vhd(326): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_19_matrixmult52.vhd Line: 326
Info (19337): VHDL info at i_store_memdep_21_matrixmult50.vhd(38): executing entity "i_store_memdep_21_matrixmult50" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_21_matrixmult50.vhd Line: 38
Info (17560): VHDL info at i_store_memdep_21_matrixmult50.vhd(326): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_21_matrixmult50.vhd Line: 326
Info (17561): VHDL info at i_store_memdep_21_matrixmult50.vhd(326): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_memdep_21_matrixmult50.vhd Line: 326
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5456): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5456
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5456): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5456
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5528): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5528
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5528): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5528
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5555): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5555
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5555): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5555
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5582): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5582
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5582): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5582
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5609): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5609
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5609): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5609
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5636): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5636
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5636): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5636
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5663): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5663
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5663): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5663
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5690): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5690
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5690): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5690
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5717): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5717
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5717): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5717
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5744): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5744
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5744): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5744
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5771): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5771
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5771): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5771
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5798): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5798
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5798): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5798
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5825): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5825
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5825): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5825
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5852): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5852
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5852): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5852
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5879): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5879
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5879): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5879
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5906): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5906
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5906): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5906
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(5936): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5936
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(5936): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 5936
Info (19337): VHDL info at i_sfc_c0_for_body_matrixmult_c0_enter_matrixmult.vhd(38): executing entity "i_sfc_c0_for_body_matrixmult_c0_enter_matrixmult" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_sfc_c0_for_body_matrixmult_c0_enter_matrixmult.vhd Line: 38
Info (19337): VHDL info at i_sfc_logic_c0_for_body_matrixmult_c0_enA0Zter_matrixmult62.vhd(38): executing entity "i_sfc_logic_c0_for_body_matrixmult_c0_enter_matrixmult62" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_sfc_logic_c0_for_body_matrixmult_c0_enA0Zter_matrixmult62.vhd Line: 38
Info (19337): VHDL info at dspba_library.vhd(18): executing entity "dspba_delay(width=1,depth=3,reset_high='0')(1,5)" with architecture "delay" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dspba_library.vhd Line: 18
Info (19337): VHDL info at i_acl_wg_limiter_exit_unnamed_matrixmult4_matrixmult67.vhd(38): executing entity "i_acl_wg_limiter_exit_unnamed_matrixmult4_matrixmult67" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_exit_unnamed_matrixmult4_matrixmult67.vhd Line: 38
Info (19337): VHDL info at wgl_exit_storage.vhd(38): executing entity "wgl_exit_storage" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/wgl_exit_storage.vhd Line: 38
Info (19337): VHDL info at i_load_memcoalesce_null_load_074_matrixmult69.vhd(38): executing entity "i_load_memcoalesce_null_load_074_matrixmult69" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_074_matrixmult69.vhd Line: 38
Info (17560): VHDL info at i_load_memcoalesce_null_load_074_matrixmult69.vhd(518): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_074_matrixmult69.vhd Line: 518
Info (17561): VHDL info at i_load_memcoalesce_null_load_074_matrixmult69.vhd(518): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_074_matrixmult69.vhd Line: 518
Info (19337): VHDL info at i_acl_wg_limiter_exit_unnamed_matrixmult5_matrixmult71.vhd(38): executing entity "i_acl_wg_limiter_exit_unnamed_matrixmult5_matrixmult71" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_exit_unnamed_matrixmult5_matrixmult71.vhd Line: 38
Info (19337): VHDL info at dupName_0_wgl_exit_storage_261i0676j68636g6u0qc0xgbuoz.vhd(38): executing entity "dupName_0_wgl_exit_storage_261i0676j68636g6u0qc0xgbuoz" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dupName_0_wgl_exit_storage_261i0676j68636g6u0qc0xgbuoz.vhd Line: 38
Info (19337): VHDL info at i_load_memcoalesce_null_load_0141_matrixmult73.vhd(38): executing entity "i_load_memcoalesce_null_load_0141_matrixmult73" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_0141_matrixmult73.vhd Line: 38
Info (17560): VHDL info at i_load_memcoalesce_null_load_0141_matrixmult73.vhd(518): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_0141_matrixmult73.vhd Line: 518
Info (17561): VHDL info at i_load_memcoalesce_null_load_0141_matrixmult73.vhd(518): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_0141_matrixmult73.vhd Line: 518
Info (19337): VHDL info at i_acl_wg_limiter_exit_unnamed_matrixmult6_matrixmult75.vhd(38): executing entity "i_acl_wg_limiter_exit_unnamed_matrixmult6_matrixmult75" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_exit_unnamed_matrixmult6_matrixmult75.vhd Line: 38
Info (19337): VHDL info at dupName_1_wgl_exit_storage_261i0676j68636g6u0qc0xgbuoz.vhd(38): executing entity "dupName_1_wgl_exit_storage_261i0676j68636g6u0qc0xgbuoz" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dupName_1_wgl_exit_storage_261i0676j68636g6u0qc0xgbuoz.vhd Line: 38
Info (19337): VHDL info at i_load_memcoalesce_null_load_0208_matrixmult77.vhd(38): executing entity "i_load_memcoalesce_null_load_0208_matrixmult77" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_0208_matrixmult77.vhd Line: 38
Info (17560): VHDL info at i_load_memcoalesce_null_load_0208_matrixmult77.vhd(518): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_0208_matrixmult77.vhd Line: 518
Info (17561): VHDL info at i_load_memcoalesce_null_load_0208_matrixmult77.vhd(518): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_0208_matrixmult77.vhd Line: 518
Info (19337): VHDL info at i_acl_wg_limiter_exit_unnamed_matrixmult7_matrixmult79.vhd(38): executing entity "i_acl_wg_limiter_exit_unnamed_matrixmult7_matrixmult79" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_exit_unnamed_matrixmult7_matrixmult79.vhd Line: 38
Info (19337): VHDL info at dupName_2_wgl_exit_storage_261i0676j68636g6u0qc0xgbuoz.vhd(38): executing entity "dupName_2_wgl_exit_storage_261i0676j68636g6u0qc0xgbuoz" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dupName_2_wgl_exit_storage_261i0676j68636g6u0qc0xgbuoz.vhd Line: 38
Info (19337): VHDL info at i_load_memcoalesce_null_load_06_matrixmult81.vhd(38): executing entity "i_load_memcoalesce_null_load_06_matrixmult81" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_06_matrixmult81.vhd Line: 38
Info (17560): VHDL info at i_load_memcoalesce_null_load_06_matrixmult81.vhd(518): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_06_matrixmult81.vhd Line: 518
Info (17561): VHDL info at i_load_memcoalesce_null_load_06_matrixmult81.vhd(518): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_06_matrixmult81.vhd Line: 518
Info (19337): VHDL info at i_acl_wg_limiter_exit_unnamed_matrixmult8_matrixmult83.vhd(38): executing entity "i_acl_wg_limiter_exit_unnamed_matrixmult8_matrixmult83" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_exit_unnamed_matrixmult8_matrixmult83.vhd Line: 38
Info (19337): VHDL info at dupName_3_wgl_exit_storage_261i0676j68636g6u0qc0xgbuoz.vhd(38): executing entity "dupName_3_wgl_exit_storage_261i0676j68636g6u0qc0xgbuoz" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dupName_3_wgl_exit_storage_261i0676j68636g6u0qc0xgbuoz.vhd Line: 38
Info (19337): VHDL info at dspba_library.vhd(18): executing entity "dspba_delay(width=1,depth=36,reset_high='0')(1,5)" with architecture "delay" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dspba_library.vhd Line: 18
Info (19337): VHDL info at i_load_memcoalesce_null_load_0_matrixmult65.vhd(38): executing entity "i_load_memcoalesce_null_load_0_matrixmult65" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_0_matrixmult65.vhd Line: 38
Info (17560): VHDL info at i_load_memcoalesce_null_load_0_matrixmult65.vhd(518): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_0_matrixmult65.vhd Line: 518
Info (17561): VHDL info at i_load_memcoalesce_null_load_0_matrixmult65.vhd(518): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_load_memcoalesce_null_load_0_matrixmult65.vhd Line: 518
Info (19337): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z3_0_matrixmult96.vhd(38): executing entity "i_acl_fp_hard_dot32_reduction_matrixmult_255_hfp_3_0_matrixmult96" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z3_0_matrixmult96.vhd Line: 38
Info (17560): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z3_0_matrixmult96.vhd(404): going to verilog side to elaborate module acl_fp_dot32_a10 File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z3_0_matrixmult96.vhd Line: 404
Info (17561): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z3_0_matrixmult96.vhd(404): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z3_0_matrixmult96.vhd Line: 404
Info (19337): VHDL info at dspba_library.vhd(18): executing entity "dspba_delay(width=32,reset_high='0')(1,5)" with architecture "delay" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dspba_library.vhd Line: 18
Info (19337): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z3_1_matrixmult98.vhd(38): executing entity "i_acl_fp_hard_dot32_reduction_matrixmult_255_hfp_3_1_matrixmult98" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z3_1_matrixmult98.vhd Line: 38
Info (17560): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z3_1_matrixmult98.vhd(404): going to verilog side to elaborate module acl_fp_dot32_a10 File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z3_1_matrixmult98.vhd Line: 404
Info (17561): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z3_1_matrixmult98.vhd(404): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z3_1_matrixmult98.vhd Line: 404
Info (19337): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z2_0_matrixmult92.vhd(38): executing entity "i_acl_fp_hard_dot32_reduction_matrixmult_191_hfp_2_0_matrixmult92" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z2_0_matrixmult92.vhd Line: 38
Info (17560): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z2_0_matrixmult92.vhd(404): going to verilog side to elaborate module acl_fp_dot32_a10 File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z2_0_matrixmult92.vhd Line: 404
Info (17561): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z2_0_matrixmult92.vhd(404): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z2_0_matrixmult92.vhd Line: 404
Info (19337): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z2_1_matrixmult94.vhd(38): executing entity "i_acl_fp_hard_dot32_reduction_matrixmult_191_hfp_2_1_matrixmult94" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z2_1_matrixmult94.vhd Line: 38
Info (17560): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z2_1_matrixmult94.vhd(404): going to verilog side to elaborate module acl_fp_dot32_a10 File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z2_1_matrixmult94.vhd Line: 404
Info (17561): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z2_1_matrixmult94.vhd(404): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z2_1_matrixmult94.vhd Line: 404
Info (19337): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z1_0_matrixmult88.vhd(38): executing entity "i_acl_fp_hard_dot32_reduction_matrixmult_127_hfp_1_0_matrixmult88" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z1_0_matrixmult88.vhd Line: 38
Info (17560): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z1_0_matrixmult88.vhd(404): going to verilog side to elaborate module acl_fp_dot32_a10 File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z1_0_matrixmult88.vhd Line: 404
Info (17561): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z1_0_matrixmult88.vhd(404): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z1_0_matrixmult88.vhd Line: 404
Info (19337): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z1_1_matrixmult90.vhd(38): executing entity "i_acl_fp_hard_dot32_reduction_matrixmult_127_hfp_1_1_matrixmult90" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z1_1_matrixmult90.vhd Line: 38
Info (17560): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z1_1_matrixmult90.vhd(404): going to verilog side to elaborate module acl_fp_dot32_a10 File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z1_1_matrixmult90.vhd Line: 404
Info (17561): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z1_1_matrixmult90.vhd(404): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z1_1_matrixmult90.vhd Line: 404
Info (19337): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z0_0_matrixmult84.vhd(38): executing entity "i_acl_fp_hard_dot32_reduction_matrixmult_63_hfp_0_0_matrixmult84" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z0_0_matrixmult84.vhd Line: 38
Info (17560): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z0_0_matrixmult84.vhd(404): going to verilog side to elaborate module acl_fp_dot32_a10 File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z0_0_matrixmult84.vhd Line: 404
Info (17561): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z0_0_matrixmult84.vhd(404): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z0_0_matrixmult84.vhd Line: 404
Info (19337): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z0_1_matrixmult86.vhd(38): executing entity "i_acl_fp_hard_dot32_reduction_matrixmult_63_hfp_0_1_matrixmult86" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z0_1_matrixmult86.vhd Line: 38
Info (17560): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z0_1_matrixmult86.vhd(404): going to verilog side to elaborate module acl_fp_dot32_a10 File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z0_1_matrixmult86.vhd Line: 404
Info (17561): VHDL info at i_acl_fp_hard_dot32_reduction_matrixmultA0Z0_1_matrixmult86.vhd(404): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_fp_hard_dot32_reduction_matrixmultA0Z0_1_matrixmult86.vhd Line: 404
Info (19337): VHDL info at i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zit_matrixmult100.vhd(38): executing entity "i_acl_sfc_exit_c0_for_body_matrixmult_c0_exit_matrixmult100" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zit_matrixmult100.vhd Line: 38
Info (19337): VHDL info at i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zult117_data_fifo.vhd(38): executing entity "i_acl_sfc_exit_c0_for_body_matrixmult_c0_exit_matrixmult117_data_fifo" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zult117_data_fifo.vhd Line: 38
Info (17560): VHDL info at i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zult117_data_fifo.vhd(181): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zult117_data_fifo.vhd Line: 181
Info (17561): VHDL info at i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zult117_data_fifo.vhd(181): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zult117_data_fifo.vhd Line: 181
Info (19337): VHDL info at i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zlt_full_detector.vhd(38): executing entity "i_acl_sfc_exit_c0_for_body_matrixmult_c0_exit_matrixmult_full_detector" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zlt_full_detector.vhd Line: 38
Info (17560): VHDL info at i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zlt_full_detector.vhd(117): going to verilog side to elaborate module acl_full_detector File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zlt_full_detector.vhd Line: 117
Warning (13469): Verilog HDL assignment warning at acl_full_detector.v(144): truncated value with size 2 to match size of target (1) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_full_detector.v Line: 144
Warning (13469): Verilog HDL assignment warning at acl_full_detector.v(155): truncated value with size 2 to match size of target (1) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_full_detector.v Line: 155
Warning (13469): Verilog HDL assignment warning at acl_full_detector.v(157): truncated value with size 2 to match size of target (1) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_full_detector.v Line: 157
Info (17561): VHDL info at i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zlt_full_detector.vhd(117): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_body_matrixmult_c0A0Zlt_full_detector.vhd Line: 117
Info (19337): VHDL info at i_sbar_unnamed_matrixmult9_matrixmult101.vhd(38): executing entity "i_sbar_unnamed_matrixmult9_matrixmult101" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_sbar_unnamed_matrixmult9_matrixmult101.vhd Line: 38
Info (17560): VHDL info at i_sbar_unnamed_matrixmult9_matrixmult101.vhd(133): going to verilog side to elaborate module acl_barrier_simple_with_stallout File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_sbar_unnamed_matrixmult9_matrixmult101.vhd Line: 133
Info (17561): VHDL info at i_sbar_unnamed_matrixmult9_matrixmult101.vhd(133): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_sbar_unnamed_matrixmult9_matrixmult101.vhd Line: 133
Info (19337): VHDL info at i_syncbuf_b_width_sync_buffer_matrixmult30.vhd(38): executing entity "i_syncbuf_b_width_sync_buffer_matrixmult30" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_b_width_sync_buffer_matrixmult30.vhd Line: 38
Info (17560): VHDL info at i_syncbuf_b_width_sync_buffer_matrixmult30.vhd(84): going to verilog side to elaborate module acl_dspba_buffer File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_b_width_sync_buffer_matrixmult30.vhd Line: 84
Info (17561): VHDL info at i_syncbuf_b_width_sync_buffer_matrixmult30.vhd(84): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_b_width_sync_buffer_matrixmult30.vhd Line: 84
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6465): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6465
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6465): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6465
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6492): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6492
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6492): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6492
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6519): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6519
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6519): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6519
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6546): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6546
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6546): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6546
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6573): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6573
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6573): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6573
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6600): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6600
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6600): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6600
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6627): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6627
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6627): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6627
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6654): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6654
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6654): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6654
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6677): going to verilog side to elaborate module acl_valid_fifo_counter File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6677
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6677): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6677
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6728): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6728
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6728): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6728
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6755): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6755
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6755): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6755
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6782): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6782
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6782): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6782
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6809): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6809
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6809): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6809
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6836): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6836
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6836): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6836
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6863): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6863
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6863): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6863
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6890): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6890
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6890): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6890
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6917): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6917
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6917): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6917
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6944): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6944
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6944): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6944
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6971): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6971
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6971): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6971
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(6998): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6998
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(6998): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 6998
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(7025): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7025
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(7025): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7025
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(7052): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7052
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(7052): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7052
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(7160): going to verilog side to elaborate module acl_valid_fifo_counter File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7160
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(7160): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7160
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(7183): going to verilog side to elaborate module acl_valid_fifo_counter File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7183
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(7183): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7183
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(7206): going to verilog side to elaborate module acl_valid_fifo_counter File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7206
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(7206): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7206
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(7229): going to verilog side to elaborate module acl_valid_fifo_counter File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7229
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(7229): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7229
Info (19337): VHDL info at matrixMult_B1_merge_reg.vhd(38): executing entity "matrixMult_B1_merge_reg" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_B1_merge_reg.vhd Line: 38
Info (17560): VHDL info at bb_matrixMult_B1_stall_region.vhd(7488): going to verilog side to elaborate module acl_valid_fifo_counter File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7488
Info (17561): VHDL info at bb_matrixMult_B1_stall_region.vhd(7488): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B1_stall_region.vhd Line: 7488
Info (19337): VHDL info at i_acl_wg_limiter_enter_l_grpid_1_matrixmult19.vhd(38): executing entity "i_acl_wg_limiter_enter_l_grpid_1_matrixmult19" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_1_matrixmult19.vhd Line: 38
Info (17560): VHDL info at i_acl_wg_limiter_enter_l_grpid_1_matrixmult19.vhd(145): going to verilog side to elaborate module acl_work_group_limiter_dspba File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_1_matrixmult19.vhd Line: 145
Info (17561): VHDL info at i_acl_wg_limiter_enter_l_grpid_1_matrixmult19.vhd(145): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_wg_limiter_enter_l_grpid_1_matrixmult19.vhd Line: 145
Info (19337): VHDL info at matrixMult_B1_branch.vhd(38): executing entity "matrixMult_B1_branch" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_B1_branch.vhd Line: 38
Info (19337): VHDL info at bb_matrixMult_B2_sr_0.vhd(38): executing entity "bb_matrixMult_B2_sr_0" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B2_sr_0.vhd Line: 38
Info (19337): VHDL info at bb_matrixMult_B2.vhd(38): executing entity "bb_matrixMult_B2" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B2.vhd Line: 38
Info (19337): VHDL info at matrixMult_B2_merge.vhd(38): executing entity "matrixMult_B2_merge" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_B2_merge.vhd Line: 38
Info (19337): VHDL info at bb_matrixMult_B2_stall_region.vhd(38): executing entity "bb_matrixMult_B2_stall_region" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B2_stall_region.vhd Line: 38
Info (17560): VHDL info at bb_matrixMult_B2_stall_region.vhd(355): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B2_stall_region.vhd Line: 355
Info (17561): VHDL info at bb_matrixMult_B2_stall_region.vhd(355): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/bb_matrixMult_B2_stall_region.vhd Line: 355
Info (19337): VHDL info at i_sfc_c0_for_end48_loopexit_matrixmult_cA0Zter12_matrixmult.vhd(38): executing entity "i_sfc_c0_for_end48_loopexit_matrixmult_c0_enter12_matrixmult" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_sfc_c0_for_end48_loopexit_matrixmult_cA0Zter12_matrixmult.vhd Line: 38
Info (19337): VHDL info at i_sfc_logic_c0_for_end48_loopexit_matrixA0Z12_matrixmult103.vhd(38): executing entity "i_sfc_logic_c0_for_end48_loopexit_matrixmult_c0_enter12_matrixmult103" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_sfc_logic_c0_for_end48_loopexit_matrixA0Z12_matrixmult103.vhd Line: 38
Info (19337): VHDL info at dspba_library.vhd(18): executing entity "dspba_delay(width=1,depth=5,reset_high='0')(1,5)" with architecture "delay" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dspba_library.vhd Line: 18
Info (19337): VHDL info at dspba_library.vhd(18): executing entity "dspba_delay(width=30,reset_high='0')(1,5)" with architecture "delay" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dspba_library.vhd Line: 18
Info (19337): VHDL info at i_syncbuf_global_size_0_sync_buffer_matrixmult105.vhd(38): executing entity "i_syncbuf_global_size_0_sync_buffer_matrixmult105" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_global_size_0_sync_buffer_matrixmult105.vhd Line: 38
Info (17560): VHDL info at i_syncbuf_global_size_0_sync_buffer_matrixmult105.vhd(83): going to verilog side to elaborate module acl_dspba_buffer File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_global_size_0_sync_buffer_matrixmult105.vhd Line: 83
Info (17561): VHDL info at i_syncbuf_global_size_0_sync_buffer_matrixmult105.vhd(83): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_global_size_0_sync_buffer_matrixmult105.vhd Line: 83
Info (19337): VHDL info at dspba_library.vhd(18): executing entity "dspba_delay(width=62,reset_high='0')(1,5)" with architecture "delay" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/dspba_library.vhd Line: 18
Info (19337): VHDL info at i_syncbuf_c_sync_buffer_matrixmult111.vhd(38): executing entity "i_syncbuf_c_sync_buffer_matrixmult111" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_c_sync_buffer_matrixmult111.vhd Line: 38
Info (17560): VHDL info at i_syncbuf_c_sync_buffer_matrixmult111.vhd(83): going to verilog side to elaborate module acl_dspba_buffer File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_c_sync_buffer_matrixmult111.vhd Line: 83
Info (17561): VHDL info at i_syncbuf_c_sync_buffer_matrixmult111.vhd(83): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_syncbuf_c_sync_buffer_matrixmult111.vhd Line: 83
Info (19337): VHDL info at i_acl_sfc_exit_c0_for_end48_loopexit_matA0Z16_matrixmult114.vhd(38): executing entity "i_acl_sfc_exit_c0_for_end48_loopexit_matrixmult_c0_exit16_matrixmult114" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_end48_loopexit_matA0Z16_matrixmult114.vhd Line: 38
Info (19337): VHDL info at i_acl_sfc_exit_c0_for_end48_loopexit_matA0Zult119_data_fifo.vhd(38): executing entity "i_acl_sfc_exit_c0_for_end48_loopexit_matrixmult_c0_exit16_matrixmult119_data_fifo" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_end48_loopexit_matA0Zult119_data_fifo.vhd Line: 38
Info (17560): VHDL info at i_acl_sfc_exit_c0_for_end48_loopexit_matA0Zult119_data_fifo.vhd(137): going to verilog side to elaborate module acl_data_fifo File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_end48_loopexit_matA0Zult119_data_fifo.vhd Line: 137
Info (17561): VHDL info at i_acl_sfc_exit_c0_for_end48_loopexit_matA0Zult119_data_fifo.vhd(137): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_end48_loopexit_matA0Zult119_data_fifo.vhd Line: 137
Info (19337): VHDL info at i_acl_sfc_exit_c0_for_end48_loopexit_matA0Zlt_full_detector.vhd(38): executing entity "i_acl_sfc_exit_c0_for_end48_loopexit_matrixmult_c0_exit16_matrixmult_full_detector" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_end48_loopexit_matA0Zlt_full_detector.vhd Line: 38
Info (17560): VHDL info at i_acl_sfc_exit_c0_for_end48_loopexit_matA0Zlt_full_detector.vhd(117): going to verilog side to elaborate module acl_full_detector File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_end48_loopexit_matA0Zlt_full_detector.vhd Line: 117
Warning (13469): Verilog HDL assignment warning at acl_full_detector.v(144): truncated value with size 2 to match size of target (1) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_full_detector.v Line: 144
Warning (13469): Verilog HDL assignment warning at acl_full_detector.v(155): truncated value with size 2 to match size of target (1) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_full_detector.v Line: 155
Warning (13469): Verilog HDL assignment warning at acl_full_detector.v(157): truncated value with size 2 to match size of target (1) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_full_detector.v Line: 157
Info (17561): VHDL info at i_acl_sfc_exit_c0_for_end48_loopexit_matA0Zlt_full_detector.vhd(117): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_acl_sfc_exit_c0_for_end48_loopexit_matA0Zlt_full_detector.vhd Line: 117
Info (19337): VHDL info at i_store_unnamed_matrixmult10_matrixmult115.vhd(38): executing entity "i_store_unnamed_matrixmult10_matrixmult115" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_unnamed_matrixmult10_matrixmult115.vhd Line: 38
Info (17560): VHDL info at i_store_unnamed_matrixmult10_matrixmult115.vhd(365): going to verilog side to elaborate module lsu_top File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_unnamed_matrixmult10_matrixmult115.vhd Line: 365
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1799): truncated value with size 28 to match size of target (27) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 1799
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1801): truncated value with size 6 to match size of target (5) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 1801
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1804): truncated value with size 8 to match size of target (7) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 1804
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1811): truncated value with size 6 to match size of target (5) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 1811
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1812): truncated value with size 11 to match size of target (10) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 1812
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1640): truncated value with size 10 to match size of target (8) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 1640
Warning (13469): Verilog HDL assignment warning at lsu_bursting_load_stores.v(1654): truncated value with size 6 to match size of target (5) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/lsu_bursting_load_stores.v Line: 1654
Info (17561): VHDL info at i_store_unnamed_matrixmult10_matrixmult115.vhd(365): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/i_store_unnamed_matrixmult10_matrixmult115.vhd Line: 365
Info (19337): VHDL info at matrixMult_B2_branch.vhd(38): executing entity "matrixMult_B2_branch" with architecture "normal" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_B2_branch.vhd Line: 38
Info (17560): VHDL info at matrixMult_function_wrapper.vhd(1149): going to verilog side to elaborate module acl_clock2x_holder File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_function_wrapper.vhd Line: 1149
Info (17561): VHDL info at matrixMult_function_wrapper.vhd(1149): back to vhdl to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrixMult_function_wrapper.vhd Line: 1149
Info (16822): Verilog HDL info at matrix_mult_system.v(1238): back to verilog to continue elaboration File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1238
Warning (16735): Verilog HDL warning at matrix_mult_system.v(1289): actual bit length 8 differs from formal bit length 24 for port "ic_arb_address" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1289
Warning (16735): Verilog HDL warning at matrix_mult_system.v(1289): actual bit length 8 differs from formal bit length 24 for port "ic_arb_address" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1289
Warning (17460): Verilog HDL warning at acl_mem1x.v(412): overwriting previous value of parameter altsyncram_component.address_reg_b File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_mem1x.v Line: 412
Warning (16735): Verilog HDL warning at matrix_mult_system.v(1640): actual bit length 6 differs from formal bit length 24 for port "ic_arb_address" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1640
Warning (16735): Verilog HDL warning at matrix_mult_system.v(1640): actual bit length 6 differs from formal bit length 24 for port "ic_arb_address" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1640
Warning (16735): Verilog HDL warning at matrix_mult_system.v(1640): actual bit length 6 differs from formal bit length 24 for port "ic_arb_address" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1640
Warning (16735): Verilog HDL warning at matrix_mult_system.v(1640): actual bit length 6 differs from formal bit length 24 for port "ic_arb_address" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1640
Warning (16735): Verilog HDL warning at matrix_mult_system.v(1640): actual bit length 6 differs from formal bit length 24 for port "ic_arb_address" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1640
Warning (16735): Verilog HDL warning at matrix_mult_system.v(1640): actual bit length 6 differs from formal bit length 24 for port "ic_arb_address" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1640
Warning (16735): Verilog HDL warning at matrix_mult_system.v(1640): actual bit length 6 differs from formal bit length 24 for port "ic_arb_address" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1640
Warning (16735): Verilog HDL warning at matrix_mult_system.v(1640): actual bit length 6 differs from formal bit length 24 for port "ic_arb_address" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1640
Warning (17460): Verilog HDL warning at acl_mem1x.v(412): overwriting previous value of parameter altsyncram_component.address_reg_b File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_mem1x.v Line: 412
Warning (16788): Net "lmem_invalid_aspaces[1]" does not have a driver at matrix_mult_system.v(1021) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/matrix_mult_system.v Line: 1021
Warning (13469): Verilog HDL assignment warning at acl_ic_slave_rrp.v(192): truncated value with size 32 to match size of target (5) File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/ip/kernel_system/kernel_system_matrix_mult_system/matrix_mult_system_140/synth/acl_ic_slave_rrp.v Line: 192
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_evq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_00r2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_00r2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_00r2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_ssq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_ssq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_ssq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_ssq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_ssq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_ssq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_ssq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_ssq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_ssq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_asq2.tdf Line: 39
Warning (287013): Variable or input pin "byteena_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_ssq2.tdf Line: 32
Warning (287013): Variable or input pin "data_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_ssq2.tdf Line: 35
Warning (287013): Variable or input pin "wren_b" is defined but never used. File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_ssq2.tdf Line: 39
Info: Found 937 design entities
Info: There are 1987 partitions after elaboration.
Info: Creating instance-specific data models and dissolving soft partitions
Info (18299): Expanding entity and wildcard assignments.
Info (18300): Expanded entity and wildcard assignments. Elapsed time: 00:00:05
Warning (14284): Synthesized away the following node(s):
    Warning (14285): Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[64]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2087
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[65]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2119
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[66]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2151
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[67]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2183
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[68]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2215
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[69]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2247
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[70]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2279
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[71]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2311
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[72]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2343
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[73]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2375
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[74]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2407
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[75]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2439
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[76]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2471
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[77]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2503
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[78]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2535
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[79]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2567
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[80]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2599
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[81]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2631
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[82]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2663
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[83]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2695
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[84]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2727
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[85]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2759
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[86]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2791
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[87]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2823
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[88]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2855
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[89]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2887
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[90]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2919
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[91]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2951
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[92]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 2983
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[93]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 3015
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[94]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 3047
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[95]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 3079
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[122]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 3943
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[123]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 3975
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[124]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 4007
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[125]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 4039
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[126]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 4071
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[127]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 4103
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[160]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5159
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[161]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5191
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[162]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5223
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[163]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5255
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[164]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5287
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[165]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5319
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[166]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5351
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[167]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5383
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[168]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5415
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[169]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5447
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[170]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5479
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[171]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5511
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[172]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5543
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[173]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5575
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[174]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5607
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[175]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5639
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[176]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5671
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[177]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5703
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[178]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5735
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[179]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5767
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[180]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5799
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[181]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5831
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[182]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5863
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[183]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5895
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[184]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5927
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[185]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5959
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[186]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 5991
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[187]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 6023
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[188]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 6055
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[189]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 6087
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[190]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 6119
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[191]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 6151
Warning (19182): The Entity SDC source file cannot be located: "board/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_clk_gen/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_interface/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_memory_bank_divider/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_reset_controller_global/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_reset_controller_pcie/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/ddr3a/ddr3a_ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/ddr3b/dd3rb_ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/flash/flash_reset_controller/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr3a_pipe/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr3b_pipe/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "mem/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Info: found pre-synthesis snapshots for 1 partition(s)
Info: Synthesizing partition "root_partition"
Info (286030): Timing-Driven Synthesis is running
Warning (276020): Inferred RAM node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_inst_0|kernel|thematrixMult_function|thebb_matrixMult_B1|thebb_matrixMult_B1_stall_region|thei_load_memcoalesce_b_load_0_matrixmult_aunroll_x|thei_load_memcoalesce_b_load_0_matrixmult47|bursting_non_aligned_read|cache_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276020): Inferred RAM node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_inst_0|kernel|thematrixMult_function|thebb_matrixMult_B1|thebb_matrixMult_B1_stall_region|thei_load_memcoalesce_b_load_0_matrixmult_aunroll_x|thei_load_memcoalesce_b_load_0_matrixmult47|bursting_non_aligned_read|cache_rtl_1" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276020): Inferred RAM node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_inst_0|kernel|thematrixMult_function|thebb_matrixMult_B1|thebb_matrixMult_B1_stall_region|thei_load_memcoalesce_a_load_0_matrixmult_aunroll_x|thei_load_memcoalesce_a_load_0_matrixmult49|bursting_non_aligned_read|cache_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276020): Inferred RAM node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_inst_0|kernel|thematrixMult_function|thebb_matrixMult_B1|thebb_matrixMult_B1_stall_region|thei_load_memcoalesce_a_load_0_matrixmult_aunroll_x|thei_load_memcoalesce_a_load_0_matrixmult49|bursting_non_aligned_read|cache_rtl_1" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
Info (19000): Inferred 8 megafunctions from design logic
    Info (276029): Inferred altsyncram megafunction from the following design logic: "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_inst_0|kernel|thematrixMult_function|thebb_matrixMult_B1|thebb_matrixMult_B1_stall_region|thei_load_memcoalesce_b_load_0_matrixmult_aunroll_x|thei_load_memcoalesce_b_load_0_matrixmult47|bursting_non_aligned_read|cache_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 18
        Info (286033): Parameter WIDTHAD_A set to 10
        Info (286033): Parameter NUMWORDS_A set to 1024
        Info (286033): Parameter WIDTH_B set to 18
        Info (286033): Parameter WIDTHAD_B set to 10
        Info (286033): Parameter NUMWORDS_B set to 1024
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter RAM_BLOCK_TYPE set to M20K
    Info (276029): Inferred altsyncram megafunction from the following design logic: "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_inst_0|kernel|thematrixMult_function|thebb_matrixMult_B1|thebb_matrixMult_B1_stall_region|thei_load_memcoalesce_b_load_0_matrixmult_aunroll_x|thei_load_memcoalesce_b_load_0_matrixmult47|bursting_non_aligned_read|cache_rtl_1" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 18
        Info (286033): Parameter WIDTHAD_A set to 10
        Info (286033): Parameter NUMWORDS_A set to 1024
        Info (286033): Parameter WIDTH_B set to 18
        Info (286033): Parameter WIDTHAD_B set to 10
        Info (286033): Parameter NUMWORDS_B set to 1024
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter RAM_BLOCK_TYPE set to M20K
    Info (276029): Inferred altsyncram megafunction from the following design logic: "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_inst_0|kernel|thematrixMult_function|thebb_matrixMult_B1|thebb_matrixMult_B1_stall_region|thei_load_memcoalesce_b_load_0_matrixmult_aunroll_x|thei_load_memcoalesce_b_load_0_matrixmult47|bursting_non_aligned_read|pipelined_read|ENABLE_CACHE.cache_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 512
        Info (286033): Parameter WIDTHAD_A set to 10
        Info (286033): Parameter NUMWORDS_A set to 1024
        Info (286033): Parameter WIDTH_B set to 512
        Info (286033): Parameter WIDTHAD_B set to 10
        Info (286033): Parameter NUMWORDS_B set to 1024
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter RAM_BLOCK_TYPE set to M20K
        Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
    Info (276029): Inferred altsyncram megafunction from the following design logic: "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_inst_0|kernel|thematrixMult_function|thebb_matrixMult_B1|thebb_matrixMult_B1_stall_region|thei_load_memcoalesce_b_load_0_matrixmult_aunroll_x|thei_load_memcoalesce_b_load_0_matrixmult47|bursting_non_aligned_read|pipelined_read|ENABLE_CACHE.cache_rtl_1" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 512
        Info (286033): Parameter WIDTHAD_A set to 10
        Info (286033): Parameter NUMWORDS_A set to 1024
        Info (286033): Parameter WIDTH_B set to 512
        Info (286033): Parameter WIDTHAD_B set to 10
        Info (286033): Parameter NUMWORDS_B set to 1024
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter RAM_BLOCK_TYPE set to M20K
        Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
    Info (276029): Inferred altsyncram megafunction from the following design logic: "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_inst_0|kernel|thematrixMult_function|thebb_matrixMult_B1|thebb_matrixMult_B1_stall_region|thei_load_memcoalesce_a_load_0_matrixmult_aunroll_x|thei_load_memcoalesce_a_load_0_matrixmult49|bursting_non_aligned_read|cache_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 18
        Info (286033): Parameter WIDTHAD_A set to 10
        Info (286033): Parameter NUMWORDS_A set to 1024
        Info (286033): Parameter WIDTH_B set to 18
        Info (286033): Parameter WIDTHAD_B set to 10
        Info (286033): Parameter NUMWORDS_B set to 1024
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter RAM_BLOCK_TYPE set to M20K
    Info (276029): Inferred altsyncram megafunction from the following design logic: "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_inst_0|kernel|thematrixMult_function|thebb_matrixMult_B1|thebb_matrixMult_B1_stall_region|thei_load_memcoalesce_a_load_0_matrixmult_aunroll_x|thei_load_memcoalesce_a_load_0_matrixmult49|bursting_non_aligned_read|cache_rtl_1" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 18
        Info (286033): Parameter WIDTHAD_A set to 10
        Info (286033): Parameter NUMWORDS_A set to 1024
        Info (286033): Parameter WIDTH_B set to 18
        Info (286033): Parameter WIDTHAD_B set to 10
        Info (286033): Parameter NUMWORDS_B set to 1024
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter RAM_BLOCK_TYPE set to M20K
    Info (276029): Inferred altsyncram megafunction from the following design logic: "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_inst_0|kernel|thematrixMult_function|thebb_matrixMult_B1|thebb_matrixMult_B1_stall_region|thei_load_memcoalesce_a_load_0_matrixmult_aunroll_x|thei_load_memcoalesce_a_load_0_matrixmult49|bursting_non_aligned_read|pipelined_read|ENABLE_CACHE.cache_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 512
        Info (286033): Parameter WIDTHAD_A set to 10
        Info (286033): Parameter NUMWORDS_A set to 1024
        Info (286033): Parameter WIDTH_B set to 512
        Info (286033): Parameter WIDTHAD_B set to 10
        Info (286033): Parameter NUMWORDS_B set to 1024
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter RAM_BLOCK_TYPE set to M20K
        Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
    Info (276029): Inferred altsyncram megafunction from the following design logic: "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_inst_0|kernel|thematrixMult_function|thebb_matrixMult_B1|thebb_matrixMult_B1_stall_region|thei_load_memcoalesce_a_load_0_matrixmult_aunroll_x|thei_load_memcoalesce_a_load_0_matrixmult49|bursting_non_aligned_read|pipelined_read|ENABLE_CACHE.cache_rtl_1" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 512
        Info (286033): Parameter WIDTHAD_A set to 10
        Info (286033): Parameter NUMWORDS_A set to 1024
        Info (286033): Parameter WIDTH_B set to 512
        Info (286033): Parameter WIDTHAD_B set to 10
        Info (286033): Parameter NUMWORDS_B set to 1024
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter RAM_BLOCK_TYPE set to M20K
        Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
Info (125061): Changed top-level design entity name to "top"
Info (125061): Changed top-level design entity name to "top"
Info (125061): Changed top-level design entity name to "top"
Info (125061): Changed top-level design entity name to "top"
Info (125061): Changed top-level design entity name to "kernel_system"
Info (125061): Changed top-level design entity name to "kernel_system"
Info (125061): Changed top-level design entity name to "kernel_system"
Info (125061): Changed top-level design entity name to "kernel_system"
Warning (14284): Synthesized away the following node(s):
    Warning (14285): Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[30]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 999
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[29]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 967
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[31]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 1031
Info (125061): Changed top-level design entity name to "top"
Info (125061): Changed top-level design entity name to "top"
Info (125061): Changed top-level design entity name to "top"
Info (125061): Changed top-level design entity name to "top"
Info (125061): Changed top-level design entity name to "kernel_system"
Info (125061): Changed top-level design entity name to "kernel_system"
Info (125061): Changed top-level design entity name to "kernel_system"
Info (125061): Changed top-level design entity name to "kernel_system"
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "kernel_mem0_address[0]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 36
    Warning (13410): Pin "kernel_mem0_address[1]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 36
    Warning (13410): Pin "kernel_mem0_address[2]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 36
    Warning (13410): Pin "kernel_mem0_address[3]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 36
    Warning (13410): Pin "kernel_mem0_address[4]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 36
    Warning (13410): Pin "kernel_mem0_address[5]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 36
    Warning (13410): Pin "kernel_mem0_debugaccess" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 40
    Warning (13410): Pin "kernel_mem1_address[0]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 46
    Warning (13410): Pin "kernel_mem1_address[1]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 46
    Warning (13410): Pin "kernel_mem1_address[2]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 46
    Warning (13410): Pin "kernel_mem1_address[3]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 46
    Warning (13410): Pin "kernel_mem1_address[4]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 46
    Warning (13410): Pin "kernel_mem1_address[5]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 46
    Warning (13410): Pin "kernel_mem1_debugaccess" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 50
    Warning (13410): Pin "kernel_output_ch0_data[0]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[1]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[2]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[3]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[4]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[5]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[6]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[7]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[8]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[9]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[10]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[11]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[12]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[13]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[14]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[15]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[16]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[17]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[18]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[19]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[20]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[21]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[22]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[23]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[24]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[25]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[26]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[27]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[28]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[29]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[30]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[31]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[32]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[33]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[34]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[35]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[36]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[37]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[38]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[39]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[40]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[41]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[42]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[43]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[44]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[45]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[46]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[47]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[48]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[49]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[50]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[51]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[52]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[53]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[54]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[55]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[56]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[57]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[58]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[59]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[60]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[61]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[62]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[63]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[64]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[65]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[66]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[67]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[68]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[69]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[70]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[71]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[72]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[73]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[74]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[75]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[76]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[77]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[78]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[79]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[80]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[81]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[82]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[83]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[84]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[85]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[86]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[87]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[88]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[89]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[90]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[91]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[92]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[93]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[94]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[95]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[96]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[97]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[98]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[99]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[100]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[101]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[102]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[103]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[104]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[105]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[106]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[107]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[108]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[109]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[110]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[111]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[112]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[113]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[114]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[115]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[116]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[117]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[118]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[119]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[120]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[121]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[122]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[123]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[124]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[125]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[126]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[127]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[128]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[129]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[130]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[131]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[132]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[133]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[134]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[135]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[136]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[137]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[138]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[139]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[140]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[141]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[142]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[143]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[144]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[145]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[146]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[147]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[148]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[149]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[150]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[151]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[152]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[153]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[154]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[155]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[156]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[157]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[158]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[159]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[160]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[161]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[162]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[163]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[164]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[165]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[166]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[167]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[168]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[169]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[170]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[171]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[172]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[173]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[174]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[175]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[176]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[177]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[178]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[179]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[180]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[181]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[182]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[183]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[184]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[185]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[186]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[187]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[188]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[189]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[190]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[191]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[192]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[193]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[194]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[195]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[196]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[197]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[198]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[199]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[200]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[201]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[202]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[203]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[204]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[205]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[206]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[207]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[208]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[209]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[210]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[211]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[212]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[213]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[214]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[215]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[216]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[217]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[218]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[219]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[220]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[221]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[222]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[223]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[224]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[225]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[226]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[227]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[228]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[229]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[230]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[231]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[232]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[233]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[234]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[235]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[236]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[237]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[238]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[239]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[240]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[241]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[242]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[243]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[244]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[245]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[246]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[247]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[248]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[249]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[250]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[251]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[252]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[253]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[254]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_data[255]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 51
    Warning (13410): Pin "kernel_output_ch0_valid" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 52
    Warning (13410): Pin "kernel_output_ch1_data[0]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[1]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[2]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[3]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[4]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[5]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[6]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[7]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[8]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[9]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[10]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[11]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[12]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[13]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[14]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[15]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[16]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[17]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[18]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[19]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[20]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[21]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[22]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[23]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[24]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[25]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[26]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[27]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[28]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[29]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[30]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[31]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[32]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[33]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[34]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[35]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[36]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[37]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[38]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[39]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[40]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[41]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[42]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[43]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[44]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[45]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[46]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[47]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[48]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[49]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[50]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[51]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[52]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[53]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[54]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[55]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[56]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[57]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[58]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[59]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[60]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[61]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[62]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[63]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[64]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[65]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[66]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[67]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[68]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[69]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[70]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[71]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[72]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[73]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[74]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[75]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[76]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[77]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[78]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[79]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[80]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[81]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[82]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[83]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[84]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[85]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[86]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[87]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[88]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[89]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[90]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[91]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[92]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[93]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[94]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[95]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[96]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[97]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[98]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[99]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[100]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[101]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[102]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[103]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[104]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[105]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[106]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[107]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[108]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[109]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[110]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[111]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[112]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[113]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[114]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[115]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[116]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[117]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[118]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[119]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[120]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[121]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[122]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[123]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[124]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[125]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[126]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[127]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[128]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[129]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[130]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[131]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[132]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[133]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[134]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[135]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[136]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[137]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[138]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[139]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[140]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[141]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[142]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[143]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[144]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[145]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[146]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[147]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[148]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[149]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[150]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[151]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[152]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[153]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[154]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[155]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[156]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[157]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[158]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[159]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[160]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[161]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[162]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[163]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[164]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[165]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[166]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[167]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[168]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[169]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[170]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[171]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[172]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[173]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[174]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[175]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[176]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[177]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[178]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[179]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[180]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[181]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[182]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[183]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[184]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[185]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[186]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[187]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[188]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[189]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[190]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[191]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[192]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[193]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[194]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[195]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[196]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[197]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[198]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[199]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[200]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[201]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[202]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[203]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[204]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[205]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[206]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[207]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[208]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[209]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[210]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[211]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[212]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[213]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[214]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[215]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[216]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[217]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[218]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[219]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[220]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[221]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[222]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[223]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[224]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[225]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[226]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[227]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[228]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[229]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[230]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[231]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[232]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[233]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[234]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[235]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[236]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[237]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[238]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[239]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[240]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[241]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[242]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[243]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[244]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[245]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[246]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[247]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[248]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[249]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[250]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[251]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[252]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[253]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[254]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_data[255]" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 54
    Warning (13410): Pin "kernel_output_ch1_valid" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 55
    Warning (13410): Pin "cc_snoop_ready" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 9
    Warning (13410): Pin "kernel_input_ch0_ready" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 26
    Warning (13410): Pin "kernel_input_ch1_ready" is stuck at GND File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/kernel_system/synth/kernel_system.v Line: 29
Warning (14284): Synthesized away the following node(s):
    Warning (14285): Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "matrix_mult_system|matrix_mult_system|matrixMult_inst|matrixMult_id_iter_inst_0|group_id_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|q_b[121]" File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/tmp-clearbox/top_synth/3719/altsyncram_18l1.tdf Line: 3911
Info (17049): 16729 registers lost all their fanouts during netlist optimizations.
Info (21057): Implemented 100393 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 1688 input pins
    Info (21059): Implemented 1816 output pins
    Info (21061): Implemented 76579 logic cells
    Info (21064): Implemented 20046 RAM segments
    Info (21062): Implemented 8 DSP elements
Info: Successfully synthesized partition
Info: Saving post-synthesis snapshots for 1 partition(s)
Info: Quartus Prime Synthesis was successful. 0 errors, 822 warnings
    Info: Peak virtual memory: 6328 megabytes
    Info: Processing ended: Wed Feb 14 18:41:17 2018
    Info: Elapsed time: 00:03:25
    Info: Total CPU time (on all processors): 00:05:39
Info (19538): Reading SDC files took 00:00:05 cumulatively in this process.
Info: *******************************************************************
Info: Running Quartus Prime Fitter
    Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Feb 14 18:41:51 2018
Info: Command: quartus_fit top -c top
Info: Using INI file /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/quartus.ini
Info: qfit2_default_script.tcl version: #1
Info: Project  = top
Info: Revision = top
Info (16677): Loading synthesized database
Info (16734): Loading "final" snapshot for partition "root_partition".
Info (16734): Loading "final" snapshot for partition "root_partition_2cedade0".
Info (16734): Loading "synthesized" snapshot for partition "kernel".
Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:14
Info (19078): Instance assignments in read-only partitions are ignored:
    Info (19079): Ignored assignment "LOCATION PIN_AM21 -to config_clk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AP26 -to kernel_pll_refclk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AL9 -to ddr0_pll_ref_clk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_E5 -to ddr1_pll_ref_clk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AP24 -to one_pps" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AL29 -to pcie_refclk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AW16 -to perstl0_n" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AN33 -to hip_serial_rx_in[0]" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AM31 -to hip_serial_rx_in[1]" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AM35 -to hip_serial_rx_in[2]" because target belongs to a read-only partition "|"
    Info (19080): Additional 288 ignored instance assignments are not displayed.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_pipe_stage_host_sch/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/flash/flash_clock_cross_flash/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_clock_cross_kernel_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_clock_cross_pcie_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_clock_cross_pcie_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "board/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_clk_gen/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_interface/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "board/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_clk_gen/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_interface/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_memory_bank_divider/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_reset_controller_global/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_reset_controller_pcie/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/ddr3a/ddr3a_ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/ddr3b/dd3rb_ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/flash/flash_reset_controller/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr3a_pipe/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr3b_pipe/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "mem/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/dd3rb_ddr3b_altera_emif_arch_nf_171_lfxywli.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/ddr3a_ddr3a_altera_emif_arch_nf_171_kvxwm2y.sdc". Evaluation of this SDC file will be skipped.
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (119006): Selected device 10AX115N3F40E2SG for design "top"
Info (21077): Core supply voltage is 0.95V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 100 degrees C
Warning (18550): Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example.
    Info (119043): Atom "board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|cal_slave_component|ioaux_soft_ram|the_altsyncram|auto_generated|ram_block1a0" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning (176050): Can't implement Global Signal option for node "ddr1_pll_ref_clk~input" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected
Warning (176050): Can't implement Global Signal option for node "ddr0_pll_ref_clk~input" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected
Info (12262): Starting Fitter periphery placement operations
Info (12290): Loading the periphery placement data.
Info (12291): Periphery placement data loaded: elapsed time is 00:00:21
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (12789): Real-time CRC ERROR_CHECK_FREQUENCY_DIVISOR value (1) in design does not match value (2) in the Quartus Prime Settings File
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Info (16210): Plan updated with currently enabled project assignments.
Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:00:00
Info (11178): Promoted 16 clocks (12 global, 2 regional, 2 periphery)
    Info (13173): board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|outclk[0]~CLKENA0 (111627 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2J_G_I5
    Info (13173): board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|outclk[1]~CLKENA0 (1 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2J_G_I2
    Info (13173): freeze_wrapper_inst|kernel_system_clock_reset_reset_reset_n~CLKENA0 (33695 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2I_G_I0
    Info (13173): board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_c_counters[3]~CLKENA0 (184 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3B_G_I16
    Info (13173): ddr0_pll_ref_clk~inputCLKENA0 (21 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3B_G_I23
    Info (13173): board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|non_hps.core_clks_rsts_inst|clk_gen_hmc.hr_qr.clk_gen_master.emif_usr_clk_buf (13760 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3G_G_I26
    Info (13173): board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|non_hps.core_clks_rsts_inst|clk_gen_hmc.hr_qr.clk_gen_master.emif_usr_clk_buf (10282 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3B_G_I28
    Info (13173): board_inst|kernel_interface|kernel_interface|reset_controller_sw|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 (4137 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1G_G_I10
    Info (13173): board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys~CORE_CLK_OUTCLKENA0 (43210 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1D_G_I15
    Info (13173): board_inst|flash|config_iopll|config_iopll|altera_iopll_i|twentynm_pll|outclk[0]~CLKENA0 (1511 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2G_G_I4
    Info (13173): config_clk~inputCLKENA0 (1890 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2I_G_I6
    Info (13173): ddr1_pll_ref_clk~inputCLKENA0 (21 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3G_G_I22
    Info (13173): board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0 (1005 fanout) drives Regional Clock Region 2, with the buffer placed at CLKCTRL_1H_R2_I2
    Info (13173): board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0 (1389 fanout) drives Regional Clock Region 2, with the buffer placed at CLKCTRL_1H_R2_I1
    Info (13173): board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0 (992 fanout) drives Periphery Clock Region 2, with the buffer placed at CLKCTRL_1H_P2_I11
    Info (13173): board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0 (1393 fanout) drives Periphery Clock Region 2, with the buffer placed at CLKCTRL_1H_P2_I8
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity alt_xcvr_resync
        Info (332166): set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}
    Info (332165): Entity altera_std_synchronizer
        Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
    Info (332165): Entity altpcie_reset_delay_sync
        Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]]
    Info (332165): Entity altpcie_sc_bitsync
        Info (332166): set_multicycle_path -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3
        Info (332166): set_false_path -hold -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]]
        Info (332166): set_multicycle_path -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3
        Info (332166): set_false_path -hold -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]]
    Info (332165): Entity dcfifo_6ei1
        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_3v8:dffpipe16|dffe17a* 
        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_2v8:dffpipe13|dffe14a* 
    Info (332165): Entity alt_sld_fab_0_altera_a10_xcvr_reset_sequencer_171_2ufaxda
        Info (332166): if { [get_collection_size [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o]] > 0 } { create_clock -name ~ALTERA_CLKUSR~ -period 8 [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o] }
Warning (332174): Ignored filter at qfit2_default_fitter_flow.tcl(340): *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*] could not be matched with a keeper File: /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
Warning (332049): Ignored set_multicycle_path at qfit2_default_fitter_flow.tcl(340): Argument <to> is an empty collection File: /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
    Info (332050): eval "fit_plan $create_fitter_netlist_args" File: /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
Warning (332049): Ignored set_false_path at qfit2_default_fitter_flow.tcl(340): Argument <to> is an empty collection File: /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
    Info (332050): eval "fit_plan $create_fitter_netlist_args" File: /home/admin/intelFPGA_pro/17.1/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:03.
Info (332104): Reading SDC File: 'kernel_system/altera_reset_controller_171/synth/altera_reset_controller.sdc'
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'board/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'board/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/a10_sl2_txrx/xcvr_sl2_txrx/altera_xcvr_native_a10_171/synth/altera_xcvr_native_a10_false_paths.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_pcie/altera_xcvr_native_a10_171/synth/altera_xcvr_native_a10_false_paths.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_pcie/altera_pcie_a10_hip_171/synth/altera_pci_express.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_clock_cross_kernel_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/flash/flash_clock_cross_flash/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_reset_controller_pcie/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_memory_bank_divider/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_kernel_clk_gen/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_kernel_clk_gen/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/flash/flash_reset_controller/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_pipe_stage_host_sch/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_clock_cross_kernel_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_clock_cross_pcie_to_ddr3a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_reset_controller_ddr3b_pipe/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_clock_cross_pcie_to_ddr3b/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_kernel_interface/mem_org_mode_100/synth/mem_org_mode.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_kernel_interface/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_kernel_interface/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_reset_controller_global/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_reset_controller_ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/flash/flash_pll_locked_to_reset/nalla_locked_to_reset_11/synth/nalla_locked_to_reset.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_temperature/acl_temperature_a10_151/synth/temp_sense_a10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_reset_controller_ddr3a_pipe/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'mem/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_reset_controller_ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/ddr3a/ddr3a_ddr3a/altera_emif_arch_nf_171/synth/ddr3a_ddr3a_altera_emif_arch_nf_171_kvxwm2y.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/ddr3a/ddr3a_ddr3a/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_alt_pr/alt_pr_171/synth/rtl/alt_pr.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/ddr3b/dd3rb_ddr3b/altera_emif_arch_nf_171/synth/dd3rb_ddr3b_altera_emif_arch_nf_171_lfxywli.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/ddr3b/dd3rb_ddr3b/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/mem/mem_uniphy_status_20nm/uniphy_status_20nm_141/synth/uniphy_status_20nm.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332104): Reading SDC File: 'base.sdc'
Warning (332043): Overwriting existing clock: ~ALTERA_CLKUSR~
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|rx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|rx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|rx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|rx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|rx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_rx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|rx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_rx_clk}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys|pll_fixed_clk_central} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|wys~CORE_CLK_OUT} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys|core_clk_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys~CORE_CLK_OUTCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|pcie|pld_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys|pld_clk}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -duty_cycle 50.00 -name {board_inst|pcie|hip_cmn_clk[0]} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pld_pcs_interface.inst_twentynm_hssi_common_pld_pcs_interface|hip_cmn_clk[0]}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|avmmclk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|avmmclk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|avmmclk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|avmmclk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|avmmclk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|avmmclk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|avmmclk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {config_clk~inputCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|avmmclk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_refclk_select_inst|refclk} -multiply_by 25 -duty_cycle 50.00 -name {board_inst|pcie|tx_serial_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_inst|clk0}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_refclk_select_inst|refclk} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|pll_pcie_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_inst|hclk_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_lc_refclk_select_mux_inst|lvpecl_in} -multiply_by 40 -duty_cycle 50.00 -name {board_inst|pcie|twentynm_atx_pll_inst~O_CLK0_8G} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst|clk0_8g}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pld_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|tx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|tx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|tx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|tx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|tx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|tx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|tx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[2]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[2]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[2]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|rx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[2]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|rx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[1]|tx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|rx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|rx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[2]|tx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|rx_pma_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[1]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|rx_pma_div_clk} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch0|g_xcvr_native_insts[3]|tx_coreclkin} {board_inst|sl2_ch0|sl2_ch0|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|tx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|tx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|tx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|tx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 32 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|tx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb|cpulse_x6_dn_bus[5]} -divide_by 33 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|tx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser|clk_divtx_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|rx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|rx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[1]|tx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|rx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|rx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[2]|tx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -divide_by 4 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|rx_pma_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -divide_by 33 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|rx_pma_div_clk} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv_user}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pma_clkdiv_tx_user~CLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|sl2_ch1|g_xcvr_native_insts[3]|tx_coreclkin} {board_inst|sl2_ch1|sl2_ch1|u1|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|clk_fpll_b} -divide_by 16 -duty_cycle 50.00 -name {board_inst|pcie|tx_bonding_clocks[0]} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch0|sl2_ch0|u0|xcvr_fpll_a10_0|fpll_refclk_select_inst|ref_iqclk[2]} -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch0|mcgb_serial_clk} {board_inst|sl2_ch0|sl2_ch0|u0|xcvr_fpll_a10_0|twentynm_hssi_pma_cgb_master_inst|cpulse_out_bus[5]}
    Info (332110): create_generated_clock -source {board_inst|sl2_ch1|sl2_ch1|u0|xcvr_fpll_a10_0|fpll_refclk_select_inst|refclk} -multiply_by 8 -duty_cycle 50.00 -name {board_inst|sl2_ch1|mcgb_serial_clk} {board_inst|sl2_ch1|sl2_ch1|u0|xcvr_fpll_a10_0|twentynm_hssi_pma_cgb_master_inst|cpulse_out_bus[5]}
    Info (332110): create_generated_clock -source {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]} -divide_by 4 -multiply_by 6 -duty_cycle 50.00 -name {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|outclk0} {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|iopll_inst|outclk[0]}
    Info (332110): create_generated_clock -source {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]} -divide_by 2 -multiply_by 6 -duty_cycle 50.00 -name {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|outclk1} {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|iopll_inst|outclk[1]}
    Info (332110): create_generated_clock -source {board_inst|flash|config_iopll|config_iopll|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]} -divide_by 24 -multiply_by 6 -duty_cycle 50.00 -name {board_inst|flash|config_iopll|config_iopll|outclk0} {board_inst|flash|config_iopll|config_iopll|altera_iopll_i|twentynm_pll|iopll_inst|outclk[0]}
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst|loaden[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst|lvds_clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst|outclk[3]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst|loaden[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst|lvds_clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate|loaden[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate|lvds_clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|loaden[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|lvds_clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate|loaden[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate|lvds_clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|loaden[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|lvds_clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[1]|rx_clkout
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[1]|rx_clk
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[2]|rx_clkout
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[2]|rx_clk
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[3]|rx_clkout
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[3]|rx_clk
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[4]|rx_clkout
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[4]|rx_clk
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[5]|rx_clkout
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[5]|rx_clk
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[6]|rx_clkout
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[6]|rx_clk
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[7]|rx_clkout
Warning (332043): Overwriting existing clock: board_inst|pcie|g_xcvr_native_insts[7]|rx_clk
Warning (332043): Overwriting existing clock: board_inst|pcie|tx_bonding_clocks[0]
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at base.sdc(865): a10_internal_oscillator_clock0 could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/base.sdc Line: 865
Warning (332174): Ignored filter at base.sdc(865): acl_hmcc_wrapper_inst|* could not be matched with a clock File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/base.sdc Line: 865
Warning (332054): Assignment set_clock_groups is accepted but has some problems at base.sdc(865): Argument -group with value [get_clocks {  a10_internal_oscillator_clock0  }] contains zero elements File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/base.sdc Line: 865
    Info (332050): set_clock_groups -asynchronous -group [get_clocks {  config_clk  }] -group [get_clocks {  a10_internal_oscillator_clock0  }] -group [get_clocks {  altera_ts_clk  }] -group [get_clocks {  ddr0_pll_ref_clk  }] -group [get_clocks {  ddr1_pll_ref_clk  }] -group [get_clocks {  qsfp0_refclk0  }] -group [get_clocks {  kernel_pll_refclk  }] -group [get_clocks {  pcie_refclk  board_inst|pcie|*  }] -group [get_clocks {  board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|*  }] -group [get_clocks {  acl_hmcc_wrapper_inst|*  }] -group [get_clocks {  altera_reserved_tck  }] -group [get_clocks {  ddr0_mem_dqs[0]_IN  ddr0_mem_dqs[1]_IN  ddr0_mem_dqs[2]_IN  ddr0_mem_dqs[3]_IN  ddr0_mem_dqs[4]_IN  ddr0_mem_dqs[5]_IN  ddr0_mem_dqs[6]_IN  ddr0_mem_dqs[7]_IN  board_inst|mem|ddr3a|ddr3a|*  }] -group [get_clocks {  ddr1_mem_dqs[0]_IN  ddr1_mem_dqs[1]_IN  ddr1_mem_dqs[2]_IN  ddr1_mem_dqs[3]_IN  ddr1_mem_dqs[4]_IN  ddr1_mem_dqs[5]_IN  ddr1_mem_dqs[6]_IN  ddr1_mem_dqs[7]_IN  board_inst|mem|ddr3b|ddr3b|*  }] -group [get_clocks {  board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_pma_div_clk  }] -group [get_clocks {  board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_pma_div_clk  }] -group [get_clocks {  board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_pma_div_clk  }] -group [get_clocks {  board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_pma_div_clk  }]  File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/base.sdc Line: 865
Warning (332054): Assignment set_clock_groups is accepted but has some problems at base.sdc(865): Argument -group with value [get_clocks {  acl_hmcc_wrapper_inst|*  }] contains zero elements File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/base.sdc Line: 865
Warning (332174): Ignored filter at base.sdc(970): board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|seq_if_inst|afi_cal_success_sync_inst|din_s1|*data could not be matched with a pin File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/base.sdc Line: 970
Warning (332174): Ignored filter at base.sdc(972): board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|din_s1|d could not be matched with a pin File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/base.sdc Line: 972
Warning (332174): Ignored filter at base.sdc(988): board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|seq_if_inst|afi_cal_success_sync_inst|din_s1|*data could not be matched with a pin File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/base.sdc Line: 988
Warning (332174): Ignored filter at base.sdc(990): board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|din_s1|d could not be matched with a pin File: /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/base.sdc Line: 990
Info (332104): Reading SDC File: '/home/rdnode/intelFPGA_pro/17.1/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc'
Info (19449): Reading SDC files elapsed 00:00:12.
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf  from: oe  to: o
    Info (332098): Cell: board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf  from: oe  to: o
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332152): The following assignments are ignored by the derive_clock_uncertainty command
Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command
    Info (332172): Setup clock transfer from board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_l_1 (Rise) to board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_core_usr_clk (Rise) has uncertainty 0.238 that is less than the recommended uncertainty 0.360
    Info (332172): Hold clock transfer from board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_l_1 (Rise) to board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_core_usr_clk (Rise) has uncertainty 0.242 that is less than the recommended uncertainty 0.360
    Info (332172): Setup clock transfer from board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_l_2 (Rise) to board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_core_usr_clk (Rise) has uncertainty 0.238 that is less than the recommended uncertainty 0.360
    Info (332172): Hold clock transfer from board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_l_2 (Rise) to board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_core_usr_clk (Rise) has uncertainty 0.242 that is less than the recommended uncertainty 0.360
    Info (332172): Setup clock transfer from board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_core_usr_clk (Rise) to board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_l_1 (Rise) has uncertainty 0.259 that is less than the recommended uncertainty 0.360
    Info (332172): Hold clock transfer from board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_core_usr_clk (Rise) to board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_l_1 (Rise) has uncertainty 0.290 that is less than the recommended uncertainty 0.360
    Info (332172): Setup clock transfer from board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_core_usr_clk (Rise) to board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_l_2 (Rise) has uncertainty 0.259 that is less than the recommended uncertainty 0.360
    Info (332172): Hold clock transfer from board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_core_usr_clk (Rise) to board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_l_2 (Rise) has uncertainty 0.290 that is less than the recommended uncertainty 0.360
    Info (332172): Setup clock transfer from board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_l_1 (Rise) to board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_core_usr_clk (Rise) has uncertainty 0.238 that is less than the recommended uncertainty 0.360
    Info (332172): Hold clock transfer from board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_l_1 (Rise) to board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_core_usr_clk (Rise) has uncertainty 0.242 that is less than the recommended uncertainty 0.360
    Info (332172): Setup clock transfer from board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_l_2 (Rise) to board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_core_usr_clk (Rise) has uncertainty 0.238 that is less than the recommended uncertainty 0.360
    Info (332172): Hold clock transfer from board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_l_2 (Rise) to board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_core_usr_clk (Rise) has uncertainty 0.242 that is less than the recommended uncertainty 0.360
    Info (332172): Setup clock transfer from board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_core_usr_clk (Rise) to board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_l_1 (Rise) has uncertainty 0.259 that is less than the recommended uncertainty 0.360
    Info (332172): Hold clock transfer from board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_core_usr_clk (Rise) to board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_l_1 (Rise) has uncertainty 0.290 that is less than the recommended uncertainty 0.360
    Info (332172): Setup clock transfer from board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_core_usr_clk (Rise) to board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_l_2 (Rise) has uncertainty 0.259 that is less than the recommended uncertainty 0.360
    Info (332172): Hold clock transfer from board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_core_usr_clk (Rise) to board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_l_2 (Rise) has uncertainty 0.290 that is less than the recommended uncertainty 0.360
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 202 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):   66.667 altera_reserved_tck
    Info (332111): 1000.000 altera_ts_clk
    Info (332111):   40.000 board_inst|flash|config_iopll|config_iopll|outclk0
    Info (332111):    2.500 board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|outclk0
    Info (332111):    1.250 board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|outclk1
    Info (332111):    6.562 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_core_cal_slave_clk
    Info (332111):    3.750 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_core_usr_clk
    Info (332111):    1.875 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_0
    Info (332111):    1.875 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_1
    Info (332111):    1.875 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_2
    Info (332111):    3.750 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_l_0
    Info (332111):    3.750 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_l_1
    Info (332111):    3.750 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_phy_clk_l_2
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_vco_clk
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_vco_clk_1
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_vco_clk_2
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_wf_clk_0
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_wf_clk_1
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_wf_clk_2
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_wf_clk_3
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_wf_clk_4
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_wf_clk_5
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_wf_clk_6
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_wf_clk_7
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_wf_clk_8
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_wf_clk_9
    Info (332111):    0.937 board_inst|mem|ddr3a|ddr3a|ddr3a_ddr3a_wf_clk_10
    Info (332111):    3.750 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_core_usr_clk
    Info (332111):    1.875 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_0
    Info (332111):    1.875 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_1
    Info (332111):    1.875 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_2
    Info (332111):    3.750 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_l_0
    Info (332111):    3.750 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_l_1
    Info (332111):    3.750 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_phy_clk_l_2
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_vco_clk
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_vco_clk_1
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_vco_clk_2
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_wf_clk_0
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_wf_clk_1
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_wf_clk_2
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_wf_clk_3
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_wf_clk_4
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_wf_clk_5
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_wf_clk_6
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_wf_clk_7
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_wf_clk_8
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_wf_clk_9
    Info (332111):    0.937 board_inst|mem|ddr3b|ddr3b|dd3rb_ddr3b_wf_clk_10
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[0]|pma_hclk_by2
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[0]|rx_clk
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[0]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[0]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[0]|rx_pma_clk
    Info (332111):    8.000 board_inst|pcie|g_xcvr_native_insts[0]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[1]|pma_hclk_by2
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[1]|rx_clk
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[1]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[1]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[1]|rx_pma_clk
    Info (332111):    8.000 board_inst|pcie|g_xcvr_native_insts[1]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[2]|pma_hclk_by2
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[2]|rx_clk
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[2]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[2]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[2]|rx_pma_clk
    Info (332111):    8.000 board_inst|pcie|g_xcvr_native_insts[2]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[3]|pma_hclk_by2
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[3]|rx_clk
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[3]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[3]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[3]|rx_pma_clk
    Info (332111):    8.000 board_inst|pcie|g_xcvr_native_insts[3]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[4]|pma_hclk_by2
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[4]|rx_clk
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[4]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[4]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[4]|rx_pma_clk
    Info (332111):    8.000 board_inst|pcie|g_xcvr_native_insts[4]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[5]|pma_hclk_by2
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[5]|rx_clk
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[5]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[5]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[5]|rx_pma_clk
    Info (332111):    8.000 board_inst|pcie|g_xcvr_native_insts[5]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[6]|pma_hclk_by2
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[6]|rx_clk
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[6]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[6]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[6]|rx_pma_clk
    Info (332111):    8.000 board_inst|pcie|g_xcvr_native_insts[6]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[7]|pma_hclk_by2
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[7]|rx_clk
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[7]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[7]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[7]|rx_pma_clk
    Info (332111):    8.000 board_inst|pcie|g_xcvr_native_insts[7]|tx_clk
    Info (332111):    2.000 board_inst|pcie|hip_cmn_clk[0]
    Info (332111):    4.000 board_inst|pcie|pld_clk
    Info (332111):    2.000 board_inst|pcie|pll_pcie_clk
    Info (332111):    2.000 board_inst|pcie|rx_pcs_clk_div_by_4[0]
    Info (332111):    2.000 board_inst|pcie|rx_pcs_clk_div_by_4[1]
    Info (332111):    2.000 board_inst|pcie|rx_pcs_clk_div_by_4[2]
    Info (332111):    2.000 board_inst|pcie|rx_pcs_clk_div_by_4[3]
    Info (332111):    2.000 board_inst|pcie|rx_pcs_clk_div_by_4[4]
    Info (332111):    2.000 board_inst|pcie|rx_pcs_clk_div_by_4[5]
    Info (332111):    2.000 board_inst|pcie|rx_pcs_clk_div_by_4[6]
    Info (332111):    2.000 board_inst|pcie|rx_pcs_clk_div_by_4[7]
    Info (332111):    0.250 board_inst|pcie|twentynm_atx_pll_inst~O_CLK0_8G
    Info (332111):    2.000 board_inst|pcie|tx_bonding_clocks[0]
    Info (332111):    8.000 board_inst|pcie|tx_clkout
    Info (332111):    2.000 board_inst|pcie|tx_pcs_clk_div_by_4[0]
    Info (332111):    2.000 board_inst|pcie|tx_pcs_clk_div_by_4[1]
    Info (332111):    2.000 board_inst|pcie|tx_pcs_clk_div_by_4[2]
    Info (332111):    2.000 board_inst|pcie|tx_pcs_clk_div_by_4[3]
    Info (332111):    2.000 board_inst|pcie|tx_pcs_clk_div_by_4[4]
    Info (332111):    2.000 board_inst|pcie|tx_pcs_clk_div_by_4[5]
    Info (332111):    2.000 board_inst|pcie|tx_pcs_clk_div_by_4[6]
    Info (332111):    2.000 board_inst|pcie|tx_pcs_clk_div_by_4[7]
    Info (332111):    0.400 board_inst|pcie|tx_serial_clk
    Info (332111):    4.000 board_inst|pcie|wys~CORE_CLK_OUT
    Info (332111):   10.000 board_inst|sl2_ch0|g_xcvr_native_insts[0]|avmmclk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[0]|rx_pma_div_clk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[0]|tx_pma_div_clk
    Info (332111):   10.000 board_inst|sl2_ch0|g_xcvr_native_insts[1]|avmmclk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[1]|rx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch0|g_xcvr_native_insts[1]|rx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[1]|rx_pma_div_clk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[1]|tx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch0|g_xcvr_native_insts[1]|tx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[1]|tx_pma_div_clk
    Info (332111):   10.000 board_inst|sl2_ch0|g_xcvr_native_insts[2]|avmmclk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[2]|rx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch0|g_xcvr_native_insts[2]|rx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[2]|rx_pma_div_clk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[2]|tx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch0|g_xcvr_native_insts[2]|tx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[2]|tx_pma_div_clk
    Info (332111):   10.000 board_inst|sl2_ch0|g_xcvr_native_insts[3]|avmmclk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[3]|rx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch0|g_xcvr_native_insts[3]|rx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[3]|rx_pma_div_clk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[3]|tx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch0|g_xcvr_native_insts[3]|tx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch0|g_xcvr_native_insts[3]|tx_pma_div_clk
    Info (332111):    0.193 board_inst|sl2_ch0|mcgb_serial_clk
    Info (332111):   10.000 board_inst|sl2_ch1|g_xcvr_native_insts[0]|avmmclk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[0]|rx_pma_div_clk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[0]|tx_pma_div_clk
    Info (332111):   10.000 board_inst|sl2_ch1|g_xcvr_native_insts[1]|avmmclk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[1]|rx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch1|g_xcvr_native_insts[1]|rx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[1]|rx_pma_div_clk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[1]|tx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch1|g_xcvr_native_insts[1]|tx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[1]|tx_pma_div_clk
    Info (332111):   10.000 board_inst|sl2_ch1|g_xcvr_native_insts[2]|avmmclk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[2]|rx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch1|g_xcvr_native_insts[2]|rx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[2]|rx_pma_div_clk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[2]|tx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch1|g_xcvr_native_insts[2]|tx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[2]|tx_pma_div_clk
    Info (332111):   10.000 board_inst|sl2_ch1|g_xcvr_native_insts[3]|avmmclk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[3]|rx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch1|g_xcvr_native_insts[3]|rx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[3]|rx_pma_div_clk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[3]|tx_coreclkin
    Info (332111):    6.204 board_inst|sl2_ch1|g_xcvr_native_insts[3]|tx_pma_clk
    Info (332111):    6.397 board_inst|sl2_ch1|g_xcvr_native_insts[3]|tx_pma_div_clk
    Info (332111):    0.193 board_inst|sl2_ch1|mcgb_serial_clk
    Info (332111):   10.000   config_clk
    Info (332111):    0.937 ddr0_mem_dqs[0]_IN
    Info (332111):    0.937 ddr0_mem_dqs[1]_IN
    Info (332111):    0.937 ddr0_mem_dqs[2]_IN
    Info (332111):    0.937 ddr0_mem_dqs[3]_IN
    Info (332111):    0.937 ddr0_mem_dqs[4]_IN
    Info (332111):    0.937 ddr0_mem_dqs[5]_IN
    Info (332111):    0.937 ddr0_mem_dqs[6]_IN
    Info (332111):    0.937 ddr0_mem_dqs[7]_IN
    Info (332111):    3.750 ddr0_pll_ref_clk
    Info (332111):    0.937 ddr1_mem_dqs[0]_IN
    Info (332111):    0.937 ddr1_mem_dqs[1]_IN
    Info (332111):    0.937 ddr1_mem_dqs[2]_IN
    Info (332111):    0.937 ddr1_mem_dqs[3]_IN
    Info (332111):    0.937 ddr1_mem_dqs[4]_IN
    Info (332111):    0.937 ddr1_mem_dqs[5]_IN
    Info (332111):    0.937 ddr1_mem_dqs[6]_IN
    Info (332111):    0.937 ddr1_mem_dqs[7]_IN
    Info (332111):    3.750 ddr1_pll_ref_clk
    Info (332111):    3.750 kernel_pll_refclk
    Info (332111):   10.000  pcie_refclk
    Info (332111):   10.000 pr_clk_enable_dclk_reg2_user_clk
    Info (332111):    1.551 qsfp0_refclk0
    Info (332111):    8.000 ~ALTERA_CLKUSR~
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176218): Packed 986 registers into blocks of type DSP block
    Extra Info (176218): Packed 5277 registers into blocks of type MLAB cell
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Info (12263): Fitter periphery placement operations ending: elapsed time is 00:06:09
Warning (12620): Input port OE of I/O output buffer "ucd_ctrlstatus_ucd_gpio21~output" is not connected, but the atom is driving a bi-directional pin
Info (11165): Fitter preparation operations ending: elapsed time is 00:05:53
Info (170189): Fitter placement preparation operations beginning
Info (14951): The Fitter is using Advanced Physical Optimization.
Info (19702): Fitter has implemented the following 787 RAMs using MLAB locations, which can behave differently during power up than dedicated RAM locations
    Info (170241): For more information about RAMs, refer to the Fitter RAM Summary report.
Info (170056): Fitter has implemented the following 787 RAMs using MLAB locations, which will have the same paused read capabilities as dedicated RAM locations
    Info (170241): For more information about RAMs, refer to the Fitter RAM Summary report.
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:07:15
Info (170191): Fitter placement operations beginning
Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/dap/dap_congestion.cpp, Line: 1525
Internal Error
Stack Trace:
    0xbb0d4: vpr_qi_jump_to_exit + 0x6f (fitter_vpr20kmain)
   0x1b6288: vpr_exit_at_line + 0x83 (fitter_vpr20kmain)


   0x562d37: dap_evaluate_move + 0x77 (fitter_vpr20kmain)
   0x416556: l_mpp_perform_moves_worker(void*) [clone .isra.671] + 0x30f (fitter_vpr20kmain)
   0x416682: l_mpp_worker_thread(void*) + 0x4a (fitter_vpr20kmain)
    0xd09d2: l_thread_start_wrapper(void*) + 0x29 (fitter_vpr20kmain)
     0x5b4c: thr_final_wrapper + 0xc (ccl_thr)
    0x3f21f: msg_thread_wrapper(void* (*)(void*), void*) + 0x62 (ccl_msg)
     0xac5c: mem_thread_wrapper(void* (*)(void*), void*) + 0x5c (ccl_mem)
     0x8b49: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err)
     0x5b8f: thr_thread_wrapper + 0x15 (ccl_thr)
     0x5e72: thr_thread_begin + 0x46 (ccl_thr)
     0x7e25: start_thread + 0xc5 (pthread)
    0xf834d: clone + 0x6d (c)

End-trace

Info: *******************************************************************
Info: Running Quartus Prime Compiler Database Interface
    Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Feb 14 17:50:38 2018
Info: Command: quartus_cdb -t import_compile.tcl
Info: Using INI file /home/admin/fpga_experiments/nallatech/examples_p385a_sch_ax115/matrix_mult/matrix_mult/bin/matrix_mult/quartus.ini
Info: Checking for OpenCL SDK installation, environment should have INTELFPGAOCLSDKROOT defined
Info: INTELFPGAOCLSDKROOT=/home/admin/intelFPGA_pro/17.1/hld
Info: Successfully completed BAK flow
Info: To reduce compile time on future compiles, you can generate a BAK cache by adding the arguments '--bsp-flow regenerate_cache' to aoc to skip BAK
Info: Retry strategy set to "retry-flat"
Info: Initial preservation set to "final"
Info (125061): Changed top-level design entity name to "top"
Info (125061): Changed top-level design entity name to "kernel_system"
Info (16677): Loading synthesized database
Info (16734): Loading "synthesized" snapshot for partition "root_partition".
Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:03
Info: Performing a fit attempt
Error: Quartus Fitter has failed! Breaking execution...