entity ODU_Serial1 is
	port
	(
		reset							:in			std_logic;  --global async reset, active low
		clock							:in			std_logic;  --43.75MHz clock
		--Processor Interface
		fpga_cs						:in			std_logic;  
		proc_addr					:in			std_logic_vector(19 downto 0);
		proc_data					:inout 		std_logic_vector(7 downto 0);
		proc_oe						:in			std_logic;
		proc_we						:in			std_logic;
		--Interrupt out of the ODUSerial module, active HIGH
		int_oduSerial1				:out			std_logic;
		--UART Interface signals (connected with N-plexer)
		------ODU Control and Telemetry------
		if_odu_telm_ch1			:in			std_logic;                        		
																									
		if_odu_cmd_ch1				:out			std_logic;									 	
		test_port_index 			:in 			std_logic_vector(3 downto 0);
		test_port					:out			std_logic_vector(31 downto 0)
	);
	end ODU_Serial1;

begin
	
		test_port <= txFIFO_data & txFIFO_q & txShiftReg & BaudClk_en & txStateMachine & txFIFO_advance & txPinData & txFIFO_wrreq & txFIFO_rdreq  when test_port_index=X"0" else
				 rxFIFO_data & rxFIFO_q & rxShiftReg & BaudClk_en & rxStateMachine & rxFIFO_advance & rxPinData & rxFIFO_wrreq & rxFIFO_rdreq  when test_port_index=X"1" else
					 fpga_cs & '0' & proc_we & proc_oe & proc_addr & proc_data;
				
		
		--FIFO used for buffering ODU command data from FPGA (Microprocessor)
		
		RxFifoOverflow	<=	rxFIFO_wrreq and rxFIFO_full;
		RxFifoUnderflow	<=	rxFIFO_rdreq and rxFIFO_empty;
		TxFifoOverflow	<=	txFIFO_wrreq and txFIFO_full;
		TxFifoUnderflow	<=	txFIFO_rdreq and txFIFO_empty;
		
		txFIFO : RadioPipe_TxRxFIFO
		port map
		(
			clock		=>	clock,
			data		=>	txFIFO_data,
			rdreq		=>	txFIFO_rdreq,
			sclr		=>	txFIFO_sclr,
			wrreq		=>	txFIFO_wrreq,
			empty		=>	txFIFO_empty,
			full		=>	txFIFO_full, 
			q			=>	txFIFO_q,
			usedw		=>	open
		);
		
		--FIFO used for buffering Telemetry data from ODU
		rxFIFO : RadioPipe_TxRxFIFO
		port map
		(
			clock		=>	clock,
			data		=>	rxFIFO_data,
			rdreq		=>	rxFIFO_rdreq,
			sclr		=>	rxFIFO_sclr,
			wrreq		=>	rxFIFO_wrreq,
			empty		=>	rxFIFO_empty,
			full		=>	rxFIFO_full, 
			q			=>	rxFIFO_q,
			usedw		=>	open
		);
		
		--Interrupt Generation
		int_oduSerial1 <= (intEnable(0) and intStatus(0)) or
		                 (intEnable(1) and intStatus(1)) or
		                 (intEnable(2) and intStatus(2)) or
		                 (intEnable(3) and intStatus(3)) or
		                 (intEnable(4) and intStatus(4)) or
		                 (intEnable(5) and intStatus(5)) or
		                 (intEnable(6) and intStatus(6)) or
		                 (intEnable(7) and intStatus(7));
		                 
		--Microprocessor Interface (Register Bank 0x803C0000 - 0x803C000F)
		proc_data <= proc_data_out when (fpga_cs='0' and proc_we='1' and proc_oe='0' and proc_addr(19 downto 8)="0000110000000000") --X"C00")
		             else "ZZZZZZZZ";
		
		process(clock,reset)
		begin
			if reset = '0' then
				intEnable <= "00000000"; -- X"00";
				intStatus <= "00000000"; --X"00";
				Rate <= "0000000000000000"; -- X"0000";
				dataBits <= "00000000"; --X"00";
				ParityEnable <= '0';
				ParityType <= '0';
				stopBits <= '0';
				pinControl(7 downto 5) <= "000";
				pinControl(3 downto 1) <= "000";
			elsif rising_edge(clock) then
				txFIFO_sclr <= '0';
				rxFIFO_sclr <= '0';
				txFIFO_advance <= '0';
				rxFIFO_advance <= '0';
				intStatus(0) <= RxDataAvail;
				intStatus(1) <= txFIFO_empty;
				intStatus(2) <= intStatus(2) or rxFrameError;
				intStatus(3) <= intStatus(3) or rxParityError;
				intStatus(4) <= intStatus(4) or RxFifoOverflow;
				intStatus(5) <= intStatus(5) or RxFifoUnderflow;
				intStatus(6) <= intStatus(6) or TxFifoOverflow;
				intStatus(7) <= intStatus(7) or TxFifoUnderflow;
				--if fpga_cs='0' and proc_we='0' and proc_oe='1' and proc_addr(19 downto 8) = "000011000000" then  --write
				if fpga_cs='0' and proc_we='0' and proc_oe='1' and proc_addr(19 downto 8) = "0000110000000000"  then --X"C00" then  
					case proc_addr(7 downto 0) is
					when "00000010" => 
						intEnable <= proc_data;
					when "00000011"  => --write "1"s to clear interrupt flags
						intStatus(7 downto 2) <= intStatus(7 downto 2) and (not proc_data(7 downto 2)); 
					when "00000100" => --write anything to advance rxFIFO
						rxFIFO_advance <= '1';
					when "00000101" =>
						txData <= proc_data;
						txFIFO_advance <= '1';
					when "00000110" =>
						txFIFO_sclr <=proc_data(1);
						rxFIFO_sclr <=proc_data(0);
					when "00000111"  => NULL;
					when "00001000" =>
						Rate(15 downto 8) <= proc_data;
					when "00001001" =>
						Rate(7 downto 0) <= proc_data;
					when "00001010" =>
						dataBits <= proc_data;
					when "00001011"=>
						ParityEnable <= proc_data(0);
						ParityType <= proc_data(1);
					when "00001100" =>
						stopBits <= proc_data(0);
					when "00001111" =>
						pinControl(7 downto 5) <= proc_data(7 downto 5);
						pinControl(3 downto 1) <= proc_data(3 downto 1);
					when others =>
						NULL;
					end case;
				elsif fpga_cs='0' and proc_we='1' and proc_oe='0' and proc_addr(19 downto 8) = "0000110000000000"  then  --X"C00" then
					case proc_addr(7 downto 0) is
					when "00000010"=>
						proc_data_out <= intEnable;
					when"00000011" =>
						proc_data_out <= intStatus;
					when "00000100" =>
						proc_data_out <= rxData;
					when "00000101"  =>
						proc_data_out <= txData;
					when "00000110" =>
						proc_data_out <= "000000" & txFIFO_sclr & rxFIFO_sclr;
					when "00000111"  =>
						proc_data_out <= "000000" & txFIFO_full & RxDataAvail;
					when "00001000" =>
						proc_data_out <= Rate(15 downto 8);
					when"00001001"  =>
						proc_data_out <= Rate(7 downto 0);
					when "00001010" =>
						proc_data_out <= dataBits;
					when "00001011" =>
						proc_data_out <= "000000" & ParityType & ParityEnable;
					when "00001100"  =>
						proc_data_out <= "0000000" & stopBits;
					when "00001101"  =>
						proc_data_out <= sampPerBit;
					when "00001111"  =>
						proc_data_out <= pinControl;
					when others =>
						proc_data_out <= "00000000";
					end case;
				end if;
			end if;
		end process;
		
		-- txFIFO Write Controlled by Microprocessor
		process(clock)
		begin
			if rising_edge(clock) then
				txFIFO_advance_z <= txFIFO_advance;
				txFIFO_wrreq <= '0'; 
				if txFIFO_advance = '0' and txFIFO_advance_z = '1' then  --falling edge of the signal "txFIFO_advance" (txData is stable now)
					if txFIFO_full = '0' then
						txFIFO_wrreq <= '1';
						txFIFO_data <= txData;
					else
						NULL; --drop data byte if txFIFO is full at the epoc processor writing txData 
					end if;
				end if;
			end if;
		end process;
		
		--rxFIFO Read Controlled by Microprocessor
		process(clock)
		begin
			if rising_edge(clock) then
				rxFIFO_advance_z <= rxFIFO_advance;
				rxFIFO_rdreq <= '0';
				if rxFIFO_empty = '0' then
					rxDataAvail <= '1';
				else
					rxDataAvail <= '0';
				end if;
				if rxFIFO_advance='1' and rxFIFO_advance_z='0' then
					if rxDataAvail = '1' then
						rxFIFO_rdreq <= '1';
					end if;
				elsif rxFIFO_advance='0' and rxFIFO_advance_z='1' then
					rxData <= rxFIFO_q;
				end if;
			end if;
		end process;
		
		--FPGA Pin Control
		process(clock)
		begin
			if rising_edge(clock) then
				if pinControl(2) = '1' then --Manual Control Enabled (Microprocessor perform bit-banning)
					if_odu_cmd_ch1 <= pinControl(3);
					pinControl(0) <= pinControl(3);
				else
					if_odu_cmd_ch1 <= txPinData xor pinControl(1); --use UART transmitter (polarity detemined by pinControl(1))
					pinControl(0) <= txPinData xor pinControl(1);
				end if; 
				if pinControl(7) = '1' then --Loopback enabled
					rxPinData <= txPinData; --polarity inversion not supported in loopback mode
					pinControl(4) <= txPinData;
				else
					rxPinData <= if_odu_telm_ch1 xor pinControl(5);
					pinControl(4) <= if_odu_telm_ch1 xor pinControl(5);
				end if;
			end if;
		end process;