Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition Info: Processing started: Mon Nov 13 10:35:34 2017 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top Info: Using INI file /home/hsuch/Downloads/arria_10_pcie_ref_design/hip_a10gx_g3_x8_avmm_dma256_1602_PS_restored_se/quartus.ini Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (16260): Previously generated files were detected in the Qsys file generation directory ("/home/hsuch/Downloads/arria_10_pcie_ref_design/hip_a10gx_g3_x8_avmm_dma256_1602_PS_restored_se/top/"). Info (16261): Skipped generation of the Qsys file "/home/hsuch/Downloads/arria_10_pcie_ref_design/hip_a10gx_g3_x8_avmm_dma256_1602_PS_restored_se/top.qsys" based on the current IP regeneration policy. You can review your IP regeneration policy in the IP Settings page of the Settings dialog box. Info (12021): Found 1 design units, including 1 entities, in source file frequency_counter.v Info (12023): Found entity 1: frequency_counter Info (12021): Found 1 design units, including 1 entities, in source file top_hw.v Info (12023): Found entity 1: top_hw Info (12021): Found 1 design units, including 1 entities, in source file top/synth/top.v Info (12023): Found entity 1: top Info (12021): Found 1 design units, including 0 entities, in source file top/synth/top_cfg.v Info (12022): Found design unit 1: top_cfg:config Info (12021): Found 1 design units, including 1 entities, in source file top/altera_reset_controller_170/synth/altera_reset_controller.v Info (12023): Found entity 1: altera_reset_controller Info (12021): Found 1 design units, including 1 entities, in source file top/altera_reset_controller_170/synth/altera_reset_synchronizer.v Info (12023): Found entity 1: altera_reset_synchronizer Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/top_altera_pcie_a10_hip_170_6po5avi.v Info (12023): Found entity 1: top_altera_pcie_a10_hip_170_6po5avi Info (12021): Found 3 design units, including 3 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_a10_hip_pipen1b.v Info (12023): Found entity 1: altpcie_a10_hip_pipen1b Info (12023): Found entity 2: altpcie_rxpolarity_decode Info (12023): Found entity 3: altpcie_grounder Info (12021): Found 2 design units, including 2 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_sc_bitsync.v Info (12023): Found entity 1: altpcie_sc_bitsync Info (12023): Found entity 2: altpcie_sc_bitsync_node Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_reset_delay_sync.v Info (12023): Found entity 1: altpcie_reset_delay_sync Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_rs_a10_hip.v Info (12023): Found entity 1: altpcie_rs_a10_hip Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_a10_hip_pllnphy.v Info (12023): Found entity 1: altpcie_a10_hip_pllnphy Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/skp_det_g3.v Info (12023): Found entity 1: skp_det_g3 Info (12021): Found 1 design units, including 0 entities, in source file top/altera_pcie_a10_hip_170/synth/altera_xcvr_functions.sv Info (12022): Found design unit 1: altera_xcvr_functions (SystemVerilog) (top_altera_pcie_a10_hip_170) Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_tlp_inspector_a10.v Info (12023): Found entity 1: altpcie_tlp_inspector_a10 Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_tlp_inspector_cseb_a10.sv Info (12023): Found entity 1: altpcie_tlp_inspector_cseb_a10 Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_tlp_inspector_monitor_a10.sv Info (12023): Found entity 1: altpcie_tlp_inspector_monitor_a10 Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_tlp_inspector_trigger_a10.v Info (12023): Found entity 1: altpcie_tlp_inspector_trigger_a10 Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_tlp_inspector_pcsig_drive_a10.v Info (12023): Found entity 1: altpcie_tlp_inspector_pcsig_drive_a10 Info (12021): Found 6 design units, including 6 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_a10_gbfifo.v Info (12023): Found entity 1: altpcie_a10_gbfifo Info (12023): Found entity 2: altpcie_a10_gbfifo_neq_5_ena Info (12023): Found entity 3: altpcie_a10_gbfifo_s5mlab Info (12023): Found entity 4: altpcie_a10_gbfifo_eq_5_ena Info (12023): Found entity 5: altpcie_a10_gbfifo_wys_lut Info (12023): Found entity 6: altpcie_a10mlab Info (12021): Found 2 design units, including 2 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_a10_scfifo_ext.v Info (12023): Found entity 1: altpcie_a10_scfifo_ext Info (12023): Found entity 2: altpcie_scfifo_aa_deep Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_scfifo_a10.v Info (12023): Found entity 1: altpcie_scfifo_a10 Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcierd_hip_rs.v Info (12023): Found entity 1: altpcierd_hip_rs Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_256_app.sv Info (12023): Found entity 1: altpcieav_256_app Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_hip_interface.sv Info (12023): Found entity 1: altpcieav_hip_interface Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_dma_rxm.sv Info (12023): Found entity 1: altpcieav_dma_rxm Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_dma_txs.sv Info (12023): Found entity 1: altpcieav_dma_txs Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_dma_rd.sv Info (12023): Found entity 1: altpcieav_dma_rd Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_dma_wr_2.sv Info (12023): Found entity 1: altpcieav_dma_wr_2 Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_dma_wr_readmem_2.sv Info (12023): Found entity 1: altpcieav_dma_wr_readmem_2 Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_dma_wr_tlpgen_2.sv Info (12023): Found entity 1: altpcieav_dma_wr_tlpgen_2 Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_dma_wr_wdalign_2.sv Info (12023): Found entity 1: altpcieav_dma_wr_wdalign_2 Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav128_dma_wr.sv Info (12023): Found entity 1: altpcieav128_dma_wr Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav128_dma_wr_readmem.sv Info (12023): Found entity 1: altpcieav128_dma_wr_readmem Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav128_dma_wr_tlpgen.sv Info (12023): Found entity 1: altpcieav128_dma_wr_tlpgen Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav128_dma_wr_wdalign.sv Info (12023): Found entity 1: altpcieav128_dma_wr_wdalign Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_arbiter.sv Info (12023): Found entity 1: altpcieav_arbiter Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_cra.sv Info (12023): Found entity 1: altpcieav_cra Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_fifo.sv Info (12023): Found entity 1: altpcie_fifo Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_dma_hprxm_rdwr.sv Info (12023): Found entity 1: altpcieav_dma_hprxm_rdwr Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_dma_hprxm_cpl.sv Info (12023): Found entity 1: altpcieav_dma_hprxm_cpl Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_dma_hprxm_txctrl.sv Info (12023): Found entity 1: altpcieav_dma_hprxm_txctrl Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcieav_dma_hprxm.sv Info (12023): Found entity 1: altpcieav_dma_hprxm Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_rxm_2_dma_controller_decode.v Info (12023): Found entity 1: altpcie_rxm_2_dma_controller_decode Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/dma_controller.sv Info (12023): Found entity 1: dma_control Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/altpcie_dynamic_control.sv Info (12023): Found entity 1: altpcie_dynamic_control Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/phy_g3x8.v Info (12023): Found entity 1: phy_g3x8 Info (12021): Found 1 design units, including 0 entities, in source file top/altera_pcie_a10_hip_170/synth/phy_g3x8_cfg.v Info (12022): Found design unit 1: phy_g3x8_cfg:config Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/alt_xcvr_resync.sv Info (12023): Found entity 1: alt_xcvr_resync Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/alt_xcvr_arbiter.sv Info (12023): Found entity 1: alt_xcvr_arbiter Info (12021): Found 8 design units, including 8 entities, in source file top/altera_xcvr_native_a10_170/synth/twentynm_pcs.sv Info (12023): Found entity 1: twentynm_pcs_rev_20nm1 Info (12023): Found entity 2: twentynm_pcs_rev_20nm2 Info (12023): Found entity 3: twentynm_pcs_rev_20nm3 Info (12023): Found entity 4: twentynm_pcs_rev_20nm4 Info (12023): Found entity 5: twentynm_pcs_rev_20nm5 Info (12023): Found entity 6: twentynm_pcs_rev_20nm5es Info (12023): Found entity 7: twentynm_pcs_rev_20nm5es2 Info (12023): Found entity 8: twentynm_pcs_rev_20nm4es Info (12021): Found 8 design units, including 8 entities, in source file top/altera_xcvr_native_a10_170/synth/twentynm_pma.sv Info (12023): Found entity 1: twentynm_pma_rev_20nm1 Info (12023): Found entity 2: twentynm_pma_rev_20nm2 Info (12023): Found entity 3: twentynm_pma_rev_20nm3 Info (12023): Found entity 4: twentynm_pma_rev_20nm4 Info (12023): Found entity 5: twentynm_pma_rev_20nm5 Info (12023): Found entity 6: twentynm_pma_rev_20nm5es Info (12023): Found entity 7: twentynm_pma_rev_20nm5es2 Info (12023): Found entity 8: twentynm_pma_rev_20nm4es Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/twentynm_xcvr_avmm.sv Info (12023): Found entity 1: twentynm_xcvr_avmm Info (12021): Found 9 design units, including 9 entities, in source file top/altera_xcvr_native_a10_170/synth/twentynm_xcvr_native.sv Info (12023): Found entity 1: twentynm_xcvr_native Info (12023): Found entity 2: twentynm_xcvr_native_rev_20nm1 Info (12023): Found entity 3: twentynm_xcvr_native_rev_20nm2 Info (12023): Found entity 4: twentynm_xcvr_native_rev_20nm3 Info (12023): Found entity 5: twentynm_xcvr_native_rev_20nm4 Info (12023): Found entity 6: twentynm_xcvr_native_rev_20nm5 Info (12023): Found entity 7: twentynm_xcvr_native_rev_20nm5es Info (12023): Found entity 8: twentynm_xcvr_native_rev_20nm5es2 Info (12023): Found entity 9: twentynm_xcvr_native_rev_20nm4es Info (12021): Found 1 design units, including 0 entities, in source file top/altera_xcvr_native_a10_170/synth/altera_xcvr_native_a10_functions_h.sv Info (12022): Found design unit 1: altera_xcvr_native_a10_functions_h (SystemVerilog) (top_altera_xcvr_native_a10_170) Info (12021): Found 1 design units, including 0 entities, in source file top/altera_xcvr_native_a10_170/synth/a10_avmm_h.sv Info (12022): Found design unit 1: a10_avmm_h (SystemVerilog) (top_altera_xcvr_native_a10_170) Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/alt_xcvr_native_pipe_retry.sv Info (12023): Found entity 1: alt_xcvr_native_pipe_retry Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/alt_xcvr_native_avmm_csr.sv Info (12023): Found entity 1: alt_xcvr_native_avmm_csr Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/alt_xcvr_native_prbs_accum.sv Info (12023): Found entity 1: alt_xcvr_native_prbs_accum Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/alt_xcvr_native_odi_accel.sv Info (12023): Found entity 1: alt_xcvr_native_odi_accel Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/alt_xcvr_native_rcfg_arb.sv Info (12023): Found entity 1: alt_xcvr_native_rcfg_arb Info (12021): Found 1 design units, including 0 entities, in source file top/altera_xcvr_native_a10_170/synth/altera_xcvr_native_pcie_dfe_params_h.sv Info (12022): Found design unit 1: altera_xcvr_native_pcie_dfe_params_h (SystemVerilog) (top_altera_xcvr_native_a10_170) Info (12021): Found 1 design units, including 0 entities, in source file top/altera_xcvr_native_a10_170/synth/pcie_mgmt_commands_h.sv Info (12022): Found design unit 1: pcie_mgmt_commands_h (SystemVerilog) (top_altera_xcvr_native_a10_170) Info (12021): Found 1 design units, including 0 entities, in source file top/altera_xcvr_native_a10_170/synth/pcie_mgmt_functions_h.sv Info (12022): Found design unit 1: pcie_mgmt_functions_h (SystemVerilog) (top_altera_xcvr_native_a10_170) Info (12021): Found 1 design units, including 0 entities, in source file top/altera_xcvr_native_a10_170/synth/pcie_mgmt_program.sv Info (12022): Found design unit 1: pcie_mgmt_program (SystemVerilog) (top_altera_xcvr_native_a10_170) Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/pcie_mgmt_cpu.sv Info (12023): Found entity 1: pcie_mgmt_cpu Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/pcie_mgmt_master.sv Info (12023): Found entity 1: pcie_mgmt_master Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/altera_xcvr_native_pcie_dfe_ip.sv Info (12023): Found entity 1: altera_xcvr_native_pcie_dfe_ip Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/top_altera_xcvr_native_a10_170_n5vprta.sv Info (12023): Found entity 1: top_altera_xcvr_native_a10_170_n5vprta Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_native_a10_170/synth/alt_xcvr_native_rcfg_opt_logic_n5vprta.sv Info (12023): Found entity 1: alt_xcvr_native_rcfg_opt_logic_n5vprta Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/fpll_g3.v Info (12023): Found entity 1: fpll_g3 Info (12021): Found 1 design units, including 0 entities, in source file top/altera_pcie_a10_hip_170/synth/fpll_g3_cfg.v Info (12022): Found design unit 1: fpll_g3_cfg:config Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_fpll_a10_170/synth/twentynm_xcvr_avmm.sv Info (12023): Found entity 1: twentynm_xcvr_avmm Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_fpll_a10_170/synth/alt_xcvr_resync.sv Info (12023): Found entity 1: alt_xcvr_resync Info (12021): Found 3 design units, including 3 entities, in source file top/altera_xcvr_fpll_a10_170/synth/altera_xcvr_fpll_a10.sv Info (12023): Found entity 1: altera_xcvr_fpll_a10 Info (12023): Found entity 2: dps_pulse_ctrl Info (12023): Found entity 3: dps_reset_gen Info (12021): Found 1 design units, including 0 entities, in source file top/altera_xcvr_fpll_a10_170/synth/a10_avmm_h.sv Info (12022): Found design unit 1: a10_avmm_h (SystemVerilog) (top_altera_xcvr_fpll_a10_170) Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_fpll_a10_170/synth/alt_xcvr_native_avmm_nf.sv Info (12023): Found entity 1: alt_xcvr_native_avmm_nf Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_fpll_a10_170/synth/alt_xcvr_pll_embedded_debug.sv Info (12023): Found entity 1: alt_xcvr_pll_embedded_debug Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_fpll_a10_170/synth/alt_xcvr_pll_avmm_csr.sv Info (12023): Found entity 1: alt_xcvr_pll_avmm_csr Info (12021): Found 1 design units, including 1 entities, in source file top/altera_pcie_a10_hip_170/synth/lcpll_g3xn.v Info (12023): Found entity 1: lcpll_g3xn Info (12021): Found 1 design units, including 0 entities, in source file top/altera_pcie_a10_hip_170/synth/lcpll_g3xn_cfg.v Info (12022): Found design unit 1: lcpll_g3xn_cfg:config Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_atx_pll_a10_170/synth/twentynm_xcvr_avmm.sv Info (12023): Found entity 1: twentynm_xcvr_avmm Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_atx_pll_a10_170/synth/alt_xcvr_resync.sv Info (12023): Found entity 1: alt_xcvr_resync Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_atx_pll_a10_170/synth/alt_xcvr_arbiter.sv Info (12023): Found entity 1: alt_xcvr_arbiter Info (12021): Found 1 design units, including 0 entities, in source file top/altera_xcvr_atx_pll_a10_170/synth/a10_avmm_h.sv Info (12022): Found design unit 1: a10_avmm_h (SystemVerilog) (top_altera_xcvr_atx_pll_a10_170) Info (12021): Found 1 design units, including 0 entities, in source file top/altera_xcvr_atx_pll_a10_170/synth/altera_xcvr_native_a10_functions_h.sv Info (12022): Found design unit 1: altera_xcvr_native_a10_functions_h (SystemVerilog) (top_altera_xcvr_atx_pll_a10_170) Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_atx_pll_a10_170/synth/alt_xcvr_atx_pll_rcfg_arb.sv Info (12023): Found entity 1: alt_xcvr_atx_pll_rcfg_arb Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_atx_pll_a10_170/synth/a10_xcvr_atx_pll.sv Info (12023): Found entity 1: a10_xcvr_atx_pll Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_atx_pll_a10_170/synth/alt_xcvr_pll_embedded_debug.sv Info (12023): Found entity 1: alt_xcvr_pll_embedded_debug Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_atx_pll_a10_170/synth/alt_xcvr_pll_avmm_csr.sv Info (12023): Found entity 1: alt_xcvr_pll_avmm_csr Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_atx_pll_a10_170/synth/top_altera_xcvr_atx_pll_a10_170_nd26ega.sv Info (12023): Found entity 1: top_altera_xcvr_atx_pll_a10_170_nd26ega Info (12021): Found 1 design units, including 1 entities, in source file top/altera_xcvr_atx_pll_a10_170/synth/alt_xcvr_atx_pll_rcfg_opt_logic_nd26ega.sv Info (12023): Found entity 1: alt_xcvr_atx_pll_rcfg_opt_logic_nd26ega Info (12021): Found 1 design units, including 1 entities, in source file top/altera_mm_interconnect_170/synth/top_altera_mm_interconnect_170_u5xbwgq.v Info (12023): Found entity 1: top_altera_mm_interconnect_170_u5xbwgq Info (12021): Found 1 design units, including 0 entities, in source file top/altera_mm_interconnect_170/synth/top_altera_mm_interconnect_170_u5xbwgq_cfg.v Info (12022): Found design unit 1: top_altera_mm_interconnect_170_u5xbwgq_cfg:config Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_multiplexer_170/synth/top_altera_merlin_multiplexer_170_yitdyoi.sv Info (12023): Found entity 1: top_altera_merlin_multiplexer_170_yitdyoi Info (12021): Found 2 design units, including 2 entities, in source file top/altera_merlin_multiplexer_170/synth/altera_merlin_arbitrator.sv Info (12023): Found entity 1: altera_merlin_arbitrator Info (12023): Found entity 2: altera_merlin_arb_adder Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_slave_agent_170/synth/altera_merlin_slave_agent.sv Info (12023): Found entity 1: altera_merlin_slave_agent Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_slave_agent_170/synth/altera_merlin_burst_uncompressor.sv Info (12023): Found entity 1: altera_merlin_burst_uncompressor Info (12021): Found 2 design units, including 2 entities, in source file top/altera_merlin_router_170/synth/top_altera_merlin_router_170_xw6e4zq.sv Info (12023): Found entity 1: top_altera_merlin_router_170_xw6e4zq_default_decode Info (12023): Found entity 2: top_altera_merlin_router_170_xw6e4zq Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_multiplexer_170/synth/top_altera_merlin_multiplexer_170_bsnxubi.sv Info (12023): Found entity 1: top_altera_merlin_multiplexer_170_bsnxubi Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_master_translator_170/synth/altera_merlin_master_translator.sv Info (12023): Found entity 1: altera_merlin_master_translator Info (12021): Found 2 design units, including 2 entities, in source file top/altera_merlin_router_170/synth/top_altera_merlin_router_170_abmhadq.sv Info (12023): Found entity 1: top_altera_merlin_router_170_abmhadq_default_decode Info (12023): Found entity 2: top_altera_merlin_router_170_abmhadq Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_slave_translator_170/synth/altera_merlin_slave_translator.sv Info (12023): Found entity 1: altera_merlin_slave_translator Info (12021): Found 1 design units, including 1 entities, in source file top/altera_avalon_sc_fifo_170/synth/altera_avalon_sc_fifo.v Info (12023): Found entity 1: altera_avalon_sc_fifo Info (12021): Found 1 design units, including 1 entities, in source file top/altera_avalon_st_adapter_170/synth/top_altera_avalon_st_adapter_170_lmw3z4y.v Info (12023): Found entity 1: top_altera_avalon_st_adapter_170_lmw3z4y Info (12021): Found 1 design units, including 0 entities, in source file top/altera_avalon_st_adapter_170/synth/top_altera_avalon_st_adapter_170_lmw3z4y_cfg.v Info (12022): Found design unit 1: top_altera_avalon_st_adapter_170_lmw3z4y_cfg:config Info (12021): Found 1 design units, including 1 entities, in source file top/error_adapter_170/synth/top_error_adapter_170_mtlhioy.sv Info (12023): Found entity 1: top_error_adapter_170_mtlhioy Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_master_agent_170/synth/altera_merlin_master_agent.sv Info (12023): Found entity 1: altera_merlin_master_agent Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_demultiplexer_170/synth/top_altera_merlin_demultiplexer_170_ptmmvpq.sv Info (12023): Found entity 1: top_altera_merlin_demultiplexer_170_ptmmvpq Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_demultiplexer_170/synth/top_altera_merlin_demultiplexer_170_bmirlai.sv Info (12023): Found entity 1: top_altera_merlin_demultiplexer_170_bmirlai Info (12021): Found 1 design units, including 1 entities, in source file top/altera_mm_interconnect_170/synth/top_altera_mm_interconnect_170_cthna2i.v Info (12023): Found entity 1: top_altera_mm_interconnect_170_cthna2i Info (12021): Found 1 design units, including 0 entities, in source file top/altera_mm_interconnect_170/synth/top_altera_mm_interconnect_170_cthna2i_cfg.v Info (12022): Found design unit 1: top_altera_mm_interconnect_170_cthna2i_cfg:config Info (12021): Found 2 design units, including 2 entities, in source file top/altera_merlin_router_170/synth/top_altera_merlin_router_170_4tza2tq.sv Info (12023): Found entity 1: top_altera_merlin_router_170_4tza2tq_default_decode Info (12023): Found entity 2: top_altera_merlin_router_170_4tza2tq Info (12021): Found 2 design units, including 2 entities, in source file top/altera_merlin_router_170/synth/top_altera_merlin_router_170_vrleuii.sv Info (12023): Found entity 1: top_altera_merlin_router_170_vrleuii_default_decode Info (12023): Found entity 2: top_altera_merlin_router_170_vrleuii Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_multiplexer_170/synth/top_altera_merlin_multiplexer_170_fzmgtca.sv Info (12023): Found entity 1: top_altera_merlin_multiplexer_170_fzmgtca Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_demultiplexer_170/synth/top_altera_merlin_demultiplexer_170_jdh2m3y.sv Info (12023): Found entity 1: top_altera_merlin_demultiplexer_170_jdh2m3y Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_width_adapter_170/synth/altera_merlin_width_adapter.sv Info (12023): Found entity 1: altera_merlin_width_adapter Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_width_adapter_170/synth/altera_merlin_address_alignment.sv Info (12023): Found entity 1: altera_merlin_address_alignment Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_width_adapter_170/synth/altera_merlin_burst_uncompressor.sv Info (12023): Found entity 1: altera_merlin_burst_uncompressor Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_demultiplexer_170/synth/top_altera_merlin_demultiplexer_170_anz2kpy.sv Info (12023): Found entity 1: top_altera_merlin_demultiplexer_170_anz2kpy Info (12021): Found 2 design units, including 2 entities, in source file top/altera_merlin_router_170/synth/top_altera_merlin_router_170_mi62fai.sv Info (12023): Found entity 1: top_altera_merlin_router_170_mi62fai_default_decode Info (12023): Found entity 2: top_altera_merlin_router_170_mi62fai Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_multiplexer_170/synth/top_altera_merlin_multiplexer_170_ovmxaly.sv Info (12023): Found entity 1: top_altera_merlin_multiplexer_170_ovmxaly Info (12021): Found 2 design units, including 2 entities, in source file top/altera_merlin_router_170/synth/top_altera_merlin_router_170_miqf3jy.sv Info (12023): Found entity 1: top_altera_merlin_router_170_miqf3jy_default_decode Info (12023): Found entity 2: top_altera_merlin_router_170_miqf3jy Info (12021): Found 1 design units, including 1 entities, in source file top/altera_avalon_st_adapter_170/synth/top_altera_avalon_st_adapter_170_bdgiasa.v Info (12023): Found entity 1: top_altera_avalon_st_adapter_170_bdgiasa Info (12021): Found 1 design units, including 0 entities, in source file top/altera_avalon_st_adapter_170/synth/top_altera_avalon_st_adapter_170_bdgiasa_cfg.v Info (12022): Found design unit 1: top_altera_avalon_st_adapter_170_bdgiasa_cfg:config Info (12021): Found 1 design units, including 1 entities, in source file top/error_adapter_170/synth/top_error_adapter_170_swe3ygy.sv Info (12023): Found entity 1: top_error_adapter_170_swe3ygy Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_multiplexer_170/synth/top_altera_merlin_multiplexer_170_ztypj2i.sv Info (12023): Found entity 1: top_altera_merlin_multiplexer_170_ztypj2i Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_multiplexer_170/synth/top_altera_merlin_multiplexer_170_ywbcz7i.sv Info (12023): Found entity 1: top_altera_merlin_multiplexer_170_ywbcz7i Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_demultiplexer_170/synth/top_altera_merlin_demultiplexer_170_biwebwq.sv Info (12023): Found entity 1: top_altera_merlin_demultiplexer_170_biwebwq Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_burst_adapter_170/synth/altera_merlin_burst_adapter.sv Info (12023): Found entity 1: altera_merlin_burst_adapter Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_burst_adapter_170/synth/altera_merlin_burst_adapter_uncmpr.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_uncompressed_only Info (12021): Found 5 design units, including 5 entities, in source file top/altera_merlin_burst_adapter_170/synth/altera_merlin_burst_adapter_13_1.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment Info (12023): Found entity 2: altera_merlin_burst_adapter_adder Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor Info (12023): Found entity 4: altera_merlin_burst_adapter_min Info (12023): Found entity 5: altera_merlin_burst_adapter_13_1 Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_burst_adapter_170/synth/altera_merlin_burst_adapter_new.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_new Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_burst_adapter_170/synth/altera_incr_burst_converter.sv Info (12023): Found entity 1: altera_incr_burst_converter Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_burst_adapter_170/synth/altera_wrap_burst_converter.sv Info (12023): Found entity 1: altera_wrap_burst_converter Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_burst_adapter_170/synth/altera_default_burst_converter.sv Info (12023): Found entity 1: altera_default_burst_converter Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_burst_adapter_170/synth/altera_merlin_address_alignment.sv Info (12023): Found entity 1: altera_merlin_address_alignment Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_burst_adapter_170/synth/altera_avalon_st_pipeline_stage.sv Info (12023): Found entity 1: altera_avalon_st_pipeline_stage Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_burst_adapter_170/synth/altera_avalon_st_pipeline_base.v Info (12023): Found entity 1: altera_avalon_st_pipeline_base Info (12021): Found 1 design units, including 1 entities, in source file top/altera_mm_interconnect_170/synth/top_altera_mm_interconnect_170_jxo6s5y.v Info (12023): Found entity 1: top_altera_mm_interconnect_170_jxo6s5y Info (12021): Found 1 design units, including 0 entities, in source file top/altera_mm_interconnect_170/synth/top_altera_mm_interconnect_170_jxo6s5y_cfg.v Info (12022): Found design unit 1: top_altera_mm_interconnect_170_jxo6s5y_cfg:config Info (12021): Found 2 design units, including 2 entities, in source file top/altera_merlin_router_170/synth/top_altera_merlin_router_170_nrj42dy.sv Info (12023): Found entity 1: top_altera_merlin_router_170_nrj42dy_default_decode Info (12023): Found entity 2: top_altera_merlin_router_170_nrj42dy Info (12021): Found 2 design units, including 2 entities, in source file top/altera_merlin_router_170/synth/top_altera_merlin_router_170_2dytdla.sv Info (12023): Found entity 1: top_altera_merlin_router_170_2dytdla_default_decode Info (12023): Found entity 2: top_altera_merlin_router_170_2dytdla Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_multiplexer_170/synth/top_altera_merlin_multiplexer_170_m5qzx3a.sv Info (12023): Found entity 1: top_altera_merlin_multiplexer_170_m5qzx3a Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_multiplexer_170/synth/top_altera_merlin_multiplexer_170_zvwmuby.sv Info (12023): Found entity 1: top_altera_merlin_multiplexer_170_zvwmuby Info (12021): Found 1 design units, including 1 entities, in source file top/altera_merlin_demultiplexer_170/synth/top_altera_merlin_demultiplexer_170_ntpavfy.sv Info (12023): Found entity 1: top_altera_merlin_demultiplexer_170_ntpavfy Info (12021): Found 1 design units, including 1 entities, in source file top/altera_avalon_onchip_memory2_170/synth/top_altera_avalon_onchip_memory2_170_owktnaq.v Info (12023): Found entity 1: top_altera_avalon_onchip_memory2_170_owktnaq Info (12127): Elaborating entity "top_hw" for the top level hierarchy Info (12128): Elaborating entity "top" for hierarchy "top:top" Info (12128): Elaborating entity "top_altera_avalon_onchip_memory2_170_owktnaq" for hierarchy "top:top|top_altera_avalon_onchip_memory2_170_owktnaq:onchip_memory2_0" Info (12128): Elaborating entity "altsyncram" for hierarchy "top:top|top_altera_avalon_onchip_memory2_170_owktnaq:onchip_memory2_0|altsyncram:the_altsyncram" Info (12130): Elaborated megafunction instantiation "top:top|top_altera_avalon_onchip_memory2_170_owktnaq:onchip_memory2_0|altsyncram:the_altsyncram" Info (12133): Instantiated megafunction "top:top|top_altera_avalon_onchip_memory2_170_owktnaq:onchip_memory2_0|altsyncram:the_altsyncram" with the following parameter: Info (12134): Parameter "address_reg_b" = "CLOCK1" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "byteena_reg_b" = "CLOCK1" Info (12134): Parameter "indata_reg_b" = "CLOCK1" Info (12134): Parameter "init_file" = "top_onchip_memory2_0.hex" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "maximum_depth" = "2080" Info (12134): Parameter "numwords_a" = "2080" Info (12134): Parameter "numwords_b" = "2080" Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "256" Info (12134): Parameter "width_b" = "256" Info (12134): Parameter "width_byteena_a" = "32" Info (12134): Parameter "width_byteena_b" = "32" Info (12134): Parameter "widthad_a" = "12" Info (12134): Parameter "widthad_b" = "12" Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_g792.tdf Info (12023): Found entity 1: altsyncram_g792 Info (12128): Elaborating entity "altsyncram_g792" for hierarchy "top:top|top_altera_avalon_onchip_memory2_170_owktnaq:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_g792:auto_generated" Info (12128): Elaborating entity "top_altera_pcie_a10_hip_170_6po5avi" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0" Info (12128): Elaborating entity "altpcie_reset_delay_sync" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_reset_delay_sync:g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl" Info (12128): Elaborating entity "altpcie_a10_hip_pipen1b" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b" Warning (10242): Verilog HDL Function Declaration warning at altpcie_a10_hip_pipen1b.v(1089): variable "return_string" may have a Don't Care value because it may not be assigned a value in every possible path through the statements preceding its use Warning (10858): Verilog HDL warning at altpcie_a10_hip_pipen1b.v(1316): object current_rate_r used but never assigned Warning (10858): Verilog HDL warning at altpcie_a10_hip_pipen1b.v(1317): object ltssm_eq_phase2_r used but never assigned Warning (10858): Verilog HDL warning at altpcie_a10_hip_pipen1b.v(1318): object ltssm_detect_quiet_r used but never assigned Warning (10858): Verilog HDL warning at altpcie_a10_hip_pipen1b.v(1319): object ltssm_detect_active_r used but never assigned Warning (10858): Verilog HDL warning at altpcie_a10_hip_pipen1b.v(3392): object skp_pat_det_g3_ps used but never assigned Info (12128): Elaborating entity "altpcie_reset_delay_sync" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_reset_delay_sync:npor_sync_altpcie_reset_delay_sync" Info (12128): Elaborating entity "altpcie_sc_bitsync_node" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_sc_bitsync_node:pld_clk_in_use_altpcie_sc_bitsync" Info (12128): Elaborating entity "altpcie_sc_bitsync" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_sc_bitsync_node:pld_clk_in_use_altpcie_sc_bitsync|altpcie_sc_bitsync:altpcie_sc_bitsync" Info (12128): Elaborating entity "altpcie_sc_bitsync_node" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_sc_bitsync_node:reset_status_altpcie_sc_bitsync" Info (12128): Elaborating entity "altpcie_sc_bitsync" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_sc_bitsync_node:reset_status_altpcie_sc_bitsync|altpcie_sc_bitsync:altpcie_sc_bitsync" Info (12128): Elaborating entity "altpcie_rs_a10_hip" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_rs_a10_hip:g_soft_reset.g02.g03.altpcie_rs_a10_hip" Warning (10036): Verilog HDL or VHDL warning at altpcie_rs_a10_hip.v(47): object "ltssm_rr" assigned a value but never read Info (12128): Elaborating entity "altpcie_reset_delay_sync" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_rs_a10_hip:g_soft_reset.g02.g03.altpcie_rs_a10_hip|altpcie_reset_delay_sync:npor_sync_altpcie_reset_delay_sync_altpcie_rs_a10_hip" Info (12128): Elaborating entity "altpcie_a10_hip_pllnphy" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy" Info (12128): Elaborating entity "phy_g3x8" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8" Info (12128): Elaborating entity "top_altera_xcvr_native_a10_170_n5vprta" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8" Warning (10230): Verilog HDL assignment warning at top_altera_xcvr_native_a10_170_n5vprta.sv(1147): truncated value with size 16 to match size of target (2) Info (12128): Elaborating entity "alt_xcvr_native_rcfg_opt_logic_n5vprta" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic" Info (12128): Elaborating entity "altera_debug_master_endpoint" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|altera_debug_master_endpoint:g_jtag.adme" Info (12130): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|altera_debug_master_endpoint:g_jtag.adme" Info (12133): Instantiated megafunction "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|altera_debug_master_endpoint:g_jtag.adme" with the following parameter: Info (12134): Parameter "ADDR_WIDTH" = "13" Info (12134): Parameter "DATA_WIDTH" = "32" Info (12134): Parameter "HAS_RDV" = "0" Info (12134): Parameter "SLAVE_MAP" = "{typeName altera_xcvr_native_a10 address 0x0 span 32768 hpath {} assignments {dataRate 5000000000 protMode pipe_g3 device_revision 20nm5}}" Info (12134): Parameter "PREFER_HOST" = " " Info (12134): Parameter "CLOCK_RATE_CLK" = "0" Info (12128): Elaborating entity "altera_fabric_endpoint" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|altera_debug_master_endpoint:g_jtag.adme|altera_fabric_endpoint:ep" Info (12131): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|altera_debug_master_endpoint:g_jtag.adme|altera_fabric_endpoint:ep", which is child of megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|altera_debug_master_endpoint:g_jtag.adme" Info (12128): Elaborating entity "alt_xcvr_native_rcfg_arb" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|alt_xcvr_native_rcfg_arb:g_arbiber_enable.alt_xcvr_rcfg_arb" Info (12128): Elaborating entity "alt_xcvr_arbiter" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|alt_xcvr_native_rcfg_arb:g_arbiber_enable.alt_xcvr_rcfg_arb|alt_xcvr_arbiter:g_arb[0].arbiter_inst" Info (12128): Elaborating entity "alt_xcvr_native_avmm_csr" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|alt_xcvr_native_avmm_csr:g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr" Info (12128): Elaborating entity "alt_xcvr_native_avmm_csr" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|alt_xcvr_native_avmm_csr:g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr" Info (12128): Elaborating entity "alt_xcvr_native_avmm_csr" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|alt_xcvr_native_avmm_csr:g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr" Info (12128): Elaborating entity "alt_xcvr_native_avmm_csr" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|alt_xcvr_native_avmm_csr:g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr" Info (12128): Elaborating entity "alt_xcvr_native_avmm_csr" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|alt_xcvr_native_avmm_csr:g_optional_chnl_reconfig_logic[4].g_avmm_csr_enabled.embedded_debug_soft_csr" Info (12128): Elaborating entity "alt_xcvr_native_avmm_csr" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|alt_xcvr_native_avmm_csr:g_optional_chnl_reconfig_logic[5].g_avmm_csr_enabled.embedded_debug_soft_csr" Info (12128): Elaborating entity "alt_xcvr_native_avmm_csr" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|alt_xcvr_native_avmm_csr:g_optional_chnl_reconfig_logic[6].g_avmm_csr_enabled.embedded_debug_soft_csr" Info (12128): Elaborating entity "alt_xcvr_native_avmm_csr" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|alt_xcvr_native_rcfg_opt_logic_n5vprta:alt_xcvr_native_optional_rcfg_logic|alt_xcvr_native_avmm_csr:g_optional_chnl_reconfig_logic[7].g_avmm_csr_enabled.embedded_debug_soft_csr" Info (12128): Elaborating entity "twentynm_xcvr_native" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_xcvr_native_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_pma_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma" Info (12128): Elaborating entity "twentynm_pcs_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs" Info (12128): Elaborating entity "twentynm_xcvr_avmm" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_xcvr_avmm:inst_twentynm_xcvr_avmm" Info (12128): Elaborating entity "alt_xcvr_resync" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_xcvr_avmm:inst_twentynm_xcvr_avmm|alt_xcvr_resync:avmm_atom_insts[0].avmm_reset_sync_inst" Info (12128): Elaborating entity "twentynm_xcvr_native" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[1].twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_xcvr_native_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_pma_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma" Info (12128): Elaborating entity "twentynm_pcs_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs" Info (12128): Elaborating entity "twentynm_xcvr_native" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[2].twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_xcvr_native_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_pma_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma" Info (12128): Elaborating entity "twentynm_pcs_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs" Info (12128): Elaborating entity "twentynm_xcvr_native" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_xcvr_native_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_pma_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma" Info (12128): Elaborating entity "twentynm_pcs_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs" Info (12128): Elaborating entity "twentynm_xcvr_native" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[4].twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_xcvr_native_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_pma_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma" Info (12128): Elaborating entity "twentynm_pcs_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs" Info (12128): Elaborating entity "twentynm_xcvr_native" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_xcvr_native_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_pma_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma" Info (12128): Elaborating entity "twentynm_pcs_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs" Info (12128): Elaborating entity "twentynm_xcvr_native" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[6].twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_xcvr_native_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_pma_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma" Info (12128): Elaborating entity "twentynm_pcs_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs" Info (12128): Elaborating entity "twentynm_xcvr_native" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[7].twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_xcvr_native_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst" Info (12128): Elaborating entity "twentynm_pma_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma" Info (12128): Elaborating entity "twentynm_pcs_rev_20nm5" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs" Info (12128): Elaborating entity "fpll_g3" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|fpll_g3:g_pll.fpll_g3" Info (12128): Elaborating entity "altera_xcvr_fpll_a10" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|fpll_g3:g_pll.fpll_g3|altera_xcvr_fpll_a10:fpll_g3" Warning (10036): Verilog HDL or VHDL warning at altera_xcvr_fpll_a10.sv(521): object "mcgb_rst_input" assigned a value but never read Info (12128): Elaborating entity "alt_xcvr_native_avmm_nf" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|fpll_g3:g_pll.fpll_g3|altera_xcvr_fpll_a10:fpll_g3|alt_xcvr_native_avmm_nf:altera_xcvr_pll_avmm_nf_inst" Info (12128): Elaborating entity "twentynm_xcvr_avmm" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|fpll_g3:g_pll.fpll_g3|altera_xcvr_fpll_a10:fpll_g3|twentynm_xcvr_avmm:xcvr_avmm_inst" Info (12128): Elaborating entity "alt_xcvr_resync" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|fpll_g3:g_pll.fpll_g3|altera_xcvr_fpll_a10:fpll_g3|twentynm_xcvr_avmm:xcvr_avmm_inst|alt_xcvr_resync:avmm_atom_insts[0].avmm_reset_sync_inst" Info (12128): Elaborating entity "dps_pulse_ctrl" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|fpll_g3:g_pll.fpll_g3|altera_xcvr_fpll_a10:fpll_g3|dps_pulse_ctrl:phase_en_pulse" Info (12128): Elaborating entity "dps_reset_gen" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|fpll_g3:g_pll.fpll_g3|altera_xcvr_fpll_a10:fpll_g3|dps_reset_gen:dps_reset_gen_1" Info (12128): Elaborating entity "lcpll_g3xn" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|lcpll_g3xn:g_pll.g_pll_g3n.lcpll_g3xn" Info (12128): Elaborating entity "top_altera_xcvr_atx_pll_a10_170_nd26ega" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|lcpll_g3xn:g_pll.g_pll_g3n.lcpll_g3xn|top_altera_xcvr_atx_pll_a10_170_nd26ega:lcpll_g3xn" Info (12128): Elaborating entity "alt_xcvr_atx_pll_rcfg_opt_logic_nd26ega" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|lcpll_g3xn:g_pll.g_pll_g3n.lcpll_g3xn|top_altera_xcvr_atx_pll_a10_170_nd26ega:lcpll_g3xn|alt_xcvr_atx_pll_rcfg_opt_logic_nd26ega:alt_xcvr_atx_pll_optional_rcfg_logic" Info (12128): Elaborating entity "a10_xcvr_atx_pll" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|lcpll_g3xn:g_pll.g_pll_g3n.lcpll_g3xn|top_altera_xcvr_atx_pll_a10_170_nd26ega:lcpll_g3xn|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst" Info (12128): Elaborating entity "twentynm_xcvr_avmm" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|lcpll_g3xn:g_pll.g_pll_g3n.lcpll_g3xn|top_altera_xcvr_atx_pll_a10_170_nd26ega:lcpll_g3xn|twentynm_xcvr_avmm:a10_xcvr_avmm_inst" Info (12128): Elaborating entity "alt_xcvr_resync" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|lcpll_g3xn:g_pll.g_pll_g3n.lcpll_g3xn|top_altera_xcvr_atx_pll_a10_170_nd26ega:lcpll_g3xn|twentynm_xcvr_avmm:a10_xcvr_avmm_inst|alt_xcvr_resync:avmm_atom_insts[0].avmm_reset_sync_inst" Info (12128): Elaborating entity "altpcie_grounder" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_grounder:eidleinfersel0_gnd" Info (12128): Elaborating entity "altpcie_grounder" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_grounder:powerdown0_gnd" Info (12128): Elaborating entity "altpcie_grounder" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_grounder:rxpolarity0_gnd" Info (12128): Elaborating entity "altpcie_grounder" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_grounder:txdata0_gnd" Info (12128): Elaborating entity "altpcie_grounder" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_grounder:txdatak0_gnd" Info (12128): Elaborating entity "altpcie_grounder" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_grounder:currentcoeff0_gnd" Info (12128): Elaborating entity "altpcie_rxm_2_dma_controller_decode" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_rxm_2_dma_controller_decode:g_dmacontrol.dmacontrol.altpcie_rxm_2_dma_controller_decode" Info (12128): Elaborating entity "dma_control" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0" Info (12128): Elaborating entity "altpcie_dynamic_control" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control" Warning (10036): Verilog HDL or VHDL warning at altpcie_dynamic_control.sv(102): object "dt_fifo_wrreq_reg1" assigned a value but never read Info (10264): Verilog HDL Case Statement information at altpcie_dynamic_control.sv(243): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcie_dynamic_control.sv(373): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcie_dynamic_control.sv(425): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcie_dynamic_control.sv(575): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcie_dynamic_control.sv(843): all case item expressions in this case statement are onehot Info (12128): Elaborating entity "scfifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo" Info (12130): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo" Info (12133): Instantiated megafunction "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo" with the following parameter: Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "intended_device_family" = "Stratix V" Info (12134): Parameter "lpm_numwords" = "256" Info (12134): Parameter "lpm_showahead" = "OFF" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "160" Info (12134): Parameter "lpm_widthu" = "8" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_c9a1.tdf Info (12023): Found entity 1: scfifo_c9a1 Info (12128): Elaborating entity "scfifo_c9a1" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated" Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_lk91.tdf Info (12023): Found entity 1: a_dpfifo_lk91 Info (12128): Elaborating entity "a_dpfifo_lk91" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_2gn1.tdf Info (12023): Found entity 1: altsyncram_2gn1 Info (12128): Elaborating entity "altsyncram_2gn1" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram" Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_kd8.tdf Info (12023): Found entity 1: cmpr_kd8 Info (12128): Elaborating entity "cmpr_kd8" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|cmpr_kd8:almost_full_comparer" Info (12128): Elaborating entity "cmpr_kd8" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|cmpr_kd8:two_comparison" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_19b.tdf Info (12023): Found entity 1: cntr_19b Info (12128): Elaborating entity "cntr_19b" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|cntr_19b:rd_ptr_msb" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_e97.tdf Info (12023): Found entity 1: cntr_e97 Info (12128): Elaborating entity "cntr_e97" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|cntr_e97:usedw_counter" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_29b.tdf Info (12023): Found entity 1: cntr_29b Info (12128): Elaborating entity "cntr_29b" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|cntr_29b:wr_ptr" Info (12128): Elaborating entity "altpcie_fifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|altpcie_fifo:ep_last_fifo" Info (12128): Elaborating entity "altpcie_dynamic_control" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control" Warning (10036): Verilog HDL or VHDL warning at altpcie_dynamic_control.sv(102): object "dt_fifo_wrreq_reg1" assigned a value but never read Info (10264): Verilog HDL Case Statement information at altpcie_dynamic_control.sv(243): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcie_dynamic_control.sv(373): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcie_dynamic_control.sv(425): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcie_dynamic_control.sv(575): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcie_dynamic_control.sv(843): all case item expressions in this case statement are onehot Info (12128): Elaborating entity "altpcieav_256_app" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app" Info (12128): Elaborating entity "altpcieav_dma_rxm" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rxm:rxm_master" Info (10264): Verilog HDL Case Statement information at altpcieav_dma_rxm.sv(345): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcieav_dma_rxm.sv(443): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcieav_dma_rxm.sv(507): all case item expressions in this case statement are onehot Info (12128): Elaborating entity "altpcieav_dma_txs" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_txs:txs_slave" Info (10264): Verilog HDL Case Statement information at altpcieav_dma_txs.sv(142): all case item expressions in this case statement are onehot Info (12128): Elaborating entity "altpcieav_hip_interface" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf" Info (12128): Elaborating entity "altpcie_fifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_eop_fifo" Info (12128): Elaborating entity "altpcie_fifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:rx_input_fifo" Info (12128): Elaborating entity "altpcie_fifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|altpcie_fifo:predecode_tag_fifo" Info (12128): Elaborating entity "scfifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|scfifo:g_tx_output_fifo.tx_output_fifo" Info (12130): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|scfifo:g_tx_output_fifo.tx_output_fifo" Info (12133): Instantiated megafunction "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|scfifo:g_tx_output_fifo.tx_output_fifo" with the following parameter: Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "intended_device_family" = "Stratix V" Info (12134): Parameter "lpm_numwords" = "64" Info (12134): Parameter "lpm_showahead" = "OFF" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "260" Info (12134): Parameter "lpm_widthu" = "6" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_o7a1.tdf Info (12023): Found entity 1: scfifo_o7a1 Info (12128): Elaborating entity "scfifo_o7a1" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|scfifo:g_tx_output_fifo.tx_output_fifo|scfifo_o7a1:auto_generated" Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_1j91.tdf Info (12023): Found entity 1: a_dpfifo_1j91 Info (12128): Elaborating entity "a_dpfifo_1j91" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|scfifo:g_tx_output_fifo.tx_output_fifo|scfifo_o7a1:auto_generated|a_dpfifo_1j91:dpfifo" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_qcn1.tdf Info (12023): Found entity 1: altsyncram_qcn1 Info (12128): Elaborating entity "altsyncram_qcn1" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|scfifo:g_tx_output_fifo.tx_output_fifo|scfifo_o7a1:auto_generated|a_dpfifo_1j91:dpfifo|altsyncram_qcn1:FIFOram" Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_id8.tdf Info (12023): Found entity 1: cmpr_id8 Info (12128): Elaborating entity "cmpr_id8" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|scfifo:g_tx_output_fifo.tx_output_fifo|scfifo_o7a1:auto_generated|a_dpfifo_1j91:dpfifo|cmpr_id8:almost_full_comparer" Info (12128): Elaborating entity "cmpr_id8" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|scfifo:g_tx_output_fifo.tx_output_fifo|scfifo_o7a1:auto_generated|a_dpfifo_1j91:dpfifo|cmpr_id8:two_comparison" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_v8b.tdf Info (12023): Found entity 1: cntr_v8b Info (12128): Elaborating entity "cntr_v8b" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|scfifo:g_tx_output_fifo.tx_output_fifo|scfifo_o7a1:auto_generated|a_dpfifo_1j91:dpfifo|cntr_v8b:rd_ptr_msb" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_c97.tdf Info (12023): Found entity 1: cntr_c97 Info (12128): Elaborating entity "cntr_c97" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|scfifo:g_tx_output_fifo.tx_output_fifo|scfifo_o7a1:auto_generated|a_dpfifo_1j91:dpfifo|cntr_c97:usedw_counter" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_09b.tdf Info (12023): Found entity 1: cntr_09b Info (12128): Elaborating entity "cntr_09b" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|scfifo:g_tx_output_fifo.tx_output_fifo|scfifo_o7a1:auto_generated|a_dpfifo_1j91:dpfifo|cntr_09b:wr_ptr" Info (12128): Elaborating entity "altpcieav_dma_rd" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover" Info (10264): Verilog HDL Case Statement information at altpcieav_dma_rd.sv(737): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcieav_dma_rd.sv(790): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcieav_dma_rd.sv(1041): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcieav_dma_rd.sv(1570): all case item expressions in this case statement are onehot Warning (10762): Verilog HDL Case Statement warning at altpcieav_dma_rd.sv(2342): can't check case statement for completeness because the case expression has too many possible states Info (10264): Verilog HDL Case Statement information at altpcieav_dma_rd.sv(2898): all case item expressions in this case statement are onehot Info (12128): Elaborating entity "altpcie_fifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:read_desc_fifo" Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|lpm_add_sub:LPM_DEST_ADD_SUB_component" Info (12130): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|lpm_add_sub:LPM_DEST_ADD_SUB_component" Info (12133): Instantiated megafunction "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|lpm_add_sub:LPM_DEST_ADD_SUB_component" with the following parameter: Info (12134): Parameter "lpm_direction" = "ADD" Info (12134): Parameter "lpm_hint" = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO" Info (12134): Parameter "lpm_pipeline" = "1" Info (12134): Parameter "lpm_representation" = "UNSIGNED" Info (12134): Parameter "lpm_type" = "LPM_ADD_SUB" Info (12134): Parameter "lpm_width" = "64" Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_17k.tdf Info (12023): Found entity 1: add_sub_17k Info (12128): Elaborating entity "add_sub_17k" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|lpm_add_sub:LPM_DEST_ADD_SUB_component|add_sub_17k:auto_generated" Info (12128): Elaborating entity "altpcie_fifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:tag_fifo" Info (12128): Elaborating entity "altpcie_fifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:tag_queu" Info (12128): Elaborating entity "scfifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|scfifo:g_avmmwr_data_fifo.avmmwr_data_fifo" Info (12130): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|scfifo:g_avmmwr_data_fifo.avmmwr_data_fifo" Info (12133): Instantiated megafunction "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|scfifo:g_avmmwr_data_fifo.avmmwr_data_fifo" with the following parameter: Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "intended_device_family" = "Stratix V" Info (12134): Parameter "lpm_numwords" = "512" Info (12134): Parameter "lpm_showahead" = "OFF" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "288" Info (12134): Parameter "lpm_widthu" = "9" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_j9a1.tdf Info (12023): Found entity 1: scfifo_j9a1 Info (12128): Elaborating entity "scfifo_j9a1" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|scfifo:g_avmmwr_data_fifo.avmmwr_data_fifo|scfifo_j9a1:auto_generated" Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_sk91.tdf Info (12023): Found entity 1: a_dpfifo_sk91 Info (12128): Elaborating entity "a_dpfifo_sk91" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|scfifo:g_avmmwr_data_fifo.avmmwr_data_fifo|scfifo_j9a1:auto_generated|a_dpfifo_sk91:dpfifo" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ggn1.tdf Info (12023): Found entity 1: altsyncram_ggn1 Info (12128): Elaborating entity "altsyncram_ggn1" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|scfifo:g_avmmwr_data_fifo.avmmwr_data_fifo|scfifo_j9a1:auto_generated|a_dpfifo_sk91:dpfifo|altsyncram_ggn1:FIFOram" Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_ld8.tdf Info (12023): Found entity 1: cmpr_ld8 Info (12128): Elaborating entity "cmpr_ld8" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|scfifo:g_avmmwr_data_fifo.avmmwr_data_fifo|scfifo_j9a1:auto_generated|a_dpfifo_sk91:dpfifo|cmpr_ld8:almost_full_comparer" Info (12128): Elaborating entity "cmpr_ld8" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|scfifo:g_avmmwr_data_fifo.avmmwr_data_fifo|scfifo_j9a1:auto_generated|a_dpfifo_sk91:dpfifo|cmpr_ld8:two_comparison" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_f97.tdf Info (12023): Found entity 1: cntr_f97 Info (12128): Elaborating entity "cntr_f97" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|scfifo:g_avmmwr_data_fifo.avmmwr_data_fifo|scfifo_j9a1:auto_generated|a_dpfifo_sk91:dpfifo|cntr_f97:usedw_counter" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_39b.tdf Info (12023): Found entity 1: cntr_39b Info (12128): Elaborating entity "cntr_39b" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|scfifo:g_avmmwr_data_fifo.avmmwr_data_fifo|scfifo_j9a1:auto_generated|a_dpfifo_sk91:dpfifo|cntr_39b:wr_ptr" Info (12128): Elaborating entity "altpcie_fifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:rxm_cmd_fifo" Info (12128): Elaborating entity "altpcie_fifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_rd:read_data_mover|altpcie_fifo:rd_status_fifo" Info (12128): Elaborating entity "altpcieav_dma_wr_2" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2" Info (12128): Elaborating entity "altpcieav_dma_wr_readmem_2" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_readmem_2:dma_wr_readmem" Info (10264): Verilog HDL Case Statement information at altpcieav_dma_wr_readmem_2.sv(344): all case item expressions in this case statement are onehot Info (10264): Verilog HDL Case Statement information at altpcieav_dma_wr_readmem_2.sv(727): all case item expressions in this case statement are onehot Info (12128): Elaborating entity "altsyncram" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_readmem_2:dma_wr_readmem|altsyncram:wr_data_buff" Info (12130): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_readmem_2:dma_wr_readmem|altsyncram:wr_data_buff" Info (12133): Instantiated megafunction "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_readmem_2:dma_wr_readmem|altsyncram:wr_data_buff" with the following parameter: Info (12134): Parameter "intended_device_family" = "Stratix V" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "width_a" = "256" Info (12134): Parameter "widthad_a" = "9" Info (12134): Parameter "numwords_a" = "512" Info (12134): Parameter "width_b" = "256" Info (12134): Parameter "widthad_b" = "9" Info (12134): Parameter "numwords_b" = "512" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "indata_aclr_a" = "NONE" Info (12134): Parameter "wrcontrol_aclr_a" = "NONE" Info (12134): Parameter "address_aclr_a" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_fst1.tdf Info (12023): Found entity 1: altsyncram_fst1 Info (12128): Elaborating entity "altsyncram_fst1" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_readmem_2:dma_wr_readmem|altsyncram:wr_data_buff|altsyncram_fst1:auto_generated" Info (12128): Elaborating entity "altpcie_fifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_readmem_2:dma_wr_readmem|altpcie_fifo:total_desc_bcnt_fifo" Info (12128): Elaborating entity "altpcie_fifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_readmem_2:dma_wr_readmem|altpcie_fifo:tlp_gen_desc_fifo" Info (12128): Elaborating entity "altpcieav_dma_wr_wdalign_2" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign" Info (10264): Verilog HDL Case Statement information at altpcieav_dma_wr_wdalign_2.sv(2213): all case item expressions in this case statement are onehot Info (12128): Elaborating entity "altsyncram" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|altsyncram:aligned_data_buff" Info (12130): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|altsyncram:aligned_data_buff" Info (12133): Instantiated megafunction "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|altsyncram:aligned_data_buff" with the following parameter: Info (12134): Parameter "intended_device_family" = "Stratix V" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "width_a" = "258" Info (12134): Parameter "widthad_a" = "9" Info (12134): Parameter "numwords_a" = "512" Info (12134): Parameter "width_b" = "258" Info (12134): Parameter "widthad_b" = "9" Info (12134): Parameter "numwords_b" = "512" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "indata_aclr_a" = "NONE" Info (12134): Parameter "wrcontrol_aclr_a" = "NONE" Info (12134): Parameter "address_aclr_a" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_jst1.tdf Info (12023): Found entity 1: altsyncram_jst1 Info (12128): Elaborating entity "altsyncram_jst1" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|altsyncram:aligned_data_buff|altsyncram_jst1:auto_generated" Info (12128): Elaborating entity "scfifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo" Info (12130): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo" Info (12133): Instantiated megafunction "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo" with the following parameter: Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "intended_device_family" = "Stratix V" Info (12134): Parameter "lpm_numwords" = "16" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "139" Info (12134): Parameter "lpm_widthu" = "4" Info (12134): Parameter "overflow_checking" = "OFF" Info (12134): Parameter "underflow_checking" = "OFF" Info (12134): Parameter "use_eab" = "OFF" Info (12128): Elaborating entity "a_fffifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo" Info (12131): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo", which is child of megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo" Info (12128): Elaborating entity "lpm_ff" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|lpm_ff:last_data_node[15]" Info (12131): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|lpm_ff:last_data_node[15]", which is child of megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo" Info (12128): Elaborating entity "lpm_mux" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux" Info (12131): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux", which is child of megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo" Info (12021): Found 1 design units, including 1 entities, in source file db/mux_ahc.tdf Info (12023): Found entity 1: mux_ahc Info (12128): Elaborating entity "mux_ahc" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux|mux_ahc:auto_generated" Info (12128): Elaborating entity "lpm_counter" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|lpm_counter:rd_ptr" Info (12131): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|lpm_counter:rd_ptr", which is child of megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_2se.tdf Info (12023): Found entity 1: cntr_2se Info (12128): Elaborating entity "cntr_2se" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|lpm_counter:rd_ptr|cntr_2se:auto_generated" Info (12128): Elaborating entity "a_fefifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|a_fefifo:fifo_state" Info (12131): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|a_fefifo:fifo_state", which is child of megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo" Info (12128): Elaborating entity "lpm_compare" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_empty_compare" Info (12131): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_empty_compare", which is child of megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo" Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_80g.tdf Info (12023): Found entity 1: cmpr_80g Info (12128): Elaborating entity "cmpr_80g" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_empty_compare|cmpr_80g:auto_generated" Info (12128): Elaborating entity "lpm_compare" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_full_compare" Info (12131): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_full_compare", which is child of megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_wdalign_2:dma_wr_wdalign|scfifo:tlp_header_fifo" Info (12128): Elaborating entity "altpcieav_dma_wr_tlpgen_2" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|altpcieav_dma_wr_tlpgen_2:dma_wr_tlpgen" Info (10264): Verilog HDL Case Statement information at altpcieav_dma_wr_tlpgen_2.sv(426): all case item expressions in this case statement are onehot Info (12128): Elaborating entity "altpcieav_arbiter" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_arbiter:arbiter_inst" Info (10264): Verilog HDL Case Statement information at altpcieav_arbiter.sv(67): all case item expressions in this case statement are onehot Info (12128): Elaborating entity "altpcieav_cra" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_cra:altpcieav_cra_inst" Info (12128): Elaborating entity "altpcie_fifo" for hierarchy "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcie_fifo:g_tx_side_fifo.tx_side_fifo" Info (12128): Elaborating entity "top_altera_mm_interconnect_170_cthna2i" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0" Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_master_translator:pcie_a10_hip_0_dma_rd_master_translator" Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_master_translator:pcie_a10_hip_0_rxm_bar4_translator" Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_slave_translator:pcie_a10_hip_0_rd_dts_slave_translator" Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_slave_translator:onchip_memory2_0_s1_translator" Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_master_agent:pcie_a10_hip_0_dma_rd_master_agent" Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_master_agent:pcie_a10_hip_0_rxm_bar4_agent" Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_slave_agent:pcie_a10_hip_0_rd_dts_slave_agent" Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_slave_agent:pcie_a10_hip_0_rd_dts_slave_agent|altera_merlin_burst_uncompressor:uncompressor" Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_avalon_sc_fifo:pcie_a10_hip_0_rd_dts_slave_agent_rsp_fifo" Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_slave_agent:onchip_memory2_0_s1_agent" Info (12128): Elaborating entity "top_altera_merlin_router_170_miqf3jy" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_router_170_miqf3jy:router" Info (12128): Elaborating entity "top_altera_merlin_router_170_miqf3jy_default_decode" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_router_170_miqf3jy:router|top_altera_merlin_router_170_miqf3jy_default_decode:the_default_decode" Info (12128): Elaborating entity "top_altera_merlin_router_170_vrleuii" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_router_170_vrleuii:router_001" Info (12128): Elaborating entity "top_altera_merlin_router_170_vrleuii_default_decode" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_router_170_vrleuii:router_001|top_altera_merlin_router_170_vrleuii_default_decode:the_default_decode" Info (12128): Elaborating entity "top_altera_merlin_router_170_4tza2tq" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_router_170_4tza2tq:router_002" Info (12128): Elaborating entity "top_altera_merlin_router_170_4tza2tq_default_decode" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_router_170_4tza2tq:router_002|top_altera_merlin_router_170_4tza2tq_default_decode:the_default_decode" Info (12128): Elaborating entity "top_altera_merlin_router_170_mi62fai" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_router_170_mi62fai:router_003" Info (12128): Elaborating entity "top_altera_merlin_router_170_mi62fai_default_decode" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_router_170_mi62fai:router_003|top_altera_merlin_router_170_mi62fai_default_decode:the_default_decode" Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_0_s1_burst_adapter" Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" Warning (10230): Verilog HDL assignment warning at altera_merlin_burst_adapter_13_1.sv(790): truncated value with size 10 to match size of target (1) Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" Info (12128): Elaborating entity "altera_merlin_burst_adapter_burstwrap_increment" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment" Info (12128): Elaborating entity "altera_merlin_burst_adapter_min" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" Info (12128): Elaborating entity "altera_merlin_burst_adapter_subtractor" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" Info (12128): Elaborating entity "altera_merlin_burst_adapter_adder" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" Info (12128): Elaborating entity "top_altera_merlin_demultiplexer_170_biwebwq" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_demultiplexer_170_biwebwq:cmd_demux" Info (12128): Elaborating entity "top_altera_merlin_demultiplexer_170_anz2kpy" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_demultiplexer_170_anz2kpy:cmd_demux_001" Info (12128): Elaborating entity "top_altera_merlin_multiplexer_170_fzmgtca" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_multiplexer_170_fzmgtca:cmd_mux" Info (12128): Elaborating entity "top_altera_merlin_multiplexer_170_ywbcz7i" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_multiplexer_170_ywbcz7i:cmd_mux_001" Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_multiplexer_170_ywbcz7i:cmd_mux_001|altera_merlin_arbitrator:arb" Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_multiplexer_170_ywbcz7i:cmd_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" Info (12128): Elaborating entity "top_altera_merlin_demultiplexer_170_jdh2m3y" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_demultiplexer_170_jdh2m3y:rsp_demux_001" Info (12128): Elaborating entity "top_altera_merlin_multiplexer_170_ztypj2i" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_multiplexer_170_ztypj2i:rsp_mux" Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_multiplexer_170_ztypj2i:rsp_mux|altera_merlin_arbitrator:arb" Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_multiplexer_170_ztypj2i:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" Info (12128): Elaborating entity "top_altera_merlin_multiplexer_170_ovmxaly" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_merlin_multiplexer_170_ovmxaly:rsp_mux_001" Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_width_adapter:pcie_a10_hip_0_rxm_bar4_rsp_width_adapter" Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_width_adapter:pcie_a10_hip_0_rxm_bar4_cmd_width_adapter" Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|altera_merlin_width_adapter:pcie_a10_hip_0_rxm_bar4_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor" Info (12128): Elaborating entity "top_altera_avalon_st_adapter_170_bdgiasa" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_avalon_st_adapter_170_bdgiasa:avalon_st_adapter" Info (12128): Elaborating entity "top_error_adapter_170_swe3ygy" for hierarchy "top:top|top_altera_mm_interconnect_170_cthna2i:mm_interconnect_0|top_altera_avalon_st_adapter_170_bdgiasa:avalon_st_adapter|top_error_adapter_170_swe3ygy:error_adapter_0" Info (12128): Elaborating entity "top_altera_mm_interconnect_170_jxo6s5y" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1" Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|altera_merlin_master_translator:pcie_a10_hip_0_dma_wr_master_translator" Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|altera_merlin_master_agent:pcie_a10_hip_0_dma_wr_master_agent" Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|altera_merlin_slave_agent:onchip_memory2_0_s2_agent" Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|altera_avalon_sc_fifo:onchip_memory2_0_s2_agent_rsp_fifo" Info (12128): Elaborating entity "top_altera_merlin_router_170_2dytdla" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|top_altera_merlin_router_170_2dytdla:router" Info (12128): Elaborating entity "top_altera_merlin_router_170_2dytdla_default_decode" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|top_altera_merlin_router_170_2dytdla:router|top_altera_merlin_router_170_2dytdla_default_decode:the_default_decode" Info (12128): Elaborating entity "top_altera_merlin_router_170_nrj42dy" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|top_altera_merlin_router_170_nrj42dy:router_001" Info (12128): Elaborating entity "top_altera_merlin_router_170_nrj42dy_default_decode" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|top_altera_merlin_router_170_nrj42dy:router_001|top_altera_merlin_router_170_nrj42dy_default_decode:the_default_decode" Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|altera_merlin_burst_adapter:onchip_memory2_0_s2_burst_adapter" Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|altera_merlin_burst_adapter:onchip_memory2_0_s2_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" Warning (10230): Verilog HDL assignment warning at altera_merlin_burst_adapter_13_1.sv(790): truncated value with size 10 to match size of target (1) Info (12128): Elaborating entity "top_altera_merlin_demultiplexer_170_ntpavfy" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|top_altera_merlin_demultiplexer_170_ntpavfy:cmd_demux" Info (12128): Elaborating entity "top_altera_merlin_multiplexer_170_m5qzx3a" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|top_altera_merlin_multiplexer_170_m5qzx3a:cmd_mux" Info (12128): Elaborating entity "top_altera_merlin_multiplexer_170_zvwmuby" for hierarchy "top:top|top_altera_mm_interconnect_170_jxo6s5y:mm_interconnect_1|top_altera_merlin_multiplexer_170_zvwmuby:rsp_mux" Info (12128): Elaborating entity "top_altera_mm_interconnect_170_u5xbwgq" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2" Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|altera_merlin_slave_translator:pcie_a10_hip_0_txs_translator" Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|altera_merlin_master_agent:pcie_a10_hip_0_rd_dcm_master_agent" Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|altera_merlin_master_agent:pcie_a10_hip_0_wr_dcm_master_agent" Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|altera_merlin_slave_agent:pcie_a10_hip_0_txs_agent" Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|altera_merlin_slave_agent:pcie_a10_hip_0_txs_agent|altera_merlin_burst_uncompressor:uncompressor" Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|altera_avalon_sc_fifo:pcie_a10_hip_0_txs_agent_rsp_fifo" Info (12128): Elaborating entity "top_altera_merlin_router_170_abmhadq" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|top_altera_merlin_router_170_abmhadq:router" Info (12128): Elaborating entity "top_altera_merlin_router_170_abmhadq_default_decode" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|top_altera_merlin_router_170_abmhadq:router|top_altera_merlin_router_170_abmhadq_default_decode:the_default_decode" Info (12128): Elaborating entity "top_altera_merlin_router_170_xw6e4zq" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|top_altera_merlin_router_170_xw6e4zq:router_002" Info (12128): Elaborating entity "top_altera_merlin_router_170_xw6e4zq_default_decode" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|top_altera_merlin_router_170_xw6e4zq:router_002|top_altera_merlin_router_170_xw6e4zq_default_decode:the_default_decode" Info (12128): Elaborating entity "top_altera_merlin_demultiplexer_170_bmirlai" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|top_altera_merlin_demultiplexer_170_bmirlai:cmd_demux" Info (12128): Elaborating entity "top_altera_merlin_multiplexer_170_bsnxubi" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|top_altera_merlin_multiplexer_170_bsnxubi:cmd_mux" Info (12128): Elaborating entity "top_altera_merlin_demultiplexer_170_ptmmvpq" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|top_altera_merlin_demultiplexer_170_ptmmvpq:rsp_demux" Info (12128): Elaborating entity "top_altera_merlin_multiplexer_170_yitdyoi" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|top_altera_merlin_multiplexer_170_yitdyoi:rsp_mux" Info (12128): Elaborating entity "top_altera_avalon_st_adapter_170_lmw3z4y" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|top_altera_avalon_st_adapter_170_lmw3z4y:avalon_st_adapter" Info (12128): Elaborating entity "top_error_adapter_170_mtlhioy" for hierarchy "top:top|top_altera_mm_interconnect_170_u5xbwgq:mm_interconnect_2|top_altera_avalon_st_adapter_170_lmw3z4y:avalon_st_adapter|top_error_adapter_170_mtlhioy:error_adapter_0" Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "top:top|altera_reset_controller:rst_controller" Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "top:top|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "top:top|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" Warning (12011): Net is missing source, defaulting to GND Warning (12110): Net "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_wr_2:write_data_mover_2|desc_fifo_count[3]" is missing source, defaulting to GND Warning (12010): Port "datab" on the entity instantiation of "LPM_DEST_ADD_SUB_component" is connected to a signal of width 12. The formal width of the signal in the module is 64. The extra bits will be driven by GND. Warning (12011): Net is missing source, defaulting to GND Warning (12110): Net "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control_0_dcs_slave_0_byteenable[7]" is missing source, defaulting to GND Warning (12110): Net "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control_0_dcs_slave_0_byteenable[6]" is missing source, defaulting to GND Warning (12110): Net "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control_0_dcs_slave_0_byteenable[5]" is missing source, defaulting to GND Warning (12110): Net "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control_0_dcs_slave_0_byteenable[4]" is missing source, defaulting to GND Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_bd84.tdf Info (12023): Found entity 1: altsyncram_bd84 Info (12021): Found 1 design units, including 1 entities, in source file db/mux_qdc.tdf Info (12023): Found entity 1: mux_qdc Info (12021): Found 1 design units, including 1 entities, in source file db/decode_cgf.tdf Info (12023): Found entity 1: decode_cgf Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_i4i.tdf Info (12023): Found entity 1: cntr_i4i Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_63c.tdf Info (12023): Found entity 1: cmpr_63c Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_fqi.tdf Info (12023): Found entity 1: cntr_fqi Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_d1i.tdf Info (12023): Found entity 1: cntr_d1i Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_q1c.tdf Info (12023): Found entity 1: cmpr_q1c Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1ki.tdf Info (12023): Found entity 1: cntr_1ki Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_m1c.tdf Info (12023): Found entity 1: cmpr_m1c Info (12033): Analysis and Synthesis generated SignalTap II or debug node instance "auto_signaltap_0" Info (11170): Starting IP generation for the debug fabric: alt_sld_fab. Info (11172): 2017.11.13.10:36:21 Progress: Loading sld4d43b179/alt_sld_fab_wrapper_hw.tcl Info (11172): Alt_sld_fab.alt_sld_fab: Avalon ST-Debug fabric agents which did not specify prefer_host were connected to JTAG Info (11172): Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG Info (11172): Alt_sld_fab: "Transforming system: alt_sld_fab" Info (11172): Alt_sld_fab: Running transform generation_view_transform Info (11172): Alt_sld_fab: Running transform generation_view_transform took 0.000s Info (11172): Alt_sld_fab: Running transform generation_view_transform Info (11172): Alt_sld_fab: Running transform generation_view_transform took 0.001s Info (11172): Presplit: Running transform generation_view_transform Info (11172): Presplit: Running transform generation_view_transform took 0.000s Info (11172): Splitter: Running transform generation_view_transform Info (11172): Splitter: Running transform generation_view_transform took 0.000s Info (11172): Memfabric: Running transform generation_view_transform Info (11172): Memfabric: Running transform generation_view_transform took 0.000s Info (11172): Host_link_jtag: Running transform generation_view_transform Info (11172): Host_link_jtag: Running transform generation_view_transform took 0.000s Info (11172): Stfabric: Running transform generation_view_transform Info (11172): Stfabric: Running transform generation_view_transform took 0.000s Info (11172): Jtagpins: Running transform generation_view_transform Info (11172): Jtagpins: Running transform generation_view_transform took 0.000s Info (11172): Sldfabric: Running transform generation_view_transform Info (11172): Sldfabric: Running transform generation_view_transform took 0.000s Info (11172): Ident: Running transform generation_view_transform Info (11172): Ident: Running transform generation_view_transform took 0.000s Info (11172): Clock: Running transform generation_view_transform Info (11172): Clock: Running transform generation_view_transform took 0.000s Info (11172): Debug_reset: Running transform generation_view_transform Info (11172): Debug_reset: Running transform generation_view_transform took 0.000s Info (11172): Transacto: Running transform generation_view_transform Info (11172): Transacto: Running transform generation_view_transform took 0.000s Info (11172): Rom: Running transform generation_view_transform Info (11172): Rom: Running transform generation_view_transform took 0.000s Info (11172): Sys_reset_0: Running transform generation_view_transform Info (11172): Sys_reset_0: Running transform generation_view_transform took 0.000s Info (11172): Bridge_0: Running transform generation_view_transform Info (11172): Bridge_0: Running transform generation_view_transform took 0.000s Info (11172): Clock: Running transform generation_view_transform Info (11172): Clock: Running transform generation_view_transform took 0.000s Info (11172): Reset: Running transform generation_view_transform Info (11172): Reset: Running transform generation_view_transform took 0.000s Info (11172): Reset1: Running transform generation_view_transform Info (11172): Reset1: Running transform generation_view_transform took 0.000s Info (11172): Jtag: Running transform generation_view_transform Info (11172): Jtag: Running transform generation_view_transform took 0.000s Info (11172): H2t_timing: Running transform generation_view_transform Info (11172): H2t_timing: Running transform generation_view_transform took 0.000s Info (11172): H2t_fifo: Running transform generation_view_transform Info (11172): H2t_fifo: Running transform generation_view_transform took 0.000s Info (11172): B2p: Running transform generation_view_transform Info (11172): B2p: Running transform generation_view_transform took 0.000s Info (11172): P2b: Running transform generation_view_transform Info (11172): P2b: Running transform generation_view_transform took 0.000s Info (11172): T2h_fifo: Running transform generation_view_transform Info (11172): T2h_fifo: Running transform generation_view_transform took 0.000s Info (11172): Clock: Running transform generation_view_transform Info (11172): Clock: Running transform generation_view_transform took 0.000s Info (11172): Reset: Running transform generation_view_transform Info (11172): Reset: Running transform generation_view_transform took 0.000s Info (11172): Demux: Running transform generation_view_transform Info (11172): Demux: Running transform generation_view_transform took 0.000s Info (11172): Mux: Running transform generation_view_transform Info (11172): Mux: Running transform generation_view_transform took 0.000s Info (11172): Mgmt_demux: Running transform generation_view_transform Info (11172): Mgmt_demux: Running transform generation_view_transform took 0.000s Info (11172): Demux_p0_sink: Running transform generation_view_transform Info (11172): Demux_p0_sink: Running transform generation_view_transform took 0.000s Info (11172): H2t_channel_adap: Running transform generation_view_transform Info (11172): H2t_channel_adap: Running transform generation_view_transform took 0.000s Info (11172): T2h_channel_adap: Running transform generation_view_transform Info (11172): T2h_channel_adap: Running transform generation_view_transform took 0.000s Info (11172): Mgmt_channel_adap: Running transform generation_view_transform Info (11172): Mgmt_channel_adap: Running transform generation_view_transform took 0.000s Info (11172): Mgmt_time_adap: Running transform generation_view_transform Info (11172): Mgmt_time_adap: Running transform generation_view_transform took 0.000s Info (11172): Bridge: Running transform generation_view_transform Info (11172): Bridge: Running transform generation_view_transform took 0.000s Info (11172): Cbrdg_clk_0: Running transform generation_view_transform Info (11172): Cbrdg_clk_0: Running transform generation_view_transform took 0.000s Info (11172): Mgmt_reset_0: Running transform generation_view_transform Info (11172): Mgmt_reset_0: Running transform generation_view_transform took 0.000s Info (11172): Mgmt_rst_synch_0: Running transform generation_view_transform Info (11172): Mgmt_rst_synch_0: Running transform generation_view_transform took 0.000s Info (11172): Reset_bridge_0: Running transform generation_view_transform Info (11172): Reset_bridge_0: Running transform generation_view_transform took 0.000s Info (11172): Bridge_0: Running transform generation_view_transform Info (11172): Bridge_0: Running transform generation_view_transform took 0.000s Info (11172): H2t0_fifo: Running transform generation_view_transform Info (11172): H2t0_fifo: Running transform generation_view_transform took 0.000s Info (11172): T2h0_fifo: Running transform generation_view_transform Info (11172): T2h0_fifo: Running transform generation_view_transform took 0.000s Info (11172): Alt_sld_fab: Running transform merlin_avalon_transform Info (11172): Alt_sld_fab: Running transform merlin_avalon_transform took 0.019s Info (11172): Alt_sld_fab: Running transform merlin_avalon_transform Info (11172): Alt_sld_fab: Running transform merlin_avalon_transform took 0.073s Info (11172): Memfabric: Running transform merlin_avalon_transform Info (11172): Memfabric: Running transform merlin_avalon_transform took 0.520s Info (11172): Host_link_jtag: Running transform merlin_avalon_transform Info (11172): Host_link_jtag: Running transform merlin_avalon_transform took 0.008s Info (11172): Stfabric: Running transform merlin_avalon_transform Info (11172): Stfabric: Running transform merlin_avalon_transform took 0.009s Info (11172): Mm_interconnect_0: Running transform merlin_avalon_transform Info (11172): Avalon_st_adapter: Inserting error_adapter: error_adapter_0 Info (11172): Avalon_st_adapter_001: Inserting error_adapter: error_adapter_0 Info (11172): Mm_interconnect_0: Running transform merlin_avalon_transform took 0.211s Info (11172): Avalon_st_adapter: Running transform merlin_avalon_transform Info (11172): Avalon_st_adapter: Running transform merlin_avalon_transform took 0.008s Info (11172): Avalon_st_adapter_001: Running transform merlin_avalon_transform Info (11172): Avalon_st_adapter_001: Running transform merlin_avalon_transform took 0.009s Info (11172): Alt_sld_fab: "Naming system components in system: alt_sld_fab" Info (11172): Alt_sld_fab: "Processing generation queue" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_alt_sld_fab_170_tp5onsa" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_super_splitter_170_vg6hbvi" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_sld_splitter_170_ovmsk6a" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_transacto_fabric_170_xrot3yi" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_jtag_debug_link_internal_170_vgwe3oy" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_debug_fabric_170_q4gthiy" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_sld_jtag_hub_170_qxujbrq" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_connection_identification_hub_170_d7i3xiy" Info (11172): Alt_sld_fab: "Generating: altera_avalon_packets_to_master" Info (11172): Alt_sld_fab: "Generating: altera_trace_rom" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_mm_interconnect_170_km3cwsi" Info (11172): Alt_sld_fab: "Generating: altera_avalon_st_jtag_interface" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_timing_adapter_170_4cm4kaa" Info (11172): Alt_sld_fab: "Generating: altera_avalon_sc_fifo" Info (11172): Alt_sld_fab: "Generating: altera_avalon_st_bytes_to_packets" Info (11172): Alt_sld_fab: "Generating: altera_avalon_st_packets_to_bytes" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_demultiplexer_170_6kfaiqy" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_multiplexer_170_ruhk6pi" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_demultiplexer_170_iosysty" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_channel_adapter_170_rf7hkxq" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_channel_adapter_170_kmsfrsa" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_channel_adapter_170_dwcbxiq" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_timing_adapter_170_jv2llua" Info (11172): Alt_sld_fab: "Generating: altera_mgmt_reset" Info (11172): Alt_sld_fab: "Generating: altera_reset_controller" Info (11172): Alt_sld_fab: "Generating: altera_avalon_dc_fifo" Info (11172): Alt_sld_fab: "Generating: altera_merlin_master_translator" Info (11172): Alt_sld_fab: "Generating: altera_merlin_slave_translator" Info (11172): Alt_sld_fab: "Generating: altera_merlin_master_agent" Info (11172): Alt_sld_fab: "Generating: altera_merlin_slave_agent" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_merlin_router_170_gvmgc4q" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_merlin_router_170_25td5oy" Info (11172): Alt_sld_fab: "Generating: altera_merlin_traffic_limiter" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_merlin_demultiplexer_170_rkgro3a" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_merlin_multiplexer_170_aeieauy" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_merlin_demultiplexer_170_bdkxjki" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_merlin_multiplexer_170_ar6przi" Info (11172): Alt_sld_fab: "Generating: altera_avalon_st_pipeline_stage" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_altera_avalon_st_adapter_170_23bxk2a" Info (11172): Alt_sld_fab: "Generating: alt_sld_fab_error_adapter_170_mtlhioy" Info (11172): Alt_sld_fab: Done "alt_sld_fab" with 41 modules, 70 files Info (11171): Finished IP generation for the debug fabric: alt_sld_fab. Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/alt_sld_fab_170/synth/alt_sld_fab_alt_sld_fab_170_tp5onsa.v Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_170_tp5onsa Info (12021): Found 1 design units, including 0 entities, in source file db/ip/sld4d43b179/alt_sld_fab_170/synth/alt_sld_fab_alt_sld_fab_170_tp5onsa_cfg.v Info (12022): Found design unit 1: alt_sld_fab_alt_sld_fab_170_tp5onsa_cfg:config Info (12021): Found 0 design units, including 0 entities, in source file db/ip/sld4d43b179/altera_avalon_dc_fifo_170/synth/altera_avalon_dc_fifo.sdc Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_avalon_dc_fifo_170/synth/altera_avalon_dc_fifo.v Info (12023): Found entity 1: altera_avalon_dc_fifo Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_avalon_dc_fifo_170/synth/altera_dcfifo_synchronizer_bundle.v Info (12023): Found entity 1: altera_dcfifo_synchronizer_bundle Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_avalon_dc_fifo_170/synth/altera_std_synchronizer_nocut.v Info (12023): Found entity 1: altera_std_synchronizer_nocut Info (12021): Found 7 design units, including 7 entities, in source file db/ip/sld4d43b179/altera_avalon_packets_to_master_170/synth/altera_avalon_packets_to_master.v Info (12023): Found entity 1: altera_avalon_packets_to_master Info (12023): Found entity 2: packets_to_fifo Info (12023): Found entity 3: fifo_buffer_single_clock_fifo Info (12023): Found entity 4: fifo_buffer_scfifo_with_controls Info (12023): Found entity 5: fifo_buffer Info (12023): Found entity 6: fifo_to_packet Info (12023): Found entity 7: packets_to_master Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_avalon_sc_fifo_170/synth/altera_avalon_sc_fifo.v Info (12023): Found entity 1: altera_avalon_sc_fifo Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_avalon_st_adapter_170/synth/alt_sld_fab_altera_avalon_st_adapter_170_23bxk2a.v Info (12023): Found entity 1: alt_sld_fab_altera_avalon_st_adapter_170_23bxk2a Info (12021): Found 1 design units, including 0 entities, in source file db/ip/sld4d43b179/altera_avalon_st_adapter_170/synth/alt_sld_fab_altera_avalon_st_adapter_170_23bxk2a_cfg.v Info (12022): Found design unit 1: alt_sld_fab_altera_avalon_st_adapter_170_23bxk2a_cfg:config Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_avalon_st_bytes_to_packets_170/synth/altera_avalon_st_bytes_to_packets.v Info (12023): Found entity 1: altera_avalon_st_bytes_to_packets Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_avalon_st_packets_to_bytes_170/synth/altera_avalon_st_packets_to_bytes.v Info (12023): Found entity 1: altera_avalon_st_packets_to_bytes Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_avalon_st_pipeline_stage_170/synth/altera_avalon_st_pipeline_base.v Info (12023): Found entity 1: altera_avalon_st_pipeline_base Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_avalon_st_pipeline_stage_170/synth/altera_avalon_st_pipeline_stage.sv Info (12023): Found entity 1: altera_avalon_st_pipeline_stage Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_connection_identification_hub_170/synth/alt_sld_fab_altera_connection_identification_hub_170_d7i3xiy.sv Info (12023): Found entity 1: alt_sld_fab_altera_connection_identification_hub_170_d7i3xiy Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_debug_fabric_170/synth/alt_sld_fab_altera_debug_fabric_170_q4gthiy.v Info (12023): Found entity 1: alt_sld_fab_altera_debug_fabric_170_q4gthiy Info (12021): Found 1 design units, including 0 entities, in source file db/ip/sld4d43b179/altera_debug_fabric_170/synth/alt_sld_fab_altera_debug_fabric_170_q4gthiy_cfg.v Info (12022): Found design unit 1: alt_sld_fab_altera_debug_fabric_170_q4gthiy_cfg:config Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_jtag_dc_streaming_170/synth/altera_avalon_st_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_clock_crosser Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_jtag_dc_streaming_170/synth/altera_avalon_st_idle_inserter.v Info (12023): Found entity 1: altera_avalon_st_idle_inserter Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_jtag_dc_streaming_170/synth/altera_avalon_st_idle_remover.v Info (12023): Found entity 1: altera_avalon_st_idle_remover Info (12021): Found 0 design units, including 0 entities, in source file db/ip/sld4d43b179/altera_jtag_dc_streaming_170/synth/altera_avalon_st_jtag_interface.sdc Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_jtag_dc_streaming_170/synth/altera_avalon_st_jtag_interface.v Info (12023): Found entity 1: altera_avalon_st_jtag_interface Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_jtag_dc_streaming_170/synth/altera_avalon_st_pipeline_base.v Info (12023): Found entity 1: altera_avalon_st_pipeline_base Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_jtag_dc_streaming_170/synth/altera_avalon_st_pipeline_stage.sv Info (12023): Found entity 1: altera_avalon_st_pipeline_stage Info (12021): Found 3 design units, including 3 entities, in source file db/ip/sld4d43b179/altera_jtag_dc_streaming_170/synth/altera_jtag_dc_streaming.v Info (12023): Found entity 1: altera_jtag_control_signal_crosser Info (12023): Found entity 2: altera_jtag_src_crosser Info (12023): Found entity 3: altera_jtag_dc_streaming Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_jtag_dc_streaming_170/synth/altera_jtag_sld_node.v Info (12023): Found entity 1: altera_jtag_sld_node Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_jtag_dc_streaming_170/synth/altera_jtag_streaming.v Info (12023): Found entity 1: altera_jtag_streaming Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_jtag_dc_streaming_170/synth/altera_std_synchronizer_nocut.v Info (12023): Found entity 1: altera_std_synchronizer_nocut Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_jtag_debug_link_internal_170/synth/alt_sld_fab_altera_jtag_debug_link_internal_170_vgwe3oy.v Info (12023): Found entity 1: alt_sld_fab_altera_jtag_debug_link_internal_170_vgwe3oy Info (12021): Found 1 design units, including 0 entities, in source file db/ip/sld4d43b179/altera_jtag_debug_link_internal_170/synth/alt_sld_fab_altera_jtag_debug_link_internal_170_vgwe3oy_cfg.v Info (12022): Found design unit 1: alt_sld_fab_altera_jtag_debug_link_internal_170_vgwe3oy_cfg:config Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_merlin_demultiplexer_170/synth/alt_sld_fab_altera_merlin_demultiplexer_170_bdkxjki.sv Info (12023): Found entity 1: alt_sld_fab_altera_merlin_demultiplexer_170_bdkxjki Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_merlin_demultiplexer_170/synth/alt_sld_fab_altera_merlin_demultiplexer_170_rkgro3a.sv Info (12023): Found entity 1: alt_sld_fab_altera_merlin_demultiplexer_170_rkgro3a Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_merlin_master_agent_170/synth/altera_merlin_master_agent.sv Info (12023): Found entity 1: altera_merlin_master_agent Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_merlin_master_translator_170/synth/altera_merlin_master_translator.sv Info (12023): Found entity 1: altera_merlin_master_translator Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_merlin_multiplexer_170/synth/alt_sld_fab_altera_merlin_multiplexer_170_aeieauy.sv Info (12023): Found entity 1: alt_sld_fab_altera_merlin_multiplexer_170_aeieauy Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_merlin_multiplexer_170/synth/alt_sld_fab_altera_merlin_multiplexer_170_ar6przi.sv Info (12023): Found entity 1: alt_sld_fab_altera_merlin_multiplexer_170_ar6przi Info (12021): Found 2 design units, including 2 entities, in source file db/ip/sld4d43b179/altera_merlin_multiplexer_170/synth/altera_merlin_arbitrator.sv Info (12023): Found entity 1: altera_merlin_arbitrator Info (12023): Found entity 2: altera_merlin_arb_adder Info (12021): Found 2 design units, including 2 entities, in source file db/ip/sld4d43b179/altera_merlin_router_170/synth/alt_sld_fab_altera_merlin_router_170_25td5oy.sv Info (12023): Found entity 1: alt_sld_fab_altera_merlin_router_170_25td5oy_default_decode Info (12023): Found entity 2: alt_sld_fab_altera_merlin_router_170_25td5oy Info (12021): Found 2 design units, including 2 entities, in source file db/ip/sld4d43b179/altera_merlin_router_170/synth/alt_sld_fab_altera_merlin_router_170_gvmgc4q.sv Info (12023): Found entity 1: alt_sld_fab_altera_merlin_router_170_gvmgc4q_default_decode Info (12023): Found entity 2: alt_sld_fab_altera_merlin_router_170_gvmgc4q Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_merlin_slave_agent_170/synth/altera_merlin_burst_uncompressor.sv Info (12023): Found entity 1: altera_merlin_burst_uncompressor Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_merlin_slave_agent_170/synth/altera_merlin_slave_agent.sv Info (12023): Found entity 1: altera_merlin_slave_agent Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_merlin_slave_translator_170/synth/altera_merlin_slave_translator.sv Info (12023): Found entity 1: altera_merlin_slave_translator Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_merlin_traffic_limiter_170/synth/altera_avalon_sc_fifo.v Info (12023): Found entity 1: altera_avalon_sc_fifo Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_merlin_traffic_limiter_170/synth/altera_avalon_st_pipeline_base.v Info (12023): Found entity 1: altera_avalon_st_pipeline_base Info (12021): Found 2 design units, including 2 entities, in source file db/ip/sld4d43b179/altera_merlin_traffic_limiter_170/synth/altera_merlin_reorder_memory.sv Info (12023): Found entity 1: altera_merlin_reorder_memory Info (12023): Found entity 2: memory_pointer_controller Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_merlin_traffic_limiter_170/synth/altera_merlin_traffic_limiter.sv Info (12023): Found entity 1: altera_merlin_traffic_limiter Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_mgmt_reset_170/synth/altera_mgmt_reset.v Info (12023): Found entity 1: altera_mgmt_reset Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_mm_interconnect_170/synth/alt_sld_fab_altera_mm_interconnect_170_km3cwsi.v Info (12023): Found entity 1: alt_sld_fab_altera_mm_interconnect_170_km3cwsi Info (12021): Found 1 design units, including 0 entities, in source file db/ip/sld4d43b179/altera_mm_interconnect_170/synth/alt_sld_fab_altera_mm_interconnect_170_km3cwsi_cfg.v Info (12022): Found design unit 1: alt_sld_fab_altera_mm_interconnect_170_km3cwsi_cfg:config Info (12021): Found 0 design units, including 0 entities, in source file db/ip/sld4d43b179/altera_reset_controller_170/synth/altera_reset_controller.sdc Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_reset_controller_170/synth/altera_reset_controller.v Info (12023): Found entity 1: altera_reset_controller Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_reset_controller_170/synth/altera_reset_synchronizer.v Info (12023): Found entity 1: altera_reset_synchronizer Info (12021): Found 2 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_sld_jtag_hub_170/synth/alt_sld_fab_altera_sld_jtag_hub_170_qxujbrq.vhd Info (12022): Found design unit 1: alt_sld_fab_altera_sld_jtag_hub_170_qxujbrq-rtl Info (12023): Found entity 1: alt_sld_fab_altera_sld_jtag_hub_170_qxujbrq Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_sld_splitter_170/synth/alt_sld_fab_altera_sld_splitter_170_ovmsk6a.sv Info (12023): Found entity 1: alt_sld_fab_altera_sld_splitter_170_ovmsk6a Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_super_splitter_170/synth/alt_sld_fab_altera_super_splitter_170_vg6hbvi.sv Info (12023): Found entity 1: alt_sld_fab_altera_super_splitter_170_vg6hbvi Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_trace_rom_170/synth/altera_trace_rom.v Info (12023): Found entity 1: altera_trace_rom Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/altera_transacto_fabric_170/synth/alt_sld_fab_altera_transacto_fabric_170_xrot3yi.v Info (12023): Found entity 1: alt_sld_fab_altera_transacto_fabric_170_xrot3yi Info (12021): Found 1 design units, including 0 entities, in source file db/ip/sld4d43b179/altera_transacto_fabric_170/synth/alt_sld_fab_altera_transacto_fabric_170_xrot3yi_cfg.v Info (12022): Found design unit 1: alt_sld_fab_altera_transacto_fabric_170_xrot3yi_cfg:config Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/channel_adapter_170/synth/alt_sld_fab_channel_adapter_170_dwcbxiq.sv Info (12023): Found entity 1: alt_sld_fab_channel_adapter_170_dwcbxiq Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/channel_adapter_170/synth/alt_sld_fab_channel_adapter_170_kmsfrsa.sv Info (12023): Found entity 1: alt_sld_fab_channel_adapter_170_kmsfrsa Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/channel_adapter_170/synth/alt_sld_fab_channel_adapter_170_rf7hkxq.sv Info (12023): Found entity 1: alt_sld_fab_channel_adapter_170_rf7hkxq Info (12021): Found 2 design units, including 2 entities, in source file db/ip/sld4d43b179/demultiplexer_170/synth/alt_sld_fab_demultiplexer_170_6kfaiqy.sv Info (12023): Found entity 1: alt_sld_fab_demultiplexer_170_6kfaiqy Info (12023): Found entity 2: alt_sld_fab_demultiplexer_170_6kfaiqy_1stage_pipeline Info (12021): Found 2 design units, including 2 entities, in source file db/ip/sld4d43b179/demultiplexer_170/synth/alt_sld_fab_demultiplexer_170_iosysty.sv Info (12023): Found entity 1: alt_sld_fab_demultiplexer_170_iosysty Info (12023): Found entity 2: alt_sld_fab_demultiplexer_170_iosysty_1stage_pipeline Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/error_adapter_170/synth/alt_sld_fab_error_adapter_170_mtlhioy.sv Info (12023): Found entity 1: alt_sld_fab_error_adapter_170_mtlhioy Info (12021): Found 2 design units, including 2 entities, in source file db/ip/sld4d43b179/multiplexer_170/synth/alt_sld_fab_multiplexer_170_ruhk6pi.sv Info (12023): Found entity 1: alt_sld_fab_multiplexer_170_ruhk6pi Info (12023): Found entity 2: alt_sld_fab_multiplexer_170_ruhk6pi_1stage_pipeline Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/synth/alt_sld_fab.v Info (12023): Found entity 1: alt_sld_fab Info (12021): Found 1 design units, including 0 entities, in source file db/ip/sld4d43b179/synth/alt_sld_fab_cfg.v Info (12022): Found design unit 1: alt_sld_fab_cfg:config Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/timing_adapter_170/synth/alt_sld_fab_timing_adapter_170_4cm4kaa.sv Info (12023): Found entity 1: alt_sld_fab_timing_adapter_170_4cm4kaa Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld4d43b179/timing_adapter_170/synth/alt_sld_fab_timing_adapter_170_jv2llua.sv Info (12023): Found entity 1: alt_sld_fab_timing_adapter_170_jv2llua Warning (10230): Verilog HDL assignment warning at altera_merlin_traffic_limiter.sv(721): truncated value with size 2 to match size of target (1) Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_timing_adapter_170_4cm4kaa.sv(82): object "in_ready" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_timing_adapter_170_jv2llua.sv(84): object "in_ready" assigned a value but never read Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following RAM node(s): Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[154]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[155]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[156]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[157]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[158]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[154]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[155]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[156]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[157]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[158]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[159]" Info (286031): Timing-Driven Synthesis is running on partition "Top" Info (19000): Inferred 2 megafunctions from design logic Info (276034): Inferred altshift_taps megafunction from the following design logic: "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|rx_input_data_reg_rtl_0" Info (286033): Parameter NUMBER_OF_TAPS set to 1 Info (286033): Parameter TAP_DISTANCE set to 4 Info (286033): Parameter WIDTH set to 242 Info (286033): Parameter POWER_UP_STATE set to DONT_CARE Info (276034): Inferred altshift_taps megafunction from the following design logic: "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|rx_input_data_reg2_rtl_0" Info (286033): Parameter NUMBER_OF_TAPS set to 1 Info (286033): Parameter TAP_DISTANCE set to 3 Info (286033): Parameter WIDTH set to 14 Info (286033): Parameter POWER_UP_STATE set to DONT_CARE Info (12130): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|altshift_taps:rx_input_data_reg2_rtl_0" Info (12133): Instantiated megafunction "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|altshift_taps:rx_input_data_reg2_rtl_0" with the following parameter: Info (12134): Parameter "NUMBER_OF_TAPS" = "1" Info (12134): Parameter "TAP_DISTANCE" = "3" Info (12134): Parameter "WIDTH" = "14" Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_l8v.tdf Info (12023): Found entity 1: shift_taps_l8v Info (12130): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|altshift_taps:rx_input_data_reg2_rtl_0|shift_taps_l8v:auto_generated|altera_counter:altera_counter1" Info (12133): Instantiated megafunction "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|altshift_taps:rx_input_data_reg2_rtl_0|shift_taps_l8v:auto_generated|altera_counter:altera_counter1" with the following parameter: Info (12134): Parameter "DIRECTION" = "UP" Info (12134): Parameter "WIDTH" = "2" Info (12021): Found 1 design units, including 1 entities, in source file db/altera_syncram_7k81.tdf Info (12023): Found entity 1: altera_syncram_7k81 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_5c84.tdf Info (12023): Found entity 1: altsyncram_5c84 Info (12130): Elaborated megafunction instantiation "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|altshift_taps:rx_input_data_reg_rtl_0" Info (12133): Instantiated megafunction "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_hip_interface:hip_inf|altshift_taps:rx_input_data_reg_rtl_0" with the following parameter: Info (12134): Parameter "NUMBER_OF_TAPS" = "1" Info (12134): Parameter "TAP_DISTANCE" = "4" Info (12134): Parameter "WIDTH" = "242" Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_9av.tdf Info (12023): Found entity 1: shift_taps_9av Info (12021): Found 1 design units, including 1 entities, in source file db/altera_syncram_dn81.tdf Info (12023): Found entity 1: altera_syncram_dn81 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_bf84.tdf Info (12023): Found entity 1: altsyncram_bf84 Warning (12241): 21 hierarchies have connectivity warnings - see the Connectivity Checks report folder Info (13000): Registers with preset signals will power-up high Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following RAM node(s): Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[32]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[33]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[34]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[35]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[36]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[37]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[38]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[39]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[40]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[41]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[42]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[43]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[44]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[45]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[46]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[47]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[48]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[49]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[50]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[51]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[52]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[53]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[54]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[55]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[56]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[57]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[58]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[59]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[60]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[61]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[62]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:write_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[63]" Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following RAM node(s): Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[124]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[123]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[122]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[121]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[120]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[119]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[118]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[117]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[116]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[115]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[114]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[113]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[112]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[111]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[110]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[109]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[108]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[107]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[106]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[105]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[104]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[103]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[102]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[101]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[100]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[99]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[98]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[97]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[96]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[127]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[126]" Warning (14320): Synthesized away node "top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|dma_control:g_dmacontrol.dmacontrol.dma_control_0|altpcie_dynamic_control:read_control|scfifo:g_dt_fifo.dt_fifo|scfifo_c9a1:auto_generated|a_dpfifo_lk91:dpfifo|altsyncram_2gn1:FIFOram|q_b[125]" Info (17049): 2487 registers lost all their fanouts during netlist optimizations. Info (144001): Generated suppressed messages file /home/hsuch/Downloads/arria_10_pcie_ref_design/hip_a10gx_g3_x8_avmm_dma256_1602_PS_restored_se/output_files/top.map.smsg Info (35024): Successfully connected in-system debug instance "auto_signaltap_0" to all 1339 required data inputs, trigger inputs, acquisition clocks, and dynamic pins Info (21057): Implemented 42338 device resources after synthesis - the final resource count might be different Info (21058): Implemented 14 input pins Info (21059): Implemented 9 output pins Info (21061): Implemented 39558 logic cells Info (21064): Implemented 2508 RAM segments Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 109 warnings Info: Peak virtual memory: 2111 megabytes Info: Processing ended: Mon Nov 13 10:37:42 2017 Info: Elapsed time: 00:02:08 Info: Total CPU time (on all processors): 00:02:53 Info: ******************************************************************* Info: Running Quartus Prime Fitter Info: Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition Info: Processing started: Mon Nov 13 10:37:43 2017 Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off top -c top Info: Using INI file /home/hsuch/Downloads/arria_10_pcie_ref_design/hip_a10gx_g3_x8_avmm_dma256_1602_PS_restored_se/quartus.ini Info: qfit2_default_script.tcl version: #1 Info: Project = top Info: Revision = top Info (12262): Starting Fitter periphery placement operations Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (119006): Selected device 10AX115S2F45I1SG for design "top" Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'. Info (21077): Low junction temperature is -40 degrees C Info (21077): High junction temperature is 100 degrees C Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (12290): Loading the periphery placement data. Info (12291): Periphery placement data loaded: elapsed time is 00:00:26 Info (12627): Pin ~ALTERA_DATA0~ is reserved at location AU27 Info (12627): Pin ~ALTERA_CLKUSR~ is reserved at location BD32 Info (18163): Pin ~ALTERA_CLKUSR~ was reserved for calibration. This pin must be assigned a 100-125 MHz clock. Info (11685): 17 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins Info (11684): Differential I/O pin "hip_serial_tx_out0" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_tx_out0(n)" Info (11684): Differential I/O pin "hip_serial_tx_out1" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_tx_out1(n)" Info (11684): Differential I/O pin "hip_serial_tx_out2" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_tx_out2(n)" Info (11684): Differential I/O pin "hip_serial_tx_out3" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_tx_out3(n)" Info (11684): Differential I/O pin "hip_serial_tx_out4" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_tx_out4(n)" Info (11684): Differential I/O pin "hip_serial_tx_out5" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_tx_out5(n)" Info (11684): Differential I/O pin "hip_serial_tx_out6" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_tx_out6(n)" Info (11684): Differential I/O pin "hip_serial_tx_out7" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_tx_out7(n)" Info (11684): Differential I/O pin "refclk_clk" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "refclk_clk(n)" Info (11684): Differential I/O pin "hip_serial_rx_in0" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_rx_in0(n)" Info (11684): Differential I/O pin "hip_serial_rx_in1" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_rx_in1(n)" Info (11684): Differential I/O pin "hip_serial_rx_in2" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_rx_in2(n)" Info (11684): Differential I/O pin "hip_serial_rx_in3" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_rx_in3(n)" Info (11684): Differential I/O pin "hip_serial_rx_in4" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_rx_in4(n)" Info (11684): Differential I/O pin "hip_serial_rx_in5" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_rx_in5(n)" Info (11684): Differential I/O pin "hip_serial_rx_in6" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_rx_in6(n)" Info (11684): Differential I/O pin "hip_serial_rx_in7" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "hip_serial_rx_in7(n)" Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (16210): Plan updated with currently enabled project assignments. Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:00:03 Warning (18708): ATX/FPLL < top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|lcpll_g3xn:g_pll.g_pll_g3n.lcpll_g3xn|top_altera_xcvr_atx_pll_a10_170_nd26ega:lcpll_g3xn|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst > is not placed in the same bank as the reference clock. Warning (18576): The transceivers with supply "VCCR_GXB" on the left HSSI strip use "1.03V". The default voltage for unused HSSI channel(s) has been overridden by "1.03V". Warning (18576): The transceivers with supply "VCCT_GXB" on the left HSSI strip use "1.03V". The default voltage for unused HSSI channel(s) has been overridden by "1.03V". Critical Warning (17951): There are 64 unused RX channels in the design. If you intend to use any of these channels in the future, you must add the assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to ' in your QSF file. This assignment will preserve the performance of specified channels over time. Note that unused channel preservation only works if the design uses or instantiates atleast 1 transceiver channel. Critical Warning (18655): There are 64 unused TX channels in the design. If you intend to use any of these channels in the future, you must add the assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to ' in your QSF file. This assignment will preserve the performance of specified channels over time. Note that unused channel preservation only works if the design uses or instantiates atleast 1 transceiver channel. Warning (18576): The transceivers with supply "VCCR_GXB" on the left HSSI strip use "1.03V". The default voltage for unused HSSI channel(s) has been overridden by "1.03V". Warning (18576): The transceivers with supply "VCCT_GXB" on the left HSSI strip use "1.03V". The default voltage for unused HSSI channel(s) has been overridden by "1.03V". Info (11178): Promoted 2 clocks (2 global) Info (13173): refclk_clk~inputFITTER_INSERTEDCLKENA0 (992 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1C_G_I0 Info (13173): top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|coreclkout~CLKENA0 (30944 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1D_G_I14 Info (11191): Automatically promoted 1 clock (1 global) Info (13173): altera_internal_jtag~TCKUTAPCLKENA0 (3827 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3A_G_I30 Info (176233): Starting register packing Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity alt_xcvr_resync Info (332166): set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs} Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity altpcie_reset_delay_sync Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *npor_sync_altpcie_reset_delay_sync_altpcie_rs_a10_hip*rs_meta[*]] -to [get_keepers *npor_sync_altpcie_reset_delay_sync_altpcie_rs_a10_hip*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *npor_sync_altpcie_reset_delay_sync_altpcie_rs_a10_hip*rs_meta[*]] -to [get_keepers *npor_sync_altpcie_reset_delay_sync_altpcie_rs_a10_hip*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *npor_sync_altpcie_reset_delay_sync_altpcie_rs_a10_hip*rs_meta[*]] -to [get_keepers *npor_sync_altpcie_reset_delay_sync_altpcie_rs_a10_hip*rs_meta[*]] Info (332165): Entity altpcie_sc_bitsync Info (332166): set_multicycle_path -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3 Info (332166): set_false_path -hold -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] Info (332166): set_multicycle_path -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3 Info (332166): set_false_path -hold -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] Info (332165): Entity sld_hub Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 30MHz Info (332166): if { [string equal quartus_fit $::TimeQuestInfo(nameofexecutable)] } { set_max_delay -to [get_ports { altera_reserved_tdo } ] 0 } Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} Info (332104): Reading SDC File: 'top_hw.sdc' Info (332110): Deriving PLL clocks Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|pll_fixed_clk_central} -divide_by 2 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|coreclkout} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|core_clk_out} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|coreclkout~CLKENA0|outclk} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|pld_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|pld_clk} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_refclk_select_inst|ref_iqclk[11]} -multiply_by 25 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|tx_serial_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_inst|clk0} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_refclk_select_inst|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|pll_pcie_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_inst|hclk_out} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_lc_refclk_select_mux_inst|ref_iqclk[11]} -invert -multiply_by 40 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|pll_serial_clk_8g} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst|clk0_8g} Info (332110): create_generated_clock -source {refclk_clk~inputFITTER_INSERTEDCLKENA0|outclk} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk} Info (332110): create_generated_clock -source {refclk_clk~inputFITTER_INSERTEDCLKENA0|outclk} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk} Info (332110): create_generated_clock -source {refclk_clk~inputFITTER_INSERTEDCLKENA0|outclk} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk} Info (332110): create_generated_clock -source {refclk_clk~inputFITTER_INSERTEDCLKENA0|outclk} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk} Info (332110): create_generated_clock -source {refclk_clk~inputFITTER_INSERTEDCLKENA0|outclk} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk} Info (332110): create_generated_clock -source {refclk_clk~inputFITTER_INSERTEDCLKENA0|outclk} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk} Info (332110): create_generated_clock -source {refclk_clk~inputFITTER_INSERTEDCLKENA0|outclk} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk} Info (332110): create_generated_clock -source {refclk_clk~inputFITTER_INSERTEDCLKENA0|outclk} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmclk} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clkout} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clkout} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clkout} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clkout} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clkout} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|hip_cmn_clk[0]} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pld_pcs_interface.inst_twentynm_hssi_common_pld_pcs_interface|hip_cmn_clk[0]} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clkout} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clkout} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clkout} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[0]|pma_hclk_by2} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[1]|pma_hclk_by2} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[2]|pma_hclk_by2} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[3]|pma_hclk_by2} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[4]|pma_hclk_by2} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[5]|pma_hclk_by2} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[10]} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[6]|pma_hclk_by2} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[10]} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[7]|pma_hclk_by2} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[10]} -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -multiply_by 5 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[0]|tx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -multiply_by 5 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[1]|tx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[2]|tx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pld_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|tx_clkout} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1_out} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[3]|tx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[4]|tx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[10]} -multiply_by 5 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[5]|tx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[10]} -multiply_by 5 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[6]|tx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[10]} -multiply_by 5 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|g_xcvr_native_insts[7]|tx_clk} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1} Info (332110): create_generated_clock -source {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|clk_fpll_b} -divide_by 16 -duty_cycle 50.00 -name {top|pcie_a10_hip_0|tx_bonding_clocks[0]} {top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|cpulse_out_bus[0]} Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332043): Overwriting existing clock: altera_reserved_tck Warning (332174): Ignored filter at top_hw.sdc(18): dk_alive_led could not be matched with a port Warning (332049): Ignored set_false_path at top_hw.sdc(18): Argument is an empty collection Info (332050): set_false_path -to [get_ports {dk_alive_led}] Info (332104): Reading SDC File: 'top/altera_reset_controller_170/synth/altera_reset_controller.sdc' Info (332104): Reading SDC File: 'top/altera_pcie_a10_hip_170/synth/altera_pci_express.sdc' Info (332104): Reading SDC File: 'top/altera_xcvr_native_a10_170/synth/altera_xcvr_native_a10_false_paths.sdc' Warning (332174): Ignored filter at altera_xcvr_native_a10_false_paths.sdc(53): *twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n could not be matched with a pin Warning (332174): Ignored filter at altera_xcvr_native_a10_false_paths.sdc(63): *twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n could not be matched with a pin Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg Warning (332060): Node: top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment. Info (13166): Register top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by top:top|top_altera_pcie_a10_hip_170_6po5avi:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_native_a10_170_n5vprta:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg Warning (332070): Port "altera_reserved_tdi" relative to the falling edge of clock "altera_reserved_tck" does not specify a min-fall input delay Warning (332070): Port "altera_reserved_tdi" relative to the falling edge of clock "altera_reserved_tck" does not specify a min-rise input delay Warning (332070): Port "altera_reserved_tms" relative to the falling edge of clock "altera_reserved_tck" does not specify a min-fall input delay Warning (332070): Port "altera_reserved_tms" relative to the falling edge of clock "altera_reserved_tck" does not specify a min-rise input delay Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Warning (332088): No paths exist between clock target "top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|core_clk_out" of clock "top|pcie_a10_hip_0|coreclkout" and its clock source. Assuming zero source clock latency. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 66 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 41.667 altera_reserved_tck Info (332111): 10.000 refclk_clk Info (332111): 4.000 top|pcie_a10_hip_0|coreclkout Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332111): 4.000 top|pcie_a10_hip_0|g_xcvr_native_insts[0]|pma_hclk_by2 Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clkout Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332111): 2.000 top|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[0]|tx_clk Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332111): 4.000 top|pcie_a10_hip_0|g_xcvr_native_insts[1]|pma_hclk_by2 Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clkout Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332111): 2.000 top|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[1]|tx_clk Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332111): 4.000 top|pcie_a10_hip_0|g_xcvr_native_insts[2]|pma_hclk_by2 Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clkout Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332111): 2.000 top|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[2]|tx_clk Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332111): 4.000 top|pcie_a10_hip_0|g_xcvr_native_insts[3]|pma_hclk_by2 Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clkout Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332111): 2.000 top|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[3]|tx_clk Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332111): 4.000 top|pcie_a10_hip_0|g_xcvr_native_insts[4]|pma_hclk_by2 Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clkout Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332111): 2.000 top|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[4]|tx_clk Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332111): 4.000 top|pcie_a10_hip_0|g_xcvr_native_insts[5]|pma_hclk_by2 Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clkout Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332111): 2.000 top|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[5]|tx_clk Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332111): 4.000 top|pcie_a10_hip_0|g_xcvr_native_insts[6]|pma_hclk_by2 Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clkout Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332111): 2.000 top|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[6]|tx_clk Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332111): 4.000 top|pcie_a10_hip_0|g_xcvr_native_insts[7]|pma_hclk_by2 Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clkout Info (332111): 10.000 top|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332111): 2.000 top|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332111): 25.600 top|pcie_a10_hip_0|g_xcvr_native_insts[7]|tx_clk Info (332111): 2.000 top|pcie_a10_hip_0|hip_cmn_clk[0] Info (332111): 4.000 top|pcie_a10_hip_0|pld_clk Info (332111): 2.000 top|pcie_a10_hip_0|pll_pcie_clk Info (332111): 0.250 top|pcie_a10_hip_0|pll_serial_clk_8g Info (332111): 6.400 top|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332111): 25.600 top|pcie_a10_hip_0|tx_clkout Info (332111): 0.400 top|pcie_a10_hip_0|tx_serial_clk Info (176235): Finished register packing Extra Info (176218): Packed 292 registers into blocks of type Block RAM Warning (18576): The transceivers with supply "VCCR_GXB" on the left HSSI strip use "1.03V". The default voltage for unused HSSI channel(s) has been overridden by "1.03V". Warning (18576): The transceivers with supply "VCCT_GXB" on the left HSSI strip use "1.03V". The default voltage for unused HSSI channel(s) has been overridden by "1.03V". Info (12263): Fitter periphery placement operations ending: elapsed time is 00:01:37 Warning (15705): Ignored locations or region assignments to the following nodes Warning (15706): Node "local_rstn" is assigned to location or region, but does not exist in design Info (11165): Fitter preparation operations ending: elapsed time is 00:01:47 Info (170189): Fitter placement preparation operations beginning Info (14951): The Fitter is using Advanced Physical Optimization. Warning (170052): Fitter has implemented the following 40 RAMs using MLAB locations, which can behave differently during power up than dedicated RAM locations Info (170241): For more information about RAMs, refer to the Fitter RAM Summary report. Info (170056): Fitter has implemented the following 40 RAMs using MLAB locations, which will have the same paused read capabilities as dedicated RAM locations Info (170241): For more information about RAMs, refer to the Fitter RAM Summary report. Info (170190): Fitter placement preparation operations ending: elapsed time is 00:01:26 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:53 Info (11888): Total time spent on timing analysis during Placement is 41.06 seconds. Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 1% of the available device resources Info (170196): Router estimated peak interconnect usage is 39% of the available device resources in the region that extends from location X35_Y23 to location X46_Y34 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped Info (11888): Total time spent on timing analysis during Routing is 15.71 seconds. Info (16607): Fitter routing operations ending: elapsed time is 00:01:57 Info (11888): Total time spent on timing analysis during Post-Routing is 2.78 seconds. Info (16557): Fitter post-fit operations ending: elapsed time is 00:03:09 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Info (144001): Generated suppressed messages file /home/hsuch/Downloads/arria_10_pcie_ref_design/hip_a10gx_g3_x8_avmm_dma256_1602_PS_restored_se/output_files/top.fit.smsg Info (11793): Fitter databases successfully split. Info: Quartus Prime Fitter was successful. 0 errors, 41 warnings Info: Peak virtual memory: 11265 megabytes Info: Processing ended: Mon Nov 13 10:48:54 2017 Info: Elapsed time: 00:11:11 Info: Total CPU time (on all processors): 00:30:45 Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition Info: Processing started: Mon Nov 13 10:49:07 2017 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off top -c top Info: Using INI file /home/hsuch/Downloads/arria_10_pcie_ref_design/hip_a10gx_g3_x8_avmm_dma256_1602_PS_restored_se/quartus.ini Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Error (210027): Can't use configuration device EPCQL256 with selected programming mode Error: Quartus Prime Assembler was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 8534 megabytes Error: Processing ended: Mon Nov 13 10:50:14 2017 Error: Elapsed time: 00:01:07 Error: Total CPU time (on all processors): 00:01:22 Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 151 warnings