{ 
  "configurations" : [
    { 
      "name" : "0",
      "parameters" :{
        "aib_clk1_sel" : "aib_clk1_pld_pcs_tx_clk_out",
        "aib_clk2_sel" : "aib_clk2_pld_pcs_tx_clk_out",
        "hdpldadapt_aib_fabric_pld_pma_hclk_hz" : "31'd0",
        "hdpldadapt_aib_fabric_pma_aib_tx_clk_hz" : "31'd644531250",
        "bonding_dft_en" : "dft_dis",
        "bonding_dft_val" : "dft_0",
        "chnl_bonding" : "disable",
        "hdpldadapt_csr_clk_hz" : "31'd0",
        "ctrl_plane_bonding" : "individual",
        "ds_bypass_pipeln" : "ds_bypass_pipeln_dis",
        "duplex_mode" : "enable",
        "dv_bond" : "dv_bond_dis",
        "dv_gen" : "dv_gen_dis",
        "fifo_double_write" : "fifo_double_write_en",
        "fifo_mode" : "phase_comp",
        "fifo_rd_clk_frm_gen_scg_en" : "enable",
        "fifo_rd_clk_scg_en" : "disable",
        "fifo_rd_clk_sel" : "fifo_rd_pma_aib_tx_clk",
        "fifo_stop_rd" : "rd_empty",
        "fifo_stop_wr" : "wr_full",
        "fifo_width" : "fifo_double_width",
        "fifo_wr_clk_scg_en" : "disable",
        "fpll_shared_direct_async_in_sel" : "fpll_shared_direct_async_in_rowclk",
        "frmgen_burst" : "frmgen_burst_dis",
        "frmgen_bypass" : "frmgen_bypass_en",
        "frmgen_mfrm_length" : "16'd2048",
        "frmgen_pipeln" : "frmgen_pipeln_en",
        "frmgen_pyld_ins" : "frmgen_pyld_ins_dis",
        "frmgen_wordslip" : "frmgen_wordslip_dis",
        "fsr_hip_fsr_in_bit0_rst_val" : "reset_to_one_hfsrin0",
        "fsr_hip_fsr_in_bit1_rst_val" : "reset_to_one_hfsrin1",
        "fsr_hip_fsr_in_bit2_rst_val" : "reset_to_one_hfsrin2",
        "fsr_hip_fsr_in_bit3_rst_val" : "reset_to_zero_hfsrin3",
        "fsr_hip_fsr_out_bit0_rst_val" : "reset_to_one_hfsrout0",
        "fsr_hip_fsr_out_bit1_rst_val" : "reset_to_one_hfsrout1",
        "fsr_hip_fsr_out_bit2_rst_val" : "reset_to_zero_hfsrout2",
        "fsr_hip_fsr_out_bit3_rst_val" : "reset_to_zero_hfsrout3",
        "fsr_mask_tx_pll_rst_val" : "reset_to_zero_maskpll",
        "fsr_pld_txelecidle_rst_val" : "reset_to_zero_txelec",
        "gb_tx_idwidth" : "idwidth_66",
        "gb_tx_odwidth" : "odwidth_32",
        "hip_mode" : "disable_hip",
        "hip_osc_clk_scg_en" : "enable",
        "hrdrst_dcd_cal_done_bypass" : "disable",
        "hrdrst_rx_osc_clk_scg_en" : "disable",
        "hrdrst_user_ctl_en" : "disable",
        "indv" : "indv_en",
        "loopback_mode" : "disable",
        "low_latency_en" : "disable",
        "osc_clk_scg_en" : "disable",
        "phcomp_rd_del" : "phcomp_rd_del3",
        "pipe_mode" : "disable_pipe",
        "hdpldadapt_pld_avmm1_clk_rowclk_hz" : "31'd0",
        "hdpldadapt_pld_avmm2_clk_rowclk_hz" : "31'd0",
        "pld_clk1_delay_en" : "enable",
        "pld_clk1_delay_sel" : "delay_path15",
        "pld_clk1_inv_en" : "disable",
        "hdpldadapt_pld_sclk1_rowclk_hz" : "31'd0",
        "hdpldadapt_pld_sclk2_rowclk_hz" : "31'd0",
        "hdpldadapt_pld_tx_clk1_dcm_hz" : "31'd156250000",
        "hdpldadapt_pld_tx_clk1_rowclk_hz" : "31'd156250000",
        "hdpldadapt_pld_tx_clk2_dcm_hz" : "31'd644531250",
        "hdpldadapt_pld_tx_clk2_rowclk_hz" : "31'd644531250",
        "pma_aib_tx_clk_expected_setting" : "x2",
        "powerdown_mode" : "powerup",
        "sh_err" : "sh_err_dis",
        "hdpldadapt_speed_grade" : "dash_2",
        "stretch_num_stages" : "four_stage",
        "sup_mode" : "user_mode",
        "tx_datapath_tb_sel" : "cp_bond",
        "tx_fastbond_rden" : "rden_ds_fast_us_fast",
        "tx_fastbond_wren" : "wren_ds_fast_us_fast",
        "tx_fifo_power_mode" : "full_width_ps_dw",
        "tx_fifo_read_latency_adjust" : "disable",
        "tx_fifo_write_latency_adjust" : "disable",
        "tx_hip_aib_ssr_in_polling_bypass" : "disable",
        "tx_osc_clock_setting" : "osc_clk_div_by1",
        "tx_pld_10g_tx_bitslip_polling_bypass" : "disable",
        "tx_pld_8g_tx_boundary_sel_polling_bypass" : "disable",
        "tx_pld_pma_fpll_cnt_sel_polling_bypass" : "disable",
        "tx_pld_pma_fpll_num_phase_shifts_polling_bypass" : "disable",
        "tx_usertest_sel" : "enable",
        "txfifo_empty" : "empty_default",
        "txfifo_full" : "full_pc_dw",
        "txfifo_mode" : "txphase_comp",
        "txfifo_pempty" : "5'd2",
        "txfifo_pfull" : "5'd10",
        "us_bypass_pipeln" : "us_bypass_pipeln_dis",
        "word_align_enable" : "enable",
        "word_mark" : "wm_en",
        "silicon_rev" : "14nm5bcr2eb"
      }
    }
  ]
}

