# system info address_decoder_top on 2020.01.29.11:21:22
system_info:
name,value
DEVICE,1SG165HU2F50E2VG
DEVICE_FAMILY,Stratix 10
GENERATION_ID,0
#
#
# Files generated for address_decoder_top on 2020.01.29.11:21:22
files:
filepath,kind,attributes,module,is_top
sim/address_decoder_top.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_top,true
altera_mm_interconnect_191/sim/address_decoder_top_altera_mm_interconnect_191_3kbf4ri_multi_channel_avalon_universal_slave_0_translator.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_top_altera_mm_interconnect_191_3kbf4ri,false
altera_mm_interconnect_191/sim/address_decoder_top_altera_mm_interconnect_191_3kbf4ri_mm_clock_crossing_bridge_s0_translator.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_top_altera_mm_interconnect_191_3kbf4ri,false
altera_mm_interconnect_191/sim/address_decoder_top_altera_mm_interconnect_191_3kbf4ri.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_top_altera_mm_interconnect_191_3kbf4ri,false
altera_mm_interconnect_191/sim/address_decoder_top_altera_mm_interconnect_191_fv6bu5i.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_top_altera_mm_interconnect_191_fv6bu5i,false
altera_reset_controller_191/sim/mentor/altera_reset_controller.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/mentor/altera_reset_synchronizer.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/aldec/altera_reset_controller.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/aldec/altera_reset_synchronizer.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/cadence/altera_reset_controller.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/cadence/altera_reset_synchronizer.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/synopsys/altera_reset_controller.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/synopsys/altera_reset_synchronizer.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_reset_controller,false
altera_merlin_master_translator_191/sim/address_decoder_top_altera_merlin_master_translator_191_g7h47bq.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_master_translator_191_g7h47bq,false
altera_merlin_slave_translator_191/sim/address_decoder_top_altera_merlin_slave_translator_191_x56fcki.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_slave_translator_191_x56fcki,false
altera_merlin_master_agent_191/sim/address_decoder_top_altera_merlin_master_agent_191_mpbm6tq.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_master_agent_191_mpbm6tq,false
altera_merlin_slave_agent_191/sim/address_decoder_top_altera_merlin_slave_agent_191_ncfkfri.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_slave_agent_191_ncfkfri,false
altera_merlin_slave_agent_191/sim/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_slave_agent_191_ncfkfri,false
altera_merlin_router_191/sim/address_decoder_top_altera_merlin_router_191_fwgsesi.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_router_191_fwgsesi,false
altera_merlin_router_191/sim/address_decoder_top_altera_merlin_router_191_eo734fy.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_router_191_eo734fy,false
altera_merlin_demultiplexer_191/sim/address_decoder_top_altera_merlin_demultiplexer_191_cvl73xa.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_demultiplexer_191_cvl73xa,false
altera_merlin_multiplexer_191/sim/address_decoder_top_altera_merlin_multiplexer_191_mbb35ky.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_multiplexer_191_mbb35ky,false
altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_multiplexer_191_mbb35ky,false
altera_merlin_demultiplexer_191/sim/address_decoder_top_altera_merlin_demultiplexer_191_6ywz4pa.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_demultiplexer_191_6ywz4pa,false
altera_merlin_multiplexer_191/sim/address_decoder_top_altera_merlin_multiplexer_191_drzivnq.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_multiplexer_191_drzivnq,false
altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_multiplexer_191_drzivnq,false
altera_merlin_router_191/sim/address_decoder_top_altera_merlin_router_191_oyu3via.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_router_191_oyu3via,false
altera_merlin_router_191/sim/address_decoder_top_altera_merlin_router_191_eyt5dgy.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_router_191_eyt5dgy,false
altera_merlin_traffic_limiter_191/sim/altera_merlin_reorder_memory.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_traffic_limiter_191_kcba44q,false
altera_merlin_traffic_limiter_191/sim/altera_avalon_st_pipeline_base.v,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_traffic_limiter_191_kcba44q,false
altera_merlin_traffic_limiter_191/sim/address_decoder_top_altera_merlin_traffic_limiter_191_kcba44q.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_traffic_limiter_191_kcba44q,false
altera_merlin_demultiplexer_191/sim/address_decoder_top_altera_merlin_demultiplexer_191_mkj5isy.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_demultiplexer_191_mkj5isy,false
altera_merlin_multiplexer_191/sim/address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy,false
altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy,false
altera_merlin_demultiplexer_191/sim/address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa,false
altera_merlin_multiplexer_191/sim/address_decoder_top_altera_merlin_multiplexer_191_hkbv22i.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_multiplexer_191_hkbv22i,false
altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,address_decoder_top_altera_merlin_multiplexer_191_hkbv22i,false
altera_merlin_traffic_limiter_191/sim/address_decoder_top_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_191_zonrf6q.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_top_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_191_zonrf6q,false
altera_avalon_sc_fifo_191/sim/address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq.v,VERILOG,,address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq,false
altera_merlin_traffic_limiter_191/sim/address_decoder_top_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_top_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi,false
alt_hiconnect_sc_fifo_191/sim/address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq.sv,SYSTEM_VERILOG,,address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq,false
alt_hiconnect_sc_fifo_191/sim/alt_st_infer_scfifo.sv,SYSTEM_VERILOG,,address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq,false
alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo.sv,SYSTEM_VERILOG,,address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq,false
alt_hiconnect_sc_fifo_191/sim/alt_st_fifo_empty.sv,SYSTEM_VERILOG,,address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq,false
alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo_a6.sv,SYSTEM_VERILOG,,address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq,false
alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo_a7.sv,SYSTEM_VERILOG,,address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq,false
alt_hiconnect_sc_fifo_191/sim/alt_st_reg_scfifo.sv,SYSTEM_VERILOG,,address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
address_decoder_top.csr_clk,address_decoder_top_csr_clk
address_decoder_top.mac_clk,address_decoder_top_mac_clk
address_decoder_top.master,address_decoder_top_master
address_decoder_top.mm_clock_crossing_bridge,address_decoder_top_mm_clock_crossing_bridge
address_decoder_top.multi_channel,address_decoder_top_multi_channel
address_decoder_top.traffic_controller_ch_0_1,address_decoder_top_traffic_controller_ch_0_1
address_decoder_top.traffic_controller_ch_10_11,address_decoder_top_traffic_controller_ch_10_11
address_decoder_top.traffic_controller_ch_2_3,address_decoder_top_traffic_controller_ch_2_3
address_decoder_top.traffic_controller_ch_4_5,address_decoder_top_traffic_controller_ch_4_5
address_decoder_top.traffic_controller_ch_6_7,address_decoder_top_traffic_controller_ch_6_7
address_decoder_top.traffic_controller_ch_8_9,address_decoder_top_traffic_controller_ch_8_9
address_decoder_top.mm_interconnect_0,address_decoder_top_altera_mm_interconnect_191_3kbf4ri
address_decoder_top.mm_interconnect_0.master_avalon_universal_master_0_translator,address_decoder_top_altera_merlin_master_translator_191_g7h47bq
address_decoder_top.mm_interconnect_0.multi_channel_avalon_universal_slave_0_translator,address_decoder_top_altera_merlin_slave_translator_191_x56fcki
address_decoder_top.mm_interconnect_0.mm_clock_crossing_bridge_s0_translator,address_decoder_top_altera_merlin_slave_translator_191_x56fcki
address_decoder_top.mm_interconnect_0.master_avalon_universal_master_0_agent,address_decoder_top_altera_merlin_master_agent_191_mpbm6tq
address_decoder_top.mm_interconnect_0.multi_channel_avalon_universal_slave_0_agent,address_decoder_top_altera_merlin_slave_agent_191_ncfkfri
address_decoder_top.mm_interconnect_0.mm_clock_crossing_bridge_s0_agent,address_decoder_top_altera_merlin_slave_agent_191_ncfkfri
address_decoder_top.mm_interconnect_0.multi_channel_avalon_universal_slave_0_agent_rsp_fifo,address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_top.mm_interconnect_0.mm_clock_crossing_bridge_s0_agent_rsp_fifo,address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_top.mm_interconnect_0.router,address_decoder_top_altera_merlin_router_191_fwgsesi
address_decoder_top.mm_interconnect_0.router_001,address_decoder_top_altera_merlin_router_191_eo734fy
address_decoder_top.mm_interconnect_0.router_002,address_decoder_top_altera_merlin_router_191_eo734fy
address_decoder_top.mm_interconnect_0.cmd_demux,address_decoder_top_altera_merlin_demultiplexer_191_cvl73xa
address_decoder_top.mm_interconnect_0.cmd_mux,address_decoder_top_altera_merlin_multiplexer_191_mbb35ky
address_decoder_top.mm_interconnect_0.cmd_mux_001,address_decoder_top_altera_merlin_multiplexer_191_mbb35ky
address_decoder_top.mm_interconnect_0.rsp_demux,address_decoder_top_altera_merlin_demultiplexer_191_6ywz4pa
address_decoder_top.mm_interconnect_0.rsp_demux_001,address_decoder_top_altera_merlin_demultiplexer_191_6ywz4pa
address_decoder_top.mm_interconnect_0.rsp_mux,address_decoder_top_altera_merlin_multiplexer_191_drzivnq
address_decoder_top.mm_interconnect_1,address_decoder_top_altera_mm_interconnect_191_fv6bu5i
address_decoder_top.mm_interconnect_1.mm_clock_crossing_bridge_m0_translator,address_decoder_top_altera_merlin_master_translator_191_g7h47bq
address_decoder_top.mm_interconnect_1.traffic_controller_ch_0_1_avalon_universal_slave_0_translator,address_decoder_top_altera_merlin_slave_translator_191_x56fcki
address_decoder_top.mm_interconnect_1.traffic_controller_ch_2_3_avalon_universal_slave_0_translator,address_decoder_top_altera_merlin_slave_translator_191_x56fcki
address_decoder_top.mm_interconnect_1.traffic_controller_ch_4_5_avalon_universal_slave_0_translator,address_decoder_top_altera_merlin_slave_translator_191_x56fcki
address_decoder_top.mm_interconnect_1.traffic_controller_ch_6_7_avalon_universal_slave_0_translator,address_decoder_top_altera_merlin_slave_translator_191_x56fcki
address_decoder_top.mm_interconnect_1.traffic_controller_ch_8_9_avalon_universal_slave_0_translator,address_decoder_top_altera_merlin_slave_translator_191_x56fcki
address_decoder_top.mm_interconnect_1.traffic_controller_ch_10_11_avalon_universal_slave_0_translator,address_decoder_top_altera_merlin_slave_translator_191_x56fcki
address_decoder_top.mm_interconnect_1.mm_clock_crossing_bridge_m0_agent,address_decoder_top_altera_merlin_master_agent_191_mpbm6tq
address_decoder_top.mm_interconnect_1.traffic_controller_ch_0_1_avalon_universal_slave_0_agent,address_decoder_top_altera_merlin_slave_agent_191_ncfkfri
address_decoder_top.mm_interconnect_1.traffic_controller_ch_2_3_avalon_universal_slave_0_agent,address_decoder_top_altera_merlin_slave_agent_191_ncfkfri
address_decoder_top.mm_interconnect_1.traffic_controller_ch_4_5_avalon_universal_slave_0_agent,address_decoder_top_altera_merlin_slave_agent_191_ncfkfri
address_decoder_top.mm_interconnect_1.traffic_controller_ch_6_7_avalon_universal_slave_0_agent,address_decoder_top_altera_merlin_slave_agent_191_ncfkfri
address_decoder_top.mm_interconnect_1.traffic_controller_ch_8_9_avalon_universal_slave_0_agent,address_decoder_top_altera_merlin_slave_agent_191_ncfkfri
address_decoder_top.mm_interconnect_1.traffic_controller_ch_10_11_avalon_universal_slave_0_agent,address_decoder_top_altera_merlin_slave_agent_191_ncfkfri
address_decoder_top.mm_interconnect_1.traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo,address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_top.mm_interconnect_1.traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo,address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_top.mm_interconnect_1.traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo,address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_top.mm_interconnect_1.traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo,address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_top.mm_interconnect_1.traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo,address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_top.mm_interconnect_1.traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo,address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_top.mm_interconnect_1.router,address_decoder_top_altera_merlin_router_191_oyu3via
address_decoder_top.mm_interconnect_1.router_001,address_decoder_top_altera_merlin_router_191_eyt5dgy
address_decoder_top.mm_interconnect_1.router_002,address_decoder_top_altera_merlin_router_191_eyt5dgy
address_decoder_top.mm_interconnect_1.router_003,address_decoder_top_altera_merlin_router_191_eyt5dgy
address_decoder_top.mm_interconnect_1.router_004,address_decoder_top_altera_merlin_router_191_eyt5dgy
address_decoder_top.mm_interconnect_1.router_005,address_decoder_top_altera_merlin_router_191_eyt5dgy
address_decoder_top.mm_interconnect_1.router_006,address_decoder_top_altera_merlin_router_191_eyt5dgy
address_decoder_top.mm_interconnect_1.mm_clock_crossing_bridge_m0_limiter,address_decoder_top_altera_merlin_traffic_limiter_191_kcba44q
address_decoder_top.mm_interconnect_1.mm_clock_crossing_bridge_m0_limiter.my_altera_avalon_sc_fifo_dest_id_fifo,address_decoder_top_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_191_zonrf6q
address_decoder_top.mm_interconnect_1.mm_clock_crossing_bridge_m0_limiter.my_altera_avalon_sc_fifo_dest_id_fifo.my_altera_avalon_sc_fifo_dest_id_fifo,address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_top.mm_interconnect_1.mm_clock_crossing_bridge_m0_limiter.my_alt_hiconnect_sc_fifo_dest_id_fifo,address_decoder_top_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi
address_decoder_top.mm_interconnect_1.mm_clock_crossing_bridge_m0_limiter.my_alt_hiconnect_sc_fifo_dest_id_fifo.my_alt_hiconnect_sc_fifo_dest_id_fifo,address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq
address_decoder_top.mm_interconnect_1.cmd_demux,address_decoder_top_altera_merlin_demultiplexer_191_mkj5isy
address_decoder_top.mm_interconnect_1.cmd_mux,address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy
address_decoder_top.mm_interconnect_1.cmd_mux_001,address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy
address_decoder_top.mm_interconnect_1.cmd_mux_002,address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy
address_decoder_top.mm_interconnect_1.cmd_mux_003,address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy
address_decoder_top.mm_interconnect_1.cmd_mux_004,address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy
address_decoder_top.mm_interconnect_1.cmd_mux_005,address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy
address_decoder_top.mm_interconnect_1.rsp_demux,address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa
address_decoder_top.mm_interconnect_1.rsp_demux_001,address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa
address_decoder_top.mm_interconnect_1.rsp_demux_002,address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa
address_decoder_top.mm_interconnect_1.rsp_demux_003,address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa
address_decoder_top.mm_interconnect_1.rsp_demux_004,address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa
address_decoder_top.mm_interconnect_1.rsp_demux_005,address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa
address_decoder_top.mm_interconnect_1.rsp_mux,address_decoder_top_altera_merlin_multiplexer_191_hkbv22i
address_decoder_top.rst_controller,altera_reset_controller
address_decoder_top.rst_controller_001,altera_reset_controller
