-- alt_jtag_csr_master_altera_jtag_avalon_master_191_3zppvky.vhd

-- This file was auto-generated from altera_jtag_avalon_master_hw.tcl.  If you edit it your changes
-- will probably be lost.
-- 
-- Generated using ACDS version 19.4 64

library IEEE;
library altera_jtag_dc_streaming_191;
library timing_adapter_191;
library altera_avalon_sc_fifo_191;
library altera_avalon_st_bytes_to_packets_1910;
library altera_avalon_st_packets_to_bytes_1910;
library altera_avalon_packets_to_master_1910;
library channel_adapter_191;
library altera_reset_controller_191;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity alt_jtag_csr_master_altera_jtag_avalon_master_191_3zppvky is
	generic (
		USE_PLI     : integer := 0;
		PLI_PORT    : integer := 50000;
		FIFO_DEPTHS : integer := 2
	);
	port (
		clk_clk              : in  std_logic                     := '0';             --          clk.clk
		clk_reset_reset      : in  std_logic                     := '0';             --    clk_reset.reset
		master_reset_reset   : out std_logic;                                        -- master_reset.reset
		master_address       : out std_logic_vector(31 downto 0);                    --       master.address
		master_readdata      : in  std_logic_vector(31 downto 0) := (others => '0'); --             .readdata
		master_read          : out std_logic;                                        --             .read
		master_write         : out std_logic;                                        --             .write
		master_writedata     : out std_logic_vector(31 downto 0);                    --             .writedata
		master_waitrequest   : in  std_logic                     := '0';             --             .waitrequest
		master_readdatavalid : in  std_logic                     := '0';             --             .readdatavalid
		master_byteenable    : out std_logic_vector(3 downto 0)                      --             .byteenable
	);
end entity alt_jtag_csr_master_altera_jtag_avalon_master_191_3zppvky;

architecture rtl of alt_jtag_csr_master_altera_jtag_avalon_master_191_3zppvky is
	component altera_avalon_st_jtag_interface_cmp is
		generic (
			PURPOSE              : integer := 0;
			UPSTREAM_FIFO_SIZE   : integer := 0;
			DOWNSTREAM_FIFO_SIZE : integer := 0;
			MGMT_CHANNEL_WIDTH   : integer := -1;
			EXPORT_JTAG          : integer := 0;
			USE_PLI              : integer := 0;
			PLI_PORT             : integer := 50000
		);
		port (
			clk             : in  std_logic                    := 'X';             -- clk
			reset_n         : in  std_logic                    := 'X';             -- reset_n
			source_data     : out std_logic_vector(7 downto 0);                    -- data
			source_valid    : out std_logic;                                       -- valid
			sink_data       : in  std_logic_vector(7 downto 0) := (others => 'X'); -- data
			sink_valid      : in  std_logic                    := 'X';             -- valid
			sink_ready      : out std_logic;                                       -- ready
			resetrequest    : out std_logic;                                       -- reset
			source_ready    : in  std_logic                    := 'X';             -- ready
			mgmt_valid      : out std_logic;                                       -- valid
			mgmt_channel    : out std_logic_vector(0 downto 0);                    -- channel
			mgmt_data       : out std_logic;                                       -- data
			jtag_tck        : in  std_logic                    := 'X';             -- clk
			jtag_tms        : in  std_logic                    := 'X';             -- tms
			jtag_tdi        : in  std_logic                    := 'X';             -- tdi
			jtag_tdo        : out std_logic;                                       -- tdo
			jtag_ena        : in  std_logic                    := 'X';             -- ena
			jtag_usr1       : in  std_logic                    := 'X';             -- usr1
			jtag_clr        : in  std_logic                    := 'X';             -- clr
			jtag_clrn       : in  std_logic                    := 'X';             -- clrn
			jtag_state_tlr  : in  std_logic                    := 'X';             -- jtag_state_tlr
			jtag_state_rti  : in  std_logic                    := 'X';             -- jtag_state_rti
			jtag_state_sdrs : in  std_logic                    := 'X';             -- jtag_state_sdrs
			jtag_state_cdr  : in  std_logic                    := 'X';             -- jtag_state_cdr
			jtag_state_sdr  : in  std_logic                    := 'X';             -- jtag_state_sdr
			jtag_state_e1dr : in  std_logic                    := 'X';             -- jtag_state_e1dr
			jtag_state_pdr  : in  std_logic                    := 'X';             -- jtag_state_pdr
			jtag_state_e2dr : in  std_logic                    := 'X';             -- jtag_state_e2dr
			jtag_state_udr  : in  std_logic                    := 'X';             -- jtag_state_udr
			jtag_state_sirs : in  std_logic                    := 'X';             -- jtag_state_sirs
			jtag_state_cir  : in  std_logic                    := 'X';             -- jtag_state_cir
			jtag_state_sir  : in  std_logic                    := 'X';             -- jtag_state_sir
			jtag_state_e1ir : in  std_logic                    := 'X';             -- jtag_state_e1ir
			jtag_state_pir  : in  std_logic                    := 'X';             -- jtag_state_pir
			jtag_state_e2ir : in  std_logic                    := 'X';             -- jtag_state_e2ir
			jtag_state_uir  : in  std_logic                    := 'X';             -- jtag_state_uir
			jtag_ir_in      : in  std_logic_vector(2 downto 0) := (others => 'X'); -- ir_in
			jtag_irq        : out std_logic;                                       -- irq
			jtag_ir_out     : out std_logic_vector(2 downto 0)                     -- ir_out
		);
	end component altera_avalon_st_jtag_interface_cmp;

	component alt_jtag_csr_master_timing_adapter_191_rrgemwi_cmp is
		port (
			clk       : in  std_logic                    := 'X';             -- clk
			reset_n   : in  std_logic                    := 'X';             -- reset_n
			in_data   : in  std_logic_vector(7 downto 0) := (others => 'X'); -- data
			in_valid  : in  std_logic                    := 'X';             -- valid
			out_data  : out std_logic_vector(7 downto 0);                    -- data
			out_valid : out std_logic;                                       -- valid
			out_ready : in  std_logic                    := 'X'              -- ready
		);
	end component alt_jtag_csr_master_timing_adapter_191_rrgemwi_cmp;

	component alt_jtag_csr_master_altera_avalon_sc_fifo_191_e5eqkcq_cmp is
		generic (
			SYMBOLS_PER_BEAT    : integer := 1;
			BITS_PER_SYMBOL     : integer := 8;
			FIFO_DEPTH          : integer := 16;
			CHANNEL_WIDTH       : integer := 0;
			ERROR_WIDTH         : integer := 0;
			USE_PACKETS         : integer := 0;
			USE_FILL_LEVEL      : integer := 0;
			EMPTY_LATENCY       : integer := 3;
			USE_MEMORY_BLOCKS   : integer := 1;
			USE_STORE_FORWARD   : integer := 0;
			USE_ALMOST_FULL_IF  : integer := 0;
			USE_ALMOST_EMPTY_IF : integer := 0;
			EMPTY_WIDTH         : integer := 1;
			SYNC_RESET          : integer := 0
		);
		port (
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X';             -- reset
			in_data           : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- data
			in_valid          : in  std_logic                     := 'X';             -- valid
			in_ready          : out std_logic;                                        -- ready
			out_data          : out std_logic_vector(7 downto 0);                     -- data
			out_valid         : out std_logic;                                        -- valid
			out_ready         : in  std_logic                     := 'X';             -- ready
			csr_address       : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- address
			csr_read          : in  std_logic                     := 'X';             -- read
			csr_write         : in  std_logic                     := 'X';             -- write
			csr_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			csr_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			almost_full_data  : out std_logic;                                        -- data
			almost_empty_data : out std_logic;                                        -- data
			in_startofpacket  : in  std_logic                     := 'X';             -- startofpacket
			in_endofpacket    : in  std_logic                     := 'X';             -- endofpacket
			out_startofpacket : out std_logic;                                        -- startofpacket
			out_endofpacket   : out std_logic;                                        -- endofpacket
			in_empty          : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- empty
			out_empty         : out std_logic_vector(0 downto 0);                     -- empty
			in_error          : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- error
			out_error         : out std_logic_vector(0 downto 0);                     -- error
			in_channel        : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- channel
			out_channel       : out std_logic_vector(0 downto 0)                      -- channel
		);
	end component alt_jtag_csr_master_altera_avalon_sc_fifo_191_e5eqkcq_cmp;

	component altera_avalon_st_bytes_to_packets_cmp is
		generic (
			CHANNEL_WIDTH : integer := 8;
			ENCODING      : integer := 0
		);
		port (
			clk               : in  std_logic                    := 'X';             -- clk
			reset_n           : in  std_logic                    := 'X';             -- reset_n
			out_channel       : out std_logic_vector(7 downto 0);                    -- channel
			out_ready         : in  std_logic                    := 'X';             -- ready
			out_valid         : out std_logic;                                       -- valid
			out_data          : out std_logic_vector(7 downto 0);                    -- data
			out_startofpacket : out std_logic;                                       -- startofpacket
			out_endofpacket   : out std_logic;                                       -- endofpacket
			in_ready          : out std_logic;                                       -- ready
			in_valid          : in  std_logic                    := 'X';             -- valid
			in_data           : in  std_logic_vector(7 downto 0) := (others => 'X')  -- data
		);
	end component altera_avalon_st_bytes_to_packets_cmp;

	component altera_avalon_st_packets_to_bytes_cmp is
		generic (
			CHANNEL_WIDTH : integer := 8;
			ENCODING      : integer := 0
		);
		port (
			clk              : in  std_logic                    := 'X';             -- clk
			reset_n          : in  std_logic                    := 'X';             -- reset_n
			in_ready         : out std_logic;                                       -- ready
			in_valid         : in  std_logic                    := 'X';             -- valid
			in_data          : in  std_logic_vector(7 downto 0) := (others => 'X'); -- data
			in_channel       : in  std_logic_vector(7 downto 0) := (others => 'X'); -- channel
			in_startofpacket : in  std_logic                    := 'X';             -- startofpacket
			in_endofpacket   : in  std_logic                    := 'X';             -- endofpacket
			out_ready        : in  std_logic                    := 'X';             -- ready
			out_valid        : out std_logic;                                       -- valid
			out_data         : out std_logic_vector(7 downto 0)                     -- data
		);
	end component altera_avalon_st_packets_to_bytes_cmp;

	component altera_avalon_packets_to_master_cmp is
		generic (
			FAST_VER    : integer := 0;
			FIFO_DEPTHS : integer := 2;
			FIFO_WIDTHU : integer := 1
		);
		port (
			clk               : in  std_logic                     := 'X';             -- clk
			reset_n           : in  std_logic                     := 'X';             -- reset_n
			out_ready         : in  std_logic                     := 'X';             -- ready
			out_valid         : out std_logic;                                        -- valid
			out_data          : out std_logic_vector(7 downto 0);                     -- data
			out_startofpacket : out std_logic;                                        -- startofpacket
			out_endofpacket   : out std_logic;                                        -- endofpacket
			in_ready          : out std_logic;                                        -- ready
			in_valid          : in  std_logic                     := 'X';             -- valid
			in_data           : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- data
			in_startofpacket  : in  std_logic                     := 'X';             -- startofpacket
			in_endofpacket    : in  std_logic                     := 'X';             -- endofpacket
			address           : out std_logic_vector(31 downto 0);                    -- address
			readdata          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			read              : out std_logic;                                        -- read
			write             : out std_logic;                                        -- write
			writedata         : out std_logic_vector(31 downto 0);                    -- writedata
			waitrequest       : in  std_logic                     := 'X';             -- waitrequest
			readdatavalid     : in  std_logic                     := 'X';             -- readdatavalid
			byteenable        : out std_logic_vector(3 downto 0)                      -- byteenable
		);
	end component altera_avalon_packets_to_master_cmp;

	component alt_jtag_csr_master_channel_adapter_191_uc27kqq_cmp is
		port (
			clk               : in  std_logic                    := 'X';             -- clk
			reset_n           : in  std_logic                    := 'X';             -- reset_n
			in_data           : in  std_logic_vector(7 downto 0) := (others => 'X'); -- data
			in_valid          : in  std_logic                    := 'X';             -- valid
			in_ready          : out std_logic;                                       -- ready
			in_startofpacket  : in  std_logic                    := 'X';             -- startofpacket
			in_endofpacket    : in  std_logic                    := 'X';             -- endofpacket
			in_channel        : in  std_logic_vector(7 downto 0) := (others => 'X'); -- channel
			out_data          : out std_logic_vector(7 downto 0);                    -- data
			out_valid         : out std_logic;                                       -- valid
			out_ready         : in  std_logic                    := 'X';             -- ready
			out_startofpacket : out std_logic;                                       -- startofpacket
			out_endofpacket   : out std_logic                                        -- endofpacket
		);
	end component alt_jtag_csr_master_channel_adapter_191_uc27kqq_cmp;

	component alt_jtag_csr_master_channel_adapter_191_cco4x3a_cmp is
		port (
			clk               : in  std_logic                    := 'X';             -- clk
			reset_n           : in  std_logic                    := 'X';             -- reset_n
			in_data           : in  std_logic_vector(7 downto 0) := (others => 'X'); -- data
			in_valid          : in  std_logic                    := 'X';             -- valid
			in_ready          : out std_logic;                                       -- ready
			in_startofpacket  : in  std_logic                    := 'X';             -- startofpacket
			in_endofpacket    : in  std_logic                    := 'X';             -- endofpacket
			out_data          : out std_logic_vector(7 downto 0);                    -- data
			out_valid         : out std_logic;                                       -- valid
			out_ready         : in  std_logic                    := 'X';             -- ready
			out_startofpacket : out std_logic;                                       -- startofpacket
			out_endofpacket   : out std_logic;                                       -- endofpacket
			out_channel       : out std_logic_vector(7 downto 0)                     -- channel
		);
	end component alt_jtag_csr_master_channel_adapter_191_cco4x3a_cmp;

	component altera_reset_controller_cmp is
		generic (
			NUM_RESET_INPUTS          : integer := 6;
			OUTPUT_RESET_SYNC_EDGES   : string  := "deassert";
			SYNC_DEPTH                : integer := 2;
			RESET_REQUEST_PRESENT     : integer := 0;
			RESET_REQ_WAIT_TIME       : integer := 1;
			MIN_RST_ASSERTION_TIME    : integer := 3;
			RESET_REQ_EARLY_DSRT_TIME : integer := 1;
			USE_RESET_REQUEST_IN0     : integer := 0;
			USE_RESET_REQUEST_IN1     : integer := 0;
			USE_RESET_REQUEST_IN2     : integer := 0;
			USE_RESET_REQUEST_IN3     : integer := 0;
			USE_RESET_REQUEST_IN4     : integer := 0;
			USE_RESET_REQUEST_IN5     : integer := 0;
			USE_RESET_REQUEST_IN6     : integer := 0;
			USE_RESET_REQUEST_IN7     : integer := 0;
			USE_RESET_REQUEST_IN8     : integer := 0;
			USE_RESET_REQUEST_IN9     : integer := 0;
			USE_RESET_REQUEST_IN10    : integer := 0;
			USE_RESET_REQUEST_IN11    : integer := 0;
			USE_RESET_REQUEST_IN12    : integer := 0;
			USE_RESET_REQUEST_IN13    : integer := 0;
			USE_RESET_REQUEST_IN14    : integer := 0;
			USE_RESET_REQUEST_IN15    : integer := 0;
			ADAPT_RESET_REQUEST       : integer := 0
		);
		port (
			reset_in0      : in  std_logic := 'X'; -- reset
			clk            : in  std_logic := 'X'; -- clk
			reset_out      : out std_logic;        -- reset
			reset_req      : out std_logic;        -- reset_req
			reset_req_in0  : in  std_logic := 'X'; -- reset_req
			reset_in1      : in  std_logic := 'X'; -- reset
			reset_req_in1  : in  std_logic := 'X'; -- reset_req
			reset_in2      : in  std_logic := 'X'; -- reset
			reset_req_in2  : in  std_logic := 'X'; -- reset_req
			reset_in3      : in  std_logic := 'X'; -- reset
			reset_req_in3  : in  std_logic := 'X'; -- reset_req
			reset_in4      : in  std_logic := 'X'; -- reset
			reset_req_in4  : in  std_logic := 'X'; -- reset_req
			reset_in5      : in  std_logic := 'X'; -- reset
			reset_req_in5  : in  std_logic := 'X'; -- reset_req
			reset_in6      : in  std_logic := 'X'; -- reset
			reset_req_in6  : in  std_logic := 'X'; -- reset_req
			reset_in7      : in  std_logic := 'X'; -- reset
			reset_req_in7  : in  std_logic := 'X'; -- reset_req
			reset_in8      : in  std_logic := 'X'; -- reset
			reset_req_in8  : in  std_logic := 'X'; -- reset_req
			reset_in9      : in  std_logic := 'X'; -- reset
			reset_req_in9  : in  std_logic := 'X'; -- reset_req
			reset_in10     : in  std_logic := 'X'; -- reset
			reset_req_in10 : in  std_logic := 'X'; -- reset_req
			reset_in11     : in  std_logic := 'X'; -- reset
			reset_req_in11 : in  std_logic := 'X'; -- reset_req
			reset_in12     : in  std_logic := 'X'; -- reset
			reset_req_in12 : in  std_logic := 'X'; -- reset_req
			reset_in13     : in  std_logic := 'X'; -- reset
			reset_req_in13 : in  std_logic := 'X'; -- reset_req
			reset_in14     : in  std_logic := 'X'; -- reset
			reset_req_in14 : in  std_logic := 'X'; -- reset_req
			reset_in15     : in  std_logic := 'X'; -- reset
			reset_req_in15 : in  std_logic := 'X'  -- reset_req
		);
	end component altera_reset_controller_cmp;

	signal jtag_phy_embedded_in_jtag_master_src_valid : std_logic;                    -- jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
	signal jtag_phy_embedded_in_jtag_master_src_data  : std_logic_vector(7 downto 0); -- jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
	signal timing_adt_out_valid                       : std_logic;                    -- timing_adt:out_valid -> fifo:in_valid
	signal timing_adt_out_data                        : std_logic_vector(7 downto 0); -- timing_adt:out_data -> fifo:in_data
	signal timing_adt_out_ready                       : std_logic;                    -- fifo:in_ready -> timing_adt:out_ready
	signal fifo_out_valid                             : std_logic;                    -- fifo:out_valid -> b2p:in_valid
	signal fifo_out_data                              : std_logic_vector(7 downto 0); -- fifo:out_data -> b2p:in_data
	signal fifo_out_ready                             : std_logic;                    -- b2p:in_ready -> fifo:out_ready
	signal b2p_out_packets_stream_valid               : std_logic;                    -- b2p:out_valid -> b2p_adapter:in_valid
	signal b2p_out_packets_stream_data                : std_logic_vector(7 downto 0); -- b2p:out_data -> b2p_adapter:in_data
	signal b2p_out_packets_stream_ready               : std_logic;                    -- b2p_adapter:in_ready -> b2p:out_ready
	signal b2p_out_packets_stream_channel             : std_logic_vector(7 downto 0); -- b2p:out_channel -> b2p_adapter:in_channel
	signal b2p_out_packets_stream_startofpacket       : std_logic;                    -- b2p:out_startofpacket -> b2p_adapter:in_startofpacket
	signal b2p_out_packets_stream_endofpacket         : std_logic;                    -- b2p:out_endofpacket -> b2p_adapter:in_endofpacket
	signal b2p_adapter_out_valid                      : std_logic;                    -- b2p_adapter:out_valid -> transacto:in_valid
	signal b2p_adapter_out_data                       : std_logic_vector(7 downto 0); -- b2p_adapter:out_data -> transacto:in_data
	signal b2p_adapter_out_ready                      : std_logic;                    -- transacto:in_ready -> b2p_adapter:out_ready
	signal b2p_adapter_out_startofpacket              : std_logic;                    -- b2p_adapter:out_startofpacket -> transacto:in_startofpacket
	signal b2p_adapter_out_endofpacket                : std_logic;                    -- b2p_adapter:out_endofpacket -> transacto:in_endofpacket
	signal transacto_out_stream_valid                 : std_logic;                    -- transacto:out_valid -> p2b_adapter:in_valid
	signal transacto_out_stream_data                  : std_logic_vector(7 downto 0); -- transacto:out_data -> p2b_adapter:in_data
	signal transacto_out_stream_ready                 : std_logic;                    -- p2b_adapter:in_ready -> transacto:out_ready
	signal transacto_out_stream_startofpacket         : std_logic;                    -- transacto:out_startofpacket -> p2b_adapter:in_startofpacket
	signal transacto_out_stream_endofpacket           : std_logic;                    -- transacto:out_endofpacket -> p2b_adapter:in_endofpacket
	signal p2b_adapter_out_valid                      : std_logic;                    -- p2b_adapter:out_valid -> p2b:in_valid
	signal p2b_adapter_out_data                       : std_logic_vector(7 downto 0); -- p2b_adapter:out_data -> p2b:in_data
	signal p2b_adapter_out_ready                      : std_logic;                    -- p2b:in_ready -> p2b_adapter:out_ready
	signal p2b_adapter_out_channel                    : std_logic_vector(7 downto 0); -- p2b_adapter:out_channel -> p2b:in_channel
	signal p2b_adapter_out_startofpacket              : std_logic;                    -- p2b_adapter:out_startofpacket -> p2b:in_startofpacket
	signal p2b_adapter_out_endofpacket                : std_logic;                    -- p2b_adapter:out_endofpacket -> p2b:in_endofpacket
	signal p2b_out_bytes_stream_valid                 : std_logic;                    -- p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
	signal p2b_out_bytes_stream_data                  : std_logic_vector(7 downto 0); -- p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
	signal p2b_out_bytes_stream_ready                 : std_logic;                    -- jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
	signal rst_controller_reset_out_reset             : std_logic;                    -- rst_controller:reset_out -> [fifo:reset, rst_controller_reset_out_reset:in]
	signal rst_controller_reset_out_reset_ports_inv   : std_logic;                    -- rst_controller_reset_out_reset:inv -> [b2p:reset_n, b2p_adapter:reset_n, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]

	for jtag_phy_embedded_in_jtag_master : altera_avalon_st_jtag_interface_cmp
		use entity altera_jtag_dc_streaming_191.altera_avalon_st_jtag_interface;
	for timing_adt : alt_jtag_csr_master_timing_adapter_191_rrgemwi_cmp
		use entity timing_adapter_191.alt_jtag_csr_master_timing_adapter_191_rrgemwi;
	for fifo : alt_jtag_csr_master_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.alt_jtag_csr_master_altera_avalon_sc_fifo_191_e5eqkcq;
	for b2p : altera_avalon_st_bytes_to_packets_cmp
		use entity altera_avalon_st_bytes_to_packets_1910.altera_avalon_st_bytes_to_packets;
	for p2b : altera_avalon_st_packets_to_bytes_cmp
		use entity altera_avalon_st_packets_to_bytes_1910.altera_avalon_st_packets_to_bytes;
	for transacto : altera_avalon_packets_to_master_cmp
		use entity altera_avalon_packets_to_master_1910.altera_avalon_packets_to_master;
	for b2p_adapter : alt_jtag_csr_master_channel_adapter_191_uc27kqq_cmp
		use entity channel_adapter_191.alt_jtag_csr_master_channel_adapter_191_uc27kqq;
	for p2b_adapter : alt_jtag_csr_master_channel_adapter_191_cco4x3a_cmp
		use entity channel_adapter_191.alt_jtag_csr_master_channel_adapter_191_cco4x3a;
	for rst_controller : altera_reset_controller_cmp
		use entity altera_reset_controller_191.altera_reset_controller;
begin

	use_pli_check : if USE_PLI /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pli_port_check : if PLI_PORT /= 50000 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	fifo_depths_check : if FIFO_DEPTHS /= 2 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	jtag_phy_embedded_in_jtag_master : component altera_avalon_st_jtag_interface_cmp
		generic map (
			PURPOSE              => 1,
			UPSTREAM_FIFO_SIZE   => 0,
			DOWNSTREAM_FIFO_SIZE => 64,
			MGMT_CHANNEL_WIDTH   => -1,
			EXPORT_JTAG          => 0,
			USE_PLI              => 0,
			PLI_PORT             => 50000
		)
		port map (
			clk             => clk_clk,                                    --        clock.clk
			reset_n         => rst_controller_reset_out_reset_ports_inv,   --  clock_reset.reset_n
			source_data     => jtag_phy_embedded_in_jtag_master_src_data,  --          src.data
			source_valid    => jtag_phy_embedded_in_jtag_master_src_valid, --             .valid
			sink_data       => p2b_out_bytes_stream_data,                  --         sink.data
			sink_valid      => p2b_out_bytes_stream_valid,                 --             .valid
			sink_ready      => p2b_out_bytes_stream_ready,                 --             .ready
			resetrequest    => master_reset_reset,                         -- resetrequest.reset
			source_ready    => '1',                                        --  (terminated)
			mgmt_valid      => open,                                       --  (terminated)
			mgmt_channel    => open,                                       --  (terminated)
			mgmt_data       => open,                                       --  (terminated)
			jtag_tck        => '0',                                        --  (terminated)
			jtag_tms        => '0',                                        --  (terminated)
			jtag_tdi        => '0',                                        --  (terminated)
			jtag_tdo        => open,                                       --  (terminated)
			jtag_ena        => '0',                                        --  (terminated)
			jtag_usr1       => '0',                                        --  (terminated)
			jtag_clr        => '0',                                        --  (terminated)
			jtag_clrn       => '0',                                        --  (terminated)
			jtag_state_tlr  => '0',                                        --  (terminated)
			jtag_state_rti  => '0',                                        --  (terminated)
			jtag_state_sdrs => '0',                                        --  (terminated)
			jtag_state_cdr  => '0',                                        --  (terminated)
			jtag_state_sdr  => '0',                                        --  (terminated)
			jtag_state_e1dr => '0',                                        --  (terminated)
			jtag_state_pdr  => '0',                                        --  (terminated)
			jtag_state_e2dr => '0',                                        --  (terminated)
			jtag_state_udr  => '0',                                        --  (terminated)
			jtag_state_sirs => '0',                                        --  (terminated)
			jtag_state_cir  => '0',                                        --  (terminated)
			jtag_state_sir  => '0',                                        --  (terminated)
			jtag_state_e1ir => '0',                                        --  (terminated)
			jtag_state_pir  => '0',                                        --  (terminated)
			jtag_state_e2ir => '0',                                        --  (terminated)
			jtag_state_uir  => '0',                                        --  (terminated)
			jtag_ir_in      => "000",                                      --  (terminated)
			jtag_irq        => open,                                       --  (terminated)
			jtag_ir_out     => open                                        --  (terminated)
		);

	timing_adt : component alt_jtag_csr_master_timing_adapter_191_rrgemwi_cmp
		port map (
			clk       => clk_clk,                                    --   clk.clk
			reset_n   => rst_controller_reset_out_reset_ports_inv,   -- reset.reset_n
			in_data   => jtag_phy_embedded_in_jtag_master_src_data,  --    in.data
			in_valid  => jtag_phy_embedded_in_jtag_master_src_valid, --      .valid
			out_data  => timing_adt_out_data,                        --   out.data
			out_valid => timing_adt_out_valid,                       --      .valid
			out_ready => timing_adt_out_ready                        --      .ready
		);

	fifo : component alt_jtag_csr_master_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 8,
			FIFO_DEPTH          => 64,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 0,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 3,
			USE_MEMORY_BLOCKS   => 1,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => clk_clk,                            --       clk.clk
			reset             => rst_controller_reset_out_reset,     -- clk_reset.reset
			in_data           => timing_adt_out_data,                --        in.data
			in_valid          => timing_adt_out_valid,               --          .valid
			in_ready          => timing_adt_out_ready,               --          .ready
			out_data          => fifo_out_data,                      --       out.data
			out_valid         => fifo_out_valid,                     --          .valid
			out_ready         => fifo_out_ready,                     --          .ready
			csr_address       => "00",                               -- (terminated)
			csr_read          => '0',                                -- (terminated)
			csr_write         => '0',                                -- (terminated)
			csr_readdata      => open,                               -- (terminated)
			csr_writedata     => "00000000000000000000000000000000", -- (terminated)
			almost_full_data  => open,                               -- (terminated)
			almost_empty_data => open,                               -- (terminated)
			in_startofpacket  => '0',                                -- (terminated)
			in_endofpacket    => '0',                                -- (terminated)
			out_startofpacket => open,                               -- (terminated)
			out_endofpacket   => open,                               -- (terminated)
			in_empty          => "0",                                -- (terminated)
			out_empty         => open,                               -- (terminated)
			in_error          => "0",                                -- (terminated)
			out_error         => open,                               -- (terminated)
			in_channel        => "0",                                -- (terminated)
			out_channel       => open                                -- (terminated)
		);

	b2p : component altera_avalon_st_bytes_to_packets_cmp
		generic map (
			CHANNEL_WIDTH => 8,
			ENCODING      => 0
		)
		port map (
			clk               => clk_clk,                                  --                clk.clk
			reset_n           => rst_controller_reset_out_reset_ports_inv, --          clk_reset.reset_n
			out_channel       => b2p_out_packets_stream_channel,           -- out_packets_stream.channel
			out_ready         => b2p_out_packets_stream_ready,             --                   .ready
			out_valid         => b2p_out_packets_stream_valid,             --                   .valid
			out_data          => b2p_out_packets_stream_data,              --                   .data
			out_startofpacket => b2p_out_packets_stream_startofpacket,     --                   .startofpacket
			out_endofpacket   => b2p_out_packets_stream_endofpacket,       --                   .endofpacket
			in_ready          => fifo_out_ready,                           --    in_bytes_stream.ready
			in_valid          => fifo_out_valid,                           --                   .valid
			in_data           => fifo_out_data                             --                   .data
		);

	p2b : component altera_avalon_st_packets_to_bytes_cmp
		generic map (
			CHANNEL_WIDTH => 8,
			ENCODING      => 0
		)
		port map (
			clk              => clk_clk,                                  --               clk.clk
			reset_n          => rst_controller_reset_out_reset_ports_inv, --         clk_reset.reset_n
			in_ready         => p2b_adapter_out_ready,                    -- in_packets_stream.ready
			in_valid         => p2b_adapter_out_valid,                    --                  .valid
			in_data          => p2b_adapter_out_data,                     --                  .data
			in_channel       => p2b_adapter_out_channel,                  --                  .channel
			in_startofpacket => p2b_adapter_out_startofpacket,            --                  .startofpacket
			in_endofpacket   => p2b_adapter_out_endofpacket,              --                  .endofpacket
			out_ready        => p2b_out_bytes_stream_ready,               --  out_bytes_stream.ready
			out_valid        => p2b_out_bytes_stream_valid,               --                  .valid
			out_data         => p2b_out_bytes_stream_data                 --                  .data
		);

	transacto : component altera_avalon_packets_to_master_cmp
		generic map (
			FAST_VER    => 0,
			FIFO_DEPTHS => 2,
			FIFO_WIDTHU => 1
		)
		port map (
			clk               => clk_clk,                                  --           clk.clk
			reset_n           => rst_controller_reset_out_reset_ports_inv, --     clk_reset.reset_n
			out_ready         => transacto_out_stream_ready,               --    out_stream.ready
			out_valid         => transacto_out_stream_valid,               --              .valid
			out_data          => transacto_out_stream_data,                --              .data
			out_startofpacket => transacto_out_stream_startofpacket,       --              .startofpacket
			out_endofpacket   => transacto_out_stream_endofpacket,         --              .endofpacket
			in_ready          => b2p_adapter_out_ready,                    --     in_stream.ready
			in_valid          => b2p_adapter_out_valid,                    --              .valid
			in_data           => b2p_adapter_out_data,                     --              .data
			in_startofpacket  => b2p_adapter_out_startofpacket,            --              .startofpacket
			in_endofpacket    => b2p_adapter_out_endofpacket,              --              .endofpacket
			address           => master_address,                           -- avalon_master.address
			readdata          => master_readdata,                          --              .readdata
			read              => master_read,                              --              .read
			write             => master_write,                             --              .write
			writedata         => master_writedata,                         --              .writedata
			waitrequest       => master_waitrequest,                       --              .waitrequest
			readdatavalid     => master_readdatavalid,                     --              .readdatavalid
			byteenable        => master_byteenable                         --              .byteenable
		);

	b2p_adapter : component alt_jtag_csr_master_channel_adapter_191_uc27kqq_cmp
		port map (
			clk               => clk_clk,                                  --   clk.clk
			reset_n           => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
			in_data           => b2p_out_packets_stream_data,              --    in.data
			in_valid          => b2p_out_packets_stream_valid,             --      .valid
			in_ready          => b2p_out_packets_stream_ready,             --      .ready
			in_startofpacket  => b2p_out_packets_stream_startofpacket,     --      .startofpacket
			in_endofpacket    => b2p_out_packets_stream_endofpacket,       --      .endofpacket
			in_channel        => b2p_out_packets_stream_channel,           --      .channel
			out_data          => b2p_adapter_out_data,                     --   out.data
			out_valid         => b2p_adapter_out_valid,                    --      .valid
			out_ready         => b2p_adapter_out_ready,                    --      .ready
			out_startofpacket => b2p_adapter_out_startofpacket,            --      .startofpacket
			out_endofpacket   => b2p_adapter_out_endofpacket               --      .endofpacket
		);

	p2b_adapter : component alt_jtag_csr_master_channel_adapter_191_cco4x3a_cmp
		port map (
			clk               => clk_clk,                                  --   clk.clk
			reset_n           => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
			in_data           => transacto_out_stream_data,                --    in.data
			in_valid          => transacto_out_stream_valid,               --      .valid
			in_ready          => transacto_out_stream_ready,               --      .ready
			in_startofpacket  => transacto_out_stream_startofpacket,       --      .startofpacket
			in_endofpacket    => transacto_out_stream_endofpacket,         --      .endofpacket
			out_data          => p2b_adapter_out_data,                     --   out.data
			out_valid         => p2b_adapter_out_valid,                    --      .valid
			out_ready         => p2b_adapter_out_ready,                    --      .ready
			out_startofpacket => p2b_adapter_out_startofpacket,            --      .startofpacket
			out_endofpacket   => p2b_adapter_out_endofpacket,              --      .endofpacket
			out_channel       => p2b_adapter_out_channel                   --      .channel
		);

	rst_controller : component altera_reset_controller_cmp
		generic map (
			NUM_RESET_INPUTS          => 1,
			OUTPUT_RESET_SYNC_EDGES   => "deassert",
			SYNC_DEPTH                => 2,
			RESET_REQUEST_PRESENT     => 0,
			RESET_REQ_WAIT_TIME       => 1,
			MIN_RST_ASSERTION_TIME    => 3,
			RESET_REQ_EARLY_DSRT_TIME => 1,
			USE_RESET_REQUEST_IN0     => 0,
			USE_RESET_REQUEST_IN1     => 0,
			USE_RESET_REQUEST_IN2     => 0,
			USE_RESET_REQUEST_IN3     => 0,
			USE_RESET_REQUEST_IN4     => 0,
			USE_RESET_REQUEST_IN5     => 0,
			USE_RESET_REQUEST_IN6     => 0,
			USE_RESET_REQUEST_IN7     => 0,
			USE_RESET_REQUEST_IN8     => 0,
			USE_RESET_REQUEST_IN9     => 0,
			USE_RESET_REQUEST_IN10    => 0,
			USE_RESET_REQUEST_IN11    => 0,
			USE_RESET_REQUEST_IN12    => 0,
			USE_RESET_REQUEST_IN13    => 0,
			USE_RESET_REQUEST_IN14    => 0,
			USE_RESET_REQUEST_IN15    => 0,
			ADAPT_RESET_REQUEST       => 0
		)
		port map (
			reset_in0      => clk_reset_reset,                -- reset_in0.reset
			clk            => clk_clk,                        --       clk.clk
			reset_out      => rst_controller_reset_out_reset, -- reset_out.reset
			reset_req      => open,                           -- (terminated)
			reset_req_in0  => '0',                            -- (terminated)
			reset_in1      => '0',                            -- (terminated)
			reset_req_in1  => '0',                            -- (terminated)
			reset_in2      => '0',                            -- (terminated)
			reset_req_in2  => '0',                            -- (terminated)
			reset_in3      => '0',                            -- (terminated)
			reset_req_in3  => '0',                            -- (terminated)
			reset_in4      => '0',                            -- (terminated)
			reset_req_in4  => '0',                            -- (terminated)
			reset_in5      => '0',                            -- (terminated)
			reset_req_in5  => '0',                            -- (terminated)
			reset_in6      => '0',                            -- (terminated)
			reset_req_in6  => '0',                            -- (terminated)
			reset_in7      => '0',                            -- (terminated)
			reset_req_in7  => '0',                            -- (terminated)
			reset_in8      => '0',                            -- (terminated)
			reset_req_in8  => '0',                            -- (terminated)
			reset_in9      => '0',                            -- (terminated)
			reset_req_in9  => '0',                            -- (terminated)
			reset_in10     => '0',                            -- (terminated)
			reset_req_in10 => '0',                            -- (terminated)
			reset_in11     => '0',                            -- (terminated)
			reset_req_in11 => '0',                            -- (terminated)
			reset_in12     => '0',                            -- (terminated)
			reset_req_in12 => '0',                            -- (terminated)
			reset_in13     => '0',                            -- (terminated)
			reset_req_in13 => '0',                            -- (terminated)
			reset_in14     => '0',                            -- (terminated)
			reset_req_in14 => '0',                            -- (terminated)
			reset_in15     => '0',                            -- (terminated)
			reset_req_in15 => '0'                             -- (terminated)
		);

	rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;

end architecture rtl; -- of alt_jtag_csr_master_altera_jtag_avalon_master_191_3zppvky
