-- address_decoder_multi_channel.vhd

-- Generated using ACDS version 19.4 64

library IEEE;
library address_decoder_multi_channel_channel_0;
library address_decoder_multi_channel_channel_1;
library address_decoder_multi_channel_channel_10;
library address_decoder_multi_channel_channel_11;
library address_decoder_multi_channel_channel_2;
library address_decoder_multi_channel_channel_3;
library address_decoder_multi_channel_channel_4;
library address_decoder_multi_channel_channel_5;
library address_decoder_multi_channel_channel_6;
library address_decoder_multi_channel_channel_7;
library address_decoder_multi_channel_channel_8;
library address_decoder_multi_channel_channel_9;
library address_decoder_multi_channel_csr_clk;
library address_decoder_multi_channel_master;
library altera_mm_interconnect_191;
library altera_reset_controller_191;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity address_decoder_multi_channel is
	port (
		channel_0_address      : out std_logic_vector(15 downto 0);                    --     channel_0.address
		channel_0_write        : out std_logic;                                        --              .write
		channel_0_read         : out std_logic;                                        --              .read
		channel_0_readdata     : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		channel_0_writedata    : out std_logic_vector(31 downto 0);                    --              .writedata
		channel_0_waitrequest  : in  std_logic                     := '0';             --              .waitrequest
		channel_1_address      : out std_logic_vector(15 downto 0);                    --     channel_1.address
		channel_1_write        : out std_logic;                                        --              .write
		channel_1_read         : out std_logic;                                        --              .read
		channel_1_readdata     : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		channel_1_writedata    : out std_logic_vector(31 downto 0);                    --              .writedata
		channel_1_waitrequest  : in  std_logic                     := '0';             --              .waitrequest
		channel_10_address     : out std_logic_vector(15 downto 0);                    --    channel_10.address
		channel_10_write       : out std_logic;                                        --              .write
		channel_10_read        : out std_logic;                                        --              .read
		channel_10_readdata    : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		channel_10_writedata   : out std_logic_vector(31 downto 0);                    --              .writedata
		channel_10_waitrequest : in  std_logic                     := '0';             --              .waitrequest
		channel_11_address     : out std_logic_vector(15 downto 0);                    --    channel_11.address
		channel_11_write       : out std_logic;                                        --              .write
		channel_11_read        : out std_logic;                                        --              .read
		channel_11_readdata    : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		channel_11_writedata   : out std_logic_vector(31 downto 0);                    --              .writedata
		channel_11_waitrequest : in  std_logic                     := '0';             --              .waitrequest
		channel_2_address      : out std_logic_vector(15 downto 0);                    --     channel_2.address
		channel_2_write        : out std_logic;                                        --              .write
		channel_2_read         : out std_logic;                                        --              .read
		channel_2_readdata     : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		channel_2_writedata    : out std_logic_vector(31 downto 0);                    --              .writedata
		channel_2_waitrequest  : in  std_logic                     := '0';             --              .waitrequest
		channel_3_address      : out std_logic_vector(15 downto 0);                    --     channel_3.address
		channel_3_write        : out std_logic;                                        --              .write
		channel_3_read         : out std_logic;                                        --              .read
		channel_3_readdata     : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		channel_3_writedata    : out std_logic_vector(31 downto 0);                    --              .writedata
		channel_3_waitrequest  : in  std_logic                     := '0';             --              .waitrequest
		channel_4_address      : out std_logic_vector(15 downto 0);                    --     channel_4.address
		channel_4_write        : out std_logic;                                        --              .write
		channel_4_read         : out std_logic;                                        --              .read
		channel_4_readdata     : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		channel_4_writedata    : out std_logic_vector(31 downto 0);                    --              .writedata
		channel_4_waitrequest  : in  std_logic                     := '0';             --              .waitrequest
		channel_5_address      : out std_logic_vector(15 downto 0);                    --     channel_5.address
		channel_5_write        : out std_logic;                                        --              .write
		channel_5_read         : out std_logic;                                        --              .read
		channel_5_readdata     : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		channel_5_writedata    : out std_logic_vector(31 downto 0);                    --              .writedata
		channel_5_waitrequest  : in  std_logic                     := '0';             --              .waitrequest
		channel_6_address      : out std_logic_vector(15 downto 0);                    --     channel_6.address
		channel_6_write        : out std_logic;                                        --              .write
		channel_6_read         : out std_logic;                                        --              .read
		channel_6_readdata     : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		channel_6_writedata    : out std_logic_vector(31 downto 0);                    --              .writedata
		channel_6_waitrequest  : in  std_logic                     := '0';             --              .waitrequest
		channel_7_address      : out std_logic_vector(15 downto 0);                    --     channel_7.address
		channel_7_write        : out std_logic;                                        --              .write
		channel_7_read         : out std_logic;                                        --              .read
		channel_7_readdata     : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		channel_7_writedata    : out std_logic_vector(31 downto 0);                    --              .writedata
		channel_7_waitrequest  : in  std_logic                     := '0';             --              .waitrequest
		channel_8_address      : out std_logic_vector(15 downto 0);                    --     channel_8.address
		channel_8_write        : out std_logic;                                        --              .write
		channel_8_read         : out std_logic;                                        --              .read
		channel_8_readdata     : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		channel_8_writedata    : out std_logic_vector(31 downto 0);                    --              .writedata
		channel_8_waitrequest  : in  std_logic                     := '0';             --              .waitrequest
		channel_9_address      : out std_logic_vector(15 downto 0);                    --     channel_9.address
		channel_9_write        : out std_logic;                                        --              .write
		channel_9_read         : out std_logic;                                        --              .read
		channel_9_readdata     : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		channel_9_writedata    : out std_logic_vector(31 downto 0);                    --              .writedata
		channel_9_waitrequest  : in  std_logic                     := '0';             --              .waitrequest
		csr_clk_clk            : in  std_logic                     := '0';             --       csr_clk.clk
		csr_clk_reset_reset_n  : in  std_logic                     := '0';             -- csr_clk_reset.reset_n
		slave_address          : in  std_logic_vector(19 downto 0) := (others => '0'); --         slave.address
		slave_waitrequest      : out std_logic;                                        --              .waitrequest
		slave_read             : in  std_logic                     := '0';             --              .read
		slave_readdata         : out std_logic_vector(31 downto 0);                    --              .readdata
		slave_write            : in  std_logic                     := '0';             --              .write
		slave_writedata        : in  std_logic_vector(31 downto 0) := (others => '0')  --              .writedata
	);
end entity address_decoder_multi_channel;

architecture rtl of address_decoder_multi_channel is
	component address_decoder_multi_channel_channel_0_cmp is
		port (
			av_address        : out std_logic_vector(15 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_channel_0_cmp;

	component address_decoder_multi_channel_channel_1_cmp is
		port (
			av_address        : out std_logic_vector(15 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_channel_1_cmp;

	component address_decoder_multi_channel_channel_10_cmp is
		port (
			av_address        : out std_logic_vector(15 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_channel_10_cmp;

	component address_decoder_multi_channel_channel_11_cmp is
		port (
			av_address        : out std_logic_vector(15 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_channel_11_cmp;

	component address_decoder_multi_channel_channel_2_cmp is
		port (
			av_address        : out std_logic_vector(15 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_channel_2_cmp;

	component address_decoder_multi_channel_channel_3_cmp is
		port (
			av_address        : out std_logic_vector(15 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_channel_3_cmp;

	component address_decoder_multi_channel_channel_4_cmp is
		port (
			av_address        : out std_logic_vector(15 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_channel_4_cmp;

	component address_decoder_multi_channel_channel_5_cmp is
		port (
			av_address        : out std_logic_vector(15 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_channel_5_cmp;

	component address_decoder_multi_channel_channel_6_cmp is
		port (
			av_address        : out std_logic_vector(15 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_channel_6_cmp;

	component address_decoder_multi_channel_channel_7_cmp is
		port (
			av_address        : out std_logic_vector(15 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_channel_7_cmp;

	component address_decoder_multi_channel_channel_8_cmp is
		port (
			av_address        : out std_logic_vector(15 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_channel_8_cmp;

	component address_decoder_multi_channel_channel_9_cmp is
		port (
			av_address        : out std_logic_vector(15 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_channel_9_cmp;

	component address_decoder_multi_channel_csr_clk_cmp is
		port (
			clk_out     : out std_logic;        -- clk
			in_clk      : in  std_logic := 'X'; -- clk
			reset_n     : in  std_logic := 'X'; -- reset_n
			reset_n_out : out std_logic         -- reset_n
		);
	end component address_decoder_multi_channel_csr_clk_cmp;

	component address_decoder_multi_channel_master_cmp is
		port (
			av_address        : in  std_logic_vector(19 downto 0) := (others => 'X'); -- address
			av_waitrequest    : out std_logic;                                        -- waitrequest
			av_read           : in  std_logic                     := 'X';             -- read
			av_readdata       : out std_logic_vector(31 downto 0);                    -- readdata
			av_write          : in  std_logic                     := 'X';             -- write
			av_writedata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_address       : out std_logic_vector(31 downto 0);                    -- address
			uav_burstcount    : out std_logic_vector(2 downto 0);                     -- burstcount
			uav_read          : out std_logic;                                        -- read
			uav_write         : out std_logic;                                        -- write
			uav_waitrequest   : in  std_logic                     := 'X';             -- waitrequest
			uav_readdatavalid : in  std_logic                     := 'X';             -- readdatavalid
			uav_byteenable    : out std_logic_vector(3 downto 0);                     -- byteenable
			uav_readdata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			uav_writedata     : out std_logic_vector(31 downto 0);                    -- writedata
			uav_lock          : out std_logic;                                        -- lock
			uav_debugaccess   : out std_logic;                                        -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_multi_channel_master_cmp;

	component address_decoder_multi_channel_altera_mm_interconnect_191_yxycpgi_cmp is
		port (
			master_avalon_universal_master_0_address          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- address
			master_avalon_universal_master_0_waitrequest      : out std_logic;                                        -- waitrequest
			master_avalon_universal_master_0_burstcount       : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			master_avalon_universal_master_0_byteenable       : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			master_avalon_universal_master_0_read             : in  std_logic                     := 'X';             -- read
			master_avalon_universal_master_0_readdata         : out std_logic_vector(31 downto 0);                    -- readdata
			master_avalon_universal_master_0_readdatavalid    : out std_logic;                                        -- readdatavalid
			master_avalon_universal_master_0_write            : in  std_logic                     := 'X';             -- write
			master_avalon_universal_master_0_writedata        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			master_avalon_universal_master_0_lock             : in  std_logic                     := 'X';             -- lock
			master_avalon_universal_master_0_debugaccess      : in  std_logic                     := 'X';             -- debugaccess
			channel_1_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    -- address
			channel_1_avalon_universal_slave_0_write          : out std_logic;                                        -- write
			channel_1_avalon_universal_slave_0_read           : out std_logic;                                        -- read
			channel_1_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			channel_1_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			channel_1_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     -- burstcount
			channel_1_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     -- byteenable
			channel_1_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := 'X';             -- readdatavalid
			channel_1_avalon_universal_slave_0_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			channel_1_avalon_universal_slave_0_lock           : out std_logic;                                        -- lock
			channel_1_avalon_universal_slave_0_debugaccess    : out std_logic;                                        -- debugaccess
			channel_0_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    -- address
			channel_0_avalon_universal_slave_0_write          : out std_logic;                                        -- write
			channel_0_avalon_universal_slave_0_read           : out std_logic;                                        -- read
			channel_0_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			channel_0_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			channel_0_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     -- burstcount
			channel_0_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     -- byteenable
			channel_0_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := 'X';             -- readdatavalid
			channel_0_avalon_universal_slave_0_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			channel_0_avalon_universal_slave_0_lock           : out std_logic;                                        -- lock
			channel_0_avalon_universal_slave_0_debugaccess    : out std_logic;                                        -- debugaccess
			channel_2_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    -- address
			channel_2_avalon_universal_slave_0_write          : out std_logic;                                        -- write
			channel_2_avalon_universal_slave_0_read           : out std_logic;                                        -- read
			channel_2_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			channel_2_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			channel_2_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     -- burstcount
			channel_2_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     -- byteenable
			channel_2_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := 'X';             -- readdatavalid
			channel_2_avalon_universal_slave_0_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			channel_2_avalon_universal_slave_0_lock           : out std_logic;                                        -- lock
			channel_2_avalon_universal_slave_0_debugaccess    : out std_logic;                                        -- debugaccess
			channel_3_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    -- address
			channel_3_avalon_universal_slave_0_write          : out std_logic;                                        -- write
			channel_3_avalon_universal_slave_0_read           : out std_logic;                                        -- read
			channel_3_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			channel_3_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			channel_3_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     -- burstcount
			channel_3_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     -- byteenable
			channel_3_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := 'X';             -- readdatavalid
			channel_3_avalon_universal_slave_0_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			channel_3_avalon_universal_slave_0_lock           : out std_logic;                                        -- lock
			channel_3_avalon_universal_slave_0_debugaccess    : out std_logic;                                        -- debugaccess
			channel_4_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    -- address
			channel_4_avalon_universal_slave_0_write          : out std_logic;                                        -- write
			channel_4_avalon_universal_slave_0_read           : out std_logic;                                        -- read
			channel_4_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			channel_4_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			channel_4_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     -- burstcount
			channel_4_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     -- byteenable
			channel_4_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := 'X';             -- readdatavalid
			channel_4_avalon_universal_slave_0_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			channel_4_avalon_universal_slave_0_lock           : out std_logic;                                        -- lock
			channel_4_avalon_universal_slave_0_debugaccess    : out std_logic;                                        -- debugaccess
			channel_5_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    -- address
			channel_5_avalon_universal_slave_0_write          : out std_logic;                                        -- write
			channel_5_avalon_universal_slave_0_read           : out std_logic;                                        -- read
			channel_5_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			channel_5_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			channel_5_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     -- burstcount
			channel_5_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     -- byteenable
			channel_5_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := 'X';             -- readdatavalid
			channel_5_avalon_universal_slave_0_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			channel_5_avalon_universal_slave_0_lock           : out std_logic;                                        -- lock
			channel_5_avalon_universal_slave_0_debugaccess    : out std_logic;                                        -- debugaccess
			channel_6_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    -- address
			channel_6_avalon_universal_slave_0_write          : out std_logic;                                        -- write
			channel_6_avalon_universal_slave_0_read           : out std_logic;                                        -- read
			channel_6_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			channel_6_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			channel_6_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     -- burstcount
			channel_6_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     -- byteenable
			channel_6_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := 'X';             -- readdatavalid
			channel_6_avalon_universal_slave_0_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			channel_6_avalon_universal_slave_0_lock           : out std_logic;                                        -- lock
			channel_6_avalon_universal_slave_0_debugaccess    : out std_logic;                                        -- debugaccess
			channel_7_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    -- address
			channel_7_avalon_universal_slave_0_write          : out std_logic;                                        -- write
			channel_7_avalon_universal_slave_0_read           : out std_logic;                                        -- read
			channel_7_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			channel_7_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			channel_7_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     -- burstcount
			channel_7_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     -- byteenable
			channel_7_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := 'X';             -- readdatavalid
			channel_7_avalon_universal_slave_0_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			channel_7_avalon_universal_slave_0_lock           : out std_logic;                                        -- lock
			channel_7_avalon_universal_slave_0_debugaccess    : out std_logic;                                        -- debugaccess
			channel_8_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    -- address
			channel_8_avalon_universal_slave_0_write          : out std_logic;                                        -- write
			channel_8_avalon_universal_slave_0_read           : out std_logic;                                        -- read
			channel_8_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			channel_8_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			channel_8_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     -- burstcount
			channel_8_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     -- byteenable
			channel_8_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := 'X';             -- readdatavalid
			channel_8_avalon_universal_slave_0_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			channel_8_avalon_universal_slave_0_lock           : out std_logic;                                        -- lock
			channel_8_avalon_universal_slave_0_debugaccess    : out std_logic;                                        -- debugaccess
			channel_9_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    -- address
			channel_9_avalon_universal_slave_0_write          : out std_logic;                                        -- write
			channel_9_avalon_universal_slave_0_read           : out std_logic;                                        -- read
			channel_9_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			channel_9_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			channel_9_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     -- burstcount
			channel_9_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     -- byteenable
			channel_9_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := 'X';             -- readdatavalid
			channel_9_avalon_universal_slave_0_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			channel_9_avalon_universal_slave_0_lock           : out std_logic;                                        -- lock
			channel_9_avalon_universal_slave_0_debugaccess    : out std_logic;                                        -- debugaccess
			channel_10_avalon_universal_slave_0_address       : out std_logic_vector(15 downto 0);                    -- address
			channel_10_avalon_universal_slave_0_write         : out std_logic;                                        -- write
			channel_10_avalon_universal_slave_0_read          : out std_logic;                                        -- read
			channel_10_avalon_universal_slave_0_readdata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			channel_10_avalon_universal_slave_0_writedata     : out std_logic_vector(31 downto 0);                    -- writedata
			channel_10_avalon_universal_slave_0_burstcount    : out std_logic_vector(2 downto 0);                     -- burstcount
			channel_10_avalon_universal_slave_0_byteenable    : out std_logic_vector(3 downto 0);                     -- byteenable
			channel_10_avalon_universal_slave_0_readdatavalid : in  std_logic                     := 'X';             -- readdatavalid
			channel_10_avalon_universal_slave_0_waitrequest   : in  std_logic                     := 'X';             -- waitrequest
			channel_10_avalon_universal_slave_0_lock          : out std_logic;                                        -- lock
			channel_10_avalon_universal_slave_0_debugaccess   : out std_logic;                                        -- debugaccess
			channel_11_avalon_universal_slave_0_address       : out std_logic_vector(15 downto 0);                    -- address
			channel_11_avalon_universal_slave_0_write         : out std_logic;                                        -- write
			channel_11_avalon_universal_slave_0_read          : out std_logic;                                        -- read
			channel_11_avalon_universal_slave_0_readdata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			channel_11_avalon_universal_slave_0_writedata     : out std_logic_vector(31 downto 0);                    -- writedata
			channel_11_avalon_universal_slave_0_burstcount    : out std_logic_vector(2 downto 0);                     -- burstcount
			channel_11_avalon_universal_slave_0_byteenable    : out std_logic_vector(3 downto 0);                     -- byteenable
			channel_11_avalon_universal_slave_0_readdatavalid : in  std_logic                     := 'X';             -- readdatavalid
			channel_11_avalon_universal_slave_0_waitrequest   : in  std_logic                     := 'X';             -- waitrequest
			channel_11_avalon_universal_slave_0_lock          : out std_logic;                                        -- lock
			channel_11_avalon_universal_slave_0_debugaccess   : out std_logic;                                        -- debugaccess
			master_reset_reset_bridge_in_reset_reset          : in  std_logic                     := 'X';             -- reset
			csr_clk_clk_clk                                   : in  std_logic                     := 'X'              -- clk
		);
	end component address_decoder_multi_channel_altera_mm_interconnect_191_yxycpgi_cmp;

	component altera_reset_controller_cmp is
		generic (
			NUM_RESET_INPUTS          : integer := 6;
			OUTPUT_RESET_SYNC_EDGES   : string  := "deassert";
			SYNC_DEPTH                : integer := 2;
			RESET_REQUEST_PRESENT     : integer := 0;
			RESET_REQ_WAIT_TIME       : integer := 1;
			MIN_RST_ASSERTION_TIME    : integer := 3;
			RESET_REQ_EARLY_DSRT_TIME : integer := 1;
			USE_RESET_REQUEST_IN0     : integer := 0;
			USE_RESET_REQUEST_IN1     : integer := 0;
			USE_RESET_REQUEST_IN2     : integer := 0;
			USE_RESET_REQUEST_IN3     : integer := 0;
			USE_RESET_REQUEST_IN4     : integer := 0;
			USE_RESET_REQUEST_IN5     : integer := 0;
			USE_RESET_REQUEST_IN6     : integer := 0;
			USE_RESET_REQUEST_IN7     : integer := 0;
			USE_RESET_REQUEST_IN8     : integer := 0;
			USE_RESET_REQUEST_IN9     : integer := 0;
			USE_RESET_REQUEST_IN10    : integer := 0;
			USE_RESET_REQUEST_IN11    : integer := 0;
			USE_RESET_REQUEST_IN12    : integer := 0;
			USE_RESET_REQUEST_IN13    : integer := 0;
			USE_RESET_REQUEST_IN14    : integer := 0;
			USE_RESET_REQUEST_IN15    : integer := 0;
			ADAPT_RESET_REQUEST       : integer := 0
		);
		port (
			reset_in0      : in  std_logic := 'X'; -- reset
			clk            : in  std_logic := 'X'; -- clk
			reset_out      : out std_logic;        -- reset
			reset_req      : out std_logic;        -- reset_req
			reset_req_in0  : in  std_logic := 'X'; -- reset_req
			reset_in1      : in  std_logic := 'X'; -- reset
			reset_req_in1  : in  std_logic := 'X'; -- reset_req
			reset_in2      : in  std_logic := 'X'; -- reset
			reset_req_in2  : in  std_logic := 'X'; -- reset_req
			reset_in3      : in  std_logic := 'X'; -- reset
			reset_req_in3  : in  std_logic := 'X'; -- reset_req
			reset_in4      : in  std_logic := 'X'; -- reset
			reset_req_in4  : in  std_logic := 'X'; -- reset_req
			reset_in5      : in  std_logic := 'X'; -- reset
			reset_req_in5  : in  std_logic := 'X'; -- reset_req
			reset_in6      : in  std_logic := 'X'; -- reset
			reset_req_in6  : in  std_logic := 'X'; -- reset_req
			reset_in7      : in  std_logic := 'X'; -- reset
			reset_req_in7  : in  std_logic := 'X'; -- reset_req
			reset_in8      : in  std_logic := 'X'; -- reset
			reset_req_in8  : in  std_logic := 'X'; -- reset_req
			reset_in9      : in  std_logic := 'X'; -- reset
			reset_req_in9  : in  std_logic := 'X'; -- reset_req
			reset_in10     : in  std_logic := 'X'; -- reset
			reset_req_in10 : in  std_logic := 'X'; -- reset_req
			reset_in11     : in  std_logic := 'X'; -- reset
			reset_req_in11 : in  std_logic := 'X'; -- reset_req
			reset_in12     : in  std_logic := 'X'; -- reset
			reset_req_in12 : in  std_logic := 'X'; -- reset_req
			reset_in13     : in  std_logic := 'X'; -- reset
			reset_req_in13 : in  std_logic := 'X'; -- reset_req
			reset_in14     : in  std_logic := 'X'; -- reset
			reset_req_in14 : in  std_logic := 'X'; -- reset_req
			reset_in15     : in  std_logic := 'X'; -- reset
			reset_req_in15 : in  std_logic := 'X'  -- reset_req
		);
	end component altera_reset_controller_cmp;

	signal csr_clk_clk_clk                                                     : std_logic;                     -- csr_clk:clk_out -> [channel_0:clk, channel_10:clk, channel_11:clk, channel_1:clk, channel_2:clk, channel_3:clk, channel_4:clk, channel_5:clk, channel_6:clk, channel_7:clk, channel_8:clk, channel_9:clk, master:clk, mm_interconnect_0:csr_clk_clk_clk, rst_controller:clk]
	signal master_avalon_universal_master_0_waitrequest                        : std_logic;                     -- mm_interconnect_0:master_avalon_universal_master_0_waitrequest -> master:uav_waitrequest
	signal master_avalon_universal_master_0_readdata                           : std_logic_vector(31 downto 0); -- mm_interconnect_0:master_avalon_universal_master_0_readdata -> master:uav_readdata
	signal master_avalon_universal_master_0_debugaccess                        : std_logic;                     -- master:uav_debugaccess -> mm_interconnect_0:master_avalon_universal_master_0_debugaccess
	signal master_avalon_universal_master_0_address                            : std_logic_vector(31 downto 0); -- master:uav_address -> mm_interconnect_0:master_avalon_universal_master_0_address
	signal master_avalon_universal_master_0_read                               : std_logic;                     -- master:uav_read -> mm_interconnect_0:master_avalon_universal_master_0_read
	signal master_avalon_universal_master_0_byteenable                         : std_logic_vector(3 downto 0);  -- master:uav_byteenable -> mm_interconnect_0:master_avalon_universal_master_0_byteenable
	signal master_avalon_universal_master_0_readdatavalid                      : std_logic;                     -- mm_interconnect_0:master_avalon_universal_master_0_readdatavalid -> master:uav_readdatavalid
	signal master_avalon_universal_master_0_lock                               : std_logic;                     -- master:uav_lock -> mm_interconnect_0:master_avalon_universal_master_0_lock
	signal master_avalon_universal_master_0_write                              : std_logic;                     -- master:uav_write -> mm_interconnect_0:master_avalon_universal_master_0_write
	signal master_avalon_universal_master_0_writedata                          : std_logic_vector(31 downto 0); -- master:uav_writedata -> mm_interconnect_0:master_avalon_universal_master_0_writedata
	signal master_avalon_universal_master_0_burstcount                         : std_logic_vector(2 downto 0);  -- master:uav_burstcount -> mm_interconnect_0:master_avalon_universal_master_0_burstcount
	signal mm_interconnect_0_channel_1_avalon_universal_slave_0_readdata       : std_logic_vector(31 downto 0); -- channel_1:uav_readdata -> mm_interconnect_0:channel_1_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_channel_1_avalon_universal_slave_0_waitrequest    : std_logic;                     -- channel_1:uav_waitrequest -> mm_interconnect_0:channel_1_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_channel_1_avalon_universal_slave_0_debugaccess    : std_logic;                     -- mm_interconnect_0:channel_1_avalon_universal_slave_0_debugaccess -> channel_1:uav_debugaccess
	signal mm_interconnect_0_channel_1_avalon_universal_slave_0_address        : std_logic_vector(15 downto 0); -- mm_interconnect_0:channel_1_avalon_universal_slave_0_address -> channel_1:uav_address
	signal mm_interconnect_0_channel_1_avalon_universal_slave_0_read           : std_logic;                     -- mm_interconnect_0:channel_1_avalon_universal_slave_0_read -> channel_1:uav_read
	signal mm_interconnect_0_channel_1_avalon_universal_slave_0_byteenable     : std_logic_vector(3 downto 0);  -- mm_interconnect_0:channel_1_avalon_universal_slave_0_byteenable -> channel_1:uav_byteenable
	signal mm_interconnect_0_channel_1_avalon_universal_slave_0_readdatavalid  : std_logic;                     -- channel_1:uav_readdatavalid -> mm_interconnect_0:channel_1_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_channel_1_avalon_universal_slave_0_lock           : std_logic;                     -- mm_interconnect_0:channel_1_avalon_universal_slave_0_lock -> channel_1:uav_lock
	signal mm_interconnect_0_channel_1_avalon_universal_slave_0_write          : std_logic;                     -- mm_interconnect_0:channel_1_avalon_universal_slave_0_write -> channel_1:uav_write
	signal mm_interconnect_0_channel_1_avalon_universal_slave_0_writedata      : std_logic_vector(31 downto 0); -- mm_interconnect_0:channel_1_avalon_universal_slave_0_writedata -> channel_1:uav_writedata
	signal mm_interconnect_0_channel_1_avalon_universal_slave_0_burstcount     : std_logic_vector(2 downto 0);  -- mm_interconnect_0:channel_1_avalon_universal_slave_0_burstcount -> channel_1:uav_burstcount
	signal mm_interconnect_0_channel_0_avalon_universal_slave_0_readdata       : std_logic_vector(31 downto 0); -- channel_0:uav_readdata -> mm_interconnect_0:channel_0_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_channel_0_avalon_universal_slave_0_waitrequest    : std_logic;                     -- channel_0:uav_waitrequest -> mm_interconnect_0:channel_0_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_channel_0_avalon_universal_slave_0_debugaccess    : std_logic;                     -- mm_interconnect_0:channel_0_avalon_universal_slave_0_debugaccess -> channel_0:uav_debugaccess
	signal mm_interconnect_0_channel_0_avalon_universal_slave_0_address        : std_logic_vector(15 downto 0); -- mm_interconnect_0:channel_0_avalon_universal_slave_0_address -> channel_0:uav_address
	signal mm_interconnect_0_channel_0_avalon_universal_slave_0_read           : std_logic;                     -- mm_interconnect_0:channel_0_avalon_universal_slave_0_read -> channel_0:uav_read
	signal mm_interconnect_0_channel_0_avalon_universal_slave_0_byteenable     : std_logic_vector(3 downto 0);  -- mm_interconnect_0:channel_0_avalon_universal_slave_0_byteenable -> channel_0:uav_byteenable
	signal mm_interconnect_0_channel_0_avalon_universal_slave_0_readdatavalid  : std_logic;                     -- channel_0:uav_readdatavalid -> mm_interconnect_0:channel_0_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_channel_0_avalon_universal_slave_0_lock           : std_logic;                     -- mm_interconnect_0:channel_0_avalon_universal_slave_0_lock -> channel_0:uav_lock
	signal mm_interconnect_0_channel_0_avalon_universal_slave_0_write          : std_logic;                     -- mm_interconnect_0:channel_0_avalon_universal_slave_0_write -> channel_0:uav_write
	signal mm_interconnect_0_channel_0_avalon_universal_slave_0_writedata      : std_logic_vector(31 downto 0); -- mm_interconnect_0:channel_0_avalon_universal_slave_0_writedata -> channel_0:uav_writedata
	signal mm_interconnect_0_channel_0_avalon_universal_slave_0_burstcount     : std_logic_vector(2 downto 0);  -- mm_interconnect_0:channel_0_avalon_universal_slave_0_burstcount -> channel_0:uav_burstcount
	signal mm_interconnect_0_channel_2_avalon_universal_slave_0_readdata       : std_logic_vector(31 downto 0); -- channel_2:uav_readdata -> mm_interconnect_0:channel_2_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_channel_2_avalon_universal_slave_0_waitrequest    : std_logic;                     -- channel_2:uav_waitrequest -> mm_interconnect_0:channel_2_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_channel_2_avalon_universal_slave_0_debugaccess    : std_logic;                     -- mm_interconnect_0:channel_2_avalon_universal_slave_0_debugaccess -> channel_2:uav_debugaccess
	signal mm_interconnect_0_channel_2_avalon_universal_slave_0_address        : std_logic_vector(15 downto 0); -- mm_interconnect_0:channel_2_avalon_universal_slave_0_address -> channel_2:uav_address
	signal mm_interconnect_0_channel_2_avalon_universal_slave_0_read           : std_logic;                     -- mm_interconnect_0:channel_2_avalon_universal_slave_0_read -> channel_2:uav_read
	signal mm_interconnect_0_channel_2_avalon_universal_slave_0_byteenable     : std_logic_vector(3 downto 0);  -- mm_interconnect_0:channel_2_avalon_universal_slave_0_byteenable -> channel_2:uav_byteenable
	signal mm_interconnect_0_channel_2_avalon_universal_slave_0_readdatavalid  : std_logic;                     -- channel_2:uav_readdatavalid -> mm_interconnect_0:channel_2_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_channel_2_avalon_universal_slave_0_lock           : std_logic;                     -- mm_interconnect_0:channel_2_avalon_universal_slave_0_lock -> channel_2:uav_lock
	signal mm_interconnect_0_channel_2_avalon_universal_slave_0_write          : std_logic;                     -- mm_interconnect_0:channel_2_avalon_universal_slave_0_write -> channel_2:uav_write
	signal mm_interconnect_0_channel_2_avalon_universal_slave_0_writedata      : std_logic_vector(31 downto 0); -- mm_interconnect_0:channel_2_avalon_universal_slave_0_writedata -> channel_2:uav_writedata
	signal mm_interconnect_0_channel_2_avalon_universal_slave_0_burstcount     : std_logic_vector(2 downto 0);  -- mm_interconnect_0:channel_2_avalon_universal_slave_0_burstcount -> channel_2:uav_burstcount
	signal mm_interconnect_0_channel_3_avalon_universal_slave_0_readdata       : std_logic_vector(31 downto 0); -- channel_3:uav_readdata -> mm_interconnect_0:channel_3_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_channel_3_avalon_universal_slave_0_waitrequest    : std_logic;                     -- channel_3:uav_waitrequest -> mm_interconnect_0:channel_3_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_channel_3_avalon_universal_slave_0_debugaccess    : std_logic;                     -- mm_interconnect_0:channel_3_avalon_universal_slave_0_debugaccess -> channel_3:uav_debugaccess
	signal mm_interconnect_0_channel_3_avalon_universal_slave_0_address        : std_logic_vector(15 downto 0); -- mm_interconnect_0:channel_3_avalon_universal_slave_0_address -> channel_3:uav_address
	signal mm_interconnect_0_channel_3_avalon_universal_slave_0_read           : std_logic;                     -- mm_interconnect_0:channel_3_avalon_universal_slave_0_read -> channel_3:uav_read
	signal mm_interconnect_0_channel_3_avalon_universal_slave_0_byteenable     : std_logic_vector(3 downto 0);  -- mm_interconnect_0:channel_3_avalon_universal_slave_0_byteenable -> channel_3:uav_byteenable
	signal mm_interconnect_0_channel_3_avalon_universal_slave_0_readdatavalid  : std_logic;                     -- channel_3:uav_readdatavalid -> mm_interconnect_0:channel_3_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_channel_3_avalon_universal_slave_0_lock           : std_logic;                     -- mm_interconnect_0:channel_3_avalon_universal_slave_0_lock -> channel_3:uav_lock
	signal mm_interconnect_0_channel_3_avalon_universal_slave_0_write          : std_logic;                     -- mm_interconnect_0:channel_3_avalon_universal_slave_0_write -> channel_3:uav_write
	signal mm_interconnect_0_channel_3_avalon_universal_slave_0_writedata      : std_logic_vector(31 downto 0); -- mm_interconnect_0:channel_3_avalon_universal_slave_0_writedata -> channel_3:uav_writedata
	signal mm_interconnect_0_channel_3_avalon_universal_slave_0_burstcount     : std_logic_vector(2 downto 0);  -- mm_interconnect_0:channel_3_avalon_universal_slave_0_burstcount -> channel_3:uav_burstcount
	signal mm_interconnect_0_channel_4_avalon_universal_slave_0_readdata       : std_logic_vector(31 downto 0); -- channel_4:uav_readdata -> mm_interconnect_0:channel_4_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_channel_4_avalon_universal_slave_0_waitrequest    : std_logic;                     -- channel_4:uav_waitrequest -> mm_interconnect_0:channel_4_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_channel_4_avalon_universal_slave_0_debugaccess    : std_logic;                     -- mm_interconnect_0:channel_4_avalon_universal_slave_0_debugaccess -> channel_4:uav_debugaccess
	signal mm_interconnect_0_channel_4_avalon_universal_slave_0_address        : std_logic_vector(15 downto 0); -- mm_interconnect_0:channel_4_avalon_universal_slave_0_address -> channel_4:uav_address
	signal mm_interconnect_0_channel_4_avalon_universal_slave_0_read           : std_logic;                     -- mm_interconnect_0:channel_4_avalon_universal_slave_0_read -> channel_4:uav_read
	signal mm_interconnect_0_channel_4_avalon_universal_slave_0_byteenable     : std_logic_vector(3 downto 0);  -- mm_interconnect_0:channel_4_avalon_universal_slave_0_byteenable -> channel_4:uav_byteenable
	signal mm_interconnect_0_channel_4_avalon_universal_slave_0_readdatavalid  : std_logic;                     -- channel_4:uav_readdatavalid -> mm_interconnect_0:channel_4_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_channel_4_avalon_universal_slave_0_lock           : std_logic;                     -- mm_interconnect_0:channel_4_avalon_universal_slave_0_lock -> channel_4:uav_lock
	signal mm_interconnect_0_channel_4_avalon_universal_slave_0_write          : std_logic;                     -- mm_interconnect_0:channel_4_avalon_universal_slave_0_write -> channel_4:uav_write
	signal mm_interconnect_0_channel_4_avalon_universal_slave_0_writedata      : std_logic_vector(31 downto 0); -- mm_interconnect_0:channel_4_avalon_universal_slave_0_writedata -> channel_4:uav_writedata
	signal mm_interconnect_0_channel_4_avalon_universal_slave_0_burstcount     : std_logic_vector(2 downto 0);  -- mm_interconnect_0:channel_4_avalon_universal_slave_0_burstcount -> channel_4:uav_burstcount
	signal mm_interconnect_0_channel_5_avalon_universal_slave_0_readdata       : std_logic_vector(31 downto 0); -- channel_5:uav_readdata -> mm_interconnect_0:channel_5_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_channel_5_avalon_universal_slave_0_waitrequest    : std_logic;                     -- channel_5:uav_waitrequest -> mm_interconnect_0:channel_5_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_channel_5_avalon_universal_slave_0_debugaccess    : std_logic;                     -- mm_interconnect_0:channel_5_avalon_universal_slave_0_debugaccess -> channel_5:uav_debugaccess
	signal mm_interconnect_0_channel_5_avalon_universal_slave_0_address        : std_logic_vector(15 downto 0); -- mm_interconnect_0:channel_5_avalon_universal_slave_0_address -> channel_5:uav_address
	signal mm_interconnect_0_channel_5_avalon_universal_slave_0_read           : std_logic;                     -- mm_interconnect_0:channel_5_avalon_universal_slave_0_read -> channel_5:uav_read
	signal mm_interconnect_0_channel_5_avalon_universal_slave_0_byteenable     : std_logic_vector(3 downto 0);  -- mm_interconnect_0:channel_5_avalon_universal_slave_0_byteenable -> channel_5:uav_byteenable
	signal mm_interconnect_0_channel_5_avalon_universal_slave_0_readdatavalid  : std_logic;                     -- channel_5:uav_readdatavalid -> mm_interconnect_0:channel_5_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_channel_5_avalon_universal_slave_0_lock           : std_logic;                     -- mm_interconnect_0:channel_5_avalon_universal_slave_0_lock -> channel_5:uav_lock
	signal mm_interconnect_0_channel_5_avalon_universal_slave_0_write          : std_logic;                     -- mm_interconnect_0:channel_5_avalon_universal_slave_0_write -> channel_5:uav_write
	signal mm_interconnect_0_channel_5_avalon_universal_slave_0_writedata      : std_logic_vector(31 downto 0); -- mm_interconnect_0:channel_5_avalon_universal_slave_0_writedata -> channel_5:uav_writedata
	signal mm_interconnect_0_channel_5_avalon_universal_slave_0_burstcount     : std_logic_vector(2 downto 0);  -- mm_interconnect_0:channel_5_avalon_universal_slave_0_burstcount -> channel_5:uav_burstcount
	signal mm_interconnect_0_channel_6_avalon_universal_slave_0_readdata       : std_logic_vector(31 downto 0); -- channel_6:uav_readdata -> mm_interconnect_0:channel_6_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_channel_6_avalon_universal_slave_0_waitrequest    : std_logic;                     -- channel_6:uav_waitrequest -> mm_interconnect_0:channel_6_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_channel_6_avalon_universal_slave_0_debugaccess    : std_logic;                     -- mm_interconnect_0:channel_6_avalon_universal_slave_0_debugaccess -> channel_6:uav_debugaccess
	signal mm_interconnect_0_channel_6_avalon_universal_slave_0_address        : std_logic_vector(15 downto 0); -- mm_interconnect_0:channel_6_avalon_universal_slave_0_address -> channel_6:uav_address
	signal mm_interconnect_0_channel_6_avalon_universal_slave_0_read           : std_logic;                     -- mm_interconnect_0:channel_6_avalon_universal_slave_0_read -> channel_6:uav_read
	signal mm_interconnect_0_channel_6_avalon_universal_slave_0_byteenable     : std_logic_vector(3 downto 0);  -- mm_interconnect_0:channel_6_avalon_universal_slave_0_byteenable -> channel_6:uav_byteenable
	signal mm_interconnect_0_channel_6_avalon_universal_slave_0_readdatavalid  : std_logic;                     -- channel_6:uav_readdatavalid -> mm_interconnect_0:channel_6_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_channel_6_avalon_universal_slave_0_lock           : std_logic;                     -- mm_interconnect_0:channel_6_avalon_universal_slave_0_lock -> channel_6:uav_lock
	signal mm_interconnect_0_channel_6_avalon_universal_slave_0_write          : std_logic;                     -- mm_interconnect_0:channel_6_avalon_universal_slave_0_write -> channel_6:uav_write
	signal mm_interconnect_0_channel_6_avalon_universal_slave_0_writedata      : std_logic_vector(31 downto 0); -- mm_interconnect_0:channel_6_avalon_universal_slave_0_writedata -> channel_6:uav_writedata
	signal mm_interconnect_0_channel_6_avalon_universal_slave_0_burstcount     : std_logic_vector(2 downto 0);  -- mm_interconnect_0:channel_6_avalon_universal_slave_0_burstcount -> channel_6:uav_burstcount
	signal mm_interconnect_0_channel_7_avalon_universal_slave_0_readdata       : std_logic_vector(31 downto 0); -- channel_7:uav_readdata -> mm_interconnect_0:channel_7_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_channel_7_avalon_universal_slave_0_waitrequest    : std_logic;                     -- channel_7:uav_waitrequest -> mm_interconnect_0:channel_7_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_channel_7_avalon_universal_slave_0_debugaccess    : std_logic;                     -- mm_interconnect_0:channel_7_avalon_universal_slave_0_debugaccess -> channel_7:uav_debugaccess
	signal mm_interconnect_0_channel_7_avalon_universal_slave_0_address        : std_logic_vector(15 downto 0); -- mm_interconnect_0:channel_7_avalon_universal_slave_0_address -> channel_7:uav_address
	signal mm_interconnect_0_channel_7_avalon_universal_slave_0_read           : std_logic;                     -- mm_interconnect_0:channel_7_avalon_universal_slave_0_read -> channel_7:uav_read
	signal mm_interconnect_0_channel_7_avalon_universal_slave_0_byteenable     : std_logic_vector(3 downto 0);  -- mm_interconnect_0:channel_7_avalon_universal_slave_0_byteenable -> channel_7:uav_byteenable
	signal mm_interconnect_0_channel_7_avalon_universal_slave_0_readdatavalid  : std_logic;                     -- channel_7:uav_readdatavalid -> mm_interconnect_0:channel_7_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_channel_7_avalon_universal_slave_0_lock           : std_logic;                     -- mm_interconnect_0:channel_7_avalon_universal_slave_0_lock -> channel_7:uav_lock
	signal mm_interconnect_0_channel_7_avalon_universal_slave_0_write          : std_logic;                     -- mm_interconnect_0:channel_7_avalon_universal_slave_0_write -> channel_7:uav_write
	signal mm_interconnect_0_channel_7_avalon_universal_slave_0_writedata      : std_logic_vector(31 downto 0); -- mm_interconnect_0:channel_7_avalon_universal_slave_0_writedata -> channel_7:uav_writedata
	signal mm_interconnect_0_channel_7_avalon_universal_slave_0_burstcount     : std_logic_vector(2 downto 0);  -- mm_interconnect_0:channel_7_avalon_universal_slave_0_burstcount -> channel_7:uav_burstcount
	signal mm_interconnect_0_channel_8_avalon_universal_slave_0_readdata       : std_logic_vector(31 downto 0); -- channel_8:uav_readdata -> mm_interconnect_0:channel_8_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_channel_8_avalon_universal_slave_0_waitrequest    : std_logic;                     -- channel_8:uav_waitrequest -> mm_interconnect_0:channel_8_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_channel_8_avalon_universal_slave_0_debugaccess    : std_logic;                     -- mm_interconnect_0:channel_8_avalon_universal_slave_0_debugaccess -> channel_8:uav_debugaccess
	signal mm_interconnect_0_channel_8_avalon_universal_slave_0_address        : std_logic_vector(15 downto 0); -- mm_interconnect_0:channel_8_avalon_universal_slave_0_address -> channel_8:uav_address
	signal mm_interconnect_0_channel_8_avalon_universal_slave_0_read           : std_logic;                     -- mm_interconnect_0:channel_8_avalon_universal_slave_0_read -> channel_8:uav_read
	signal mm_interconnect_0_channel_8_avalon_universal_slave_0_byteenable     : std_logic_vector(3 downto 0);  -- mm_interconnect_0:channel_8_avalon_universal_slave_0_byteenable -> channel_8:uav_byteenable
	signal mm_interconnect_0_channel_8_avalon_universal_slave_0_readdatavalid  : std_logic;                     -- channel_8:uav_readdatavalid -> mm_interconnect_0:channel_8_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_channel_8_avalon_universal_slave_0_lock           : std_logic;                     -- mm_interconnect_0:channel_8_avalon_universal_slave_0_lock -> channel_8:uav_lock
	signal mm_interconnect_0_channel_8_avalon_universal_slave_0_write          : std_logic;                     -- mm_interconnect_0:channel_8_avalon_universal_slave_0_write -> channel_8:uav_write
	signal mm_interconnect_0_channel_8_avalon_universal_slave_0_writedata      : std_logic_vector(31 downto 0); -- mm_interconnect_0:channel_8_avalon_universal_slave_0_writedata -> channel_8:uav_writedata
	signal mm_interconnect_0_channel_8_avalon_universal_slave_0_burstcount     : std_logic_vector(2 downto 0);  -- mm_interconnect_0:channel_8_avalon_universal_slave_0_burstcount -> channel_8:uav_burstcount
	signal mm_interconnect_0_channel_9_avalon_universal_slave_0_readdata       : std_logic_vector(31 downto 0); -- channel_9:uav_readdata -> mm_interconnect_0:channel_9_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_channel_9_avalon_universal_slave_0_waitrequest    : std_logic;                     -- channel_9:uav_waitrequest -> mm_interconnect_0:channel_9_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_channel_9_avalon_universal_slave_0_debugaccess    : std_logic;                     -- mm_interconnect_0:channel_9_avalon_universal_slave_0_debugaccess -> channel_9:uav_debugaccess
	signal mm_interconnect_0_channel_9_avalon_universal_slave_0_address        : std_logic_vector(15 downto 0); -- mm_interconnect_0:channel_9_avalon_universal_slave_0_address -> channel_9:uav_address
	signal mm_interconnect_0_channel_9_avalon_universal_slave_0_read           : std_logic;                     -- mm_interconnect_0:channel_9_avalon_universal_slave_0_read -> channel_9:uav_read
	signal mm_interconnect_0_channel_9_avalon_universal_slave_0_byteenable     : std_logic_vector(3 downto 0);  -- mm_interconnect_0:channel_9_avalon_universal_slave_0_byteenable -> channel_9:uav_byteenable
	signal mm_interconnect_0_channel_9_avalon_universal_slave_0_readdatavalid  : std_logic;                     -- channel_9:uav_readdatavalid -> mm_interconnect_0:channel_9_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_channel_9_avalon_universal_slave_0_lock           : std_logic;                     -- mm_interconnect_0:channel_9_avalon_universal_slave_0_lock -> channel_9:uav_lock
	signal mm_interconnect_0_channel_9_avalon_universal_slave_0_write          : std_logic;                     -- mm_interconnect_0:channel_9_avalon_universal_slave_0_write -> channel_9:uav_write
	signal mm_interconnect_0_channel_9_avalon_universal_slave_0_writedata      : std_logic_vector(31 downto 0); -- mm_interconnect_0:channel_9_avalon_universal_slave_0_writedata -> channel_9:uav_writedata
	signal mm_interconnect_0_channel_9_avalon_universal_slave_0_burstcount     : std_logic_vector(2 downto 0);  -- mm_interconnect_0:channel_9_avalon_universal_slave_0_burstcount -> channel_9:uav_burstcount
	signal mm_interconnect_0_channel_10_avalon_universal_slave_0_readdata      : std_logic_vector(31 downto 0); -- channel_10:uav_readdata -> mm_interconnect_0:channel_10_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_channel_10_avalon_universal_slave_0_waitrequest   : std_logic;                     -- channel_10:uav_waitrequest -> mm_interconnect_0:channel_10_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_channel_10_avalon_universal_slave_0_debugaccess   : std_logic;                     -- mm_interconnect_0:channel_10_avalon_universal_slave_0_debugaccess -> channel_10:uav_debugaccess
	signal mm_interconnect_0_channel_10_avalon_universal_slave_0_address       : std_logic_vector(15 downto 0); -- mm_interconnect_0:channel_10_avalon_universal_slave_0_address -> channel_10:uav_address
	signal mm_interconnect_0_channel_10_avalon_universal_slave_0_read          : std_logic;                     -- mm_interconnect_0:channel_10_avalon_universal_slave_0_read -> channel_10:uav_read
	signal mm_interconnect_0_channel_10_avalon_universal_slave_0_byteenable    : std_logic_vector(3 downto 0);  -- mm_interconnect_0:channel_10_avalon_universal_slave_0_byteenable -> channel_10:uav_byteenable
	signal mm_interconnect_0_channel_10_avalon_universal_slave_0_readdatavalid : std_logic;                     -- channel_10:uav_readdatavalid -> mm_interconnect_0:channel_10_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_channel_10_avalon_universal_slave_0_lock          : std_logic;                     -- mm_interconnect_0:channel_10_avalon_universal_slave_0_lock -> channel_10:uav_lock
	signal mm_interconnect_0_channel_10_avalon_universal_slave_0_write         : std_logic;                     -- mm_interconnect_0:channel_10_avalon_universal_slave_0_write -> channel_10:uav_write
	signal mm_interconnect_0_channel_10_avalon_universal_slave_0_writedata     : std_logic_vector(31 downto 0); -- mm_interconnect_0:channel_10_avalon_universal_slave_0_writedata -> channel_10:uav_writedata
	signal mm_interconnect_0_channel_10_avalon_universal_slave_0_burstcount    : std_logic_vector(2 downto 0);  -- mm_interconnect_0:channel_10_avalon_universal_slave_0_burstcount -> channel_10:uav_burstcount
	signal mm_interconnect_0_channel_11_avalon_universal_slave_0_readdata      : std_logic_vector(31 downto 0); -- channel_11:uav_readdata -> mm_interconnect_0:channel_11_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_channel_11_avalon_universal_slave_0_waitrequest   : std_logic;                     -- channel_11:uav_waitrequest -> mm_interconnect_0:channel_11_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_channel_11_avalon_universal_slave_0_debugaccess   : std_logic;                     -- mm_interconnect_0:channel_11_avalon_universal_slave_0_debugaccess -> channel_11:uav_debugaccess
	signal mm_interconnect_0_channel_11_avalon_universal_slave_0_address       : std_logic_vector(15 downto 0); -- mm_interconnect_0:channel_11_avalon_universal_slave_0_address -> channel_11:uav_address
	signal mm_interconnect_0_channel_11_avalon_universal_slave_0_read          : std_logic;                     -- mm_interconnect_0:channel_11_avalon_universal_slave_0_read -> channel_11:uav_read
	signal mm_interconnect_0_channel_11_avalon_universal_slave_0_byteenable    : std_logic_vector(3 downto 0);  -- mm_interconnect_0:channel_11_avalon_universal_slave_0_byteenable -> channel_11:uav_byteenable
	signal mm_interconnect_0_channel_11_avalon_universal_slave_0_readdatavalid : std_logic;                     -- channel_11:uav_readdatavalid -> mm_interconnect_0:channel_11_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_channel_11_avalon_universal_slave_0_lock          : std_logic;                     -- mm_interconnect_0:channel_11_avalon_universal_slave_0_lock -> channel_11:uav_lock
	signal mm_interconnect_0_channel_11_avalon_universal_slave_0_write         : std_logic;                     -- mm_interconnect_0:channel_11_avalon_universal_slave_0_write -> channel_11:uav_write
	signal mm_interconnect_0_channel_11_avalon_universal_slave_0_writedata     : std_logic_vector(31 downto 0); -- mm_interconnect_0:channel_11_avalon_universal_slave_0_writedata -> channel_11:uav_writedata
	signal mm_interconnect_0_channel_11_avalon_universal_slave_0_burstcount    : std_logic_vector(2 downto 0);  -- mm_interconnect_0:channel_11_avalon_universal_slave_0_burstcount -> channel_11:uav_burstcount
	signal rst_controller_reset_out_reset                                      : std_logic;                     -- rst_controller:reset_out -> [channel_0:reset, channel_10:reset, channel_11:reset, channel_1:reset, channel_2:reset, channel_3:reset, channel_4:reset, channel_5:reset, channel_6:reset, channel_7:reset, channel_8:reset, channel_9:reset, master:reset, mm_interconnect_0:master_reset_reset_bridge_in_reset_reset]
	signal csr_clk_clk_reset_reset                                             : std_logic;                     -- csr_clk:reset_n_out -> csr_clk_clk_reset_reset:in
	signal csr_clk_clk_reset_reset_ports_inv                                   : std_logic;                     -- csr_clk_clk_reset_reset:inv -> rst_controller:reset_in0

	for channel_0 : address_decoder_multi_channel_channel_0_cmp
		use entity address_decoder_multi_channel_channel_0.address_decoder_multi_channel_channel_0;
	for channel_1 : address_decoder_multi_channel_channel_1_cmp
		use entity address_decoder_multi_channel_channel_1.address_decoder_multi_channel_channel_1;
	for channel_10 : address_decoder_multi_channel_channel_10_cmp
		use entity address_decoder_multi_channel_channel_10.address_decoder_multi_channel_channel_10;
	for channel_11 : address_decoder_multi_channel_channel_11_cmp
		use entity address_decoder_multi_channel_channel_11.address_decoder_multi_channel_channel_11;
	for channel_2 : address_decoder_multi_channel_channel_2_cmp
		use entity address_decoder_multi_channel_channel_2.address_decoder_multi_channel_channel_2;
	for channel_3 : address_decoder_multi_channel_channel_3_cmp
		use entity address_decoder_multi_channel_channel_3.address_decoder_multi_channel_channel_3;
	for channel_4 : address_decoder_multi_channel_channel_4_cmp
		use entity address_decoder_multi_channel_channel_4.address_decoder_multi_channel_channel_4;
	for channel_5 : address_decoder_multi_channel_channel_5_cmp
		use entity address_decoder_multi_channel_channel_5.address_decoder_multi_channel_channel_5;
	for channel_6 : address_decoder_multi_channel_channel_6_cmp
		use entity address_decoder_multi_channel_channel_6.address_decoder_multi_channel_channel_6;
	for channel_7 : address_decoder_multi_channel_channel_7_cmp
		use entity address_decoder_multi_channel_channel_7.address_decoder_multi_channel_channel_7;
	for channel_8 : address_decoder_multi_channel_channel_8_cmp
		use entity address_decoder_multi_channel_channel_8.address_decoder_multi_channel_channel_8;
	for channel_9 : address_decoder_multi_channel_channel_9_cmp
		use entity address_decoder_multi_channel_channel_9.address_decoder_multi_channel_channel_9;
	for csr_clk : address_decoder_multi_channel_csr_clk_cmp
		use entity address_decoder_multi_channel_csr_clk.address_decoder_multi_channel_csr_clk;
	for master : address_decoder_multi_channel_master_cmp
		use entity address_decoder_multi_channel_master.address_decoder_multi_channel_master;
	for mm_interconnect_0 : address_decoder_multi_channel_altera_mm_interconnect_191_yxycpgi_cmp
		use entity altera_mm_interconnect_191.address_decoder_multi_channel_altera_mm_interconnect_191_yxycpgi;
	for rst_controller : altera_reset_controller_cmp
		use entity altera_reset_controller_191.altera_reset_controller;
begin

	channel_0 : component address_decoder_multi_channel_channel_0_cmp
		port map (
			av_address        => channel_0_address,                                                  --      avalon_anti_slave_0.address
			av_write          => channel_0_write,                                                    --                         .write
			av_read           => channel_0_read,                                                     --                         .read
			av_readdata       => channel_0_readdata,                                                 --                         .readdata
			av_writedata      => channel_0_writedata,                                                --                         .writedata
			av_waitrequest    => channel_0_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_channel_0_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_channel_0_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_channel_0_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_channel_0_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_channel_0_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_channel_0_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_channel_0_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_channel_0_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_channel_0_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_channel_0_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_channel_0_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                    --                      clk.clk
			reset             => rst_controller_reset_out_reset                                      --                    reset.reset
		);

	channel_1 : component address_decoder_multi_channel_channel_1_cmp
		port map (
			av_address        => channel_1_address,                                                  --      avalon_anti_slave_0.address
			av_write          => channel_1_write,                                                    --                         .write
			av_read           => channel_1_read,                                                     --                         .read
			av_readdata       => channel_1_readdata,                                                 --                         .readdata
			av_writedata      => channel_1_writedata,                                                --                         .writedata
			av_waitrequest    => channel_1_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_channel_1_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_channel_1_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_channel_1_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_channel_1_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_channel_1_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_channel_1_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_channel_1_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_channel_1_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_channel_1_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_channel_1_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_channel_1_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                    --                      clk.clk
			reset             => rst_controller_reset_out_reset                                      --                    reset.reset
		);

	channel_10 : component address_decoder_multi_channel_channel_10_cmp
		port map (
			av_address        => channel_10_address,                                                  --      avalon_anti_slave_0.address
			av_write          => channel_10_write,                                                    --                         .write
			av_read           => channel_10_read,                                                     --                         .read
			av_readdata       => channel_10_readdata,                                                 --                         .readdata
			av_writedata      => channel_10_writedata,                                                --                         .writedata
			av_waitrequest    => channel_10_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_channel_10_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_channel_10_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_channel_10_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_channel_10_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_channel_10_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_channel_10_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_channel_10_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_channel_10_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_channel_10_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_channel_10_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_channel_10_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                     --                      clk.clk
			reset             => rst_controller_reset_out_reset                                       --                    reset.reset
		);

	channel_11 : component address_decoder_multi_channel_channel_11_cmp
		port map (
			av_address        => channel_11_address,                                                  --      avalon_anti_slave_0.address
			av_write          => channel_11_write,                                                    --                         .write
			av_read           => channel_11_read,                                                     --                         .read
			av_readdata       => channel_11_readdata,                                                 --                         .readdata
			av_writedata      => channel_11_writedata,                                                --                         .writedata
			av_waitrequest    => channel_11_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_channel_11_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_channel_11_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_channel_11_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_channel_11_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_channel_11_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_channel_11_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_channel_11_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_channel_11_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_channel_11_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_channel_11_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_channel_11_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                     --                      clk.clk
			reset             => rst_controller_reset_out_reset                                       --                    reset.reset
		);

	channel_2 : component address_decoder_multi_channel_channel_2_cmp
		port map (
			av_address        => channel_2_address,                                                  --      avalon_anti_slave_0.address
			av_write          => channel_2_write,                                                    --                         .write
			av_read           => channel_2_read,                                                     --                         .read
			av_readdata       => channel_2_readdata,                                                 --                         .readdata
			av_writedata      => channel_2_writedata,                                                --                         .writedata
			av_waitrequest    => channel_2_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_channel_2_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_channel_2_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_channel_2_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_channel_2_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_channel_2_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_channel_2_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_channel_2_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_channel_2_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_channel_2_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_channel_2_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_channel_2_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                    --                      clk.clk
			reset             => rst_controller_reset_out_reset                                      --                    reset.reset
		);

	channel_3 : component address_decoder_multi_channel_channel_3_cmp
		port map (
			av_address        => channel_3_address,                                                  --      avalon_anti_slave_0.address
			av_write          => channel_3_write,                                                    --                         .write
			av_read           => channel_3_read,                                                     --                         .read
			av_readdata       => channel_3_readdata,                                                 --                         .readdata
			av_writedata      => channel_3_writedata,                                                --                         .writedata
			av_waitrequest    => channel_3_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_channel_3_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_channel_3_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_channel_3_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_channel_3_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_channel_3_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_channel_3_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_channel_3_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_channel_3_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_channel_3_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_channel_3_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_channel_3_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                    --                      clk.clk
			reset             => rst_controller_reset_out_reset                                      --                    reset.reset
		);

	channel_4 : component address_decoder_multi_channel_channel_4_cmp
		port map (
			av_address        => channel_4_address,                                                  --      avalon_anti_slave_0.address
			av_write          => channel_4_write,                                                    --                         .write
			av_read           => channel_4_read,                                                     --                         .read
			av_readdata       => channel_4_readdata,                                                 --                         .readdata
			av_writedata      => channel_4_writedata,                                                --                         .writedata
			av_waitrequest    => channel_4_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_channel_4_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_channel_4_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_channel_4_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_channel_4_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_channel_4_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_channel_4_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_channel_4_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_channel_4_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_channel_4_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_channel_4_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_channel_4_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                    --                      clk.clk
			reset             => rst_controller_reset_out_reset                                      --                    reset.reset
		);

	channel_5 : component address_decoder_multi_channel_channel_5_cmp
		port map (
			av_address        => channel_5_address,                                                  --      avalon_anti_slave_0.address
			av_write          => channel_5_write,                                                    --                         .write
			av_read           => channel_5_read,                                                     --                         .read
			av_readdata       => channel_5_readdata,                                                 --                         .readdata
			av_writedata      => channel_5_writedata,                                                --                         .writedata
			av_waitrequest    => channel_5_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_channel_5_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_channel_5_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_channel_5_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_channel_5_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_channel_5_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_channel_5_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_channel_5_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_channel_5_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_channel_5_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_channel_5_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_channel_5_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                    --                      clk.clk
			reset             => rst_controller_reset_out_reset                                      --                    reset.reset
		);

	channel_6 : component address_decoder_multi_channel_channel_6_cmp
		port map (
			av_address        => channel_6_address,                                                  --      avalon_anti_slave_0.address
			av_write          => channel_6_write,                                                    --                         .write
			av_read           => channel_6_read,                                                     --                         .read
			av_readdata       => channel_6_readdata,                                                 --                         .readdata
			av_writedata      => channel_6_writedata,                                                --                         .writedata
			av_waitrequest    => channel_6_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_channel_6_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_channel_6_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_channel_6_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_channel_6_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_channel_6_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_channel_6_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_channel_6_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_channel_6_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_channel_6_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_channel_6_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_channel_6_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                    --                      clk.clk
			reset             => rst_controller_reset_out_reset                                      --                    reset.reset
		);

	channel_7 : component address_decoder_multi_channel_channel_7_cmp
		port map (
			av_address        => channel_7_address,                                                  --      avalon_anti_slave_0.address
			av_write          => channel_7_write,                                                    --                         .write
			av_read           => channel_7_read,                                                     --                         .read
			av_readdata       => channel_7_readdata,                                                 --                         .readdata
			av_writedata      => channel_7_writedata,                                                --                         .writedata
			av_waitrequest    => channel_7_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_channel_7_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_channel_7_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_channel_7_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_channel_7_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_channel_7_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_channel_7_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_channel_7_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_channel_7_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_channel_7_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_channel_7_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_channel_7_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                    --                      clk.clk
			reset             => rst_controller_reset_out_reset                                      --                    reset.reset
		);

	channel_8 : component address_decoder_multi_channel_channel_8_cmp
		port map (
			av_address        => channel_8_address,                                                  --      avalon_anti_slave_0.address
			av_write          => channel_8_write,                                                    --                         .write
			av_read           => channel_8_read,                                                     --                         .read
			av_readdata       => channel_8_readdata,                                                 --                         .readdata
			av_writedata      => channel_8_writedata,                                                --                         .writedata
			av_waitrequest    => channel_8_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_channel_8_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_channel_8_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_channel_8_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_channel_8_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_channel_8_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_channel_8_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_channel_8_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_channel_8_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_channel_8_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_channel_8_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_channel_8_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                    --                      clk.clk
			reset             => rst_controller_reset_out_reset                                      --                    reset.reset
		);

	channel_9 : component address_decoder_multi_channel_channel_9_cmp
		port map (
			av_address        => channel_9_address,                                                  --      avalon_anti_slave_0.address
			av_write          => channel_9_write,                                                    --                         .write
			av_read           => channel_9_read,                                                     --                         .read
			av_readdata       => channel_9_readdata,                                                 --                         .readdata
			av_writedata      => channel_9_writedata,                                                --                         .writedata
			av_waitrequest    => channel_9_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_channel_9_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_channel_9_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_channel_9_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_channel_9_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_channel_9_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_channel_9_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_channel_9_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_channel_9_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_channel_9_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_channel_9_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_channel_9_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                    --                      clk.clk
			reset             => rst_controller_reset_out_reset                                      --                    reset.reset
		);

	csr_clk : component address_decoder_multi_channel_csr_clk_cmp
		port map (
			clk_out     => csr_clk_clk_clk,         --          clk.clk
			in_clk      => csr_clk_clk,             --       clk_in.clk
			reset_n     => csr_clk_reset_reset_n,   -- clk_in_reset.reset_n
			reset_n_out => csr_clk_clk_reset_reset  --    clk_reset.reset_n
		);

	master : component address_decoder_multi_channel_master_cmp
		port map (
			av_address        => slave_address,                                  --      avalon_anti_master_0.address
			av_waitrequest    => slave_waitrequest,                              --                          .waitrequest
			av_read           => slave_read,                                     --                          .read
			av_readdata       => slave_readdata,                                 --                          .readdata
			av_write          => slave_write,                                    --                          .write
			av_writedata      => slave_writedata,                                --                          .writedata
			uav_address       => master_avalon_universal_master_0_address,       -- avalon_universal_master_0.address
			uav_burstcount    => master_avalon_universal_master_0_burstcount,    --                          .burstcount
			uav_read          => master_avalon_universal_master_0_read,          --                          .read
			uav_write         => master_avalon_universal_master_0_write,         --                          .write
			uav_waitrequest   => master_avalon_universal_master_0_waitrequest,   --                          .waitrequest
			uav_readdatavalid => master_avalon_universal_master_0_readdatavalid, --                          .readdatavalid
			uav_byteenable    => master_avalon_universal_master_0_byteenable,    --                          .byteenable
			uav_readdata      => master_avalon_universal_master_0_readdata,      --                          .readdata
			uav_writedata     => master_avalon_universal_master_0_writedata,     --                          .writedata
			uav_lock          => master_avalon_universal_master_0_lock,          --                          .lock
			uav_debugaccess   => master_avalon_universal_master_0_debugaccess,   --                          .debugaccess
			clk               => csr_clk_clk_clk,                                --                       clk.clk
			reset             => rst_controller_reset_out_reset                  --                     reset.reset
		);

	mm_interconnect_0 : component address_decoder_multi_channel_altera_mm_interconnect_191_yxycpgi_cmp
		port map (
			master_avalon_universal_master_0_address          => master_avalon_universal_master_0_address,                            --    master_avalon_universal_master_0.address
			master_avalon_universal_master_0_waitrequest      => master_avalon_universal_master_0_waitrequest,                        --                                    .waitrequest
			master_avalon_universal_master_0_burstcount       => master_avalon_universal_master_0_burstcount,                         --                                    .burstcount
			master_avalon_universal_master_0_byteenable       => master_avalon_universal_master_0_byteenable,                         --                                    .byteenable
			master_avalon_universal_master_0_read             => master_avalon_universal_master_0_read,                               --                                    .read
			master_avalon_universal_master_0_readdata         => master_avalon_universal_master_0_readdata,                           --                                    .readdata
			master_avalon_universal_master_0_readdatavalid    => master_avalon_universal_master_0_readdatavalid,                      --                                    .readdatavalid
			master_avalon_universal_master_0_write            => master_avalon_universal_master_0_write,                              --                                    .write
			master_avalon_universal_master_0_writedata        => master_avalon_universal_master_0_writedata,                          --                                    .writedata
			master_avalon_universal_master_0_lock             => master_avalon_universal_master_0_lock,                               --                                    .lock
			master_avalon_universal_master_0_debugaccess      => master_avalon_universal_master_0_debugaccess,                        --                                    .debugaccess
			channel_1_avalon_universal_slave_0_address        => mm_interconnect_0_channel_1_avalon_universal_slave_0_address,        --  channel_1_avalon_universal_slave_0.address
			channel_1_avalon_universal_slave_0_write          => mm_interconnect_0_channel_1_avalon_universal_slave_0_write,          --                                    .write
			channel_1_avalon_universal_slave_0_read           => mm_interconnect_0_channel_1_avalon_universal_slave_0_read,           --                                    .read
			channel_1_avalon_universal_slave_0_readdata       => mm_interconnect_0_channel_1_avalon_universal_slave_0_readdata,       --                                    .readdata
			channel_1_avalon_universal_slave_0_writedata      => mm_interconnect_0_channel_1_avalon_universal_slave_0_writedata,      --                                    .writedata
			channel_1_avalon_universal_slave_0_burstcount     => mm_interconnect_0_channel_1_avalon_universal_slave_0_burstcount,     --                                    .burstcount
			channel_1_avalon_universal_slave_0_byteenable     => mm_interconnect_0_channel_1_avalon_universal_slave_0_byteenable,     --                                    .byteenable
			channel_1_avalon_universal_slave_0_readdatavalid  => mm_interconnect_0_channel_1_avalon_universal_slave_0_readdatavalid,  --                                    .readdatavalid
			channel_1_avalon_universal_slave_0_waitrequest    => mm_interconnect_0_channel_1_avalon_universal_slave_0_waitrequest,    --                                    .waitrequest
			channel_1_avalon_universal_slave_0_lock           => mm_interconnect_0_channel_1_avalon_universal_slave_0_lock,           --                                    .lock
			channel_1_avalon_universal_slave_0_debugaccess    => mm_interconnect_0_channel_1_avalon_universal_slave_0_debugaccess,    --                                    .debugaccess
			channel_0_avalon_universal_slave_0_address        => mm_interconnect_0_channel_0_avalon_universal_slave_0_address,        --  channel_0_avalon_universal_slave_0.address
			channel_0_avalon_universal_slave_0_write          => mm_interconnect_0_channel_0_avalon_universal_slave_0_write,          --                                    .write
			channel_0_avalon_universal_slave_0_read           => mm_interconnect_0_channel_0_avalon_universal_slave_0_read,           --                                    .read
			channel_0_avalon_universal_slave_0_readdata       => mm_interconnect_0_channel_0_avalon_universal_slave_0_readdata,       --                                    .readdata
			channel_0_avalon_universal_slave_0_writedata      => mm_interconnect_0_channel_0_avalon_universal_slave_0_writedata,      --                                    .writedata
			channel_0_avalon_universal_slave_0_burstcount     => mm_interconnect_0_channel_0_avalon_universal_slave_0_burstcount,     --                                    .burstcount
			channel_0_avalon_universal_slave_0_byteenable     => mm_interconnect_0_channel_0_avalon_universal_slave_0_byteenable,     --                                    .byteenable
			channel_0_avalon_universal_slave_0_readdatavalid  => mm_interconnect_0_channel_0_avalon_universal_slave_0_readdatavalid,  --                                    .readdatavalid
			channel_0_avalon_universal_slave_0_waitrequest    => mm_interconnect_0_channel_0_avalon_universal_slave_0_waitrequest,    --                                    .waitrequest
			channel_0_avalon_universal_slave_0_lock           => mm_interconnect_0_channel_0_avalon_universal_slave_0_lock,           --                                    .lock
			channel_0_avalon_universal_slave_0_debugaccess    => mm_interconnect_0_channel_0_avalon_universal_slave_0_debugaccess,    --                                    .debugaccess
			channel_2_avalon_universal_slave_0_address        => mm_interconnect_0_channel_2_avalon_universal_slave_0_address,        --  channel_2_avalon_universal_slave_0.address
			channel_2_avalon_universal_slave_0_write          => mm_interconnect_0_channel_2_avalon_universal_slave_0_write,          --                                    .write
			channel_2_avalon_universal_slave_0_read           => mm_interconnect_0_channel_2_avalon_universal_slave_0_read,           --                                    .read
			channel_2_avalon_universal_slave_0_readdata       => mm_interconnect_0_channel_2_avalon_universal_slave_0_readdata,       --                                    .readdata
			channel_2_avalon_universal_slave_0_writedata      => mm_interconnect_0_channel_2_avalon_universal_slave_0_writedata,      --                                    .writedata
			channel_2_avalon_universal_slave_0_burstcount     => mm_interconnect_0_channel_2_avalon_universal_slave_0_burstcount,     --                                    .burstcount
			channel_2_avalon_universal_slave_0_byteenable     => mm_interconnect_0_channel_2_avalon_universal_slave_0_byteenable,     --                                    .byteenable
			channel_2_avalon_universal_slave_0_readdatavalid  => mm_interconnect_0_channel_2_avalon_universal_slave_0_readdatavalid,  --                                    .readdatavalid
			channel_2_avalon_universal_slave_0_waitrequest    => mm_interconnect_0_channel_2_avalon_universal_slave_0_waitrequest,    --                                    .waitrequest
			channel_2_avalon_universal_slave_0_lock           => mm_interconnect_0_channel_2_avalon_universal_slave_0_lock,           --                                    .lock
			channel_2_avalon_universal_slave_0_debugaccess    => mm_interconnect_0_channel_2_avalon_universal_slave_0_debugaccess,    --                                    .debugaccess
			channel_3_avalon_universal_slave_0_address        => mm_interconnect_0_channel_3_avalon_universal_slave_0_address,        --  channel_3_avalon_universal_slave_0.address
			channel_3_avalon_universal_slave_0_write          => mm_interconnect_0_channel_3_avalon_universal_slave_0_write,          --                                    .write
			channel_3_avalon_universal_slave_0_read           => mm_interconnect_0_channel_3_avalon_universal_slave_0_read,           --                                    .read
			channel_3_avalon_universal_slave_0_readdata       => mm_interconnect_0_channel_3_avalon_universal_slave_0_readdata,       --                                    .readdata
			channel_3_avalon_universal_slave_0_writedata      => mm_interconnect_0_channel_3_avalon_universal_slave_0_writedata,      --                                    .writedata
			channel_3_avalon_universal_slave_0_burstcount     => mm_interconnect_0_channel_3_avalon_universal_slave_0_burstcount,     --                                    .burstcount
			channel_3_avalon_universal_slave_0_byteenable     => mm_interconnect_0_channel_3_avalon_universal_slave_0_byteenable,     --                                    .byteenable
			channel_3_avalon_universal_slave_0_readdatavalid  => mm_interconnect_0_channel_3_avalon_universal_slave_0_readdatavalid,  --                                    .readdatavalid
			channel_3_avalon_universal_slave_0_waitrequest    => mm_interconnect_0_channel_3_avalon_universal_slave_0_waitrequest,    --                                    .waitrequest
			channel_3_avalon_universal_slave_0_lock           => mm_interconnect_0_channel_3_avalon_universal_slave_0_lock,           --                                    .lock
			channel_3_avalon_universal_slave_0_debugaccess    => mm_interconnect_0_channel_3_avalon_universal_slave_0_debugaccess,    --                                    .debugaccess
			channel_4_avalon_universal_slave_0_address        => mm_interconnect_0_channel_4_avalon_universal_slave_0_address,        --  channel_4_avalon_universal_slave_0.address
			channel_4_avalon_universal_slave_0_write          => mm_interconnect_0_channel_4_avalon_universal_slave_0_write,          --                                    .write
			channel_4_avalon_universal_slave_0_read           => mm_interconnect_0_channel_4_avalon_universal_slave_0_read,           --                                    .read
			channel_4_avalon_universal_slave_0_readdata       => mm_interconnect_0_channel_4_avalon_universal_slave_0_readdata,       --                                    .readdata
			channel_4_avalon_universal_slave_0_writedata      => mm_interconnect_0_channel_4_avalon_universal_slave_0_writedata,      --                                    .writedata
			channel_4_avalon_universal_slave_0_burstcount     => mm_interconnect_0_channel_4_avalon_universal_slave_0_burstcount,     --                                    .burstcount
			channel_4_avalon_universal_slave_0_byteenable     => mm_interconnect_0_channel_4_avalon_universal_slave_0_byteenable,     --                                    .byteenable
			channel_4_avalon_universal_slave_0_readdatavalid  => mm_interconnect_0_channel_4_avalon_universal_slave_0_readdatavalid,  --                                    .readdatavalid
			channel_4_avalon_universal_slave_0_waitrequest    => mm_interconnect_0_channel_4_avalon_universal_slave_0_waitrequest,    --                                    .waitrequest
			channel_4_avalon_universal_slave_0_lock           => mm_interconnect_0_channel_4_avalon_universal_slave_0_lock,           --                                    .lock
			channel_4_avalon_universal_slave_0_debugaccess    => mm_interconnect_0_channel_4_avalon_universal_slave_0_debugaccess,    --                                    .debugaccess
			channel_5_avalon_universal_slave_0_address        => mm_interconnect_0_channel_5_avalon_universal_slave_0_address,        --  channel_5_avalon_universal_slave_0.address
			channel_5_avalon_universal_slave_0_write          => mm_interconnect_0_channel_5_avalon_universal_slave_0_write,          --                                    .write
			channel_5_avalon_universal_slave_0_read           => mm_interconnect_0_channel_5_avalon_universal_slave_0_read,           --                                    .read
			channel_5_avalon_universal_slave_0_readdata       => mm_interconnect_0_channel_5_avalon_universal_slave_0_readdata,       --                                    .readdata
			channel_5_avalon_universal_slave_0_writedata      => mm_interconnect_0_channel_5_avalon_universal_slave_0_writedata,      --                                    .writedata
			channel_5_avalon_universal_slave_0_burstcount     => mm_interconnect_0_channel_5_avalon_universal_slave_0_burstcount,     --                                    .burstcount
			channel_5_avalon_universal_slave_0_byteenable     => mm_interconnect_0_channel_5_avalon_universal_slave_0_byteenable,     --                                    .byteenable
			channel_5_avalon_universal_slave_0_readdatavalid  => mm_interconnect_0_channel_5_avalon_universal_slave_0_readdatavalid,  --                                    .readdatavalid
			channel_5_avalon_universal_slave_0_waitrequest    => mm_interconnect_0_channel_5_avalon_universal_slave_0_waitrequest,    --                                    .waitrequest
			channel_5_avalon_universal_slave_0_lock           => mm_interconnect_0_channel_5_avalon_universal_slave_0_lock,           --                                    .lock
			channel_5_avalon_universal_slave_0_debugaccess    => mm_interconnect_0_channel_5_avalon_universal_slave_0_debugaccess,    --                                    .debugaccess
			channel_6_avalon_universal_slave_0_address        => mm_interconnect_0_channel_6_avalon_universal_slave_0_address,        --  channel_6_avalon_universal_slave_0.address
			channel_6_avalon_universal_slave_0_write          => mm_interconnect_0_channel_6_avalon_universal_slave_0_write,          --                                    .write
			channel_6_avalon_universal_slave_0_read           => mm_interconnect_0_channel_6_avalon_universal_slave_0_read,           --                                    .read
			channel_6_avalon_universal_slave_0_readdata       => mm_interconnect_0_channel_6_avalon_universal_slave_0_readdata,       --                                    .readdata
			channel_6_avalon_universal_slave_0_writedata      => mm_interconnect_0_channel_6_avalon_universal_slave_0_writedata,      --                                    .writedata
			channel_6_avalon_universal_slave_0_burstcount     => mm_interconnect_0_channel_6_avalon_universal_slave_0_burstcount,     --                                    .burstcount
			channel_6_avalon_universal_slave_0_byteenable     => mm_interconnect_0_channel_6_avalon_universal_slave_0_byteenable,     --                                    .byteenable
			channel_6_avalon_universal_slave_0_readdatavalid  => mm_interconnect_0_channel_6_avalon_universal_slave_0_readdatavalid,  --                                    .readdatavalid
			channel_6_avalon_universal_slave_0_waitrequest    => mm_interconnect_0_channel_6_avalon_universal_slave_0_waitrequest,    --                                    .waitrequest
			channel_6_avalon_universal_slave_0_lock           => mm_interconnect_0_channel_6_avalon_universal_slave_0_lock,           --                                    .lock
			channel_6_avalon_universal_slave_0_debugaccess    => mm_interconnect_0_channel_6_avalon_universal_slave_0_debugaccess,    --                                    .debugaccess
			channel_7_avalon_universal_slave_0_address        => mm_interconnect_0_channel_7_avalon_universal_slave_0_address,        --  channel_7_avalon_universal_slave_0.address
			channel_7_avalon_universal_slave_0_write          => mm_interconnect_0_channel_7_avalon_universal_slave_0_write,          --                                    .write
			channel_7_avalon_universal_slave_0_read           => mm_interconnect_0_channel_7_avalon_universal_slave_0_read,           --                                    .read
			channel_7_avalon_universal_slave_0_readdata       => mm_interconnect_0_channel_7_avalon_universal_slave_0_readdata,       --                                    .readdata
			channel_7_avalon_universal_slave_0_writedata      => mm_interconnect_0_channel_7_avalon_universal_slave_0_writedata,      --                                    .writedata
			channel_7_avalon_universal_slave_0_burstcount     => mm_interconnect_0_channel_7_avalon_universal_slave_0_burstcount,     --                                    .burstcount
			channel_7_avalon_universal_slave_0_byteenable     => mm_interconnect_0_channel_7_avalon_universal_slave_0_byteenable,     --                                    .byteenable
			channel_7_avalon_universal_slave_0_readdatavalid  => mm_interconnect_0_channel_7_avalon_universal_slave_0_readdatavalid,  --                                    .readdatavalid
			channel_7_avalon_universal_slave_0_waitrequest    => mm_interconnect_0_channel_7_avalon_universal_slave_0_waitrequest,    --                                    .waitrequest
			channel_7_avalon_universal_slave_0_lock           => mm_interconnect_0_channel_7_avalon_universal_slave_0_lock,           --                                    .lock
			channel_7_avalon_universal_slave_0_debugaccess    => mm_interconnect_0_channel_7_avalon_universal_slave_0_debugaccess,    --                                    .debugaccess
			channel_8_avalon_universal_slave_0_address        => mm_interconnect_0_channel_8_avalon_universal_slave_0_address,        --  channel_8_avalon_universal_slave_0.address
			channel_8_avalon_universal_slave_0_write          => mm_interconnect_0_channel_8_avalon_universal_slave_0_write,          --                                    .write
			channel_8_avalon_universal_slave_0_read           => mm_interconnect_0_channel_8_avalon_universal_slave_0_read,           --                                    .read
			channel_8_avalon_universal_slave_0_readdata       => mm_interconnect_0_channel_8_avalon_universal_slave_0_readdata,       --                                    .readdata
			channel_8_avalon_universal_slave_0_writedata      => mm_interconnect_0_channel_8_avalon_universal_slave_0_writedata,      --                                    .writedata
			channel_8_avalon_universal_slave_0_burstcount     => mm_interconnect_0_channel_8_avalon_universal_slave_0_burstcount,     --                                    .burstcount
			channel_8_avalon_universal_slave_0_byteenable     => mm_interconnect_0_channel_8_avalon_universal_slave_0_byteenable,     --                                    .byteenable
			channel_8_avalon_universal_slave_0_readdatavalid  => mm_interconnect_0_channel_8_avalon_universal_slave_0_readdatavalid,  --                                    .readdatavalid
			channel_8_avalon_universal_slave_0_waitrequest    => mm_interconnect_0_channel_8_avalon_universal_slave_0_waitrequest,    --                                    .waitrequest
			channel_8_avalon_universal_slave_0_lock           => mm_interconnect_0_channel_8_avalon_universal_slave_0_lock,           --                                    .lock
			channel_8_avalon_universal_slave_0_debugaccess    => mm_interconnect_0_channel_8_avalon_universal_slave_0_debugaccess,    --                                    .debugaccess
			channel_9_avalon_universal_slave_0_address        => mm_interconnect_0_channel_9_avalon_universal_slave_0_address,        --  channel_9_avalon_universal_slave_0.address
			channel_9_avalon_universal_slave_0_write          => mm_interconnect_0_channel_9_avalon_universal_slave_0_write,          --                                    .write
			channel_9_avalon_universal_slave_0_read           => mm_interconnect_0_channel_9_avalon_universal_slave_0_read,           --                                    .read
			channel_9_avalon_universal_slave_0_readdata       => mm_interconnect_0_channel_9_avalon_universal_slave_0_readdata,       --                                    .readdata
			channel_9_avalon_universal_slave_0_writedata      => mm_interconnect_0_channel_9_avalon_universal_slave_0_writedata,      --                                    .writedata
			channel_9_avalon_universal_slave_0_burstcount     => mm_interconnect_0_channel_9_avalon_universal_slave_0_burstcount,     --                                    .burstcount
			channel_9_avalon_universal_slave_0_byteenable     => mm_interconnect_0_channel_9_avalon_universal_slave_0_byteenable,     --                                    .byteenable
			channel_9_avalon_universal_slave_0_readdatavalid  => mm_interconnect_0_channel_9_avalon_universal_slave_0_readdatavalid,  --                                    .readdatavalid
			channel_9_avalon_universal_slave_0_waitrequest    => mm_interconnect_0_channel_9_avalon_universal_slave_0_waitrequest,    --                                    .waitrequest
			channel_9_avalon_universal_slave_0_lock           => mm_interconnect_0_channel_9_avalon_universal_slave_0_lock,           --                                    .lock
			channel_9_avalon_universal_slave_0_debugaccess    => mm_interconnect_0_channel_9_avalon_universal_slave_0_debugaccess,    --                                    .debugaccess
			channel_10_avalon_universal_slave_0_address       => mm_interconnect_0_channel_10_avalon_universal_slave_0_address,       -- channel_10_avalon_universal_slave_0.address
			channel_10_avalon_universal_slave_0_write         => mm_interconnect_0_channel_10_avalon_universal_slave_0_write,         --                                    .write
			channel_10_avalon_universal_slave_0_read          => mm_interconnect_0_channel_10_avalon_universal_slave_0_read,          --                                    .read
			channel_10_avalon_universal_slave_0_readdata      => mm_interconnect_0_channel_10_avalon_universal_slave_0_readdata,      --                                    .readdata
			channel_10_avalon_universal_slave_0_writedata     => mm_interconnect_0_channel_10_avalon_universal_slave_0_writedata,     --                                    .writedata
			channel_10_avalon_universal_slave_0_burstcount    => mm_interconnect_0_channel_10_avalon_universal_slave_0_burstcount,    --                                    .burstcount
			channel_10_avalon_universal_slave_0_byteenable    => mm_interconnect_0_channel_10_avalon_universal_slave_0_byteenable,    --                                    .byteenable
			channel_10_avalon_universal_slave_0_readdatavalid => mm_interconnect_0_channel_10_avalon_universal_slave_0_readdatavalid, --                                    .readdatavalid
			channel_10_avalon_universal_slave_0_waitrequest   => mm_interconnect_0_channel_10_avalon_universal_slave_0_waitrequest,   --                                    .waitrequest
			channel_10_avalon_universal_slave_0_lock          => mm_interconnect_0_channel_10_avalon_universal_slave_0_lock,          --                                    .lock
			channel_10_avalon_universal_slave_0_debugaccess   => mm_interconnect_0_channel_10_avalon_universal_slave_0_debugaccess,   --                                    .debugaccess
			channel_11_avalon_universal_slave_0_address       => mm_interconnect_0_channel_11_avalon_universal_slave_0_address,       -- channel_11_avalon_universal_slave_0.address
			channel_11_avalon_universal_slave_0_write         => mm_interconnect_0_channel_11_avalon_universal_slave_0_write,         --                                    .write
			channel_11_avalon_universal_slave_0_read          => mm_interconnect_0_channel_11_avalon_universal_slave_0_read,          --                                    .read
			channel_11_avalon_universal_slave_0_readdata      => mm_interconnect_0_channel_11_avalon_universal_slave_0_readdata,      --                                    .readdata
			channel_11_avalon_universal_slave_0_writedata     => mm_interconnect_0_channel_11_avalon_universal_slave_0_writedata,     --                                    .writedata
			channel_11_avalon_universal_slave_0_burstcount    => mm_interconnect_0_channel_11_avalon_universal_slave_0_burstcount,    --                                    .burstcount
			channel_11_avalon_universal_slave_0_byteenable    => mm_interconnect_0_channel_11_avalon_universal_slave_0_byteenable,    --                                    .byteenable
			channel_11_avalon_universal_slave_0_readdatavalid => mm_interconnect_0_channel_11_avalon_universal_slave_0_readdatavalid, --                                    .readdatavalid
			channel_11_avalon_universal_slave_0_waitrequest   => mm_interconnect_0_channel_11_avalon_universal_slave_0_waitrequest,   --                                    .waitrequest
			channel_11_avalon_universal_slave_0_lock          => mm_interconnect_0_channel_11_avalon_universal_slave_0_lock,          --                                    .lock
			channel_11_avalon_universal_slave_0_debugaccess   => mm_interconnect_0_channel_11_avalon_universal_slave_0_debugaccess,   --                                    .debugaccess
			master_reset_reset_bridge_in_reset_reset          => rst_controller_reset_out_reset,                                      --  master_reset_reset_bridge_in_reset.reset
			csr_clk_clk_clk                                   => csr_clk_clk_clk                                                      --                         csr_clk_clk.clk
		);

	rst_controller : component altera_reset_controller_cmp
		generic map (
			NUM_RESET_INPUTS          => 1,
			OUTPUT_RESET_SYNC_EDGES   => "deassert",
			SYNC_DEPTH                => 2,
			RESET_REQUEST_PRESENT     => 0,
			RESET_REQ_WAIT_TIME       => 1,
			MIN_RST_ASSERTION_TIME    => 3,
			RESET_REQ_EARLY_DSRT_TIME => 1,
			USE_RESET_REQUEST_IN0     => 0,
			USE_RESET_REQUEST_IN1     => 0,
			USE_RESET_REQUEST_IN2     => 0,
			USE_RESET_REQUEST_IN3     => 0,
			USE_RESET_REQUEST_IN4     => 0,
			USE_RESET_REQUEST_IN5     => 0,
			USE_RESET_REQUEST_IN6     => 0,
			USE_RESET_REQUEST_IN7     => 0,
			USE_RESET_REQUEST_IN8     => 0,
			USE_RESET_REQUEST_IN9     => 0,
			USE_RESET_REQUEST_IN10    => 0,
			USE_RESET_REQUEST_IN11    => 0,
			USE_RESET_REQUEST_IN12    => 0,
			USE_RESET_REQUEST_IN13    => 0,
			USE_RESET_REQUEST_IN14    => 0,
			USE_RESET_REQUEST_IN15    => 0,
			ADAPT_RESET_REQUEST       => 0
		)
		port map (
			reset_in0      => csr_clk_clk_reset_reset_ports_inv, -- reset_in0.reset
			clk            => csr_clk_clk_clk,                   --       clk.clk
			reset_out      => rst_controller_reset_out_reset,    -- reset_out.reset
			reset_req      => open,                              -- (terminated)
			reset_req_in0  => '0',                               -- (terminated)
			reset_in1      => '0',                               -- (terminated)
			reset_req_in1  => '0',                               -- (terminated)
			reset_in2      => '0',                               -- (terminated)
			reset_req_in2  => '0',                               -- (terminated)
			reset_in3      => '0',                               -- (terminated)
			reset_req_in3  => '0',                               -- (terminated)
			reset_in4      => '0',                               -- (terminated)
			reset_req_in4  => '0',                               -- (terminated)
			reset_in5      => '0',                               -- (terminated)
			reset_req_in5  => '0',                               -- (terminated)
			reset_in6      => '0',                               -- (terminated)
			reset_req_in6  => '0',                               -- (terminated)
			reset_in7      => '0',                               -- (terminated)
			reset_req_in7  => '0',                               -- (terminated)
			reset_in8      => '0',                               -- (terminated)
			reset_req_in8  => '0',                               -- (terminated)
			reset_in9      => '0',                               -- (terminated)
			reset_req_in9  => '0',                               -- (terminated)
			reset_in10     => '0',                               -- (terminated)
			reset_req_in10 => '0',                               -- (terminated)
			reset_in11     => '0',                               -- (terminated)
			reset_req_in11 => '0',                               -- (terminated)
			reset_in12     => '0',                               -- (terminated)
			reset_req_in12 => '0',                               -- (terminated)
			reset_in13     => '0',                               -- (terminated)
			reset_req_in13 => '0',                               -- (terminated)
			reset_in14     => '0',                               -- (terminated)
			reset_req_in14 => '0',                               -- (terminated)
			reset_in15     => '0',                               -- (terminated)
			reset_req_in15 => '0'                                -- (terminated)
		);

	csr_clk_clk_reset_reset_ports_inv <= not csr_clk_clk_reset_reset;

end architecture rtl; -- of address_decoder_multi_channel
