# system info address_decoder_channel on 2020.01.29.11:18:10
system_info:
name,value
DEVICE,1SG165HU2F50E2VG
DEVICE_FAMILY,Stratix 10
GENERATION_ID,0
#
#
# Files generated for address_decoder_channel on 2020.01.29.11:18:10
files:
filepath,kind,attributes,module,is_top
sim/address_decoder_channel.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_channel,true
altera_mm_interconnect_191/sim/address_decoder_channel_altera_mm_interconnect_191_wasz7ki_mac_avalon_universal_slave_0_translator.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_channel_altera_mm_interconnect_191_wasz7ki,false
altera_mm_interconnect_191/sim/address_decoder_channel_altera_mm_interconnect_191_wasz7ki_phy_avalon_universal_slave_0_translator.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_channel_altera_mm_interconnect_191_wasz7ki,false
altera_mm_interconnect_191/sim/address_decoder_channel_altera_mm_interconnect_191_wasz7ki.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_channel_altera_mm_interconnect_191_wasz7ki,false
altera_reset_controller_191/sim/mentor/altera_reset_controller.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/mentor/altera_reset_synchronizer.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/aldec/altera_reset_controller.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/aldec/altera_reset_synchronizer.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/cadence/altera_reset_controller.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/cadence/altera_reset_synchronizer.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/synopsys/altera_reset_controller.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/synopsys/altera_reset_synchronizer.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_reset_controller,false
altera_merlin_master_translator_191/sim/address_decoder_channel_altera_merlin_master_translator_191_g7h47bq.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_master_translator_191_g7h47bq,false
altera_merlin_slave_translator_191/sim/address_decoder_channel_altera_merlin_slave_translator_191_x56fcki.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_slave_translator_191_x56fcki,false
altera_merlin_master_agent_191/sim/address_decoder_channel_altera_merlin_master_agent_191_mpbm6tq.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_master_agent_191_mpbm6tq,false
altera_merlin_slave_agent_191/sim/address_decoder_channel_altera_merlin_slave_agent_191_ncfkfri.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_slave_agent_191_ncfkfri,false
altera_merlin_slave_agent_191/sim/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_slave_agent_191_ncfkfri,false
altera_merlin_router_191/sim/address_decoder_channel_altera_merlin_router_191_6k4dpta.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_router_191_6k4dpta,false
altera_merlin_router_191/sim/address_decoder_channel_altera_merlin_router_191_bli6daa.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_router_191_bli6daa,false
altera_merlin_traffic_limiter_191/sim/altera_merlin_reorder_memory.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_traffic_limiter_191_kcba44q,false
altera_merlin_traffic_limiter_191/sim/altera_avalon_st_pipeline_base.v,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_traffic_limiter_191_kcba44q,false
altera_merlin_traffic_limiter_191/sim/address_decoder_channel_altera_merlin_traffic_limiter_191_kcba44q.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_traffic_limiter_191_kcba44q,false
altera_merlin_demultiplexer_191/sim/address_decoder_channel_altera_merlin_demultiplexer_191_exog3dy.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_demultiplexer_191_exog3dy,false
altera_merlin_multiplexer_191/sim/address_decoder_channel_altera_merlin_multiplexer_191_bhqatui.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_multiplexer_191_bhqatui,false
altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_multiplexer_191_bhqatui,false
altera_merlin_demultiplexer_191/sim/address_decoder_channel_altera_merlin_demultiplexer_191_z5qvpii.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_demultiplexer_191_z5qvpii,false
altera_merlin_multiplexer_191/sim/address_decoder_channel_altera_merlin_multiplexer_191_om25mwy.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_multiplexer_191_om25mwy,false
altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,address_decoder_channel_altera_merlin_multiplexer_191_om25mwy,false
altera_merlin_traffic_limiter_191/sim/address_decoder_channel_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_191_zonrf6q.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_channel_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_191_zonrf6q,false
altera_avalon_sc_fifo_191/sim/address_decoder_channel_altera_avalon_sc_fifo_191_e5eqkcq.v,VERILOG,,address_decoder_channel_altera_avalon_sc_fifo_191_e5eqkcq,false
altera_merlin_traffic_limiter_191/sim/address_decoder_channel_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,address_decoder_channel_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi,false
alt_hiconnect_sc_fifo_191/sim/address_decoder_channel_alt_hiconnect_sc_fifo_191_7qtmpqq.sv,SYSTEM_VERILOG,,address_decoder_channel_alt_hiconnect_sc_fifo_191_7qtmpqq,false
alt_hiconnect_sc_fifo_191/sim/alt_st_infer_scfifo.sv,SYSTEM_VERILOG,,address_decoder_channel_alt_hiconnect_sc_fifo_191_7qtmpqq,false
alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo.sv,SYSTEM_VERILOG,,address_decoder_channel_alt_hiconnect_sc_fifo_191_7qtmpqq,false
alt_hiconnect_sc_fifo_191/sim/alt_st_fifo_empty.sv,SYSTEM_VERILOG,,address_decoder_channel_alt_hiconnect_sc_fifo_191_7qtmpqq,false
alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo_a6.sv,SYSTEM_VERILOG,,address_decoder_channel_alt_hiconnect_sc_fifo_191_7qtmpqq,false
alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo_a7.sv,SYSTEM_VERILOG,,address_decoder_channel_alt_hiconnect_sc_fifo_191_7qtmpqq,false
alt_hiconnect_sc_fifo_191/sim/alt_st_reg_scfifo.sv,SYSTEM_VERILOG,,address_decoder_channel_alt_hiconnect_sc_fifo_191_7qtmpqq,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
address_decoder_channel.csr_clk,address_decoder_channel_csr_clk
address_decoder_channel.mac,address_decoder_channel_mac
address_decoder_channel.master,address_decoder_channel_master
address_decoder_channel.phy,address_decoder_channel_phy
address_decoder_channel.xcvr_rcfg,address_decoder_channel_xcvr_rcfg
address_decoder_channel.mm_interconnect_0,address_decoder_channel_altera_mm_interconnect_191_wasz7ki
address_decoder_channel.mm_interconnect_0.master_avalon_universal_master_0_translator,address_decoder_channel_altera_merlin_master_translator_191_g7h47bq
address_decoder_channel.mm_interconnect_0.mac_avalon_universal_slave_0_translator,address_decoder_channel_altera_merlin_slave_translator_191_x56fcki
address_decoder_channel.mm_interconnect_0.phy_avalon_universal_slave_0_translator,address_decoder_channel_altera_merlin_slave_translator_191_x56fcki
address_decoder_channel.mm_interconnect_0.xcvr_rcfg_avalon_universal_slave_0_translator,address_decoder_channel_altera_merlin_slave_translator_191_x56fcki
address_decoder_channel.mm_interconnect_0.master_avalon_universal_master_0_agent,address_decoder_channel_altera_merlin_master_agent_191_mpbm6tq
address_decoder_channel.mm_interconnect_0.mac_avalon_universal_slave_0_agent,address_decoder_channel_altera_merlin_slave_agent_191_ncfkfri
address_decoder_channel.mm_interconnect_0.phy_avalon_universal_slave_0_agent,address_decoder_channel_altera_merlin_slave_agent_191_ncfkfri
address_decoder_channel.mm_interconnect_0.xcvr_rcfg_avalon_universal_slave_0_agent,address_decoder_channel_altera_merlin_slave_agent_191_ncfkfri
address_decoder_channel.mm_interconnect_0.mac_avalon_universal_slave_0_agent_rsp_fifo,address_decoder_channel_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_channel.mm_interconnect_0.phy_avalon_universal_slave_0_agent_rsp_fifo,address_decoder_channel_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_channel.mm_interconnect_0.xcvr_rcfg_avalon_universal_slave_0_agent_rsp_fifo,address_decoder_channel_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_channel.mm_interconnect_0.router,address_decoder_channel_altera_merlin_router_191_6k4dpta
address_decoder_channel.mm_interconnect_0.router_001,address_decoder_channel_altera_merlin_router_191_bli6daa
address_decoder_channel.mm_interconnect_0.router_002,address_decoder_channel_altera_merlin_router_191_bli6daa
address_decoder_channel.mm_interconnect_0.router_003,address_decoder_channel_altera_merlin_router_191_bli6daa
address_decoder_channel.mm_interconnect_0.master_avalon_universal_master_0_limiter,address_decoder_channel_altera_merlin_traffic_limiter_191_kcba44q
address_decoder_channel.mm_interconnect_0.master_avalon_universal_master_0_limiter.my_altera_avalon_sc_fifo_dest_id_fifo,address_decoder_channel_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_191_zonrf6q
address_decoder_channel.mm_interconnect_0.master_avalon_universal_master_0_limiter.my_altera_avalon_sc_fifo_dest_id_fifo.my_altera_avalon_sc_fifo_dest_id_fifo,address_decoder_channel_altera_avalon_sc_fifo_191_e5eqkcq
address_decoder_channel.mm_interconnect_0.master_avalon_universal_master_0_limiter.my_alt_hiconnect_sc_fifo_dest_id_fifo,address_decoder_channel_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi
address_decoder_channel.mm_interconnect_0.master_avalon_universal_master_0_limiter.my_alt_hiconnect_sc_fifo_dest_id_fifo.my_alt_hiconnect_sc_fifo_dest_id_fifo,address_decoder_channel_alt_hiconnect_sc_fifo_191_7qtmpqq
address_decoder_channel.mm_interconnect_0.cmd_demux,address_decoder_channel_altera_merlin_demultiplexer_191_exog3dy
address_decoder_channel.mm_interconnect_0.cmd_mux,address_decoder_channel_altera_merlin_multiplexer_191_bhqatui
address_decoder_channel.mm_interconnect_0.cmd_mux_001,address_decoder_channel_altera_merlin_multiplexer_191_bhqatui
address_decoder_channel.mm_interconnect_0.cmd_mux_002,address_decoder_channel_altera_merlin_multiplexer_191_bhqatui
address_decoder_channel.mm_interconnect_0.rsp_demux,address_decoder_channel_altera_merlin_demultiplexer_191_z5qvpii
address_decoder_channel.mm_interconnect_0.rsp_demux_001,address_decoder_channel_altera_merlin_demultiplexer_191_z5qvpii
address_decoder_channel.mm_interconnect_0.rsp_demux_002,address_decoder_channel_altera_merlin_demultiplexer_191_z5qvpii
address_decoder_channel.mm_interconnect_0.rsp_mux,address_decoder_channel_altera_merlin_multiplexer_191_om25mwy
address_decoder_channel.rst_controller,altera_reset_controller
