# system info alt_usxgmii_phy on 2020.01.29.11:15:58
system_info:
name,value
DEVICE,1SG165HU2F50E2VG
DEVICE_FAMILY,Stratix 10
GENERATION_ID,0
#
#
# Files generated for alt_usxgmii_phy on 2020.01.29.11:15:58
files:
filepath,kind,attributes,module,is_top
sim/alt_usxgmii_phy.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,alt_usxgmii_phy,true
alt_mge_phy_1930/sim/alt_usxgmii_phy_alt_mge_phy_1930_yuuknna.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,alt_usxgmii_phy_alt_mge_phy_1930_yuuknna,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_async_fifo_fpga.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_async_fifo_fpga.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_async_fifo_fpga.sv,SYSTEM_VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_async_fifo_fpga.sv,SYSTEM_VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_bitsync.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_bitsync.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_bitsync.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_bitsync.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_mbow_clock_crosser.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_mbow_clock_crosser.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_mbow_clock_crosser.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_mbow_clock_crosser.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_pcs.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_pcs.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_pcs.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_pcs.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_pcs_csr_top.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_pcs_csr_top.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_pcs_csr_top.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_pcs_csr_top.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_pcs_rst_sync.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_pcs_rst_sync.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_pcs_rst_sync.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_pcs_rst_sync.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_pipeline_base.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_pipeline_base.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_pipeline_base.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_pipeline_base.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_std_synchronizer_bundle.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_std_synchronizer_bundle.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_std_synchronizer_bundle.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_std_synchronizer_bundle.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_an_top.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_an_top.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_an_top.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_an_top.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_creg_map.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_creg_map.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_creg_map.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_creg_map.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_creg_top.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_creg_top.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_creg_top.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_creg_top.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_incr_cnt.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_incr_cnt.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_incr_cnt.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_incr_cnt.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_pcs.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_pcs.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_pcs.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_pcs.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_rx_64_to_32_wadpt.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_rx_64_to_32_wadpt.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_rx_64_to_32_wadpt.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_rx_64_to_32_wadpt.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_rx_data_derep.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_rx_data_derep.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_rx_data_derep.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_rx_data_derep.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_rx_rm_fifo.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_rx_rm_fifo.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_rx_rm_fifo.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_rx_rm_fifo.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_rx_rm_fifo_top.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_rx_rm_fifo_top.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_rx_rm_fifo_top.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_rx_rm_fifo_top.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_rx_top.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_rx_top.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_rx_top.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_rx_top.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_tx_32_to_64_wadpt.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_tx_32_to_64_wadpt.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_tx_32_to_64_wadpt.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_tx_32_to_64_wadpt.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_tx_clockcomp_fifo.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_tx_clockcomp_fifo.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_tx_clockcomp_fifo.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_tx_clockcomp_fifo.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_tx_data_mux.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_tx_data_mux.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_tx_data_mux.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_tx_data_mux.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_tx_data_rep.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_tx_data_rep.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_tx_data_rep.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_tx_data_rep.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_tx_top.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_tx_top.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_tx_top.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_tx_top.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxg32_umii_fault.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_umii_fault.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxg32_umii_fault.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxg32_umii_fault.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_xgmii_1588_latency.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_xgmii_1588_latency.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_xgmii_1588_latency.sv,SYSTEM_VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_xgmii_1588_latency.sv,SYSTEM_VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_xgmii_1588_ppm_counter.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_xgmii_1588_ppm_counter.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_xgmii_1588_ppm_counter.sv,SYSTEM_VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_xgmii_1588_ppm_counter.sv,SYSTEM_VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_xgmii_clockcomp.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_xgmii_clockcomp.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_xgmii_clockcomp.sv,SYSTEM_VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_xgmii_clockcomp.sv,SYSTEM_VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_xgmii_pcs.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_xgmii_pcs.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_xgmii_pcs.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_xgmii_pcs.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_xgmii_rx_fifo.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_xgmii_rx_fifo.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_xgmii_rx_fifo.sv,SYSTEM_VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_xgmii_rx_fifo.sv,SYSTEM_VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_xgmii_soft_fifo.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_xgmii_soft_fifo.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_xgmii_soft_fifo.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_xgmii_soft_fifo.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_1588_ppm_counter.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_1588_ppm_counter.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_1588_ppm_counter.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_1588_ppm_counter.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_a_fifo_24.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_a_fifo_24.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_a_fifo_24.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_a_fifo_24.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_carrier_sense.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_carrier_sense.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_carrier_sense.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_carrier_sense.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_clock_crosser.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_clock_crosser.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_clock_crosser.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_clock_crosser.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_colision_detect.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_colision_detect.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_colision_detect.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_colision_detect.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_control.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_control.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_control.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_control.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_gray_cnt.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_gray_cnt.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_gray_cnt.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_gray_cnt.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_gxb_aligned_rxsync.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_gxb_aligned_rxsync.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_gxb_aligned_rxsync.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_gxb_aligned_rxsync.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_host_control.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_host_control.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_host_control.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_host_control.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_mdio_reg.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_mdio_reg.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_mdio_reg.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_mdio_reg.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_mii_rx_if_pcs.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_mii_rx_if_pcs.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_mii_rx_if_pcs.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_mii_rx_if_pcs.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_mii_tx_if_pcs.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_mii_tx_if_pcs.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_mii_tx_if_pcs.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_mii_tx_if_pcs.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_ph_calculator.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_ph_calculator.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_ph_calculator.sv,SYSTEM_VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_ph_calculator.sv,SYSTEM_VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_pma_gige.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_pma_gige.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_pma_gige.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_pma_gige.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_pma.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_pma.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_pma.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_pma.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_reset_synchronizer.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_reset_synchronizer.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_reset_synchronizer.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_reset_synchronizer.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_rx_converter.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_rx_converter.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_rx_converter.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_rx_converter.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_rx_encapsulation_strx_gx.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_rx_encapsulation_strx_gx.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_rx_encapsulation_strx_gx.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_rx_encapsulation_strx_gx.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_rx_fifo_rd.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_rx_fifo_rd.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_rx_fifo_rd.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_rx_fifo_rd.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_sdpm_altsyncram.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_sdpm_altsyncram.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_sdpm_altsyncram.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_sdpm_altsyncram.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_sgmii_clk_enable.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_sgmii_clk_enable.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_sgmii_clk_enable.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_sgmii_clk_enable.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_std_synchronizer.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_std_synchronizer.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_std_synchronizer.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_std_synchronizer.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_top_1000_base_x_strx_gx.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_top_1000_base_x_strx_gx.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_top_1000_base_x_strx_gx.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_top_1000_base_x_strx_gx.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_top_autoneg.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_top_autoneg.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_top_autoneg.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_top_autoneg.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_top_pcs_strx_gx.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_top_pcs_strx_gx.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_top_pcs_strx_gx.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_top_pcs_strx_gx.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_top_rx_converter.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_top_rx_converter.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_top_rx_converter.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_top_rx_converter.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_top_sgmii_strx_gx.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_top_sgmii_strx_gx.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_top_sgmii_strx_gx.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_top_sgmii_strx_gx.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_top_tx_converter.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_top_tx_converter.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_top_tx_converter.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_top_tx_converter.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_tx_converter.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_tx_converter.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_tx_converter.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_tx_converter.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_tx_encapsulation.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_tx_encapsulation.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_tx_encapsulation.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_tx_encapsulation.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_xcvr_resync.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_xcvr_resync.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_xcvr_resync.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_xcvr_resync.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_xcvr_latency_pulse_measurement.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_xcvr_latency_pulse_measurement.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_xcvr_latency_pulse_measurement.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_xcvr_latency_pulse_measurement.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/latency_pulse_measurement.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/latency_pulse_measurement.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/latency_pulse_measurement.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/latency_pulse_measurement.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_sgmii_8_to_16_converter.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_sgmii_8_to_16_converter.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_sgmii_8_to_16_converter.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_sgmii_8_to_16_converter.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge16_pcs_sgmii_16_to_8_converter.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_sgmii_16_to_8_converter.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge16_pcs_sgmii_16_to_8_converter.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge16_pcs_sgmii_16_to_8_converter.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/mentor/alt_mge_phy_usxgmii_1588_latency.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxgmii_1588_latency.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/cadence/alt_mge_phy_usxgmii_1588_latency.sv,SYSTEM_VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/synopsys/alt_mge_phy_usxgmii_1588_latency.sv,SYSTEM_VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge_phy_pcs,false
alt_mge_phy_pcs_1930/sim/altera_std_synchronizer_nocut.v,VERILOG,,alt_mge_phy_pcs,false
alt_mge_phy_xcvr_term_1930/sim/mentor/alt_mge_phy_gf_clock_mux.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge16_phy_xcvr_term,false
alt_mge_phy_xcvr_term_1930/sim/mentor/alt_mge16_phy_xcvr_term.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_mge16_phy_xcvr_term,false
alt_mge_phy_xcvr_term_1930/sim/aldec/alt_mge_phy_gf_clock_mux.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge16_phy_xcvr_term,false
alt_mge_phy_xcvr_term_1930/sim/aldec/alt_mge16_phy_xcvr_term.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,alt_mge16_phy_xcvr_term,false
alt_mge_phy_xcvr_term_1930/sim/cadence/alt_mge_phy_gf_clock_mux.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge16_phy_xcvr_term,false
alt_mge_phy_xcvr_term_1930/sim/cadence/alt_mge16_phy_xcvr_term.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,alt_mge16_phy_xcvr_term,false
alt_mge_phy_xcvr_term_1930/sim/synopsys/alt_mge_phy_gf_clock_mux.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge16_phy_xcvr_term,false
alt_mge_phy_xcvr_term_1930/sim/synopsys/alt_mge16_phy_xcvr_term.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,alt_mge16_phy_xcvr_term,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_arbiter.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/mentor/alt_xcvr_arbiter.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/altera_std_synchronizer_nocut.v,VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_resync_std.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_reset_counter_s10.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/mentor/alt_xcvr_reset_counter_s10.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/altera_xcvr_native_s10_functions_h.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=altera_xcvr_native_s10_functions_h,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/s10_avmm_h.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_avmm_csr.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_prbs_accum.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_odi_accel.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_rcfg_arb.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_early_spd_chng_s10_htile.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_anlg_reset_seq.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_dig_reset_seq.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_reset_seq.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_anlg_reset_seq_wrapper.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_re_cal_chnl.v,VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_pcie_rx_eios_prot.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_rx_maib_wa.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/plain_files.txt,OTHER,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/mentor_files.txt,OTHER,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/cadence_files.txt,OTHER,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/synopsys_files.txt,OTHER,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/aldec_files.txt,OTHER,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/rcfg_timing_db/alt_usxgmii_phy_hssi_pldadapt_rx_rcfg_settings_x6s27ia.json,OTHER,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/rcfg_timing_db/alt_usxgmii_phy_hssi_pldadapt_tx_rcfg_settings_x6s27ia.json,OTHER,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_usxgmii_phy_ip_parameters_x6s27ia.tcl,TCL_ENTITY,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/reconfig/alt_mge_phy_reconfig_parameters_CFG0.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/reconfig/alt_mge_phy_reconfig_parameters_CFG0.h,OTHER,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/reconfig/alt_mge_phy_reconfig_parameters_CFG0.mif,OTHER,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/docs/alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia_parameters.csv,OTHER,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/docs/alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia_add_hdl_instance_example.tcl,OTHER,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_rcfg_opt_logic_x6s27ia.sv,SYSTEM_VERILOG,,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
alt_usxgmii_phy.alt_mge_phy_0,alt_usxgmii_phy_alt_mge_phy_1930_yuuknna
alt_usxgmii_phy.alt_mge_phy_0.mge_pcs,alt_mge_phy_pcs
alt_usxgmii_phy.alt_mge_phy_0.xcvr_term,alt_mge16_phy_xcvr_term
alt_usxgmii_phy.alt_mge_phy_0.alt_mge_xcvr_native,alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia
