// intel_std_18_1_dummy_mm_interconnect_0.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.1 646

`timescale 1 ps / 1 ps
module intel_std_18_1_dummy_mm_interconnect_0 (
		input  wire        clk_0_clk_clk,                                  //                          clk_0_clk.clk
		input  wire        master_reset_reset_bridge_in_reset_reset,       // master_reset_reset_bridge_in_reset.reset
		input  wire [37:0] master_avalon_universal_master_0_address,       //   master_avalon_universal_master_0.address
		output wire        master_avalon_universal_master_0_waitrequest,   //                                   .waitrequest
		input  wire [9:0]  master_avalon_universal_master_0_burstcount,    //                                   .burstcount
		input  wire [3:0]  master_avalon_universal_master_0_byteenable,    //                                   .byteenable
		input  wire        master_avalon_universal_master_0_read,          //                                   .read
		output wire [31:0] master_avalon_universal_master_0_readdata,      //                                   .readdata
		output wire        master_avalon_universal_master_0_readdatavalid, //                                   .readdatavalid
		input  wire        master_avalon_universal_master_0_write,         //                                   .write
		input  wire [31:0] master_avalon_universal_master_0_writedata,     //                                   .writedata
		input  wire        master_avalon_universal_master_0_lock,          //                                   .lock
		input  wire        master_avalon_universal_master_0_debugaccess,   //                                   .debugaccess
		output wire [31:0] slave0_avalon_universal_slave_0_address,        //    slave0_avalon_universal_slave_0.address
		output wire        slave0_avalon_universal_slave_0_write,          //                                   .write
		output wire        slave0_avalon_universal_slave_0_read,           //                                   .read
		input  wire [31:0] slave0_avalon_universal_slave_0_readdata,       //                                   .readdata
		output wire [31:0] slave0_avalon_universal_slave_0_writedata,      //                                   .writedata
		output wire [3:0]  slave0_avalon_universal_slave_0_burstcount,     //                                   .burstcount
		output wire [3:0]  slave0_avalon_universal_slave_0_byteenable,     //                                   .byteenable
		input  wire        slave0_avalon_universal_slave_0_readdatavalid,  //                                   .readdatavalid
		input  wire        slave0_avalon_universal_slave_0_waitrequest,    //                                   .waitrequest
		output wire        slave0_avalon_universal_slave_0_lock,           //                                   .lock
		output wire        slave0_avalon_universal_slave_0_debugaccess,    //                                   .debugaccess
		output wire [31:0] slave1_avalon_universal_slave_0_address,        //    slave1_avalon_universal_slave_0.address
		output wire        slave1_avalon_universal_slave_0_write,          //                                   .write
		output wire        slave1_avalon_universal_slave_0_read,           //                                   .read
		input  wire [31:0] slave1_avalon_universal_slave_0_readdata,       //                                   .readdata
		output wire [31:0] slave1_avalon_universal_slave_0_writedata,      //                                   .writedata
		output wire [3:0]  slave1_avalon_universal_slave_0_burstcount,     //                                   .burstcount
		output wire [3:0]  slave1_avalon_universal_slave_0_byteenable,     //                                   .byteenable
		input  wire        slave1_avalon_universal_slave_0_readdatavalid,  //                                   .readdatavalid
		input  wire        slave1_avalon_universal_slave_0_waitrequest,    //                                   .waitrequest
		output wire        slave1_avalon_universal_slave_0_lock,           //                                   .lock
		output wire        slave1_avalon_universal_slave_0_debugaccess     //                                   .debugaccess
	);

	wire          master_avalon_universal_master_0_translator_avalon_universal_master_0_waitrequest;   // master_avalon_universal_master_0_agent:av_waitrequest -> master_avalon_universal_master_0_translator:uav_waitrequest
	wire   [31:0] master_avalon_universal_master_0_translator_avalon_universal_master_0_readdata;      // master_avalon_universal_master_0_agent:av_readdata -> master_avalon_universal_master_0_translator:uav_readdata
	wire          master_avalon_universal_master_0_translator_avalon_universal_master_0_debugaccess;   // master_avalon_universal_master_0_translator:uav_debugaccess -> master_avalon_universal_master_0_agent:av_debugaccess
	wire   [37:0] master_avalon_universal_master_0_translator_avalon_universal_master_0_address;       // master_avalon_universal_master_0_translator:uav_address -> master_avalon_universal_master_0_agent:av_address
	wire          master_avalon_universal_master_0_translator_avalon_universal_master_0_read;          // master_avalon_universal_master_0_translator:uav_read -> master_avalon_universal_master_0_agent:av_read
	wire    [3:0] master_avalon_universal_master_0_translator_avalon_universal_master_0_byteenable;    // master_avalon_universal_master_0_translator:uav_byteenable -> master_avalon_universal_master_0_agent:av_byteenable
	wire          master_avalon_universal_master_0_translator_avalon_universal_master_0_readdatavalid; // master_avalon_universal_master_0_agent:av_readdatavalid -> master_avalon_universal_master_0_translator:uav_readdatavalid
	wire          master_avalon_universal_master_0_translator_avalon_universal_master_0_lock;          // master_avalon_universal_master_0_translator:uav_lock -> master_avalon_universal_master_0_agent:av_lock
	wire          master_avalon_universal_master_0_translator_avalon_universal_master_0_write;         // master_avalon_universal_master_0_translator:uav_write -> master_avalon_universal_master_0_agent:av_write
	wire   [31:0] master_avalon_universal_master_0_translator_avalon_universal_master_0_writedata;     // master_avalon_universal_master_0_translator:uav_writedata -> master_avalon_universal_master_0_agent:av_writedata
	wire    [9:0] master_avalon_universal_master_0_translator_avalon_universal_master_0_burstcount;    // master_avalon_universal_master_0_translator:uav_burstcount -> master_avalon_universal_master_0_agent:av_burstcount
	wire   [31:0] slave0_avalon_universal_slave_0_agent_m0_readdata;                                   // slave0_avalon_universal_slave_0_translator:uav_readdata -> slave0_avalon_universal_slave_0_agent:m0_readdata
	wire          slave0_avalon_universal_slave_0_agent_m0_waitrequest;                                // slave0_avalon_universal_slave_0_translator:uav_waitrequest -> slave0_avalon_universal_slave_0_agent:m0_waitrequest
	wire          slave0_avalon_universal_slave_0_agent_m0_debugaccess;                                // slave0_avalon_universal_slave_0_agent:m0_debugaccess -> slave0_avalon_universal_slave_0_translator:uav_debugaccess
	wire   [37:0] slave0_avalon_universal_slave_0_agent_m0_address;                                    // slave0_avalon_universal_slave_0_agent:m0_address -> slave0_avalon_universal_slave_0_translator:uav_address
	wire    [3:0] slave0_avalon_universal_slave_0_agent_m0_byteenable;                                 // slave0_avalon_universal_slave_0_agent:m0_byteenable -> slave0_avalon_universal_slave_0_translator:uav_byteenable
	wire          slave0_avalon_universal_slave_0_agent_m0_read;                                       // slave0_avalon_universal_slave_0_agent:m0_read -> slave0_avalon_universal_slave_0_translator:uav_read
	wire          slave0_avalon_universal_slave_0_agent_m0_readdatavalid;                              // slave0_avalon_universal_slave_0_translator:uav_readdatavalid -> slave0_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          slave0_avalon_universal_slave_0_agent_m0_lock;                                       // slave0_avalon_universal_slave_0_agent:m0_lock -> slave0_avalon_universal_slave_0_translator:uav_lock
	wire   [31:0] slave0_avalon_universal_slave_0_agent_m0_writedata;                                  // slave0_avalon_universal_slave_0_agent:m0_writedata -> slave0_avalon_universal_slave_0_translator:uav_writedata
	wire          slave0_avalon_universal_slave_0_agent_m0_write;                                      // slave0_avalon_universal_slave_0_agent:m0_write -> slave0_avalon_universal_slave_0_translator:uav_write
	wire    [3:0] slave0_avalon_universal_slave_0_agent_m0_burstcount;                                 // slave0_avalon_universal_slave_0_agent:m0_burstcount -> slave0_avalon_universal_slave_0_translator:uav_burstcount
	wire          slave0_avalon_universal_slave_0_agent_rf_source_valid;                               // slave0_avalon_universal_slave_0_agent:rf_source_valid -> slave0_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire  [115:0] slave0_avalon_universal_slave_0_agent_rf_source_data;                                // slave0_avalon_universal_slave_0_agent:rf_source_data -> slave0_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          slave0_avalon_universal_slave_0_agent_rf_source_ready;                               // slave0_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> slave0_avalon_universal_slave_0_agent:rf_source_ready
	wire          slave0_avalon_universal_slave_0_agent_rf_source_startofpacket;                       // slave0_avalon_universal_slave_0_agent:rf_source_startofpacket -> slave0_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire          slave0_avalon_universal_slave_0_agent_rf_source_endofpacket;                         // slave0_avalon_universal_slave_0_agent:rf_source_endofpacket -> slave0_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          slave0_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                            // slave0_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> slave0_avalon_universal_slave_0_agent:rf_sink_valid
	wire  [115:0] slave0_avalon_universal_slave_0_agent_rsp_fifo_out_data;                             // slave0_avalon_universal_slave_0_agent_rsp_fifo:out_data -> slave0_avalon_universal_slave_0_agent:rf_sink_data
	wire          slave0_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                            // slave0_avalon_universal_slave_0_agent:rf_sink_ready -> slave0_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          slave0_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                    // slave0_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> slave0_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire          slave0_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                      // slave0_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> slave0_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire   [31:0] slave1_avalon_universal_slave_0_agent_m0_readdata;                                   // slave1_avalon_universal_slave_0_translator:uav_readdata -> slave1_avalon_universal_slave_0_agent:m0_readdata
	wire          slave1_avalon_universal_slave_0_agent_m0_waitrequest;                                // slave1_avalon_universal_slave_0_translator:uav_waitrequest -> slave1_avalon_universal_slave_0_agent:m0_waitrequest
	wire          slave1_avalon_universal_slave_0_agent_m0_debugaccess;                                // slave1_avalon_universal_slave_0_agent:m0_debugaccess -> slave1_avalon_universal_slave_0_translator:uav_debugaccess
	wire   [37:0] slave1_avalon_universal_slave_0_agent_m0_address;                                    // slave1_avalon_universal_slave_0_agent:m0_address -> slave1_avalon_universal_slave_0_translator:uav_address
	wire    [3:0] slave1_avalon_universal_slave_0_agent_m0_byteenable;                                 // slave1_avalon_universal_slave_0_agent:m0_byteenable -> slave1_avalon_universal_slave_0_translator:uav_byteenable
	wire          slave1_avalon_universal_slave_0_agent_m0_read;                                       // slave1_avalon_universal_slave_0_agent:m0_read -> slave1_avalon_universal_slave_0_translator:uav_read
	wire          slave1_avalon_universal_slave_0_agent_m0_readdatavalid;                              // slave1_avalon_universal_slave_0_translator:uav_readdatavalid -> slave1_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          slave1_avalon_universal_slave_0_agent_m0_lock;                                       // slave1_avalon_universal_slave_0_agent:m0_lock -> slave1_avalon_universal_slave_0_translator:uav_lock
	wire   [31:0] slave1_avalon_universal_slave_0_agent_m0_writedata;                                  // slave1_avalon_universal_slave_0_agent:m0_writedata -> slave1_avalon_universal_slave_0_translator:uav_writedata
	wire          slave1_avalon_universal_slave_0_agent_m0_write;                                      // slave1_avalon_universal_slave_0_agent:m0_write -> slave1_avalon_universal_slave_0_translator:uav_write
	wire    [3:0] slave1_avalon_universal_slave_0_agent_m0_burstcount;                                 // slave1_avalon_universal_slave_0_agent:m0_burstcount -> slave1_avalon_universal_slave_0_translator:uav_burstcount
	wire          slave1_avalon_universal_slave_0_agent_rf_source_valid;                               // slave1_avalon_universal_slave_0_agent:rf_source_valid -> slave1_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire  [115:0] slave1_avalon_universal_slave_0_agent_rf_source_data;                                // slave1_avalon_universal_slave_0_agent:rf_source_data -> slave1_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          slave1_avalon_universal_slave_0_agent_rf_source_ready;                               // slave1_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> slave1_avalon_universal_slave_0_agent:rf_source_ready
	wire          slave1_avalon_universal_slave_0_agent_rf_source_startofpacket;                       // slave1_avalon_universal_slave_0_agent:rf_source_startofpacket -> slave1_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire          slave1_avalon_universal_slave_0_agent_rf_source_endofpacket;                         // slave1_avalon_universal_slave_0_agent:rf_source_endofpacket -> slave1_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          slave1_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                            // slave1_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> slave1_avalon_universal_slave_0_agent:rf_sink_valid
	wire  [115:0] slave1_avalon_universal_slave_0_agent_rsp_fifo_out_data;                             // slave1_avalon_universal_slave_0_agent_rsp_fifo:out_data -> slave1_avalon_universal_slave_0_agent:rf_sink_data
	wire          slave1_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                            // slave1_avalon_universal_slave_0_agent:rf_sink_ready -> slave1_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          slave1_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                    // slave1_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> slave1_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire          slave1_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                      // slave1_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> slave1_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          master_avalon_universal_master_0_agent_cp_valid;                                     // master_avalon_universal_master_0_agent:cp_valid -> router:sink_valid
	wire  [114:0] master_avalon_universal_master_0_agent_cp_data;                                      // master_avalon_universal_master_0_agent:cp_data -> router:sink_data
	wire          master_avalon_universal_master_0_agent_cp_ready;                                     // router:sink_ready -> master_avalon_universal_master_0_agent:cp_ready
	wire          master_avalon_universal_master_0_agent_cp_startofpacket;                             // master_avalon_universal_master_0_agent:cp_startofpacket -> router:sink_startofpacket
	wire          master_avalon_universal_master_0_agent_cp_endofpacket;                               // master_avalon_universal_master_0_agent:cp_endofpacket -> router:sink_endofpacket
	wire          slave0_avalon_universal_slave_0_agent_rp_valid;                                      // slave0_avalon_universal_slave_0_agent:rp_valid -> router_001:sink_valid
	wire  [114:0] slave0_avalon_universal_slave_0_agent_rp_data;                                       // slave0_avalon_universal_slave_0_agent:rp_data -> router_001:sink_data
	wire          slave0_avalon_universal_slave_0_agent_rp_ready;                                      // router_001:sink_ready -> slave0_avalon_universal_slave_0_agent:rp_ready
	wire          slave0_avalon_universal_slave_0_agent_rp_startofpacket;                              // slave0_avalon_universal_slave_0_agent:rp_startofpacket -> router_001:sink_startofpacket
	wire          slave0_avalon_universal_slave_0_agent_rp_endofpacket;                                // slave0_avalon_universal_slave_0_agent:rp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                                // router_001:src_valid -> rsp_demux:sink_valid
	wire  [114:0] router_001_src_data;                                                                 // router_001:src_data -> rsp_demux:sink_data
	wire          router_001_src_ready;                                                                // rsp_demux:sink_ready -> router_001:src_ready
	wire    [1:0] router_001_src_channel;                                                              // router_001:src_channel -> rsp_demux:sink_channel
	wire          router_001_src_startofpacket;                                                        // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_001_src_endofpacket;                                                          // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          slave1_avalon_universal_slave_0_agent_rp_valid;                                      // slave1_avalon_universal_slave_0_agent:rp_valid -> router_002:sink_valid
	wire  [114:0] slave1_avalon_universal_slave_0_agent_rp_data;                                       // slave1_avalon_universal_slave_0_agent:rp_data -> router_002:sink_data
	wire          slave1_avalon_universal_slave_0_agent_rp_ready;                                      // router_002:sink_ready -> slave1_avalon_universal_slave_0_agent:rp_ready
	wire          slave1_avalon_universal_slave_0_agent_rp_startofpacket;                              // slave1_avalon_universal_slave_0_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire          slave1_avalon_universal_slave_0_agent_rp_endofpacket;                                // slave1_avalon_universal_slave_0_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire          router_002_src_valid;                                                                // router_002:src_valid -> rsp_demux_001:sink_valid
	wire  [114:0] router_002_src_data;                                                                 // router_002:src_data -> rsp_demux_001:sink_data
	wire          router_002_src_ready;                                                                // rsp_demux_001:sink_ready -> router_002:src_ready
	wire    [1:0] router_002_src_channel;                                                              // router_002:src_channel -> rsp_demux_001:sink_channel
	wire          router_002_src_startofpacket;                                                        // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_002_src_endofpacket;                                                          // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          router_src_valid;                                                                    // router:src_valid -> master_avalon_universal_master_0_limiter:cmd_sink_valid
	wire  [114:0] router_src_data;                                                                     // router:src_data -> master_avalon_universal_master_0_limiter:cmd_sink_data
	wire          router_src_ready;                                                                    // master_avalon_universal_master_0_limiter:cmd_sink_ready -> router:src_ready
	wire    [1:0] router_src_channel;                                                                  // router:src_channel -> master_avalon_universal_master_0_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                                            // router:src_startofpacket -> master_avalon_universal_master_0_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                                              // router:src_endofpacket -> master_avalon_universal_master_0_limiter:cmd_sink_endofpacket
	wire  [114:0] master_avalon_universal_master_0_limiter_cmd_src_data;                               // master_avalon_universal_master_0_limiter:cmd_src_data -> cmd_demux:sink_data
	wire          master_avalon_universal_master_0_limiter_cmd_src_ready;                              // cmd_demux:sink_ready -> master_avalon_universal_master_0_limiter:cmd_src_ready
	wire    [1:0] master_avalon_universal_master_0_limiter_cmd_src_channel;                            // master_avalon_universal_master_0_limiter:cmd_src_channel -> cmd_demux:sink_channel
	wire          master_avalon_universal_master_0_limiter_cmd_src_startofpacket;                      // master_avalon_universal_master_0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
	wire          master_avalon_universal_master_0_limiter_cmd_src_endofpacket;                        // master_avalon_universal_master_0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                                                   // rsp_mux:src_valid -> master_avalon_universal_master_0_limiter:rsp_sink_valid
	wire  [114:0] rsp_mux_src_data;                                                                    // rsp_mux:src_data -> master_avalon_universal_master_0_limiter:rsp_sink_data
	wire          rsp_mux_src_ready;                                                                   // master_avalon_universal_master_0_limiter:rsp_sink_ready -> rsp_mux:src_ready
	wire    [1:0] rsp_mux_src_channel;                                                                 // rsp_mux:src_channel -> master_avalon_universal_master_0_limiter:rsp_sink_channel
	wire          rsp_mux_src_startofpacket;                                                           // rsp_mux:src_startofpacket -> master_avalon_universal_master_0_limiter:rsp_sink_startofpacket
	wire          rsp_mux_src_endofpacket;                                                             // rsp_mux:src_endofpacket -> master_avalon_universal_master_0_limiter:rsp_sink_endofpacket
	wire          master_avalon_universal_master_0_limiter_rsp_src_valid;                              // master_avalon_universal_master_0_limiter:rsp_src_valid -> master_avalon_universal_master_0_agent:rp_valid
	wire  [114:0] master_avalon_universal_master_0_limiter_rsp_src_data;                               // master_avalon_universal_master_0_limiter:rsp_src_data -> master_avalon_universal_master_0_agent:rp_data
	wire          master_avalon_universal_master_0_limiter_rsp_src_ready;                              // master_avalon_universal_master_0_agent:rp_ready -> master_avalon_universal_master_0_limiter:rsp_src_ready
	wire    [1:0] master_avalon_universal_master_0_limiter_rsp_src_channel;                            // master_avalon_universal_master_0_limiter:rsp_src_channel -> master_avalon_universal_master_0_agent:rp_channel
	wire          master_avalon_universal_master_0_limiter_rsp_src_startofpacket;                      // master_avalon_universal_master_0_limiter:rsp_src_startofpacket -> master_avalon_universal_master_0_agent:rp_startofpacket
	wire          master_avalon_universal_master_0_limiter_rsp_src_endofpacket;                        // master_avalon_universal_master_0_limiter:rsp_src_endofpacket -> master_avalon_universal_master_0_agent:rp_endofpacket
	wire          cmd_mux_src_valid;                                                                   // cmd_mux:src_valid -> slave0_avalon_universal_slave_0_burst_adapter:sink0_valid
	wire  [114:0] cmd_mux_src_data;                                                                    // cmd_mux:src_data -> slave0_avalon_universal_slave_0_burst_adapter:sink0_data
	wire          cmd_mux_src_ready;                                                                   // slave0_avalon_universal_slave_0_burst_adapter:sink0_ready -> cmd_mux:src_ready
	wire    [1:0] cmd_mux_src_channel;                                                                 // cmd_mux:src_channel -> slave0_avalon_universal_slave_0_burst_adapter:sink0_channel
	wire          cmd_mux_src_startofpacket;                                                           // cmd_mux:src_startofpacket -> slave0_avalon_universal_slave_0_burst_adapter:sink0_startofpacket
	wire          cmd_mux_src_endofpacket;                                                             // cmd_mux:src_endofpacket -> slave0_avalon_universal_slave_0_burst_adapter:sink0_endofpacket
	wire          slave0_avalon_universal_slave_0_burst_adapter_source0_valid;                         // slave0_avalon_universal_slave_0_burst_adapter:source0_valid -> slave0_avalon_universal_slave_0_agent:cp_valid
	wire  [114:0] slave0_avalon_universal_slave_0_burst_adapter_source0_data;                          // slave0_avalon_universal_slave_0_burst_adapter:source0_data -> slave0_avalon_universal_slave_0_agent:cp_data
	wire          slave0_avalon_universal_slave_0_burst_adapter_source0_ready;                         // slave0_avalon_universal_slave_0_agent:cp_ready -> slave0_avalon_universal_slave_0_burst_adapter:source0_ready
	wire    [1:0] slave0_avalon_universal_slave_0_burst_adapter_source0_channel;                       // slave0_avalon_universal_slave_0_burst_adapter:source0_channel -> slave0_avalon_universal_slave_0_agent:cp_channel
	wire          slave0_avalon_universal_slave_0_burst_adapter_source0_startofpacket;                 // slave0_avalon_universal_slave_0_burst_adapter:source0_startofpacket -> slave0_avalon_universal_slave_0_agent:cp_startofpacket
	wire          slave0_avalon_universal_slave_0_burst_adapter_source0_endofpacket;                   // slave0_avalon_universal_slave_0_burst_adapter:source0_endofpacket -> slave0_avalon_universal_slave_0_agent:cp_endofpacket
	wire          cmd_mux_001_src_valid;                                                               // cmd_mux_001:src_valid -> slave1_avalon_universal_slave_0_burst_adapter:sink0_valid
	wire  [114:0] cmd_mux_001_src_data;                                                                // cmd_mux_001:src_data -> slave1_avalon_universal_slave_0_burst_adapter:sink0_data
	wire          cmd_mux_001_src_ready;                                                               // slave1_avalon_universal_slave_0_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
	wire    [1:0] cmd_mux_001_src_channel;                                                             // cmd_mux_001:src_channel -> slave1_avalon_universal_slave_0_burst_adapter:sink0_channel
	wire          cmd_mux_001_src_startofpacket;                                                       // cmd_mux_001:src_startofpacket -> slave1_avalon_universal_slave_0_burst_adapter:sink0_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                                         // cmd_mux_001:src_endofpacket -> slave1_avalon_universal_slave_0_burst_adapter:sink0_endofpacket
	wire          slave1_avalon_universal_slave_0_burst_adapter_source0_valid;                         // slave1_avalon_universal_slave_0_burst_adapter:source0_valid -> slave1_avalon_universal_slave_0_agent:cp_valid
	wire  [114:0] slave1_avalon_universal_slave_0_burst_adapter_source0_data;                          // slave1_avalon_universal_slave_0_burst_adapter:source0_data -> slave1_avalon_universal_slave_0_agent:cp_data
	wire          slave1_avalon_universal_slave_0_burst_adapter_source0_ready;                         // slave1_avalon_universal_slave_0_agent:cp_ready -> slave1_avalon_universal_slave_0_burst_adapter:source0_ready
	wire    [1:0] slave1_avalon_universal_slave_0_burst_adapter_source0_channel;                       // slave1_avalon_universal_slave_0_burst_adapter:source0_channel -> slave1_avalon_universal_slave_0_agent:cp_channel
	wire          slave1_avalon_universal_slave_0_burst_adapter_source0_startofpacket;                 // slave1_avalon_universal_slave_0_burst_adapter:source0_startofpacket -> slave1_avalon_universal_slave_0_agent:cp_startofpacket
	wire          slave1_avalon_universal_slave_0_burst_adapter_source0_endofpacket;                   // slave1_avalon_universal_slave_0_burst_adapter:source0_endofpacket -> slave1_avalon_universal_slave_0_agent:cp_endofpacket
	wire          cmd_demux_src0_valid;                                                                // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [114:0] cmd_demux_src0_data;                                                                 // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                                // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [1:0] cmd_demux_src0_channel;                                                              // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                                        // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                          // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                                // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire  [114:0] cmd_demux_src1_data;                                                                 // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_src1_ready;                                                                // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire    [1:0] cmd_demux_src1_channel;                                                              // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_src1_startofpacket;                                                        // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_src1_endofpacket;                                                          // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                                // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [114:0] rsp_demux_src0_data;                                                                 // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                                // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [1:0] rsp_demux_src0_channel;                                                              // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                                        // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                          // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                            // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire  [114:0] rsp_demux_001_src0_data;                                                             // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire          rsp_demux_001_src0_ready;                                                            // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire    [1:0] rsp_demux_001_src0_channel;                                                          // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                                                    // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                                      // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire    [1:0] master_avalon_universal_master_0_limiter_cmd_valid_data;                             // master_avalon_universal_master_0_limiter:cmd_src_valid -> cmd_demux:sink_valid
	wire          slave0_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                          // slave0_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
	wire   [33:0] slave0_avalon_universal_slave_0_agent_rdata_fifo_src_data;                           // slave0_avalon_universal_slave_0_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
	wire          slave0_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                          // avalon_st_adapter:in_0_ready -> slave0_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_out_0_valid;                                                       // avalon_st_adapter:out_0_valid -> slave0_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_out_0_data;                                                        // avalon_st_adapter:out_0_data -> slave0_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                                       // slave0_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                                       // avalon_st_adapter:out_0_error -> slave0_avalon_universal_slave_0_agent:rdata_fifo_sink_error
	wire          slave1_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                          // slave1_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
	wire   [33:0] slave1_avalon_universal_slave_0_agent_rdata_fifo_src_data;                           // slave1_avalon_universal_slave_0_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
	wire          slave1_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                          // avalon_st_adapter_001:in_0_ready -> slave1_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_001_out_0_valid;                                                   // avalon_st_adapter_001:out_0_valid -> slave1_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_001_out_0_data;                                                    // avalon_st_adapter_001:out_0_data -> slave1_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_001_out_0_ready;                                                   // slave1_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
	wire    [0:0] avalon_st_adapter_001_out_0_error;                                                   // avalon_st_adapter_001:out_0_error -> slave1_avalon_universal_slave_0_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (38),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (10),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (38),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (1),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) master_avalon_universal_master_0_translator (
		.clk                    (clk_0_clk_clk),                                                                       //                       clk.clk
		.reset                  (master_reset_reset_bridge_in_reset_reset),                                            //                     reset.reset
		.uav_address            (master_avalon_universal_master_0_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (master_avalon_universal_master_0_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (master_avalon_universal_master_0_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (master_avalon_universal_master_0_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (master_avalon_universal_master_0_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (master_avalon_universal_master_0_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (master_avalon_universal_master_0_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (master_avalon_universal_master_0_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (master_avalon_universal_master_0_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (master_avalon_universal_master_0_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (master_avalon_universal_master_0_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (master_avalon_universal_master_0_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (master_avalon_universal_master_0_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (master_avalon_universal_master_0_burstcount),                                         //                          .burstcount
		.av_byteenable          (master_avalon_universal_master_0_byteenable),                                         //                          .byteenable
		.av_read                (master_avalon_universal_master_0_read),                                               //                          .read
		.av_readdata            (master_avalon_universal_master_0_readdata),                                           //                          .readdata
		.av_readdatavalid       (master_avalon_universal_master_0_readdatavalid),                                      //                          .readdatavalid
		.av_write               (master_avalon_universal_master_0_write),                                              //                          .write
		.av_writedata           (master_avalon_universal_master_0_writedata),                                          //                          .writedata
		.av_lock                (master_avalon_universal_master_0_lock),                                               //                          .lock
		.av_debugaccess         (master_avalon_universal_master_0_debugaccess),                                        //                          .debugaccess
		.av_beginbursttransfer  (1'b0),                                                                                //               (terminated)
		.av_begintransfer       (1'b0),                                                                                //               (terminated)
		.av_chipselect          (1'b0),                                                                                //               (terminated)
		.uav_clken              (),                                                                                    //               (terminated)
		.av_clken               (1'b1),                                                                                //               (terminated)
		.uav_response           (2'b00),                                                                               //               (terminated)
		.av_response            (),                                                                                    //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                                //               (terminated)
		.av_writeresponsevalid  ()                                                                                     //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (32),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (4),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (38),
		.UAV_BURSTCOUNT_W               (4),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (1),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) slave0_avalon_universal_slave_0_translator (
		.clk                    (clk_0_clk_clk),                                          //                      clk.clk
		.reset                  (master_reset_reset_bridge_in_reset_reset),               //                    reset.reset
		.uav_address            (slave0_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (slave0_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (slave0_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write              (slave0_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest        (slave0_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (slave0_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (slave0_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (slave0_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (slave0_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock               (slave0_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (slave0_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (slave0_avalon_universal_slave_0_address),                //      avalon_anti_slave_0.address
		.av_write               (slave0_avalon_universal_slave_0_write),                  //                         .write
		.av_read                (slave0_avalon_universal_slave_0_read),                   //                         .read
		.av_readdata            (slave0_avalon_universal_slave_0_readdata),               //                         .readdata
		.av_writedata           (slave0_avalon_universal_slave_0_writedata),              //                         .writedata
		.av_burstcount          (slave0_avalon_universal_slave_0_burstcount),             //                         .burstcount
		.av_byteenable          (slave0_avalon_universal_slave_0_byteenable),             //                         .byteenable
		.av_readdatavalid       (slave0_avalon_universal_slave_0_readdatavalid),          //                         .readdatavalid
		.av_waitrequest         (slave0_avalon_universal_slave_0_waitrequest),            //                         .waitrequest
		.av_lock                (slave0_avalon_universal_slave_0_lock),                   //                         .lock
		.av_debugaccess         (slave0_avalon_universal_slave_0_debugaccess),            //                         .debugaccess
		.av_begintransfer       (),                                                       //              (terminated)
		.av_beginbursttransfer  (),                                                       //              (terminated)
		.av_writebyteenable     (),                                                       //              (terminated)
		.av_chipselect          (),                                                       //              (terminated)
		.av_clken               (),                                                       //              (terminated)
		.uav_clken              (1'b0),                                                   //              (terminated)
		.av_outputenable        (),                                                       //              (terminated)
		.uav_response           (),                                                       //              (terminated)
		.av_response            (2'b00),                                                  //              (terminated)
		.uav_writeresponsevalid (),                                                       //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                    //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (32),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (4),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (38),
		.UAV_BURSTCOUNT_W               (4),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (1),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) slave1_avalon_universal_slave_0_translator (
		.clk                    (clk_0_clk_clk),                                          //                      clk.clk
		.reset                  (master_reset_reset_bridge_in_reset_reset),               //                    reset.reset
		.uav_address            (slave1_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (slave1_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (slave1_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write              (slave1_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest        (slave1_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (slave1_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (slave1_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (slave1_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (slave1_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock               (slave1_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (slave1_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (slave1_avalon_universal_slave_0_address),                //      avalon_anti_slave_0.address
		.av_write               (slave1_avalon_universal_slave_0_write),                  //                         .write
		.av_read                (slave1_avalon_universal_slave_0_read),                   //                         .read
		.av_readdata            (slave1_avalon_universal_slave_0_readdata),               //                         .readdata
		.av_writedata           (slave1_avalon_universal_slave_0_writedata),              //                         .writedata
		.av_burstcount          (slave1_avalon_universal_slave_0_burstcount),             //                         .burstcount
		.av_byteenable          (slave1_avalon_universal_slave_0_byteenable),             //                         .byteenable
		.av_readdatavalid       (slave1_avalon_universal_slave_0_readdatavalid),          //                         .readdatavalid
		.av_waitrequest         (slave1_avalon_universal_slave_0_waitrequest),            //                         .waitrequest
		.av_lock                (slave1_avalon_universal_slave_0_lock),                   //                         .lock
		.av_debugaccess         (slave1_avalon_universal_slave_0_debugaccess),            //                         .debugaccess
		.av_begintransfer       (),                                                       //              (terminated)
		.av_beginbursttransfer  (),                                                       //              (terminated)
		.av_writebyteenable     (),                                                       //              (terminated)
		.av_chipselect          (),                                                       //              (terminated)
		.av_clken               (),                                                       //              (terminated)
		.uav_clken              (1'b0),                                                   //              (terminated)
		.av_outputenable        (),                                                       //              (terminated)
		.uav_response           (),                                                       //              (terminated)
		.av_response            (2'b00),                                                  //              (terminated)
		.uav_writeresponsevalid (),                                                       //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                    //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (114),
		.PKT_ORI_BURST_SIZE_L      (112),
		.PKT_RESPONSE_STATUS_H     (111),
		.PKT_RESPONSE_STATUS_L     (110),
		.PKT_QOS_H                 (99),
		.PKT_QOS_L                 (99),
		.PKT_DATA_SIDEBAND_H       (97),
		.PKT_DATA_SIDEBAND_L       (97),
		.PKT_ADDR_SIDEBAND_H       (96),
		.PKT_ADDR_SIDEBAND_L       (96),
		.PKT_BURST_TYPE_H          (95),
		.PKT_BURST_TYPE_L          (94),
		.PKT_CACHE_H               (109),
		.PKT_CACHE_L               (106),
		.PKT_THREAD_ID_H           (102),
		.PKT_THREAD_ID_L           (102),
		.PKT_BURST_SIZE_H          (93),
		.PKT_BURST_SIZE_L          (91),
		.PKT_TRANS_EXCLUSIVE       (79),
		.PKT_TRANS_LOCK            (78),
		.PKT_BEGIN_BURST           (98),
		.PKT_PROTECTION_H          (105),
		.PKT_PROTECTION_L          (103),
		.PKT_BURSTWRAP_H           (90),
		.PKT_BURSTWRAP_L           (90),
		.PKT_BYTE_CNT_H            (89),
		.PKT_BYTE_CNT_L            (80),
		.PKT_ADDR_H                (73),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (74),
		.PKT_TRANS_POSTED          (75),
		.PKT_TRANS_WRITE           (76),
		.PKT_TRANS_READ            (77),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (100),
		.PKT_SRC_ID_L              (100),
		.PKT_DEST_ID_H             (101),
		.PKT_DEST_ID_L             (101),
		.ST_DATA_W                 (115),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) master_avalon_universal_master_0_agent (
		.clk                   (clk_0_clk_clk),                                                                       //       clk.clk
		.reset                 (master_reset_reset_bridge_in_reset_reset),                                            // clk_reset.reset
		.av_address            (master_avalon_universal_master_0_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (master_avalon_universal_master_0_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (master_avalon_universal_master_0_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (master_avalon_universal_master_0_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (master_avalon_universal_master_0_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (master_avalon_universal_master_0_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (master_avalon_universal_master_0_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (master_avalon_universal_master_0_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (master_avalon_universal_master_0_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (master_avalon_universal_master_0_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (master_avalon_universal_master_0_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (master_avalon_universal_master_0_agent_cp_valid),                                     //        cp.valid
		.cp_data               (master_avalon_universal_master_0_agent_cp_data),                                      //          .data
		.cp_startofpacket      (master_avalon_universal_master_0_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (master_avalon_universal_master_0_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (master_avalon_universal_master_0_agent_cp_ready),                                     //          .ready
		.rp_valid              (master_avalon_universal_master_0_limiter_rsp_src_valid),                              //        rp.valid
		.rp_data               (master_avalon_universal_master_0_limiter_rsp_src_data),                               //          .data
		.rp_channel            (master_avalon_universal_master_0_limiter_rsp_src_channel),                            //          .channel
		.rp_startofpacket      (master_avalon_universal_master_0_limiter_rsp_src_startofpacket),                      //          .startofpacket
		.rp_endofpacket        (master_avalon_universal_master_0_limiter_rsp_src_endofpacket),                        //          .endofpacket
		.rp_ready              (master_avalon_universal_master_0_limiter_rsp_src_ready),                              //          .ready
		.av_response           (),                                                                                    // (terminated)
		.av_writeresponsevalid ()                                                                                     // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (114),
		.PKT_ORI_BURST_SIZE_L      (112),
		.PKT_RESPONSE_STATUS_H     (111),
		.PKT_RESPONSE_STATUS_L     (110),
		.PKT_BURST_SIZE_H          (93),
		.PKT_BURST_SIZE_L          (91),
		.PKT_TRANS_LOCK            (78),
		.PKT_BEGIN_BURST           (98),
		.PKT_PROTECTION_H          (105),
		.PKT_PROTECTION_L          (103),
		.PKT_BURSTWRAP_H           (90),
		.PKT_BURSTWRAP_L           (90),
		.PKT_BYTE_CNT_H            (89),
		.PKT_BYTE_CNT_L            (80),
		.PKT_ADDR_H                (73),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (74),
		.PKT_TRANS_POSTED          (75),
		.PKT_TRANS_WRITE           (76),
		.PKT_TRANS_READ            (77),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (100),
		.PKT_SRC_ID_L              (100),
		.PKT_DEST_ID_H             (101),
		.PKT_DEST_ID_L             (101),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (115),
		.AVS_BURSTCOUNT_W          (4),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) slave0_avalon_universal_slave_0_agent (
		.clk                     (clk_0_clk_clk),                                                       //             clk.clk
		.reset                   (master_reset_reset_bridge_in_reset_reset),                            //       clk_reset.reset
		.m0_address              (slave0_avalon_universal_slave_0_agent_m0_address),                    //              m0.address
		.m0_burstcount           (slave0_avalon_universal_slave_0_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (slave0_avalon_universal_slave_0_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (slave0_avalon_universal_slave_0_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (slave0_avalon_universal_slave_0_agent_m0_lock),                       //                .lock
		.m0_readdata             (slave0_avalon_universal_slave_0_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (slave0_avalon_universal_slave_0_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (slave0_avalon_universal_slave_0_agent_m0_read),                       //                .read
		.m0_waitrequest          (slave0_avalon_universal_slave_0_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (slave0_avalon_universal_slave_0_agent_m0_writedata),                  //                .writedata
		.m0_write                (slave0_avalon_universal_slave_0_agent_m0_write),                      //                .write
		.rp_endofpacket          (slave0_avalon_universal_slave_0_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (slave0_avalon_universal_slave_0_agent_rp_ready),                      //                .ready
		.rp_valid                (slave0_avalon_universal_slave_0_agent_rp_valid),                      //                .valid
		.rp_data                 (slave0_avalon_universal_slave_0_agent_rp_data),                       //                .data
		.rp_startofpacket        (slave0_avalon_universal_slave_0_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (slave0_avalon_universal_slave_0_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (slave0_avalon_universal_slave_0_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (slave0_avalon_universal_slave_0_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (slave0_avalon_universal_slave_0_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (slave0_avalon_universal_slave_0_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (slave0_avalon_universal_slave_0_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (slave0_avalon_universal_slave_0_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (slave0_avalon_universal_slave_0_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (slave0_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (slave0_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (slave0_avalon_universal_slave_0_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (slave0_avalon_universal_slave_0_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (slave0_avalon_universal_slave_0_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (slave0_avalon_universal_slave_0_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (slave0_avalon_universal_slave_0_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (slave0_avalon_universal_slave_0_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                       //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                        //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                       //                .error
		.rdata_fifo_src_ready    (slave0_avalon_universal_slave_0_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (slave0_avalon_universal_slave_0_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (slave0_avalon_universal_slave_0_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                               //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                 //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (116),
		.FIFO_DEPTH          (65),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) slave0_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (clk_0_clk_clk),                                                    //       clk.clk
		.reset             (master_reset_reset_bridge_in_reset_reset),                         // clk_reset.reset
		.in_data           (slave0_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (slave0_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (slave0_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (slave0_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (slave0_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (slave0_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (slave0_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (slave0_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (slave0_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (slave0_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                            // (terminated)
		.csr_read          (1'b0),                                                             // (terminated)
		.csr_write         (1'b0),                                                             // (terminated)
		.csr_readdata      (),                                                                 // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                             // (terminated)
		.almost_full_data  (),                                                                 // (terminated)
		.almost_empty_data (),                                                                 // (terminated)
		.in_empty          (1'b0),                                                             // (terminated)
		.out_empty         (),                                                                 // (terminated)
		.in_error          (1'b0),                                                             // (terminated)
		.out_error         (),                                                                 // (terminated)
		.in_channel        (1'b0),                                                             // (terminated)
		.out_channel       ()                                                                  // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (114),
		.PKT_ORI_BURST_SIZE_L      (112),
		.PKT_RESPONSE_STATUS_H     (111),
		.PKT_RESPONSE_STATUS_L     (110),
		.PKT_BURST_SIZE_H          (93),
		.PKT_BURST_SIZE_L          (91),
		.PKT_TRANS_LOCK            (78),
		.PKT_BEGIN_BURST           (98),
		.PKT_PROTECTION_H          (105),
		.PKT_PROTECTION_L          (103),
		.PKT_BURSTWRAP_H           (90),
		.PKT_BURSTWRAP_L           (90),
		.PKT_BYTE_CNT_H            (89),
		.PKT_BYTE_CNT_L            (80),
		.PKT_ADDR_H                (73),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (74),
		.PKT_TRANS_POSTED          (75),
		.PKT_TRANS_WRITE           (76),
		.PKT_TRANS_READ            (77),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (100),
		.PKT_SRC_ID_L              (100),
		.PKT_DEST_ID_H             (101),
		.PKT_DEST_ID_L             (101),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (115),
		.AVS_BURSTCOUNT_W          (4),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) slave1_avalon_universal_slave_0_agent (
		.clk                     (clk_0_clk_clk),                                                       //             clk.clk
		.reset                   (master_reset_reset_bridge_in_reset_reset),                            //       clk_reset.reset
		.m0_address              (slave1_avalon_universal_slave_0_agent_m0_address),                    //              m0.address
		.m0_burstcount           (slave1_avalon_universal_slave_0_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (slave1_avalon_universal_slave_0_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (slave1_avalon_universal_slave_0_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (slave1_avalon_universal_slave_0_agent_m0_lock),                       //                .lock
		.m0_readdata             (slave1_avalon_universal_slave_0_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (slave1_avalon_universal_slave_0_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (slave1_avalon_universal_slave_0_agent_m0_read),                       //                .read
		.m0_waitrequest          (slave1_avalon_universal_slave_0_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (slave1_avalon_universal_slave_0_agent_m0_writedata),                  //                .writedata
		.m0_write                (slave1_avalon_universal_slave_0_agent_m0_write),                      //                .write
		.rp_endofpacket          (slave1_avalon_universal_slave_0_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (slave1_avalon_universal_slave_0_agent_rp_ready),                      //                .ready
		.rp_valid                (slave1_avalon_universal_slave_0_agent_rp_valid),                      //                .valid
		.rp_data                 (slave1_avalon_universal_slave_0_agent_rp_data),                       //                .data
		.rp_startofpacket        (slave1_avalon_universal_slave_0_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (slave1_avalon_universal_slave_0_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (slave1_avalon_universal_slave_0_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (slave1_avalon_universal_slave_0_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (slave1_avalon_universal_slave_0_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (slave1_avalon_universal_slave_0_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (slave1_avalon_universal_slave_0_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (slave1_avalon_universal_slave_0_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (slave1_avalon_universal_slave_0_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (slave1_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (slave1_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (slave1_avalon_universal_slave_0_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (slave1_avalon_universal_slave_0_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (slave1_avalon_universal_slave_0_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (slave1_avalon_universal_slave_0_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (slave1_avalon_universal_slave_0_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (slave1_avalon_universal_slave_0_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),                                   // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),                                   //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),                                    //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),                                   //                .error
		.rdata_fifo_src_ready    (slave1_avalon_universal_slave_0_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (slave1_avalon_universal_slave_0_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (slave1_avalon_universal_slave_0_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                               //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                 //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (116),
		.FIFO_DEPTH          (65),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) slave1_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (clk_0_clk_clk),                                                    //       clk.clk
		.reset             (master_reset_reset_bridge_in_reset_reset),                         // clk_reset.reset
		.in_data           (slave1_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (slave1_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (slave1_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (slave1_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (slave1_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (slave1_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (slave1_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (slave1_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (slave1_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (slave1_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                            // (terminated)
		.csr_read          (1'b0),                                                             // (terminated)
		.csr_write         (1'b0),                                                             // (terminated)
		.csr_readdata      (),                                                                 // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                             // (terminated)
		.almost_full_data  (),                                                                 // (terminated)
		.almost_empty_data (),                                                                 // (terminated)
		.in_empty          (1'b0),                                                             // (terminated)
		.out_empty         (),                                                                 // (terminated)
		.in_error          (1'b0),                                                             // (terminated)
		.out_error         (),                                                                 // (terminated)
		.in_channel        (1'b0),                                                             // (terminated)
		.out_channel       ()                                                                  // (terminated)
	);

	intel_std_18_1_dummy_mm_interconnect_0_router router (
		.sink_ready         (master_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (master_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (master_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (master_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (master_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (clk_0_clk_clk),                                           //       clk.clk
		.reset              (master_reset_reset_bridge_in_reset_reset),                // clk_reset.reset
		.src_ready          (router_src_ready),                                        //       src.ready
		.src_valid          (router_src_valid),                                        //          .valid
		.src_data           (router_src_data),                                         //          .data
		.src_channel        (router_src_channel),                                      //          .channel
		.src_startofpacket  (router_src_startofpacket),                                //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                   //          .endofpacket
	);

	intel_std_18_1_dummy_mm_interconnect_0_router_001 router_001 (
		.sink_ready         (slave0_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (slave0_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (slave0_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (slave0_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (slave0_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_0_clk_clk),                                          //       clk.clk
		.reset              (master_reset_reset_bridge_in_reset_reset),               // clk_reset.reset
		.src_ready          (router_001_src_ready),                                   //       src.ready
		.src_valid          (router_001_src_valid),                                   //          .valid
		.src_data           (router_001_src_data),                                    //          .data
		.src_channel        (router_001_src_channel),                                 //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                           //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                              //          .endofpacket
	);

	intel_std_18_1_dummy_mm_interconnect_0_router_001 router_002 (
		.sink_ready         (slave1_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (slave1_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (slave1_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (slave1_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (slave1_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_0_clk_clk),                                          //       clk.clk
		.reset              (master_reset_reset_bridge_in_reset_reset),               // clk_reset.reset
		.src_ready          (router_002_src_ready),                                   //       src.ready
		.src_valid          (router_002_src_valid),                                   //          .valid
		.src_data           (router_002_src_data),                                    //          .data
		.src_channel        (router_002_src_channel),                                 //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                           //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                              //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (101),
		.PKT_DEST_ID_L             (101),
		.PKT_SRC_ID_H              (100),
		.PKT_SRC_ID_L              (100),
		.PKT_BYTE_CNT_H            (89),
		.PKT_BYTE_CNT_L            (80),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_TRANS_POSTED          (75),
		.PKT_TRANS_WRITE           (76),
		.MAX_OUTSTANDING_RESPONSES (64),
		.PIPELINED                 (0),
		.ST_DATA_W                 (115),
		.ST_CHANNEL_W              (2),
		.VALID_WIDTH               (2),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.SUPPORTS_POSTED_WRITES    (1),
		.SUPPORTS_NONPOSTED_WRITES (0),
		.REORDER                   (0)
	) master_avalon_universal_master_0_limiter (
		.clk                    (clk_0_clk_clk),                                                  //       clk.clk
		.reset                  (master_reset_reset_bridge_in_reset_reset),                       // clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                               //  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                               //          .valid
		.cmd_sink_data          (router_src_data),                                                //          .data
		.cmd_sink_channel       (router_src_channel),                                             //          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                                       //          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                         //          .endofpacket
		.cmd_src_ready          (master_avalon_universal_master_0_limiter_cmd_src_ready),         //   cmd_src.ready
		.cmd_src_data           (master_avalon_universal_master_0_limiter_cmd_src_data),          //          .data
		.cmd_src_channel        (master_avalon_universal_master_0_limiter_cmd_src_channel),       //          .channel
		.cmd_src_startofpacket  (master_avalon_universal_master_0_limiter_cmd_src_startofpacket), //          .startofpacket
		.cmd_src_endofpacket    (master_avalon_universal_master_0_limiter_cmd_src_endofpacket),   //          .endofpacket
		.rsp_sink_ready         (rsp_mux_src_ready),                                              //  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_src_valid),                                              //          .valid
		.rsp_sink_channel       (rsp_mux_src_channel),                                            //          .channel
		.rsp_sink_data          (rsp_mux_src_data),                                               //          .data
		.rsp_sink_startofpacket (rsp_mux_src_startofpacket),                                      //          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_src_endofpacket),                                        //          .endofpacket
		.rsp_src_ready          (master_avalon_universal_master_0_limiter_rsp_src_ready),         //   rsp_src.ready
		.rsp_src_valid          (master_avalon_universal_master_0_limiter_rsp_src_valid),         //          .valid
		.rsp_src_data           (master_avalon_universal_master_0_limiter_rsp_src_data),          //          .data
		.rsp_src_channel        (master_avalon_universal_master_0_limiter_rsp_src_channel),       //          .channel
		.rsp_src_startofpacket  (master_avalon_universal_master_0_limiter_rsp_src_startofpacket), //          .startofpacket
		.rsp_src_endofpacket    (master_avalon_universal_master_0_limiter_rsp_src_endofpacket),   //          .endofpacket
		.cmd_src_valid          (master_avalon_universal_master_0_limiter_cmd_valid_data)         // cmd_valid.data
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (73),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (98),
		.PKT_BYTE_CNT_H            (89),
		.PKT_BYTE_CNT_L            (80),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (93),
		.PKT_BURST_SIZE_L          (91),
		.PKT_BURST_TYPE_H          (95),
		.PKT_BURST_TYPE_L          (94),
		.PKT_BURSTWRAP_H           (90),
		.PKT_BURSTWRAP_L           (90),
		.PKT_TRANS_COMPRESSED_READ (74),
		.PKT_TRANS_WRITE           (76),
		.PKT_TRANS_READ            (77),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (115),
		.ST_CHANNEL_W              (2),
		.OUT_BYTE_CNT_H            (83),
		.OUT_BURSTWRAP_H           (90),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (1),
		.BURSTWRAP_CONST_VALUE     (1),
		.ADAPTER_VERSION           ("13.1")
	) slave0_avalon_universal_slave_0_burst_adapter (
		.clk                   (clk_0_clk_clk),                                                       //       cr0.clk
		.reset                 (master_reset_reset_bridge_in_reset_reset),                            // cr0_reset.reset
		.sink0_valid           (cmd_mux_src_valid),                                                   //     sink0.valid
		.sink0_data            (cmd_mux_src_data),                                                    //          .data
		.sink0_channel         (cmd_mux_src_channel),                                                 //          .channel
		.sink0_startofpacket   (cmd_mux_src_startofpacket),                                           //          .startofpacket
		.sink0_endofpacket     (cmd_mux_src_endofpacket),                                             //          .endofpacket
		.sink0_ready           (cmd_mux_src_ready),                                                   //          .ready
		.source0_valid         (slave0_avalon_universal_slave_0_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (slave0_avalon_universal_slave_0_burst_adapter_source0_data),          //          .data
		.source0_channel       (slave0_avalon_universal_slave_0_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (slave0_avalon_universal_slave_0_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (slave0_avalon_universal_slave_0_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (slave0_avalon_universal_slave_0_burst_adapter_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (73),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (98),
		.PKT_BYTE_CNT_H            (89),
		.PKT_BYTE_CNT_L            (80),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (93),
		.PKT_BURST_SIZE_L          (91),
		.PKT_BURST_TYPE_H          (95),
		.PKT_BURST_TYPE_L          (94),
		.PKT_BURSTWRAP_H           (90),
		.PKT_BURSTWRAP_L           (90),
		.PKT_TRANS_COMPRESSED_READ (74),
		.PKT_TRANS_WRITE           (76),
		.PKT_TRANS_READ            (77),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (115),
		.ST_CHANNEL_W              (2),
		.OUT_BYTE_CNT_H            (83),
		.OUT_BURSTWRAP_H           (90),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (1),
		.BURSTWRAP_CONST_VALUE     (1),
		.ADAPTER_VERSION           ("13.1")
	) slave1_avalon_universal_slave_0_burst_adapter (
		.clk                   (clk_0_clk_clk),                                                       //       cr0.clk
		.reset                 (master_reset_reset_bridge_in_reset_reset),                            // cr0_reset.reset
		.sink0_valid           (cmd_mux_001_src_valid),                                               //     sink0.valid
		.sink0_data            (cmd_mux_001_src_data),                                                //          .data
		.sink0_channel         (cmd_mux_001_src_channel),                                             //          .channel
		.sink0_startofpacket   (cmd_mux_001_src_startofpacket),                                       //          .startofpacket
		.sink0_endofpacket     (cmd_mux_001_src_endofpacket),                                         //          .endofpacket
		.sink0_ready           (cmd_mux_001_src_ready),                                               //          .ready
		.source0_valid         (slave1_avalon_universal_slave_0_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (slave1_avalon_universal_slave_0_burst_adapter_source0_data),          //          .data
		.source0_channel       (slave1_avalon_universal_slave_0_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (slave1_avalon_universal_slave_0_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (slave1_avalon_universal_slave_0_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (slave1_avalon_universal_slave_0_burst_adapter_source0_ready)          //          .ready
	);

	intel_std_18_1_dummy_mm_interconnect_0_cmd_demux cmd_demux (
		.clk                (clk_0_clk_clk),                                                  //        clk.clk
		.reset              (master_reset_reset_bridge_in_reset_reset),                       //  clk_reset.reset
		.sink_ready         (master_avalon_universal_master_0_limiter_cmd_src_ready),         //       sink.ready
		.sink_channel       (master_avalon_universal_master_0_limiter_cmd_src_channel),       //           .channel
		.sink_data          (master_avalon_universal_master_0_limiter_cmd_src_data),          //           .data
		.sink_startofpacket (master_avalon_universal_master_0_limiter_cmd_src_startofpacket), //           .startofpacket
		.sink_endofpacket   (master_avalon_universal_master_0_limiter_cmd_src_endofpacket),   //           .endofpacket
		.sink_valid         (master_avalon_universal_master_0_limiter_cmd_valid_data),        // sink_valid.data
		.src0_ready         (cmd_demux_src0_ready),                                           //       src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                           //           .valid
		.src0_data          (cmd_demux_src0_data),                                            //           .data
		.src0_channel       (cmd_demux_src0_channel),                                         //           .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                   //           .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                                     //           .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                                           //       src1.ready
		.src1_valid         (cmd_demux_src1_valid),                                           //           .valid
		.src1_data          (cmd_demux_src1_data),                                            //           .data
		.src1_channel       (cmd_demux_src1_channel),                                         //           .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                                   //           .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket)                                      //           .endofpacket
	);

	intel_std_18_1_dummy_mm_interconnect_0_cmd_mux cmd_mux (
		.clk                 (clk_0_clk_clk),                            //       clk.clk
		.reset               (master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                        //       src.ready
		.src_valid           (cmd_mux_src_valid),                        //          .valid
		.src_data            (cmd_mux_src_data),                         //          .data
		.src_channel         (cmd_mux_src_channel),                      //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                  //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                     //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                     //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                   //          .channel
		.sink0_data          (cmd_demux_src0_data),                      //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),             //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                //          .endofpacket
	);

	intel_std_18_1_dummy_mm_interconnect_0_cmd_mux cmd_mux_001 (
		.clk                 (clk_0_clk_clk),                            //       clk.clk
		.reset               (master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                    //       src.ready
		.src_valid           (cmd_mux_001_src_valid),                    //          .valid
		.src_data            (cmd_mux_001_src_data),                     //          .data
		.src_channel         (cmd_mux_001_src_channel),                  //          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),            //          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),              //          .endofpacket
		.sink0_ready         (cmd_demux_src1_ready),                     //     sink0.ready
		.sink0_valid         (cmd_demux_src1_valid),                     //          .valid
		.sink0_channel       (cmd_demux_src1_channel),                   //          .channel
		.sink0_data          (cmd_demux_src1_data),                      //          .data
		.sink0_startofpacket (cmd_demux_src1_startofpacket),             //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src1_endofpacket)                //          .endofpacket
	);

	intel_std_18_1_dummy_mm_interconnect_0_rsp_demux rsp_demux (
		.clk                (clk_0_clk_clk),                            //       clk.clk
		.reset              (master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                     //      sink.ready
		.sink_channel       (router_001_src_channel),                   //          .channel
		.sink_data          (router_001_src_data),                      //          .data
		.sink_startofpacket (router_001_src_startofpacket),             //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),               //          .endofpacket
		.sink_valid         (router_001_src_valid),                     //          .valid
		.src0_ready         (rsp_demux_src0_ready),                     //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                     //          .valid
		.src0_data          (rsp_demux_src0_data),                      //          .data
		.src0_channel       (rsp_demux_src0_channel),                   //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),             //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                //          .endofpacket
	);

	intel_std_18_1_dummy_mm_interconnect_0_rsp_demux rsp_demux_001 (
		.clk                (clk_0_clk_clk),                            //       clk.clk
		.reset              (master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_002_src_ready),                     //      sink.ready
		.sink_channel       (router_002_src_channel),                   //          .channel
		.sink_data          (router_002_src_data),                      //          .data
		.sink_startofpacket (router_002_src_startofpacket),             //          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),               //          .endofpacket
		.sink_valid         (router_002_src_valid),                     //          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                 //      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                 //          .valid
		.src0_data          (rsp_demux_001_src0_data),                  //          .data
		.src0_channel       (rsp_demux_001_src0_channel),               //          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),         //          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)            //          .endofpacket
	);

	intel_std_18_1_dummy_mm_interconnect_0_rsp_mux rsp_mux (
		.clk                 (clk_0_clk_clk),                            //       clk.clk
		.reset               (master_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                        //       src.ready
		.src_valid           (rsp_mux_src_valid),                        //          .valid
		.src_data            (rsp_mux_src_data),                         //          .data
		.src_channel         (rsp_mux_src_channel),                      //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                  //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                     //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                     //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                   //          .channel
		.sink0_data          (rsp_demux_src0_data),                      //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),             //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket),               //          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),                 //     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),                 //          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),               //          .channel
		.sink1_data          (rsp_demux_001_src0_data),                  //          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),         //          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket)            //          .endofpacket
	);

	intel_std_18_1_dummy_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (clk_0_clk_clk),                                              // in_clk_0.clk
		.in_rst_0_reset (master_reset_reset_bridge_in_reset_reset),                   // in_rst_0.reset
		.in_0_data      (slave0_avalon_universal_slave_0_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (slave0_avalon_universal_slave_0_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (slave0_avalon_universal_slave_0_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                               //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                              //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                              //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                               //         .error
	);

	intel_std_18_1_dummy_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_001 (
		.in_clk_0_clk   (clk_0_clk_clk),                                              // in_clk_0.clk
		.in_rst_0_reset (master_reset_reset_bridge_in_reset_reset),                   // in_rst_0.reset
		.in_0_data      (slave1_avalon_universal_slave_0_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (slave1_avalon_universal_slave_0_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (slave1_avalon_universal_slave_0_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_001_out_0_data),                           //    out_0.data
		.out_0_valid    (avalon_st_adapter_001_out_0_valid),                          //         .valid
		.out_0_ready    (avalon_st_adapter_001_out_0_ready),                          //         .ready
		.out_0_error    (avalon_st_adapter_001_out_0_error)                           //         .error
	);

endmodule
