	component intel_std_18_1_dummy is
		port (
			clk_clk                   : in  std_logic                     := 'X';             -- clk
			reset_reset_n             : in  std_logic                     := 'X';             -- reset_n
			in_address                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- address
			in_waitrequest            : out std_logic;                                        -- waitrequest
			in_burstcount             : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- burstcount
			in_byteenable             : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			in_read                   : in  std_logic                     := 'X';             -- read
			in_readdata               : out std_logic_vector(31 downto 0);                    -- readdata
			in_readdatavalid          : out std_logic;                                        -- readdatavalid
			in_write                  : in  std_logic                     := 'X';             -- write
			in_writedata              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			slave0_address            : out std_logic_vector(15 downto 0);                    -- address
			slave0_write              : out std_logic;                                        -- write
			slave0_read               : out std_logic;                                        -- read
			slave0_readdata           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			slave0_writedata          : out std_logic_vector(31 downto 0);                    -- writedata
			slave0_begintransfer      : out std_logic;                                        -- begintransfer
			slave0_beginbursttransfer : out std_logic;                                        -- beginbursttransfer
			slave0_burstcount         : out std_logic_vector(3 downto 0);                     -- burstcount
			slave0_byteenable         : out std_logic_vector(3 downto 0);                     -- byteenable
			slave0_readdatavalid      : in  std_logic                     := 'X';             -- readdatavalid
			slave0_waitrequest        : in  std_logic                     := 'X';             -- waitrequest
			slave1_address            : out std_logic_vector(15 downto 0);                    -- address
			slave1_write              : out std_logic;                                        -- write
			slave1_read               : out std_logic;                                        -- read
			slave1_readdata           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			slave1_writedata          : out std_logic_vector(31 downto 0);                    -- writedata
			slave1_begintransfer      : out std_logic;                                        -- begintransfer
			slave1_beginbursttransfer : out std_logic;                                        -- beginbursttransfer
			slave1_burstcount         : out std_logic_vector(3 downto 0);                     -- burstcount
			slave1_byteenable         : out std_logic_vector(3 downto 0);                     -- byteenable
			slave1_readdatavalid      : in  std_logic                     := 'X';             -- readdatavalid
			slave1_waitrequest        : in  std_logic                     := 'X'              -- waitrequest
		);
	end component intel_std_18_1_dummy;

	u0 : component intel_std_18_1_dummy
		port map (
			clk_clk                   => CONNECTED_TO_clk_clk,                   --    clk.clk
			reset_reset_n             => CONNECTED_TO_reset_reset_n,             --  reset.reset_n
			in_address                => CONNECTED_TO_in_address,                --     in.address
			in_waitrequest            => CONNECTED_TO_in_waitrequest,            --       .waitrequest
			in_burstcount             => CONNECTED_TO_in_burstcount,             --       .burstcount
			in_byteenable             => CONNECTED_TO_in_byteenable,             --       .byteenable
			in_read                   => CONNECTED_TO_in_read,                   --       .read
			in_readdata               => CONNECTED_TO_in_readdata,               --       .readdata
			in_readdatavalid          => CONNECTED_TO_in_readdatavalid,          --       .readdatavalid
			in_write                  => CONNECTED_TO_in_write,                  --       .write
			in_writedata              => CONNECTED_TO_in_writedata,              --       .writedata
			slave0_address            => CONNECTED_TO_slave0_address,            -- slave0.address
			slave0_write              => CONNECTED_TO_slave0_write,              --       .write
			slave0_read               => CONNECTED_TO_slave0_read,               --       .read
			slave0_readdata           => CONNECTED_TO_slave0_readdata,           --       .readdata
			slave0_writedata          => CONNECTED_TO_slave0_writedata,          --       .writedata
			slave0_begintransfer      => CONNECTED_TO_slave0_begintransfer,      --       .begintransfer
			slave0_beginbursttransfer => CONNECTED_TO_slave0_beginbursttransfer, --       .beginbursttransfer
			slave0_burstcount         => CONNECTED_TO_slave0_burstcount,         --       .burstcount
			slave0_byteenable         => CONNECTED_TO_slave0_byteenable,         --       .byteenable
			slave0_readdatavalid      => CONNECTED_TO_slave0_readdatavalid,      --       .readdatavalid
			slave0_waitrequest        => CONNECTED_TO_slave0_waitrequest,        --       .waitrequest
			slave1_address            => CONNECTED_TO_slave1_address,            -- slave1.address
			slave1_write              => CONNECTED_TO_slave1_write,              --       .write
			slave1_read               => CONNECTED_TO_slave1_read,               --       .read
			slave1_readdata           => CONNECTED_TO_slave1_readdata,           --       .readdata
			slave1_writedata          => CONNECTED_TO_slave1_writedata,          --       .writedata
			slave1_begintransfer      => CONNECTED_TO_slave1_begintransfer,      --       .begintransfer
			slave1_beginbursttransfer => CONNECTED_TO_slave1_beginbursttransfer, --       .beginbursttransfer
			slave1_burstcount         => CONNECTED_TO_slave1_burstcount,         --       .burstcount
			slave1_byteenable         => CONNECTED_TO_slave1_byteenable,         --       .byteenable
			slave1_readdatavalid      => CONNECTED_TO_slave1_readdatavalid,      --       .readdatavalid
			slave1_waitrequest        => CONNECTED_TO_slave1_waitrequest         --       .waitrequest
		);

