-- address_decoder_top_csr_clk.vhd

-- Generated using ACDS version 19.4 64

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity address_decoder_top_csr_clk is
	port (
		in_clk      : in  std_logic := '0'; --       clk_in.clk
		reset_n     : in  std_logic := '0'; -- clk_in_reset.reset_n
		clk_out     : out std_logic;        --          clk.clk
		reset_n_out : out std_logic         --    clk_reset.reset_n
	);
end entity address_decoder_top_csr_clk;

architecture rtl of address_decoder_top_csr_clk is
begin

	clk_out <= in_clk;

	reset_n_out <= reset_n;

end architecture rtl; -- of address_decoder_top_csr_clk
