-- reset_release.vhd

-- Generated using ACDS version 19.4 64

library IEEE;
library altera_s10_user_rst_clkgate_1910;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity reset_release is
	port (
		ninit_done : out std_logic   -- ninit_done.ninit_done
	);
end entity reset_release;

architecture rtl of reset_release is
	component altera_s10_user_rst_clkgate_cmp is
		port (
			ninit_done : out std_logic   -- ninit_done
		);
	end component altera_s10_user_rst_clkgate_cmp;

	for s10_user_rst_clkgate_0 : altera_s10_user_rst_clkgate_cmp
		use entity altera_s10_user_rst_clkgate_1910.altera_s10_user_rst_clkgate;
begin

	s10_user_rst_clkgate_0 : component altera_s10_user_rst_clkgate_cmp
		port map (
			ninit_done => ninit_done  -- ninit_done.ninit_done
		);

end architecture rtl; -- of reset_release
