-- alt_mge_xcvr_reset_ctrl_channel.vhd

-- Generated using ACDS version 19.4 64

library IEEE;
library altera_xcvr_reset_control_s10_1911;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity alt_mge_xcvr_reset_ctrl_channel is
	port (
		clock                : in  std_logic                    := '0';             --                clock.clk
		reset                : in  std_logic                    := '0';             --                reset.reset
		tx_analogreset       : out std_logic_vector(0 downto 0);                    --       tx_analogreset.tx_analogreset
		tx_digitalreset      : out std_logic_vector(0 downto 0);                    --      tx_digitalreset.tx_digitalreset
		tx_ready             : out std_logic_vector(0 downto 0);                    --             tx_ready.tx_ready
		pll_locked           : in  std_logic_vector(0 downto 0) := (others => '0'); --           pll_locked.pll_locked
		pll_select           : in  std_logic_vector(0 downto 0) := (others => '0'); --           pll_select.pll_select
		tx_cal_busy          : in  std_logic_vector(0 downto 0) := (others => '0'); --          tx_cal_busy.tx_cal_busy
		tx_analogreset_stat  : in  std_logic_vector(0 downto 0) := (others => '0'); --  tx_analogreset_stat.tx_analogreset_stat
		tx_digitalreset_stat : in  std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset_stat.tx_digitalreset_stat
		pll_cal_busy         : in  std_logic_vector(0 downto 0) := (others => '0'); --         pll_cal_busy.pll_cal_busy
		rx_analogreset       : out std_logic_vector(0 downto 0);                    --       rx_analogreset.rx_analogreset
		rx_digitalreset      : out std_logic_vector(0 downto 0);                    --      rx_digitalreset.rx_digitalreset
		rx_ready             : out std_logic_vector(0 downto 0);                    --             rx_ready.rx_ready
		rx_is_lockedtodata   : in  std_logic_vector(0 downto 0) := (others => '0'); --   rx_is_lockedtodata.rx_is_lockedtodata
		rx_cal_busy          : in  std_logic_vector(0 downto 0) := (others => '0'); --          rx_cal_busy.rx_cal_busy
		rx_analogreset_stat  : in  std_logic_vector(0 downto 0) := (others => '0'); --  rx_analogreset_stat.rx_analogreset_stat
		rx_digitalreset_stat : in  std_logic_vector(0 downto 0) := (others => '0')  -- rx_digitalreset_stat.rx_digitalreset_stat
	);
end entity alt_mge_xcvr_reset_ctrl_channel;

architecture rtl of alt_mge_xcvr_reset_ctrl_channel is
	component altera_xcvr_reset_control_s10_cmp is
		generic (
			CHANNELS           : integer := 1;
			PLLS               : integer := 1;
			SYS_CLK_IN_MHZ     : integer := 250;
			REDUCED_SIM_TIME   : integer := 1;
			ENABLE_DIGITAL_SEQ : integer := 0;
			TX_PLL_ENABLE      : integer := 0;
			T_PLL_POWERDOWN    : integer := 1000;
			TX_ENABLE          : integer := 1;
			TX_PER_CHANNEL     : integer := 0;
			TX_MANUAL_RESET    : integer := 0;
			T_TX_ANALOGRESET   : integer := 0;
			T_TX_DIGITALRESET  : integer := 20;
			T_PLL_LOCK_HYST    : integer := 0;
			EN_PLL_CAL_BUSY    : integer := 0;
			RX_ENABLE          : integer := 1;
			RX_PER_CHANNEL     : integer := 0;
			RX_MANUAL_RESET    : integer := 0;
			T_RX_ANALOGRESET   : integer := 40;
			T_RX_DIGITALRESET  : integer := 5000
		);
		port (
			clock                : in  std_logic                             := 'X';             -- clk
			reset                : in  std_logic                             := 'X';             -- reset
			tx_analogreset       : out std_logic_vector(CHANNELS-1 downto 0);                    -- tx_analogreset
			tx_digitalreset      : out std_logic_vector(CHANNELS-1 downto 0);                    -- tx_digitalreset
			tx_ready             : out std_logic_vector(CHANNELS-1 downto 0);                    -- tx_ready
			pll_locked           : in  std_logic_vector(PLLS-1 downto 0)     := (others => 'X'); -- pll_locked
			pll_select           : in  std_logic_vector(0 downto 0)          := (others => 'X'); -- pll_select
			tx_cal_busy          : in  std_logic_vector(CHANNELS-1 downto 0) := (others => 'X'); -- tx_cal_busy
			tx_analogreset_stat  : in  std_logic_vector(CHANNELS-1 downto 0) := (others => 'X'); -- tx_analogreset_stat
			tx_digitalreset_stat : in  std_logic_vector(CHANNELS-1 downto 0) := (others => 'X'); -- tx_digitalreset_stat
			pll_cal_busy         : in  std_logic_vector(PLLS-1 downto 0)     := (others => 'X'); -- pll_cal_busy
			rx_analogreset       : out std_logic_vector(CHANNELS-1 downto 0);                    -- rx_analogreset
			rx_digitalreset      : out std_logic_vector(CHANNELS-1 downto 0);                    -- rx_digitalreset
			rx_ready             : out std_logic_vector(CHANNELS-1 downto 0);                    -- rx_ready
			rx_is_lockedtodata   : in  std_logic_vector(CHANNELS-1 downto 0) := (others => 'X'); -- rx_is_lockedtodata
			rx_cal_busy          : in  std_logic_vector(CHANNELS-1 downto 0) := (others => 'X'); -- rx_cal_busy
			rx_analogreset_stat  : in  std_logic_vector(CHANNELS-1 downto 0) := (others => 'X'); -- rx_analogreset_stat
			rx_digitalreset_stat : in  std_logic_vector(CHANNELS-1 downto 0) := (others => 'X'); -- rx_digitalreset_stat
			pll_powerdown        : out std_logic_vector(0 downto 0);                             -- pll_powerdown
			tx_digitalreset_or   : in  std_logic_vector(0 downto 0)          := (others => 'X'); -- tx_digitalreset_or
			rx_digitalreset_or   : in  std_logic_vector(0 downto 0)          := (others => 'X')  -- rx_digitalreset_or
		);
	end component altera_xcvr_reset_control_s10_cmp;

	for xcvr_reset_control_s10_0 : altera_xcvr_reset_control_s10_cmp
		use entity altera_xcvr_reset_control_s10_1911.altera_xcvr_reset_control_s10;
begin

	xcvr_reset_control_s10_0 : component altera_xcvr_reset_control_s10_cmp
		generic map (
			CHANNELS           => 1,
			PLLS               => 1,
			SYS_CLK_IN_MHZ     => 125,
			REDUCED_SIM_TIME   => 1,
			ENABLE_DIGITAL_SEQ => 0,
			TX_PLL_ENABLE      => 0,
			T_PLL_POWERDOWN    => 1000,
			TX_ENABLE          => 1,
			TX_PER_CHANNEL     => 0,
			TX_MANUAL_RESET    => 0,
			T_TX_ANALOGRESET   => 70000,
			T_TX_DIGITALRESET  => 70000,
			T_PLL_LOCK_HYST    => 0,
			EN_PLL_CAL_BUSY    => 1,
			RX_ENABLE          => 1,
			RX_PER_CHANNEL     => 0,
			RX_MANUAL_RESET    => 0,
			T_RX_ANALOGRESET   => 70000,
			T_RX_DIGITALRESET  => 5000
		)
		port map (
			clock                => clock,                --                clock.clk
			reset                => reset,                --                reset.reset
			tx_analogreset       => tx_analogreset,       --       tx_analogreset.tx_analogreset
			tx_digitalreset      => tx_digitalreset,      --      tx_digitalreset.tx_digitalreset
			tx_ready             => tx_ready,             --             tx_ready.tx_ready
			pll_locked           => pll_locked,           --           pll_locked.pll_locked
			pll_select           => pll_select,           --           pll_select.pll_select
			tx_cal_busy          => tx_cal_busy,          --          tx_cal_busy.tx_cal_busy
			tx_analogreset_stat  => tx_analogreset_stat,  --  tx_analogreset_stat.tx_analogreset_stat
			tx_digitalreset_stat => tx_digitalreset_stat, -- tx_digitalreset_stat.tx_digitalreset_stat
			pll_cal_busy         => pll_cal_busy,         --         pll_cal_busy.pll_cal_busy
			rx_analogreset       => rx_analogreset,       --       rx_analogreset.rx_analogreset
			rx_digitalreset      => rx_digitalreset,      --      rx_digitalreset.rx_digitalreset
			rx_ready             => rx_ready,             --             rx_ready.rx_ready
			rx_is_lockedtodata   => rx_is_lockedtodata,   --   rx_is_lockedtodata.rx_is_lockedtodata
			rx_cal_busy          => rx_cal_busy,          --          rx_cal_busy.rx_cal_busy
			rx_analogreset_stat  => rx_analogreset_stat,  --  rx_analogreset_stat.rx_analogreset_stat
			rx_digitalreset_stat => rx_digitalreset_stat, -- rx_digitalreset_stat.rx_digitalreset_stat
			pll_powerdown        => open,                 --          (terminated)
			tx_digitalreset_or   => "0",                  --          (terminated)
			rx_digitalreset_or   => "0"                   --          (terminated)
		);

end architecture rtl; -- of alt_mge_xcvr_reset_ctrl_channel
