-- address_decoder_channel.vhd

-- Generated using ACDS version 19.4 64

library IEEE;
library address_decoder_channel_csr_clk;
library address_decoder_channel_mac;
library address_decoder_channel_master;
library address_decoder_channel_phy;
library address_decoder_channel_xcvr_rcfg;
library altera_mm_interconnect_191;
library altera_reset_controller_191;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity address_decoder_channel is
	port (
		csr_clk_clk           : in  std_logic                     := '0';             --       csr_clk.clk
		csr_clk_reset_reset_n : in  std_logic                     := '0';             -- csr_clk_reset.reset_n
		mac_address           : out std_logic_vector(9 downto 0);                     --           mac.address
		mac_write             : out std_logic;                                        --              .write
		mac_read              : out std_logic;                                        --              .read
		mac_readdata          : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		mac_writedata         : out std_logic_vector(31 downto 0);                    --              .writedata
		mac_waitrequest       : in  std_logic                     := '0';             --              .waitrequest
		slave_address         : in  std_logic_vector(15 downto 0) := (others => '0'); --         slave.address
		slave_waitrequest     : out std_logic;                                        --              .waitrequest
		slave_read            : in  std_logic                     := '0';             --              .read
		slave_readdata        : out std_logic_vector(31 downto 0);                    --              .readdata
		slave_write           : in  std_logic                     := '0';             --              .write
		slave_writedata       : in  std_logic_vector(31 downto 0) := (others => '0'); --              .writedata
		phy_address           : out std_logic_vector(10 downto 0);                    --           phy.address
		phy_write             : out std_logic;                                        --              .write
		phy_read              : out std_logic;                                        --              .read
		phy_readdata          : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		phy_writedata         : out std_logic_vector(31 downto 0);                    --              .writedata
		phy_waitrequest       : in  std_logic                     := '0';             --              .waitrequest
		xcvr_rcfg_address     : out std_logic_vector(10 downto 0);                    --     xcvr_rcfg.address
		xcvr_rcfg_write       : out std_logic;                                        --              .write
		xcvr_rcfg_read        : out std_logic;                                        --              .read
		xcvr_rcfg_readdata    : in  std_logic_vector(31 downto 0) := (others => '0'); --              .readdata
		xcvr_rcfg_writedata   : out std_logic_vector(31 downto 0);                    --              .writedata
		xcvr_rcfg_waitrequest : in  std_logic                     := '0'              --              .waitrequest
	);
end entity address_decoder_channel;

architecture rtl of address_decoder_channel is
	component address_decoder_channel_csr_clk_cmp is
		port (
			clk_out     : out std_logic;        -- clk
			in_clk      : in  std_logic := 'X'; -- clk
			reset_n     : in  std_logic := 'X'; -- reset_n
			reset_n_out : out std_logic         -- reset_n
		);
	end component address_decoder_channel_csr_clk_cmp;

	component address_decoder_channel_mac_cmp is
		port (
			av_address        : out std_logic_vector(9 downto 0);                     -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(11 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_channel_mac_cmp;

	component address_decoder_channel_master_cmp is
		port (
			av_address        : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
			av_waitrequest    : out std_logic;                                        -- waitrequest
			av_read           : in  std_logic                     := 'X';             -- read
			av_readdata       : out std_logic_vector(31 downto 0);                    -- readdata
			av_write          : in  std_logic                     := 'X';             -- write
			av_writedata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_address       : out std_logic_vector(31 downto 0);                    -- address
			uav_burstcount    : out std_logic_vector(2 downto 0);                     -- burstcount
			uav_read          : out std_logic;                                        -- read
			uav_write         : out std_logic;                                        -- write
			uav_waitrequest   : in  std_logic                     := 'X';             -- waitrequest
			uav_readdatavalid : in  std_logic                     := 'X';             -- readdatavalid
			uav_byteenable    : out std_logic_vector(3 downto 0);                     -- byteenable
			uav_readdata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			uav_writedata     : out std_logic_vector(31 downto 0);                    -- writedata
			uav_lock          : out std_logic;                                        -- lock
			uav_debugaccess   : out std_logic;                                        -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_channel_master_cmp;

	component address_decoder_channel_phy_cmp is
		port (
			av_address        : out std_logic_vector(10 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(12 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_channel_phy_cmp;

	component address_decoder_channel_xcvr_rcfg_cmp is
		port (
			av_address        : out std_logic_vector(10 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(11 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_channel_xcvr_rcfg_cmp;

	component address_decoder_channel_altera_mm_interconnect_191_wasz7ki_cmp is
		port (
			master_avalon_universal_master_0_address         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- address
			master_avalon_universal_master_0_waitrequest     : out std_logic;                                        -- waitrequest
			master_avalon_universal_master_0_burstcount      : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			master_avalon_universal_master_0_byteenable      : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			master_avalon_universal_master_0_read            : in  std_logic                     := 'X';             -- read
			master_avalon_universal_master_0_readdata        : out std_logic_vector(31 downto 0);                    -- readdata
			master_avalon_universal_master_0_readdatavalid   : out std_logic;                                        -- readdatavalid
			master_avalon_universal_master_0_write           : in  std_logic                     := 'X';             -- write
			master_avalon_universal_master_0_writedata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			master_avalon_universal_master_0_lock            : in  std_logic                     := 'X';             -- lock
			master_avalon_universal_master_0_debugaccess     : in  std_logic                     := 'X';             -- debugaccess
			mac_avalon_universal_slave_0_address             : out std_logic_vector(11 downto 0);                    -- address
			mac_avalon_universal_slave_0_write               : out std_logic;                                        -- write
			mac_avalon_universal_slave_0_read                : out std_logic;                                        -- read
			mac_avalon_universal_slave_0_readdata            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			mac_avalon_universal_slave_0_writedata           : out std_logic_vector(31 downto 0);                    -- writedata
			mac_avalon_universal_slave_0_burstcount          : out std_logic_vector(2 downto 0);                     -- burstcount
			mac_avalon_universal_slave_0_byteenable          : out std_logic_vector(3 downto 0);                     -- byteenable
			mac_avalon_universal_slave_0_readdatavalid       : in  std_logic                     := 'X';             -- readdatavalid
			mac_avalon_universal_slave_0_waitrequest         : in  std_logic                     := 'X';             -- waitrequest
			mac_avalon_universal_slave_0_lock                : out std_logic;                                        -- lock
			mac_avalon_universal_slave_0_debugaccess         : out std_logic;                                        -- debugaccess
			phy_avalon_universal_slave_0_address             : out std_logic_vector(12 downto 0);                    -- address
			phy_avalon_universal_slave_0_write               : out std_logic;                                        -- write
			phy_avalon_universal_slave_0_read                : out std_logic;                                        -- read
			phy_avalon_universal_slave_0_readdata            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			phy_avalon_universal_slave_0_writedata           : out std_logic_vector(31 downto 0);                    -- writedata
			phy_avalon_universal_slave_0_burstcount          : out std_logic_vector(2 downto 0);                     -- burstcount
			phy_avalon_universal_slave_0_byteenable          : out std_logic_vector(3 downto 0);                     -- byteenable
			phy_avalon_universal_slave_0_readdatavalid       : in  std_logic                     := 'X';             -- readdatavalid
			phy_avalon_universal_slave_0_waitrequest         : in  std_logic                     := 'X';             -- waitrequest
			phy_avalon_universal_slave_0_lock                : out std_logic;                                        -- lock
			phy_avalon_universal_slave_0_debugaccess         : out std_logic;                                        -- debugaccess
			xcvr_rcfg_avalon_universal_slave_0_address       : out std_logic_vector(11 downto 0);                    -- address
			xcvr_rcfg_avalon_universal_slave_0_write         : out std_logic;                                        -- write
			xcvr_rcfg_avalon_universal_slave_0_read          : out std_logic;                                        -- read
			xcvr_rcfg_avalon_universal_slave_0_readdata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			xcvr_rcfg_avalon_universal_slave_0_writedata     : out std_logic_vector(31 downto 0);                    -- writedata
			xcvr_rcfg_avalon_universal_slave_0_burstcount    : out std_logic_vector(2 downto 0);                     -- burstcount
			xcvr_rcfg_avalon_universal_slave_0_byteenable    : out std_logic_vector(3 downto 0);                     -- byteenable
			xcvr_rcfg_avalon_universal_slave_0_readdatavalid : in  std_logic                     := 'X';             -- readdatavalid
			xcvr_rcfg_avalon_universal_slave_0_waitrequest   : in  std_logic                     := 'X';             -- waitrequest
			xcvr_rcfg_avalon_universal_slave_0_lock          : out std_logic;                                        -- lock
			xcvr_rcfg_avalon_universal_slave_0_debugaccess   : out std_logic;                                        -- debugaccess
			master_reset_reset_bridge_in_reset_reset         : in  std_logic                     := 'X';             -- reset
			csr_clk_clk_clk                                  : in  std_logic                     := 'X'              -- clk
		);
	end component address_decoder_channel_altera_mm_interconnect_191_wasz7ki_cmp;

	component altera_reset_controller_cmp is
		generic (
			NUM_RESET_INPUTS          : integer := 6;
			OUTPUT_RESET_SYNC_EDGES   : string  := "deassert";
			SYNC_DEPTH                : integer := 2;
			RESET_REQUEST_PRESENT     : integer := 0;
			RESET_REQ_WAIT_TIME       : integer := 1;
			MIN_RST_ASSERTION_TIME    : integer := 3;
			RESET_REQ_EARLY_DSRT_TIME : integer := 1;
			USE_RESET_REQUEST_IN0     : integer := 0;
			USE_RESET_REQUEST_IN1     : integer := 0;
			USE_RESET_REQUEST_IN2     : integer := 0;
			USE_RESET_REQUEST_IN3     : integer := 0;
			USE_RESET_REQUEST_IN4     : integer := 0;
			USE_RESET_REQUEST_IN5     : integer := 0;
			USE_RESET_REQUEST_IN6     : integer := 0;
			USE_RESET_REQUEST_IN7     : integer := 0;
			USE_RESET_REQUEST_IN8     : integer := 0;
			USE_RESET_REQUEST_IN9     : integer := 0;
			USE_RESET_REQUEST_IN10    : integer := 0;
			USE_RESET_REQUEST_IN11    : integer := 0;
			USE_RESET_REQUEST_IN12    : integer := 0;
			USE_RESET_REQUEST_IN13    : integer := 0;
			USE_RESET_REQUEST_IN14    : integer := 0;
			USE_RESET_REQUEST_IN15    : integer := 0;
			ADAPT_RESET_REQUEST       : integer := 0
		);
		port (
			reset_in0      : in  std_logic := 'X'; -- reset
			clk            : in  std_logic := 'X'; -- clk
			reset_out      : out std_logic;        -- reset
			reset_req      : out std_logic;        -- reset_req
			reset_req_in0  : in  std_logic := 'X'; -- reset_req
			reset_in1      : in  std_logic := 'X'; -- reset
			reset_req_in1  : in  std_logic := 'X'; -- reset_req
			reset_in2      : in  std_logic := 'X'; -- reset
			reset_req_in2  : in  std_logic := 'X'; -- reset_req
			reset_in3      : in  std_logic := 'X'; -- reset
			reset_req_in3  : in  std_logic := 'X'; -- reset_req
			reset_in4      : in  std_logic := 'X'; -- reset
			reset_req_in4  : in  std_logic := 'X'; -- reset_req
			reset_in5      : in  std_logic := 'X'; -- reset
			reset_req_in5  : in  std_logic := 'X'; -- reset_req
			reset_in6      : in  std_logic := 'X'; -- reset
			reset_req_in6  : in  std_logic := 'X'; -- reset_req
			reset_in7      : in  std_logic := 'X'; -- reset
			reset_req_in7  : in  std_logic := 'X'; -- reset_req
			reset_in8      : in  std_logic := 'X'; -- reset
			reset_req_in8  : in  std_logic := 'X'; -- reset_req
			reset_in9      : in  std_logic := 'X'; -- reset
			reset_req_in9  : in  std_logic := 'X'; -- reset_req
			reset_in10     : in  std_logic := 'X'; -- reset
			reset_req_in10 : in  std_logic := 'X'; -- reset_req
			reset_in11     : in  std_logic := 'X'; -- reset
			reset_req_in11 : in  std_logic := 'X'; -- reset_req
			reset_in12     : in  std_logic := 'X'; -- reset
			reset_req_in12 : in  std_logic := 'X'; -- reset_req
			reset_in13     : in  std_logic := 'X'; -- reset
			reset_req_in13 : in  std_logic := 'X'; -- reset_req
			reset_in14     : in  std_logic := 'X'; -- reset
			reset_req_in14 : in  std_logic := 'X'; -- reset_req
			reset_in15     : in  std_logic := 'X'; -- reset
			reset_req_in15 : in  std_logic := 'X'  -- reset_req
		);
	end component altera_reset_controller_cmp;

	signal csr_clk_clk_clk                                                    : std_logic;                     -- csr_clk:clk_out -> [mac:clk, master:clk, mm_interconnect_0:csr_clk_clk_clk, phy:clk, rst_controller:clk, xcvr_rcfg:clk]
	signal master_avalon_universal_master_0_waitrequest                       : std_logic;                     -- mm_interconnect_0:master_avalon_universal_master_0_waitrequest -> master:uav_waitrequest
	signal master_avalon_universal_master_0_readdata                          : std_logic_vector(31 downto 0); -- mm_interconnect_0:master_avalon_universal_master_0_readdata -> master:uav_readdata
	signal master_avalon_universal_master_0_debugaccess                       : std_logic;                     -- master:uav_debugaccess -> mm_interconnect_0:master_avalon_universal_master_0_debugaccess
	signal master_avalon_universal_master_0_address                           : std_logic_vector(31 downto 0); -- master:uav_address -> mm_interconnect_0:master_avalon_universal_master_0_address
	signal master_avalon_universal_master_0_read                              : std_logic;                     -- master:uav_read -> mm_interconnect_0:master_avalon_universal_master_0_read
	signal master_avalon_universal_master_0_byteenable                        : std_logic_vector(3 downto 0);  -- master:uav_byteenable -> mm_interconnect_0:master_avalon_universal_master_0_byteenable
	signal master_avalon_universal_master_0_readdatavalid                     : std_logic;                     -- mm_interconnect_0:master_avalon_universal_master_0_readdatavalid -> master:uav_readdatavalid
	signal master_avalon_universal_master_0_lock                              : std_logic;                     -- master:uav_lock -> mm_interconnect_0:master_avalon_universal_master_0_lock
	signal master_avalon_universal_master_0_write                             : std_logic;                     -- master:uav_write -> mm_interconnect_0:master_avalon_universal_master_0_write
	signal master_avalon_universal_master_0_writedata                         : std_logic_vector(31 downto 0); -- master:uav_writedata -> mm_interconnect_0:master_avalon_universal_master_0_writedata
	signal master_avalon_universal_master_0_burstcount                        : std_logic_vector(2 downto 0);  -- master:uav_burstcount -> mm_interconnect_0:master_avalon_universal_master_0_burstcount
	signal mm_interconnect_0_mac_avalon_universal_slave_0_readdata            : std_logic_vector(31 downto 0); -- mac:uav_readdata -> mm_interconnect_0:mac_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_mac_avalon_universal_slave_0_waitrequest         : std_logic;                     -- mac:uav_waitrequest -> mm_interconnect_0:mac_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_mac_avalon_universal_slave_0_debugaccess         : std_logic;                     -- mm_interconnect_0:mac_avalon_universal_slave_0_debugaccess -> mac:uav_debugaccess
	signal mm_interconnect_0_mac_avalon_universal_slave_0_address             : std_logic_vector(11 downto 0); -- mm_interconnect_0:mac_avalon_universal_slave_0_address -> mac:uav_address
	signal mm_interconnect_0_mac_avalon_universal_slave_0_read                : std_logic;                     -- mm_interconnect_0:mac_avalon_universal_slave_0_read -> mac:uav_read
	signal mm_interconnect_0_mac_avalon_universal_slave_0_byteenable          : std_logic_vector(3 downto 0);  -- mm_interconnect_0:mac_avalon_universal_slave_0_byteenable -> mac:uav_byteenable
	signal mm_interconnect_0_mac_avalon_universal_slave_0_readdatavalid       : std_logic;                     -- mac:uav_readdatavalid -> mm_interconnect_0:mac_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_mac_avalon_universal_slave_0_lock                : std_logic;                     -- mm_interconnect_0:mac_avalon_universal_slave_0_lock -> mac:uav_lock
	signal mm_interconnect_0_mac_avalon_universal_slave_0_write               : std_logic;                     -- mm_interconnect_0:mac_avalon_universal_slave_0_write -> mac:uav_write
	signal mm_interconnect_0_mac_avalon_universal_slave_0_writedata           : std_logic_vector(31 downto 0); -- mm_interconnect_0:mac_avalon_universal_slave_0_writedata -> mac:uav_writedata
	signal mm_interconnect_0_mac_avalon_universal_slave_0_burstcount          : std_logic_vector(2 downto 0);  -- mm_interconnect_0:mac_avalon_universal_slave_0_burstcount -> mac:uav_burstcount
	signal mm_interconnect_0_phy_avalon_universal_slave_0_readdata            : std_logic_vector(31 downto 0); -- phy:uav_readdata -> mm_interconnect_0:phy_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_phy_avalon_universal_slave_0_waitrequest         : std_logic;                     -- phy:uav_waitrequest -> mm_interconnect_0:phy_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_phy_avalon_universal_slave_0_debugaccess         : std_logic;                     -- mm_interconnect_0:phy_avalon_universal_slave_0_debugaccess -> phy:uav_debugaccess
	signal mm_interconnect_0_phy_avalon_universal_slave_0_address             : std_logic_vector(12 downto 0); -- mm_interconnect_0:phy_avalon_universal_slave_0_address -> phy:uav_address
	signal mm_interconnect_0_phy_avalon_universal_slave_0_read                : std_logic;                     -- mm_interconnect_0:phy_avalon_universal_slave_0_read -> phy:uav_read
	signal mm_interconnect_0_phy_avalon_universal_slave_0_byteenable          : std_logic_vector(3 downto 0);  -- mm_interconnect_0:phy_avalon_universal_slave_0_byteenable -> phy:uav_byteenable
	signal mm_interconnect_0_phy_avalon_universal_slave_0_readdatavalid       : std_logic;                     -- phy:uav_readdatavalid -> mm_interconnect_0:phy_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_phy_avalon_universal_slave_0_lock                : std_logic;                     -- mm_interconnect_0:phy_avalon_universal_slave_0_lock -> phy:uav_lock
	signal mm_interconnect_0_phy_avalon_universal_slave_0_write               : std_logic;                     -- mm_interconnect_0:phy_avalon_universal_slave_0_write -> phy:uav_write
	signal mm_interconnect_0_phy_avalon_universal_slave_0_writedata           : std_logic_vector(31 downto 0); -- mm_interconnect_0:phy_avalon_universal_slave_0_writedata -> phy:uav_writedata
	signal mm_interconnect_0_phy_avalon_universal_slave_0_burstcount          : std_logic_vector(2 downto 0);  -- mm_interconnect_0:phy_avalon_universal_slave_0_burstcount -> phy:uav_burstcount
	signal mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_readdata      : std_logic_vector(31 downto 0); -- xcvr_rcfg:uav_readdata -> mm_interconnect_0:xcvr_rcfg_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_waitrequest   : std_logic;                     -- xcvr_rcfg:uav_waitrequest -> mm_interconnect_0:xcvr_rcfg_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_debugaccess   : std_logic;                     -- mm_interconnect_0:xcvr_rcfg_avalon_universal_slave_0_debugaccess -> xcvr_rcfg:uav_debugaccess
	signal mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_address       : std_logic_vector(11 downto 0); -- mm_interconnect_0:xcvr_rcfg_avalon_universal_slave_0_address -> xcvr_rcfg:uav_address
	signal mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_read          : std_logic;                     -- mm_interconnect_0:xcvr_rcfg_avalon_universal_slave_0_read -> xcvr_rcfg:uav_read
	signal mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_byteenable    : std_logic_vector(3 downto 0);  -- mm_interconnect_0:xcvr_rcfg_avalon_universal_slave_0_byteenable -> xcvr_rcfg:uav_byteenable
	signal mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_readdatavalid : std_logic;                     -- xcvr_rcfg:uav_readdatavalid -> mm_interconnect_0:xcvr_rcfg_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_lock          : std_logic;                     -- mm_interconnect_0:xcvr_rcfg_avalon_universal_slave_0_lock -> xcvr_rcfg:uav_lock
	signal mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_write         : std_logic;                     -- mm_interconnect_0:xcvr_rcfg_avalon_universal_slave_0_write -> xcvr_rcfg:uav_write
	signal mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_writedata     : std_logic_vector(31 downto 0); -- mm_interconnect_0:xcvr_rcfg_avalon_universal_slave_0_writedata -> xcvr_rcfg:uav_writedata
	signal mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_burstcount    : std_logic_vector(2 downto 0);  -- mm_interconnect_0:xcvr_rcfg_avalon_universal_slave_0_burstcount -> xcvr_rcfg:uav_burstcount
	signal rst_controller_reset_out_reset                                     : std_logic;                     -- rst_controller:reset_out -> [mac:reset, master:reset, mm_interconnect_0:master_reset_reset_bridge_in_reset_reset, phy:reset, xcvr_rcfg:reset]
	signal csr_clk_clk_reset_reset                                            : std_logic;                     -- csr_clk:reset_n_out -> csr_clk_clk_reset_reset:in
	signal csr_clk_clk_reset_reset_ports_inv                                  : std_logic;                     -- csr_clk_clk_reset_reset:inv -> rst_controller:reset_in0

	for csr_clk : address_decoder_channel_csr_clk_cmp
		use entity address_decoder_channel_csr_clk.address_decoder_channel_csr_clk;
	for mac : address_decoder_channel_mac_cmp
		use entity address_decoder_channel_mac.address_decoder_channel_mac;
	for master : address_decoder_channel_master_cmp
		use entity address_decoder_channel_master.address_decoder_channel_master;
	for phy : address_decoder_channel_phy_cmp
		use entity address_decoder_channel_phy.address_decoder_channel_phy;
	for xcvr_rcfg : address_decoder_channel_xcvr_rcfg_cmp
		use entity address_decoder_channel_xcvr_rcfg.address_decoder_channel_xcvr_rcfg;
	for mm_interconnect_0 : address_decoder_channel_altera_mm_interconnect_191_wasz7ki_cmp
		use entity altera_mm_interconnect_191.address_decoder_channel_altera_mm_interconnect_191_wasz7ki;
	for rst_controller : altera_reset_controller_cmp
		use entity altera_reset_controller_191.altera_reset_controller;
begin

	csr_clk : component address_decoder_channel_csr_clk_cmp
		port map (
			clk_out     => csr_clk_clk_clk,         --          clk.clk
			in_clk      => csr_clk_clk,             --       clk_in.clk
			reset_n     => csr_clk_reset_reset_n,   -- clk_in_reset.reset_n
			reset_n_out => csr_clk_clk_reset_reset  --    clk_reset.reset_n
		);

	mac : component address_decoder_channel_mac_cmp
		port map (
			av_address        => mac_address,                                                  --      avalon_anti_slave_0.address
			av_write          => mac_write,                                                    --                         .write
			av_read           => mac_read,                                                     --                         .read
			av_readdata       => mac_readdata,                                                 --                         .readdata
			av_writedata      => mac_writedata,                                                --                         .writedata
			av_waitrequest    => mac_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_mac_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_mac_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_mac_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_mac_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_mac_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_mac_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_mac_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_mac_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_mac_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_mac_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_mac_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                              --                      clk.clk
			reset             => rst_controller_reset_out_reset                                --                    reset.reset
		);

	master : component address_decoder_channel_master_cmp
		port map (
			av_address        => slave_address,                                  --      avalon_anti_master_0.address
			av_waitrequest    => slave_waitrequest,                              --                          .waitrequest
			av_read           => slave_read,                                     --                          .read
			av_readdata       => slave_readdata,                                 --                          .readdata
			av_write          => slave_write,                                    --                          .write
			av_writedata      => slave_writedata,                                --                          .writedata
			uav_address       => master_avalon_universal_master_0_address,       -- avalon_universal_master_0.address
			uav_burstcount    => master_avalon_universal_master_0_burstcount,    --                          .burstcount
			uav_read          => master_avalon_universal_master_0_read,          --                          .read
			uav_write         => master_avalon_universal_master_0_write,         --                          .write
			uav_waitrequest   => master_avalon_universal_master_0_waitrequest,   --                          .waitrequest
			uav_readdatavalid => master_avalon_universal_master_0_readdatavalid, --                          .readdatavalid
			uav_byteenable    => master_avalon_universal_master_0_byteenable,    --                          .byteenable
			uav_readdata      => master_avalon_universal_master_0_readdata,      --                          .readdata
			uav_writedata     => master_avalon_universal_master_0_writedata,     --                          .writedata
			uav_lock          => master_avalon_universal_master_0_lock,          --                          .lock
			uav_debugaccess   => master_avalon_universal_master_0_debugaccess,   --                          .debugaccess
			clk               => csr_clk_clk_clk,                                --                       clk.clk
			reset             => rst_controller_reset_out_reset                  --                     reset.reset
		);

	phy : component address_decoder_channel_phy_cmp
		port map (
			av_address        => phy_address,                                                  --      avalon_anti_slave_0.address
			av_write          => phy_write,                                                    --                         .write
			av_read           => phy_read,                                                     --                         .read
			av_readdata       => phy_readdata,                                                 --                         .readdata
			av_writedata      => phy_writedata,                                                --                         .writedata
			av_waitrequest    => phy_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_phy_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_phy_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_phy_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_phy_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_phy_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_phy_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_phy_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_phy_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_phy_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_phy_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_phy_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                              --                      clk.clk
			reset             => rst_controller_reset_out_reset                                --                    reset.reset
		);

	xcvr_rcfg : component address_decoder_channel_xcvr_rcfg_cmp
		port map (
			av_address        => xcvr_rcfg_address,                                                  --      avalon_anti_slave_0.address
			av_write          => xcvr_rcfg_write,                                                    --                         .write
			av_read           => xcvr_rcfg_read,                                                     --                         .read
			av_readdata       => xcvr_rcfg_readdata,                                                 --                         .readdata
			av_writedata      => xcvr_rcfg_writedata,                                                --                         .writedata
			av_waitrequest    => xcvr_rcfg_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                    --                      clk.clk
			reset             => rst_controller_reset_out_reset                                      --                    reset.reset
		);

	mm_interconnect_0 : component address_decoder_channel_altera_mm_interconnect_191_wasz7ki_cmp
		port map (
			master_avalon_universal_master_0_address         => master_avalon_universal_master_0_address,                           --   master_avalon_universal_master_0.address
			master_avalon_universal_master_0_waitrequest     => master_avalon_universal_master_0_waitrequest,                       --                                   .waitrequest
			master_avalon_universal_master_0_burstcount      => master_avalon_universal_master_0_burstcount,                        --                                   .burstcount
			master_avalon_universal_master_0_byteenable      => master_avalon_universal_master_0_byteenable,                        --                                   .byteenable
			master_avalon_universal_master_0_read            => master_avalon_universal_master_0_read,                              --                                   .read
			master_avalon_universal_master_0_readdata        => master_avalon_universal_master_0_readdata,                          --                                   .readdata
			master_avalon_universal_master_0_readdatavalid   => master_avalon_universal_master_0_readdatavalid,                     --                                   .readdatavalid
			master_avalon_universal_master_0_write           => master_avalon_universal_master_0_write,                             --                                   .write
			master_avalon_universal_master_0_writedata       => master_avalon_universal_master_0_writedata,                         --                                   .writedata
			master_avalon_universal_master_0_lock            => master_avalon_universal_master_0_lock,                              --                                   .lock
			master_avalon_universal_master_0_debugaccess     => master_avalon_universal_master_0_debugaccess,                       --                                   .debugaccess
			mac_avalon_universal_slave_0_address             => mm_interconnect_0_mac_avalon_universal_slave_0_address,             --       mac_avalon_universal_slave_0.address
			mac_avalon_universal_slave_0_write               => mm_interconnect_0_mac_avalon_universal_slave_0_write,               --                                   .write
			mac_avalon_universal_slave_0_read                => mm_interconnect_0_mac_avalon_universal_slave_0_read,                --                                   .read
			mac_avalon_universal_slave_0_readdata            => mm_interconnect_0_mac_avalon_universal_slave_0_readdata,            --                                   .readdata
			mac_avalon_universal_slave_0_writedata           => mm_interconnect_0_mac_avalon_universal_slave_0_writedata,           --                                   .writedata
			mac_avalon_universal_slave_0_burstcount          => mm_interconnect_0_mac_avalon_universal_slave_0_burstcount,          --                                   .burstcount
			mac_avalon_universal_slave_0_byteenable          => mm_interconnect_0_mac_avalon_universal_slave_0_byteenable,          --                                   .byteenable
			mac_avalon_universal_slave_0_readdatavalid       => mm_interconnect_0_mac_avalon_universal_slave_0_readdatavalid,       --                                   .readdatavalid
			mac_avalon_universal_slave_0_waitrequest         => mm_interconnect_0_mac_avalon_universal_slave_0_waitrequest,         --                                   .waitrequest
			mac_avalon_universal_slave_0_lock                => mm_interconnect_0_mac_avalon_universal_slave_0_lock,                --                                   .lock
			mac_avalon_universal_slave_0_debugaccess         => mm_interconnect_0_mac_avalon_universal_slave_0_debugaccess,         --                                   .debugaccess
			phy_avalon_universal_slave_0_address             => mm_interconnect_0_phy_avalon_universal_slave_0_address,             --       phy_avalon_universal_slave_0.address
			phy_avalon_universal_slave_0_write               => mm_interconnect_0_phy_avalon_universal_slave_0_write,               --                                   .write
			phy_avalon_universal_slave_0_read                => mm_interconnect_0_phy_avalon_universal_slave_0_read,                --                                   .read
			phy_avalon_universal_slave_0_readdata            => mm_interconnect_0_phy_avalon_universal_slave_0_readdata,            --                                   .readdata
			phy_avalon_universal_slave_0_writedata           => mm_interconnect_0_phy_avalon_universal_slave_0_writedata,           --                                   .writedata
			phy_avalon_universal_slave_0_burstcount          => mm_interconnect_0_phy_avalon_universal_slave_0_burstcount,          --                                   .burstcount
			phy_avalon_universal_slave_0_byteenable          => mm_interconnect_0_phy_avalon_universal_slave_0_byteenable,          --                                   .byteenable
			phy_avalon_universal_slave_0_readdatavalid       => mm_interconnect_0_phy_avalon_universal_slave_0_readdatavalid,       --                                   .readdatavalid
			phy_avalon_universal_slave_0_waitrequest         => mm_interconnect_0_phy_avalon_universal_slave_0_waitrequest,         --                                   .waitrequest
			phy_avalon_universal_slave_0_lock                => mm_interconnect_0_phy_avalon_universal_slave_0_lock,                --                                   .lock
			phy_avalon_universal_slave_0_debugaccess         => mm_interconnect_0_phy_avalon_universal_slave_0_debugaccess,         --                                   .debugaccess
			xcvr_rcfg_avalon_universal_slave_0_address       => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_address,       -- xcvr_rcfg_avalon_universal_slave_0.address
			xcvr_rcfg_avalon_universal_slave_0_write         => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_write,         --                                   .write
			xcvr_rcfg_avalon_universal_slave_0_read          => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_read,          --                                   .read
			xcvr_rcfg_avalon_universal_slave_0_readdata      => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_readdata,      --                                   .readdata
			xcvr_rcfg_avalon_universal_slave_0_writedata     => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_writedata,     --                                   .writedata
			xcvr_rcfg_avalon_universal_slave_0_burstcount    => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_burstcount,    --                                   .burstcount
			xcvr_rcfg_avalon_universal_slave_0_byteenable    => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_byteenable,    --                                   .byteenable
			xcvr_rcfg_avalon_universal_slave_0_readdatavalid => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_readdatavalid, --                                   .readdatavalid
			xcvr_rcfg_avalon_universal_slave_0_waitrequest   => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_waitrequest,   --                                   .waitrequest
			xcvr_rcfg_avalon_universal_slave_0_lock          => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_lock,          --                                   .lock
			xcvr_rcfg_avalon_universal_slave_0_debugaccess   => mm_interconnect_0_xcvr_rcfg_avalon_universal_slave_0_debugaccess,   --                                   .debugaccess
			master_reset_reset_bridge_in_reset_reset         => rst_controller_reset_out_reset,                                     -- master_reset_reset_bridge_in_reset.reset
			csr_clk_clk_clk                                  => csr_clk_clk_clk                                                     --                        csr_clk_clk.clk
		);

	rst_controller : component altera_reset_controller_cmp
		generic map (
			NUM_RESET_INPUTS          => 1,
			OUTPUT_RESET_SYNC_EDGES   => "deassert",
			SYNC_DEPTH                => 2,
			RESET_REQUEST_PRESENT     => 0,
			RESET_REQ_WAIT_TIME       => 1,
			MIN_RST_ASSERTION_TIME    => 3,
			RESET_REQ_EARLY_DSRT_TIME => 1,
			USE_RESET_REQUEST_IN0     => 0,
			USE_RESET_REQUEST_IN1     => 0,
			USE_RESET_REQUEST_IN2     => 0,
			USE_RESET_REQUEST_IN3     => 0,
			USE_RESET_REQUEST_IN4     => 0,
			USE_RESET_REQUEST_IN5     => 0,
			USE_RESET_REQUEST_IN6     => 0,
			USE_RESET_REQUEST_IN7     => 0,
			USE_RESET_REQUEST_IN8     => 0,
			USE_RESET_REQUEST_IN9     => 0,
			USE_RESET_REQUEST_IN10    => 0,
			USE_RESET_REQUEST_IN11    => 0,
			USE_RESET_REQUEST_IN12    => 0,
			USE_RESET_REQUEST_IN13    => 0,
			USE_RESET_REQUEST_IN14    => 0,
			USE_RESET_REQUEST_IN15    => 0,
			ADAPT_RESET_REQUEST       => 0
		)
		port map (
			reset_in0      => csr_clk_clk_reset_reset_ports_inv, -- reset_in0.reset
			clk            => csr_clk_clk_clk,                   --       clk.clk
			reset_out      => rst_controller_reset_out_reset,    -- reset_out.reset
			reset_req      => open,                              -- (terminated)
			reset_req_in0  => '0',                               -- (terminated)
			reset_in1      => '0',                               -- (terminated)
			reset_req_in1  => '0',                               -- (terminated)
			reset_in2      => '0',                               -- (terminated)
			reset_req_in2  => '0',                               -- (terminated)
			reset_in3      => '0',                               -- (terminated)
			reset_req_in3  => '0',                               -- (terminated)
			reset_in4      => '0',                               -- (terminated)
			reset_req_in4  => '0',                               -- (terminated)
			reset_in5      => '0',                               -- (terminated)
			reset_req_in5  => '0',                               -- (terminated)
			reset_in6      => '0',                               -- (terminated)
			reset_req_in6  => '0',                               -- (terminated)
			reset_in7      => '0',                               -- (terminated)
			reset_req_in7  => '0',                               -- (terminated)
			reset_in8      => '0',                               -- (terminated)
			reset_req_in8  => '0',                               -- (terminated)
			reset_in9      => '0',                               -- (terminated)
			reset_req_in9  => '0',                               -- (terminated)
			reset_in10     => '0',                               -- (terminated)
			reset_req_in10 => '0',                               -- (terminated)
			reset_in11     => '0',                               -- (terminated)
			reset_req_in11 => '0',                               -- (terminated)
			reset_in12     => '0',                               -- (terminated)
			reset_req_in12 => '0',                               -- (terminated)
			reset_in13     => '0',                               -- (terminated)
			reset_req_in13 => '0',                               -- (terminated)
			reset_in14     => '0',                               -- (terminated)
			reset_req_in14 => '0',                               -- (terminated)
			reset_in15     => '0',                               -- (terminated)
			reset_req_in15 => '0'                                -- (terminated)
		);

	csr_clk_clk_reset_reset_ports_inv <= not csr_clk_clk_reset_reset;

end architecture rtl; -- of address_decoder_channel
