-- address_decoder_multi_channel_altera_mm_interconnect_191_yxycpgi.vhd

-- This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
-- will probably be lost.
-- 
-- Generated using ACDS version 19.4 64

library IEEE;
library altera_merlin_master_translator_191;
library altera_merlin_slave_translator_191;
library altera_merlin_master_agent_191;
library altera_merlin_slave_agent_191;
library altera_avalon_sc_fifo_191;
library altera_merlin_router_191;
library altera_merlin_traffic_limiter_191;
library altera_merlin_demultiplexer_191;
library altera_merlin_multiplexer_191;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity address_decoder_multi_channel_altera_mm_interconnect_191_yxycpgi is
	port (
		master_avalon_universal_master_0_address          : in  std_logic_vector(31 downto 0) := (others => '0'); --    master_avalon_universal_master_0.address
		master_avalon_universal_master_0_waitrequest      : out std_logic;                                        --                                    .waitrequest
		master_avalon_universal_master_0_burstcount       : in  std_logic_vector(2 downto 0)  := (others => '0'); --                                    .burstcount
		master_avalon_universal_master_0_byteenable       : in  std_logic_vector(3 downto 0)  := (others => '0'); --                                    .byteenable
		master_avalon_universal_master_0_read             : in  std_logic                     := '0';             --                                    .read
		master_avalon_universal_master_0_readdata         : out std_logic_vector(31 downto 0);                    --                                    .readdata
		master_avalon_universal_master_0_readdatavalid    : out std_logic;                                        --                                    .readdatavalid
		master_avalon_universal_master_0_write            : in  std_logic                     := '0';             --                                    .write
		master_avalon_universal_master_0_writedata        : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .writedata
		master_avalon_universal_master_0_lock             : in  std_logic                     := '0';             --                                    .lock
		master_avalon_universal_master_0_debugaccess      : in  std_logic                     := '0';             --                                    .debugaccess
		channel_1_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    --  channel_1_avalon_universal_slave_0.address
		channel_1_avalon_universal_slave_0_write          : out std_logic;                                        --                                    .write
		channel_1_avalon_universal_slave_0_read           : out std_logic;                                        --                                    .read
		channel_1_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .readdata
		channel_1_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    --                                    .writedata
		channel_1_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     --                                    .burstcount
		channel_1_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     --                                    .byteenable
		channel_1_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := '0';             --                                    .readdatavalid
		channel_1_avalon_universal_slave_0_waitrequest    : in  std_logic                     := '0';             --                                    .waitrequest
		channel_1_avalon_universal_slave_0_lock           : out std_logic;                                        --                                    .lock
		channel_1_avalon_universal_slave_0_debugaccess    : out std_logic;                                        --                                    .debugaccess
		channel_0_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    --  channel_0_avalon_universal_slave_0.address
		channel_0_avalon_universal_slave_0_write          : out std_logic;                                        --                                    .write
		channel_0_avalon_universal_slave_0_read           : out std_logic;                                        --                                    .read
		channel_0_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .readdata
		channel_0_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    --                                    .writedata
		channel_0_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     --                                    .burstcount
		channel_0_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     --                                    .byteenable
		channel_0_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := '0';             --                                    .readdatavalid
		channel_0_avalon_universal_slave_0_waitrequest    : in  std_logic                     := '0';             --                                    .waitrequest
		channel_0_avalon_universal_slave_0_lock           : out std_logic;                                        --                                    .lock
		channel_0_avalon_universal_slave_0_debugaccess    : out std_logic;                                        --                                    .debugaccess
		channel_2_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    --  channel_2_avalon_universal_slave_0.address
		channel_2_avalon_universal_slave_0_write          : out std_logic;                                        --                                    .write
		channel_2_avalon_universal_slave_0_read           : out std_logic;                                        --                                    .read
		channel_2_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .readdata
		channel_2_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    --                                    .writedata
		channel_2_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     --                                    .burstcount
		channel_2_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     --                                    .byteenable
		channel_2_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := '0';             --                                    .readdatavalid
		channel_2_avalon_universal_slave_0_waitrequest    : in  std_logic                     := '0';             --                                    .waitrequest
		channel_2_avalon_universal_slave_0_lock           : out std_logic;                                        --                                    .lock
		channel_2_avalon_universal_slave_0_debugaccess    : out std_logic;                                        --                                    .debugaccess
		channel_3_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    --  channel_3_avalon_universal_slave_0.address
		channel_3_avalon_universal_slave_0_write          : out std_logic;                                        --                                    .write
		channel_3_avalon_universal_slave_0_read           : out std_logic;                                        --                                    .read
		channel_3_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .readdata
		channel_3_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    --                                    .writedata
		channel_3_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     --                                    .burstcount
		channel_3_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     --                                    .byteenable
		channel_3_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := '0';             --                                    .readdatavalid
		channel_3_avalon_universal_slave_0_waitrequest    : in  std_logic                     := '0';             --                                    .waitrequest
		channel_3_avalon_universal_slave_0_lock           : out std_logic;                                        --                                    .lock
		channel_3_avalon_universal_slave_0_debugaccess    : out std_logic;                                        --                                    .debugaccess
		channel_4_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    --  channel_4_avalon_universal_slave_0.address
		channel_4_avalon_universal_slave_0_write          : out std_logic;                                        --                                    .write
		channel_4_avalon_universal_slave_0_read           : out std_logic;                                        --                                    .read
		channel_4_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .readdata
		channel_4_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    --                                    .writedata
		channel_4_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     --                                    .burstcount
		channel_4_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     --                                    .byteenable
		channel_4_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := '0';             --                                    .readdatavalid
		channel_4_avalon_universal_slave_0_waitrequest    : in  std_logic                     := '0';             --                                    .waitrequest
		channel_4_avalon_universal_slave_0_lock           : out std_logic;                                        --                                    .lock
		channel_4_avalon_universal_slave_0_debugaccess    : out std_logic;                                        --                                    .debugaccess
		channel_5_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    --  channel_5_avalon_universal_slave_0.address
		channel_5_avalon_universal_slave_0_write          : out std_logic;                                        --                                    .write
		channel_5_avalon_universal_slave_0_read           : out std_logic;                                        --                                    .read
		channel_5_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .readdata
		channel_5_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    --                                    .writedata
		channel_5_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     --                                    .burstcount
		channel_5_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     --                                    .byteenable
		channel_5_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := '0';             --                                    .readdatavalid
		channel_5_avalon_universal_slave_0_waitrequest    : in  std_logic                     := '0';             --                                    .waitrequest
		channel_5_avalon_universal_slave_0_lock           : out std_logic;                                        --                                    .lock
		channel_5_avalon_universal_slave_0_debugaccess    : out std_logic;                                        --                                    .debugaccess
		channel_6_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    --  channel_6_avalon_universal_slave_0.address
		channel_6_avalon_universal_slave_0_write          : out std_logic;                                        --                                    .write
		channel_6_avalon_universal_slave_0_read           : out std_logic;                                        --                                    .read
		channel_6_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .readdata
		channel_6_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    --                                    .writedata
		channel_6_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     --                                    .burstcount
		channel_6_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     --                                    .byteenable
		channel_6_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := '0';             --                                    .readdatavalid
		channel_6_avalon_universal_slave_0_waitrequest    : in  std_logic                     := '0';             --                                    .waitrequest
		channel_6_avalon_universal_slave_0_lock           : out std_logic;                                        --                                    .lock
		channel_6_avalon_universal_slave_0_debugaccess    : out std_logic;                                        --                                    .debugaccess
		channel_7_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    --  channel_7_avalon_universal_slave_0.address
		channel_7_avalon_universal_slave_0_write          : out std_logic;                                        --                                    .write
		channel_7_avalon_universal_slave_0_read           : out std_logic;                                        --                                    .read
		channel_7_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .readdata
		channel_7_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    --                                    .writedata
		channel_7_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     --                                    .burstcount
		channel_7_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     --                                    .byteenable
		channel_7_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := '0';             --                                    .readdatavalid
		channel_7_avalon_universal_slave_0_waitrequest    : in  std_logic                     := '0';             --                                    .waitrequest
		channel_7_avalon_universal_slave_0_lock           : out std_logic;                                        --                                    .lock
		channel_7_avalon_universal_slave_0_debugaccess    : out std_logic;                                        --                                    .debugaccess
		channel_8_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    --  channel_8_avalon_universal_slave_0.address
		channel_8_avalon_universal_slave_0_write          : out std_logic;                                        --                                    .write
		channel_8_avalon_universal_slave_0_read           : out std_logic;                                        --                                    .read
		channel_8_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .readdata
		channel_8_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    --                                    .writedata
		channel_8_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     --                                    .burstcount
		channel_8_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     --                                    .byteenable
		channel_8_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := '0';             --                                    .readdatavalid
		channel_8_avalon_universal_slave_0_waitrequest    : in  std_logic                     := '0';             --                                    .waitrequest
		channel_8_avalon_universal_slave_0_lock           : out std_logic;                                        --                                    .lock
		channel_8_avalon_universal_slave_0_debugaccess    : out std_logic;                                        --                                    .debugaccess
		channel_9_avalon_universal_slave_0_address        : out std_logic_vector(15 downto 0);                    --  channel_9_avalon_universal_slave_0.address
		channel_9_avalon_universal_slave_0_write          : out std_logic;                                        --                                    .write
		channel_9_avalon_universal_slave_0_read           : out std_logic;                                        --                                    .read
		channel_9_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .readdata
		channel_9_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    --                                    .writedata
		channel_9_avalon_universal_slave_0_burstcount     : out std_logic_vector(2 downto 0);                     --                                    .burstcount
		channel_9_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     --                                    .byteenable
		channel_9_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := '0';             --                                    .readdatavalid
		channel_9_avalon_universal_slave_0_waitrequest    : in  std_logic                     := '0';             --                                    .waitrequest
		channel_9_avalon_universal_slave_0_lock           : out std_logic;                                        --                                    .lock
		channel_9_avalon_universal_slave_0_debugaccess    : out std_logic;                                        --                                    .debugaccess
		channel_10_avalon_universal_slave_0_address       : out std_logic_vector(15 downto 0);                    -- channel_10_avalon_universal_slave_0.address
		channel_10_avalon_universal_slave_0_write         : out std_logic;                                        --                                    .write
		channel_10_avalon_universal_slave_0_read          : out std_logic;                                        --                                    .read
		channel_10_avalon_universal_slave_0_readdata      : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .readdata
		channel_10_avalon_universal_slave_0_writedata     : out std_logic_vector(31 downto 0);                    --                                    .writedata
		channel_10_avalon_universal_slave_0_burstcount    : out std_logic_vector(2 downto 0);                     --                                    .burstcount
		channel_10_avalon_universal_slave_0_byteenable    : out std_logic_vector(3 downto 0);                     --                                    .byteenable
		channel_10_avalon_universal_slave_0_readdatavalid : in  std_logic                     := '0';             --                                    .readdatavalid
		channel_10_avalon_universal_slave_0_waitrequest   : in  std_logic                     := '0';             --                                    .waitrequest
		channel_10_avalon_universal_slave_0_lock          : out std_logic;                                        --                                    .lock
		channel_10_avalon_universal_slave_0_debugaccess   : out std_logic;                                        --                                    .debugaccess
		channel_11_avalon_universal_slave_0_address       : out std_logic_vector(15 downto 0);                    -- channel_11_avalon_universal_slave_0.address
		channel_11_avalon_universal_slave_0_write         : out std_logic;                                        --                                    .write
		channel_11_avalon_universal_slave_0_read          : out std_logic;                                        --                                    .read
		channel_11_avalon_universal_slave_0_readdata      : in  std_logic_vector(31 downto 0) := (others => '0'); --                                    .readdata
		channel_11_avalon_universal_slave_0_writedata     : out std_logic_vector(31 downto 0);                    --                                    .writedata
		channel_11_avalon_universal_slave_0_burstcount    : out std_logic_vector(2 downto 0);                     --                                    .burstcount
		channel_11_avalon_universal_slave_0_byteenable    : out std_logic_vector(3 downto 0);                     --                                    .byteenable
		channel_11_avalon_universal_slave_0_readdatavalid : in  std_logic                     := '0';             --                                    .readdatavalid
		channel_11_avalon_universal_slave_0_waitrequest   : in  std_logic                     := '0';             --                                    .waitrequest
		channel_11_avalon_universal_slave_0_lock          : out std_logic;                                        --                                    .lock
		channel_11_avalon_universal_slave_0_debugaccess   : out std_logic;                                        --                                    .debugaccess
		master_reset_reset_bridge_in_reset_reset          : in  std_logic                     := '0';             --  master_reset_reset_bridge_in_reset.reset
		csr_clk_clk_clk                                   : in  std_logic                     := '0'              --                         csr_clk_clk.clk
	);
end entity address_decoder_multi_channel_altera_mm_interconnect_191_yxycpgi;

architecture rtl of address_decoder_multi_channel_altera_mm_interconnect_191_yxycpgi is
	component address_decoder_multi_channel_altera_merlin_master_translator_191_g7h47bq_cmp is
		generic (
			AV_ADDRESS_W                : integer := 32;
			AV_DATA_W                   : integer := 32;
			AV_BURSTCOUNT_W             : integer := 4;
			AV_BYTEENABLE_W             : integer := 4;
			UAV_ADDRESS_W               : integer := 38;
			UAV_BURSTCOUNT_W            : integer := 10;
			USE_READ                    : integer := 1;
			USE_WRITE                   : integer := 1;
			USE_BEGINBURSTTRANSFER      : integer := 0;
			USE_BEGINTRANSFER           : integer := 0;
			USE_CHIPSELECT              : integer := 0;
			USE_BURSTCOUNT              : integer := 1;
			USE_READDATAVALID           : integer := 1;
			USE_WAITREQUEST             : integer := 1;
			USE_READRESPONSE            : integer := 0;
			USE_WRITERESPONSE           : integer := 0;
			AV_SYMBOLS_PER_WORD         : integer := 4;
			AV_ADDRESS_SYMBOLS          : integer := 0;
			AV_BURSTCOUNT_SYMBOLS       : integer := 0;
			AV_CONSTANT_BURST_BEHAVIOR  : integer := 0;
			UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
			AV_LINEWRAPBURSTS           : integer := 0;
			AV_REGISTERINCOMINGSIGNALS  : integer := 0;
			SYNC_RESET                  : integer := 0;
			WAITREQUEST_ALLOWANCE       : integer := 0
		);
		port (
			clk                    : in  std_logic                     := 'X';             -- clk
			reset                  : in  std_logic                     := 'X';             -- reset
			uav_address            : out std_logic_vector(31 downto 0);                    -- address
			uav_burstcount         : out std_logic_vector(2 downto 0);                     -- burstcount
			uav_read               : out std_logic;                                        -- read
			uav_write              : out std_logic;                                        -- write
			uav_waitrequest        : in  std_logic                     := 'X';             -- waitrequest
			uav_readdatavalid      : in  std_logic                     := 'X';             -- readdatavalid
			uav_byteenable         : out std_logic_vector(3 downto 0);                     -- byteenable
			uav_readdata           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			uav_writedata          : out std_logic_vector(31 downto 0);                    -- writedata
			uav_lock               : out std_logic;                                        -- lock
			uav_debugaccess        : out std_logic;                                        -- debugaccess
			av_address             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- address
			av_waitrequest         : out std_logic;                                        -- waitrequest
			av_burstcount          : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			av_byteenable          : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			av_read                : in  std_logic                     := 'X';             -- read
			av_readdata            : out std_logic_vector(31 downto 0);                    -- readdata
			av_readdatavalid       : out std_logic;                                        -- readdatavalid
			av_write               : in  std_logic                     := 'X';             -- write
			av_writedata           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			av_lock                : in  std_logic                     := 'X';             -- lock
			av_debugaccess         : in  std_logic                     := 'X';             -- debugaccess
			av_beginbursttransfer  : in  std_logic                     := 'X';             -- beginbursttransfer
			av_begintransfer       : in  std_logic                     := 'X';             -- begintransfer
			av_chipselect          : in  std_logic                     := 'X';             -- chipselect
			uav_clken              : out std_logic;                                        -- clken
			av_clken               : in  std_logic                     := 'X';             -- clken
			uav_response           : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- response
			av_response            : out std_logic_vector(1 downto 0);                     -- response
			uav_writeresponsevalid : in  std_logic                     := 'X';             -- writeresponsevalid
			av_writeresponsevalid  : out std_logic                                         -- writeresponsevalid
		);
	end component address_decoder_multi_channel_altera_merlin_master_translator_191_g7h47bq_cmp;

	component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp is
		generic (
			AV_ADDRESS_W                   : integer := 30;
			AV_DATA_W                      : integer := 32;
			UAV_DATA_W                     : integer := 32;
			AV_BURSTCOUNT_W                : integer := 4;
			AV_BYTEENABLE_W                : integer := 4;
			UAV_BYTEENABLE_W               : integer := 4;
			UAV_ADDRESS_W                  : integer := 32;
			UAV_BURSTCOUNT_W               : integer := 4;
			AV_READLATENCY                 : integer := 0;
			USE_READDATAVALID              : integer := 1;
			USE_WAITREQUEST                : integer := 1;
			USE_UAV_CLKEN                  : integer := 0;
			USE_READRESPONSE               : integer := 0;
			USE_WRITERESPONSE              : integer := 0;
			AV_SYMBOLS_PER_WORD            : integer := 4;
			AV_ADDRESS_SYMBOLS             : integer := 0;
			AV_BURSTCOUNT_SYMBOLS          : integer := 0;
			AV_CONSTANT_BURST_BEHAVIOR     : integer := 0;
			UAV_CONSTANT_BURST_BEHAVIOR    : integer := 0;
			AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
			CHIPSELECT_THROUGH_READLATENCY : integer := 0;
			AV_READ_WAIT_CYCLES            : integer := 0;
			AV_WRITE_WAIT_CYCLES           : integer := 0;
			AV_SETUP_WAIT_CYCLES           : integer := 0;
			AV_DATA_HOLD_CYCLES            : integer := 0;
			WAITREQUEST_ALLOWANCE          : integer := 0;
			SYNC_RESET                     : integer := 0
		);
		port (
			clk                    : in  std_logic                     := 'X';             -- clk
			reset                  : in  std_logic                     := 'X';             -- reset
			uav_address            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- address
			uav_burstcount         : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read               : in  std_logic                     := 'X';             -- read
			uav_write              : in  std_logic                     := 'X';             -- write
			uav_waitrequest        : out std_logic;                                        -- waitrequest
			uav_readdatavalid      : out std_logic;                                        -- readdatavalid
			uav_byteenable         : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata           : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock               : in  std_logic                     := 'X';             -- lock
			uav_debugaccess        : in  std_logic                     := 'X';             -- debugaccess
			av_address             : out std_logic_vector(15 downto 0);                    -- address
			av_write               : out std_logic;                                        -- write
			av_read                : out std_logic;                                        -- read
			av_readdata            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata           : out std_logic_vector(31 downto 0);                    -- writedata
			av_burstcount          : out std_logic_vector(2 downto 0);                     -- burstcount
			av_byteenable          : out std_logic_vector(3 downto 0);                     -- byteenable
			av_readdatavalid       : in  std_logic                     := 'X';             -- readdatavalid
			av_waitrequest         : in  std_logic                     := 'X';             -- waitrequest
			av_lock                : out std_logic;                                        -- lock
			av_debugaccess         : out std_logic;                                        -- debugaccess
			av_begintransfer       : out std_logic;                                        -- begintransfer
			av_beginbursttransfer  : out std_logic;                                        -- beginbursttransfer
			av_writebyteenable     : out std_logic_vector(3 downto 0);                     -- writebyteenable
			av_chipselect          : out std_logic;                                        -- chipselect
			av_clken               : out std_logic;                                        -- clken
			uav_clken              : in  std_logic                     := 'X';             -- clken
			av_outputenable        : out std_logic;                                        -- outputenable
			uav_response           : out std_logic_vector(1 downto 0);                     -- response
			av_response            : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- response
			uav_writeresponsevalid : out std_logic;                                        -- writeresponsevalid
			av_writeresponsevalid  : in  std_logic                     := 'X'              -- writeresponsevalid
		);
	end component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp;

	component address_decoder_multi_channel_altera_merlin_master_agent_191_mpbm6tq_cmp is
		generic (
			PKT_WUNIQUE               : integer := 125;
			PKT_DOMAIN_H              : integer := 124;
			PKT_DOMAIN_L              : integer := 123;
			PKT_SNOOP_H               : integer := 122;
			PKT_SNOOP_L               : integer := 119;
			PKT_BARRIER_H             : integer := 118;
			PKT_BARRIER_L             : integer := 117;
			PKT_ORI_BURST_SIZE_H      : integer := 116;
			PKT_ORI_BURST_SIZE_L      : integer := 114;
			PKT_RESPONSE_STATUS_H     : integer := 113;
			PKT_RESPONSE_STATUS_L     : integer := 112;
			PKT_QOS_H                 : integer := 111;
			PKT_QOS_L                 : integer := 108;
			PKT_DATA_SIDEBAND_H       : integer := 107;
			PKT_DATA_SIDEBAND_L       : integer := 100;
			PKT_ADDR_SIDEBAND_H       : integer := 99;
			PKT_ADDR_SIDEBAND_L       : integer := 95;
			PKT_BURST_TYPE_H          : integer := 94;
			PKT_BURST_TYPE_L          : integer := 93;
			PKT_CACHE_H               : integer := 92;
			PKT_CACHE_L               : integer := 89;
			PKT_THREAD_ID_H           : integer := 88;
			PKT_THREAD_ID_L           : integer := 87;
			PKT_BURST_SIZE_H          : integer := 86;
			PKT_BURST_SIZE_L          : integer := 84;
			PKT_TRANS_EXCLUSIVE       : integer := 83;
			PKT_TRANS_LOCK            : integer := 82;
			PKT_BEGIN_BURST           : integer := 81;
			PKT_PROTECTION_H          : integer := 80;
			PKT_PROTECTION_L          : integer := 80;
			PKT_BURSTWRAP_H           : integer := 79;
			PKT_BURSTWRAP_L           : integer := 77;
			PKT_BYTE_CNT_H            : integer := 76;
			PKT_BYTE_CNT_L            : integer := 74;
			PKT_ADDR_H                : integer := 73;
			PKT_ADDR_L                : integer := 42;
			PKT_TRANS_COMPRESSED_READ : integer := 41;
			PKT_TRANS_POSTED          : integer := 40;
			PKT_TRANS_WRITE           : integer := 39;
			PKT_TRANS_READ            : integer := 38;
			PKT_DATA_H                : integer := 37;
			PKT_DATA_L                : integer := 6;
			PKT_BYTEEN_H              : integer := 5;
			PKT_BYTEEN_L              : integer := 2;
			PKT_SRC_ID_H              : integer := 1;
			PKT_SRC_ID_L              : integer := 1;
			PKT_DEST_ID_H             : integer := 0;
			PKT_DEST_ID_L             : integer := 0;
			ST_DATA_W                 : integer := 126;
			ST_CHANNEL_W              : integer := 1;
			AV_BURSTCOUNT_W           : integer := 3;
			SUPPRESS_0_BYTEEN_RSP     : integer := 1;
			ID                        : integer := 1;
			BURSTWRAP_VALUE           : integer := 4;
			CACHE_VALUE               : integer := 0;
			SECURE_ACCESS_BIT         : integer := 1;
			USE_READRESPONSE          : integer := 0;
			USE_WRITERESPONSE         : integer := 0;
			DOMAIN_VALUE              : integer := 3;
			BARRIER_VALUE             : integer := 0;
			SNOOP_VALUE               : integer := 0;
			WUNIQUE_VALUE             : integer := 0;
			SYNC_RESET                : integer := 0
		);
		port (
			clk                   : in  std_logic                      := 'X';             -- clk
			reset                 : in  std_logic                      := 'X';             -- reset
			av_address            : in  std_logic_vector(31 downto 0)  := (others => 'X'); -- address
			av_write              : in  std_logic                      := 'X';             -- write
			av_read               : in  std_logic                      := 'X';             -- read
			av_writedata          : in  std_logic_vector(31 downto 0)  := (others => 'X'); -- writedata
			av_readdata           : out std_logic_vector(31 downto 0);                     -- readdata
			av_waitrequest        : out std_logic;                                         -- waitrequest
			av_readdatavalid      : out std_logic;                                         -- readdatavalid
			av_byteenable         : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- byteenable
			av_burstcount         : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- burstcount
			av_debugaccess        : in  std_logic                      := 'X';             -- debugaccess
			av_lock               : in  std_logic                      := 'X';             -- lock
			cp_valid              : out std_logic;                                         -- valid
			cp_data               : out std_logic_vector(116 downto 0);                    -- data
			cp_startofpacket      : out std_logic;                                         -- startofpacket
			cp_endofpacket        : out std_logic;                                         -- endofpacket
			cp_ready              : in  std_logic                      := 'X';             -- ready
			rp_valid              : in  std_logic                      := 'X';             -- valid
			rp_data               : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			rp_channel            : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			rp_startofpacket      : in  std_logic                      := 'X';             -- startofpacket
			rp_endofpacket        : in  std_logic                      := 'X';             -- endofpacket
			rp_ready              : out std_logic;                                         -- ready
			av_response           : out std_logic_vector(1 downto 0);                      -- response
			av_writeresponsevalid : out std_logic                                          -- writeresponsevalid
		);
	end component address_decoder_multi_channel_altera_merlin_master_agent_191_mpbm6tq_cmp;

	component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp is
		generic (
			PKT_ORI_BURST_SIZE_H      : integer := 90;
			PKT_ORI_BURST_SIZE_L      : integer := 88;
			PKT_RESPONSE_STATUS_H     : integer := 87;
			PKT_RESPONSE_STATUS_L     : integer := 86;
			PKT_BURST_SIZE_H          : integer := 85;
			PKT_BURST_SIZE_L          : integer := 83;
			PKT_TRANS_LOCK            : integer := 82;
			PKT_BEGIN_BURST           : integer := 81;
			PKT_PROTECTION_H          : integer := 80;
			PKT_PROTECTION_L          : integer := 80;
			PKT_BURSTWRAP_H           : integer := 79;
			PKT_BURSTWRAP_L           : integer := 77;
			PKT_BYTE_CNT_H            : integer := 76;
			PKT_BYTE_CNT_L            : integer := 74;
			PKT_ADDR_H                : integer := 73;
			PKT_ADDR_L                : integer := 42;
			PKT_TRANS_COMPRESSED_READ : integer := 41;
			PKT_TRANS_POSTED          : integer := 40;
			PKT_TRANS_WRITE           : integer := 39;
			PKT_TRANS_READ            : integer := 38;
			PKT_DATA_H                : integer := 37;
			PKT_DATA_L                : integer := 6;
			PKT_BYTEEN_H              : integer := 5;
			PKT_BYTEEN_L              : integer := 2;
			PKT_SRC_ID_H              : integer := 1;
			PKT_SRC_ID_L              : integer := 1;
			PKT_DEST_ID_H             : integer := 0;
			PKT_DEST_ID_L             : integer := 0;
			PKT_SYMBOL_W              : integer := 8;
			ST_CHANNEL_W              : integer := 8;
			ST_DATA_W                 : integer := 96;
			AVS_BURSTCOUNT_W          : integer := 4;
			SUPPRESS_0_BYTEEN_CMD     : integer := 1;
			PREVENT_FIFO_OVERFLOW     : integer := 0;
			USE_READRESPONSE          : integer := 0;
			USE_WRITERESPONSE         : integer := 0;
			ECC_ENABLE                : integer := 0;
			SYNC_RESET                : integer := 0
		);
		port (
			clk                     : in  std_logic                      := 'X';             -- clk
			reset                   : in  std_logic                      := 'X';             -- reset
			m0_address              : out std_logic_vector(31 downto 0);                     -- address
			m0_burstcount           : out std_logic_vector(2 downto 0);                      -- burstcount
			m0_byteenable           : out std_logic_vector(3 downto 0);                      -- byteenable
			m0_debugaccess          : out std_logic;                                         -- debugaccess
			m0_lock                 : out std_logic;                                         -- lock
			m0_readdata             : in  std_logic_vector(31 downto 0)  := (others => 'X'); -- readdata
			m0_readdatavalid        : in  std_logic                      := 'X';             -- readdatavalid
			m0_read                 : out std_logic;                                         -- read
			m0_waitrequest          : in  std_logic                      := 'X';             -- waitrequest
			m0_writedata            : out std_logic_vector(31 downto 0);                     -- writedata
			m0_write                : out std_logic;                                         -- write
			rp_endofpacket          : out std_logic;                                         -- endofpacket
			rp_ready                : in  std_logic                      := 'X';             -- ready
			rp_valid                : out std_logic;                                         -- valid
			rp_data                 : out std_logic_vector(116 downto 0);                    -- data
			rp_startofpacket        : out std_logic;                                         -- startofpacket
			cp_ready                : out std_logic;                                         -- ready
			cp_valid                : in  std_logic                      := 'X';             -- valid
			cp_data                 : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			cp_startofpacket        : in  std_logic                      := 'X';             -- startofpacket
			cp_endofpacket          : in  std_logic                      := 'X';             -- endofpacket
			cp_channel              : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			rf_sink_ready           : out std_logic;                                         -- ready
			rf_sink_valid           : in  std_logic                      := 'X';             -- valid
			rf_sink_startofpacket   : in  std_logic                      := 'X';             -- startofpacket
			rf_sink_endofpacket     : in  std_logic                      := 'X';             -- endofpacket
			rf_sink_data            : in  std_logic_vector(117 downto 0) := (others => 'X'); -- data
			rf_source_ready         : in  std_logic                      := 'X';             -- ready
			rf_source_valid         : out std_logic;                                         -- valid
			rf_source_startofpacket : out std_logic;                                         -- startofpacket
			rf_source_endofpacket   : out std_logic;                                         -- endofpacket
			rf_source_data          : out std_logic_vector(117 downto 0);                    -- data
			rdata_fifo_sink_ready   : out std_logic;                                         -- ready
			rdata_fifo_sink_valid   : in  std_logic                      := 'X';             -- valid
			rdata_fifo_sink_data    : in  std_logic_vector(33 downto 0)  := (others => 'X'); -- data
			rdata_fifo_src_ready    : in  std_logic                      := 'X';             -- ready
			rdata_fifo_src_valid    : out std_logic;                                         -- valid
			rdata_fifo_src_data     : out std_logic_vector(33 downto 0);                     -- data
			m0_response             : in  std_logic_vector(1 downto 0)   := (others => 'X'); -- response
			m0_writeresponsevalid   : in  std_logic                      := 'X';             -- writeresponsevalid
			rdata_fifo_sink_error   : in  std_logic                      := 'X'              -- error
		);
	end component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp;

	component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp is
		generic (
			SYMBOLS_PER_BEAT    : integer := 1;
			BITS_PER_SYMBOL     : integer := 8;
			FIFO_DEPTH          : integer := 16;
			CHANNEL_WIDTH       : integer := 0;
			ERROR_WIDTH         : integer := 0;
			USE_PACKETS         : integer := 0;
			USE_FILL_LEVEL      : integer := 0;
			EMPTY_LATENCY       : integer := 3;
			USE_MEMORY_BLOCKS   : integer := 1;
			USE_STORE_FORWARD   : integer := 0;
			USE_ALMOST_FULL_IF  : integer := 0;
			USE_ALMOST_EMPTY_IF : integer := 0;
			EMPTY_WIDTH         : integer := 1;
			SYNC_RESET          : integer := 0
		);
		port (
			clk               : in  std_logic                      := 'X';             -- clk
			reset             : in  std_logic                      := 'X';             -- reset
			in_data           : in  std_logic_vector(117 downto 0) := (others => 'X'); -- data
			in_valid          : in  std_logic                      := 'X';             -- valid
			in_ready          : out std_logic;                                         -- ready
			in_startofpacket  : in  std_logic                      := 'X';             -- startofpacket
			in_endofpacket    : in  std_logic                      := 'X';             -- endofpacket
			out_data          : out std_logic_vector(117 downto 0);                    -- data
			out_valid         : out std_logic;                                         -- valid
			out_ready         : in  std_logic                      := 'X';             -- ready
			out_startofpacket : out std_logic;                                         -- startofpacket
			out_endofpacket   : out std_logic;                                         -- endofpacket
			csr_address       : in  std_logic_vector(1 downto 0)   := (others => 'X'); -- address
			csr_read          : in  std_logic                      := 'X';             -- read
			csr_write         : in  std_logic                      := 'X';             -- write
			csr_readdata      : out std_logic_vector(31 downto 0);                     -- readdata
			csr_writedata     : in  std_logic_vector(31 downto 0)  := (others => 'X'); -- writedata
			almost_full_data  : out std_logic;                                         -- data
			almost_empty_data : out std_logic;                                         -- data
			in_empty          : in  std_logic_vector(0 downto 0)   := (others => 'X'); -- empty
			out_empty         : out std_logic_vector(0 downto 0);                      -- empty
			in_error          : in  std_logic_vector(0 downto 0)   := (others => 'X'); -- error
			out_error         : out std_logic_vector(0 downto 0);                      -- error
			in_channel        : in  std_logic_vector(0 downto 0)   := (others => 'X'); -- channel
			out_channel       : out std_logic_vector(0 downto 0)                       -- channel
		);
	end component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp;

	component address_decoder_multi_channel_altera_merlin_router_191_32egg6a_cmp is
		port (
			sink_ready         : out std_logic;                                         -- ready
			sink_valid         : in  std_logic                      := 'X';             -- valid
			sink_data          : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink_startofpacket : in  std_logic                      := 'X';             -- startofpacket
			sink_endofpacket   : in  std_logic                      := 'X';             -- endofpacket
			clk                : in  std_logic                      := 'X';             -- clk
			reset              : in  std_logic                      := 'X';             -- reset
			src_ready          : in  std_logic                      := 'X';             -- ready
			src_valid          : out std_logic;                                         -- valid
			src_data           : out std_logic_vector(116 downto 0);                    -- data
			src_channel        : out std_logic_vector(11 downto 0);                     -- channel
			src_startofpacket  : out std_logic;                                         -- startofpacket
			src_endofpacket    : out std_logic                                          -- endofpacket
		);
	end component address_decoder_multi_channel_altera_merlin_router_191_32egg6a_cmp;

	component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp is
		port (
			sink_ready         : out std_logic;                                         -- ready
			sink_valid         : in  std_logic                      := 'X';             -- valid
			sink_data          : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink_startofpacket : in  std_logic                      := 'X';             -- startofpacket
			sink_endofpacket   : in  std_logic                      := 'X';             -- endofpacket
			clk                : in  std_logic                      := 'X';             -- clk
			reset              : in  std_logic                      := 'X';             -- reset
			src_ready          : in  std_logic                      := 'X';             -- ready
			src_valid          : out std_logic;                                         -- valid
			src_data           : out std_logic_vector(116 downto 0);                    -- data
			src_channel        : out std_logic_vector(11 downto 0);                     -- channel
			src_startofpacket  : out std_logic;                                         -- startofpacket
			src_endofpacket    : out std_logic                                          -- endofpacket
		);
	end component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp;

	component address_decoder_multi_channel_altera_merlin_traffic_limiter_191_kcba44q_cmp is
		generic (
			SYNC_RESET                : integer := 0;
			PKT_DEST_ID_H             : integer := 6;
			PKT_DEST_ID_L             : integer := 6;
			PKT_SRC_ID_H              : integer := 5;
			PKT_SRC_ID_L              : integer := 5;
			PKT_BYTE_CNT_H            : integer := 4;
			PKT_BYTE_CNT_L            : integer := 4;
			PKT_BYTEEN_H              : integer := 3;
			PKT_BYTEEN_L              : integer := 3;
			PKT_TRANS_POSTED          : integer := 1;
			PKT_TRANS_WRITE           : integer := 0;
			MAX_OUTSTANDING_RESPONSES : integer := 0;
			PIPELINED                 : integer := 0;
			ST_DATA_W                 : integer := 72;
			ST_CHANNEL_W              : integer := 1;
			VALID_WIDTH               : integer := 1;
			ENFORCE_ORDER             : integer := 1;
			PREVENT_HAZARDS           : integer := 0;
			SUPPORTS_POSTED_WRITES    : integer := 1;
			SUPPORTS_NONPOSTED_WRITES : integer := 0;
			REORDER                   : integer := 0
		);
		port (
			clk                    : in  std_logic                      := 'X';             -- clk
			reset                  : in  std_logic                      := 'X';             -- reset
			cmd_sink_ready         : out std_logic;                                         -- ready
			cmd_sink_valid         : in  std_logic                      := 'X';             -- valid
			cmd_sink_data          : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			cmd_sink_channel       : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			cmd_sink_startofpacket : in  std_logic                      := 'X';             -- startofpacket
			cmd_sink_endofpacket   : in  std_logic                      := 'X';             -- endofpacket
			cmd_src_ready          : in  std_logic                      := 'X';             -- ready
			cmd_src_data           : out std_logic_vector(116 downto 0);                    -- data
			cmd_src_channel        : out std_logic_vector(11 downto 0);                     -- channel
			cmd_src_startofpacket  : out std_logic;                                         -- startofpacket
			cmd_src_endofpacket    : out std_logic;                                         -- endofpacket
			rsp_sink_ready         : out std_logic;                                         -- ready
			rsp_sink_valid         : in  std_logic                      := 'X';             -- valid
			rsp_sink_channel       : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			rsp_sink_data          : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			rsp_sink_startofpacket : in  std_logic                      := 'X';             -- startofpacket
			rsp_sink_endofpacket   : in  std_logic                      := 'X';             -- endofpacket
			rsp_src_ready          : in  std_logic                      := 'X';             -- ready
			rsp_src_valid          : out std_logic;                                         -- valid
			rsp_src_data           : out std_logic_vector(116 downto 0);                    -- data
			rsp_src_channel        : out std_logic_vector(11 downto 0);                     -- channel
			rsp_src_startofpacket  : out std_logic;                                         -- startofpacket
			rsp_src_endofpacket    : out std_logic;                                         -- endofpacket
			cmd_src_valid          : out std_logic_vector(11 downto 0)                      -- data
		);
	end component address_decoder_multi_channel_altera_merlin_traffic_limiter_191_kcba44q_cmp;

	component address_decoder_multi_channel_altera_merlin_demultiplexer_191_vs5t6hy_cmp is
		port (
			clk                 : in  std_logic                      := 'X';             -- clk
			reset               : in  std_logic                      := 'X';             -- reset
			sink_ready          : out std_logic;                                         -- ready
			sink_channel        : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink_data           : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink_startofpacket  : in  std_logic                      := 'X';             -- startofpacket
			sink_endofpacket    : in  std_logic                      := 'X';             -- endofpacket
			sink_valid          : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- data
			src0_ready          : in  std_logic                      := 'X';             -- ready
			src0_valid          : out std_logic;                                         -- valid
			src0_data           : out std_logic_vector(116 downto 0);                    -- data
			src0_channel        : out std_logic_vector(11 downto 0);                     -- channel
			src0_startofpacket  : out std_logic;                                         -- startofpacket
			src0_endofpacket    : out std_logic;                                         -- endofpacket
			src1_ready          : in  std_logic                      := 'X';             -- ready
			src1_valid          : out std_logic;                                         -- valid
			src1_data           : out std_logic_vector(116 downto 0);                    -- data
			src1_channel        : out std_logic_vector(11 downto 0);                     -- channel
			src1_startofpacket  : out std_logic;                                         -- startofpacket
			src1_endofpacket    : out std_logic;                                         -- endofpacket
			src2_ready          : in  std_logic                      := 'X';             -- ready
			src2_valid          : out std_logic;                                         -- valid
			src2_data           : out std_logic_vector(116 downto 0);                    -- data
			src2_channel        : out std_logic_vector(11 downto 0);                     -- channel
			src2_startofpacket  : out std_logic;                                         -- startofpacket
			src2_endofpacket    : out std_logic;                                         -- endofpacket
			src3_ready          : in  std_logic                      := 'X';             -- ready
			src3_valid          : out std_logic;                                         -- valid
			src3_data           : out std_logic_vector(116 downto 0);                    -- data
			src3_channel        : out std_logic_vector(11 downto 0);                     -- channel
			src3_startofpacket  : out std_logic;                                         -- startofpacket
			src3_endofpacket    : out std_logic;                                         -- endofpacket
			src4_ready          : in  std_logic                      := 'X';             -- ready
			src4_valid          : out std_logic;                                         -- valid
			src4_data           : out std_logic_vector(116 downto 0);                    -- data
			src4_channel        : out std_logic_vector(11 downto 0);                     -- channel
			src4_startofpacket  : out std_logic;                                         -- startofpacket
			src4_endofpacket    : out std_logic;                                         -- endofpacket
			src5_ready          : in  std_logic                      := 'X';             -- ready
			src5_valid          : out std_logic;                                         -- valid
			src5_data           : out std_logic_vector(116 downto 0);                    -- data
			src5_channel        : out std_logic_vector(11 downto 0);                     -- channel
			src5_startofpacket  : out std_logic;                                         -- startofpacket
			src5_endofpacket    : out std_logic;                                         -- endofpacket
			src6_ready          : in  std_logic                      := 'X';             -- ready
			src6_valid          : out std_logic;                                         -- valid
			src6_data           : out std_logic_vector(116 downto 0);                    -- data
			src6_channel        : out std_logic_vector(11 downto 0);                     -- channel
			src6_startofpacket  : out std_logic;                                         -- startofpacket
			src6_endofpacket    : out std_logic;                                         -- endofpacket
			src7_ready          : in  std_logic                      := 'X';             -- ready
			src7_valid          : out std_logic;                                         -- valid
			src7_data           : out std_logic_vector(116 downto 0);                    -- data
			src7_channel        : out std_logic_vector(11 downto 0);                     -- channel
			src7_startofpacket  : out std_logic;                                         -- startofpacket
			src7_endofpacket    : out std_logic;                                         -- endofpacket
			src8_ready          : in  std_logic                      := 'X';             -- ready
			src8_valid          : out std_logic;                                         -- valid
			src8_data           : out std_logic_vector(116 downto 0);                    -- data
			src8_channel        : out std_logic_vector(11 downto 0);                     -- channel
			src8_startofpacket  : out std_logic;                                         -- startofpacket
			src8_endofpacket    : out std_logic;                                         -- endofpacket
			src9_ready          : in  std_logic                      := 'X';             -- ready
			src9_valid          : out std_logic;                                         -- valid
			src9_data           : out std_logic_vector(116 downto 0);                    -- data
			src9_channel        : out std_logic_vector(11 downto 0);                     -- channel
			src9_startofpacket  : out std_logic;                                         -- startofpacket
			src9_endofpacket    : out std_logic;                                         -- endofpacket
			src10_ready         : in  std_logic                      := 'X';             -- ready
			src10_valid         : out std_logic;                                         -- valid
			src10_data          : out std_logic_vector(116 downto 0);                    -- data
			src10_channel       : out std_logic_vector(11 downto 0);                     -- channel
			src10_startofpacket : out std_logic;                                         -- startofpacket
			src10_endofpacket   : out std_logic;                                         -- endofpacket
			src11_ready         : in  std_logic                      := 'X';             -- ready
			src11_valid         : out std_logic;                                         -- valid
			src11_data          : out std_logic_vector(116 downto 0);                    -- data
			src11_channel       : out std_logic_vector(11 downto 0);                     -- channel
			src11_startofpacket : out std_logic;                                         -- startofpacket
			src11_endofpacket   : out std_logic                                          -- endofpacket
		);
	end component address_decoder_multi_channel_altera_merlin_demultiplexer_191_vs5t6hy_cmp;

	component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp is
		port (
			clk                 : in  std_logic                      := 'X';             -- clk
			reset               : in  std_logic                      := 'X';             -- reset
			src_ready           : in  std_logic                      := 'X';             -- ready
			src_valid           : out std_logic;                                         -- valid
			src_data            : out std_logic_vector(116 downto 0);                    -- data
			src_channel         : out std_logic_vector(11 downto 0);                     -- channel
			src_startofpacket   : out std_logic;                                         -- startofpacket
			src_endofpacket     : out std_logic;                                         -- endofpacket
			sink0_ready         : out std_logic;                                         -- ready
			sink0_valid         : in  std_logic                      := 'X';             -- valid
			sink0_channel       : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink0_data          : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink0_startofpacket : in  std_logic                      := 'X';             -- startofpacket
			sink0_endofpacket   : in  std_logic                      := 'X'              -- endofpacket
		);
	end component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp;

	component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp is
		port (
			clk                : in  std_logic                      := 'X';             -- clk
			reset              : in  std_logic                      := 'X';             -- reset
			sink_ready         : out std_logic;                                         -- ready
			sink_channel       : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink_data          : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink_startofpacket : in  std_logic                      := 'X';             -- startofpacket
			sink_endofpacket   : in  std_logic                      := 'X';             -- endofpacket
			sink_valid         : in  std_logic_vector(0 downto 0)   := (others => 'X'); -- valid
			src0_ready         : in  std_logic                      := 'X';             -- ready
			src0_valid         : out std_logic;                                         -- valid
			src0_data          : out std_logic_vector(116 downto 0);                    -- data
			src0_channel       : out std_logic_vector(11 downto 0);                     -- channel
			src0_startofpacket : out std_logic;                                         -- startofpacket
			src0_endofpacket   : out std_logic                                          -- endofpacket
		);
	end component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp;

	component address_decoder_multi_channel_altera_merlin_multiplexer_191_qznn4dq_cmp is
		port (
			clk                  : in  std_logic                      := 'X';             -- clk
			reset                : in  std_logic                      := 'X';             -- reset
			src_ready            : in  std_logic                      := 'X';             -- ready
			src_valid            : out std_logic;                                         -- valid
			src_data             : out std_logic_vector(116 downto 0);                    -- data
			src_channel          : out std_logic_vector(11 downto 0);                     -- channel
			src_startofpacket    : out std_logic;                                         -- startofpacket
			src_endofpacket      : out std_logic;                                         -- endofpacket
			sink0_ready          : out std_logic;                                         -- ready
			sink0_valid          : in  std_logic                      := 'X';             -- valid
			sink0_channel        : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink0_data           : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink0_startofpacket  : in  std_logic                      := 'X';             -- startofpacket
			sink0_endofpacket    : in  std_logic                      := 'X';             -- endofpacket
			sink1_ready          : out std_logic;                                         -- ready
			sink1_valid          : in  std_logic                      := 'X';             -- valid
			sink1_channel        : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink1_data           : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink1_startofpacket  : in  std_logic                      := 'X';             -- startofpacket
			sink1_endofpacket    : in  std_logic                      := 'X';             -- endofpacket
			sink2_ready          : out std_logic;                                         -- ready
			sink2_valid          : in  std_logic                      := 'X';             -- valid
			sink2_channel        : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink2_data           : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink2_startofpacket  : in  std_logic                      := 'X';             -- startofpacket
			sink2_endofpacket    : in  std_logic                      := 'X';             -- endofpacket
			sink3_ready          : out std_logic;                                         -- ready
			sink3_valid          : in  std_logic                      := 'X';             -- valid
			sink3_channel        : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink3_data           : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink3_startofpacket  : in  std_logic                      := 'X';             -- startofpacket
			sink3_endofpacket    : in  std_logic                      := 'X';             -- endofpacket
			sink4_ready          : out std_logic;                                         -- ready
			sink4_valid          : in  std_logic                      := 'X';             -- valid
			sink4_channel        : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink4_data           : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink4_startofpacket  : in  std_logic                      := 'X';             -- startofpacket
			sink4_endofpacket    : in  std_logic                      := 'X';             -- endofpacket
			sink5_ready          : out std_logic;                                         -- ready
			sink5_valid          : in  std_logic                      := 'X';             -- valid
			sink5_channel        : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink5_data           : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink5_startofpacket  : in  std_logic                      := 'X';             -- startofpacket
			sink5_endofpacket    : in  std_logic                      := 'X';             -- endofpacket
			sink6_ready          : out std_logic;                                         -- ready
			sink6_valid          : in  std_logic                      := 'X';             -- valid
			sink6_channel        : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink6_data           : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink6_startofpacket  : in  std_logic                      := 'X';             -- startofpacket
			sink6_endofpacket    : in  std_logic                      := 'X';             -- endofpacket
			sink7_ready          : out std_logic;                                         -- ready
			sink7_valid          : in  std_logic                      := 'X';             -- valid
			sink7_channel        : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink7_data           : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink7_startofpacket  : in  std_logic                      := 'X';             -- startofpacket
			sink7_endofpacket    : in  std_logic                      := 'X';             -- endofpacket
			sink8_ready          : out std_logic;                                         -- ready
			sink8_valid          : in  std_logic                      := 'X';             -- valid
			sink8_channel        : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink8_data           : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink8_startofpacket  : in  std_logic                      := 'X';             -- startofpacket
			sink8_endofpacket    : in  std_logic                      := 'X';             -- endofpacket
			sink9_ready          : out std_logic;                                         -- ready
			sink9_valid          : in  std_logic                      := 'X';             -- valid
			sink9_channel        : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink9_data           : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink9_startofpacket  : in  std_logic                      := 'X';             -- startofpacket
			sink9_endofpacket    : in  std_logic                      := 'X';             -- endofpacket
			sink10_ready         : out std_logic;                                         -- ready
			sink10_valid         : in  std_logic                      := 'X';             -- valid
			sink10_channel       : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink10_data          : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink10_startofpacket : in  std_logic                      := 'X';             -- startofpacket
			sink10_endofpacket   : in  std_logic                      := 'X';             -- endofpacket
			sink11_ready         : out std_logic;                                         -- ready
			sink11_valid         : in  std_logic                      := 'X';             -- valid
			sink11_channel       : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- channel
			sink11_data          : in  std_logic_vector(116 downto 0) := (others => 'X'); -- data
			sink11_startofpacket : in  std_logic                      := 'X';             -- startofpacket
			sink11_endofpacket   : in  std_logic                      := 'X'              -- endofpacket
		);
	end component address_decoder_multi_channel_altera_merlin_multiplexer_191_qznn4dq_cmp;

	signal master_avalon_universal_master_0_translator_avalon_universal_master_0_waitrequest   : std_logic;                      -- master_avalon_universal_master_0_agent:av_waitrequest -> master_avalon_universal_master_0_translator:uav_waitrequest
	signal master_avalon_universal_master_0_translator_avalon_universal_master_0_readdata      : std_logic_vector(31 downto 0);  -- master_avalon_universal_master_0_agent:av_readdata -> master_avalon_universal_master_0_translator:uav_readdata
	signal master_avalon_universal_master_0_translator_avalon_universal_master_0_debugaccess   : std_logic;                      -- master_avalon_universal_master_0_translator:uav_debugaccess -> master_avalon_universal_master_0_agent:av_debugaccess
	signal master_avalon_universal_master_0_translator_avalon_universal_master_0_address       : std_logic_vector(31 downto 0);  -- master_avalon_universal_master_0_translator:uav_address -> master_avalon_universal_master_0_agent:av_address
	signal master_avalon_universal_master_0_translator_avalon_universal_master_0_read          : std_logic;                      -- master_avalon_universal_master_0_translator:uav_read -> master_avalon_universal_master_0_agent:av_read
	signal master_avalon_universal_master_0_translator_avalon_universal_master_0_byteenable    : std_logic_vector(3 downto 0);   -- master_avalon_universal_master_0_translator:uav_byteenable -> master_avalon_universal_master_0_agent:av_byteenable
	signal master_avalon_universal_master_0_translator_avalon_universal_master_0_readdatavalid : std_logic;                      -- master_avalon_universal_master_0_agent:av_readdatavalid -> master_avalon_universal_master_0_translator:uav_readdatavalid
	signal master_avalon_universal_master_0_translator_avalon_universal_master_0_lock          : std_logic;                      -- master_avalon_universal_master_0_translator:uav_lock -> master_avalon_universal_master_0_agent:av_lock
	signal master_avalon_universal_master_0_translator_avalon_universal_master_0_write         : std_logic;                      -- master_avalon_universal_master_0_translator:uav_write -> master_avalon_universal_master_0_agent:av_write
	signal master_avalon_universal_master_0_translator_avalon_universal_master_0_writedata     : std_logic_vector(31 downto 0);  -- master_avalon_universal_master_0_translator:uav_writedata -> master_avalon_universal_master_0_agent:av_writedata
	signal master_avalon_universal_master_0_translator_avalon_universal_master_0_burstcount    : std_logic_vector(2 downto 0);   -- master_avalon_universal_master_0_translator:uav_burstcount -> master_avalon_universal_master_0_agent:av_burstcount
	signal channel_1_avalon_universal_slave_0_agent_m0_readdata                                : std_logic_vector(31 downto 0);  -- channel_1_avalon_universal_slave_0_translator:uav_readdata -> channel_1_avalon_universal_slave_0_agent:m0_readdata
	signal channel_1_avalon_universal_slave_0_agent_m0_waitrequest                             : std_logic;                      -- channel_1_avalon_universal_slave_0_translator:uav_waitrequest -> channel_1_avalon_universal_slave_0_agent:m0_waitrequest
	signal channel_1_avalon_universal_slave_0_agent_m0_debugaccess                             : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:m0_debugaccess -> channel_1_avalon_universal_slave_0_translator:uav_debugaccess
	signal channel_1_avalon_universal_slave_0_agent_m0_address                                 : std_logic_vector(31 downto 0);  -- channel_1_avalon_universal_slave_0_agent:m0_address -> channel_1_avalon_universal_slave_0_translator:uav_address
	signal channel_1_avalon_universal_slave_0_agent_m0_byteenable                              : std_logic_vector(3 downto 0);   -- channel_1_avalon_universal_slave_0_agent:m0_byteenable -> channel_1_avalon_universal_slave_0_translator:uav_byteenable
	signal channel_1_avalon_universal_slave_0_agent_m0_read                                    : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:m0_read -> channel_1_avalon_universal_slave_0_translator:uav_read
	signal channel_1_avalon_universal_slave_0_agent_m0_readdatavalid                           : std_logic;                      -- channel_1_avalon_universal_slave_0_translator:uav_readdatavalid -> channel_1_avalon_universal_slave_0_agent:m0_readdatavalid
	signal channel_1_avalon_universal_slave_0_agent_m0_lock                                    : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:m0_lock -> channel_1_avalon_universal_slave_0_translator:uav_lock
	signal channel_1_avalon_universal_slave_0_agent_m0_writedata                               : std_logic_vector(31 downto 0);  -- channel_1_avalon_universal_slave_0_agent:m0_writedata -> channel_1_avalon_universal_slave_0_translator:uav_writedata
	signal channel_1_avalon_universal_slave_0_agent_m0_write                                   : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:m0_write -> channel_1_avalon_universal_slave_0_translator:uav_write
	signal channel_1_avalon_universal_slave_0_agent_m0_burstcount                              : std_logic_vector(2 downto 0);   -- channel_1_avalon_universal_slave_0_agent:m0_burstcount -> channel_1_avalon_universal_slave_0_translator:uav_burstcount
	signal channel_1_avalon_universal_slave_0_agent_rf_source_valid                            : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:rf_source_valid -> channel_1_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	signal channel_1_avalon_universal_slave_0_agent_rf_source_data                             : std_logic_vector(117 downto 0); -- channel_1_avalon_universal_slave_0_agent:rf_source_data -> channel_1_avalon_universal_slave_0_agent_rsp_fifo:in_data
	signal channel_1_avalon_universal_slave_0_agent_rf_source_ready                            : std_logic;                      -- channel_1_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> channel_1_avalon_universal_slave_0_agent:rf_source_ready
	signal channel_1_avalon_universal_slave_0_agent_rf_source_startofpacket                    : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:rf_source_startofpacket -> channel_1_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	signal channel_1_avalon_universal_slave_0_agent_rf_source_endofpacket                      : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:rf_source_endofpacket -> channel_1_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	signal channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_valid                         : std_logic;                      -- channel_1_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> channel_1_avalon_universal_slave_0_agent:rf_sink_valid
	signal channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_data                          : std_logic_vector(117 downto 0); -- channel_1_avalon_universal_slave_0_agent_rsp_fifo:out_data -> channel_1_avalon_universal_slave_0_agent:rf_sink_data
	signal channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_ready                         : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:rf_sink_ready -> channel_1_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	signal channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket                 : std_logic;                      -- channel_1_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> channel_1_avalon_universal_slave_0_agent:rf_sink_startofpacket
	signal channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket                   : std_logic;                      -- channel_1_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> channel_1_avalon_universal_slave_0_agent:rf_sink_endofpacket
	signal channel_1_avalon_universal_slave_0_agent_rdata_fifo_src_valid                       : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> channel_1_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	signal channel_1_avalon_universal_slave_0_agent_rdata_fifo_src_data                        : std_logic_vector(33 downto 0);  -- channel_1_avalon_universal_slave_0_agent:rdata_fifo_src_data -> channel_1_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	signal channel_1_avalon_universal_slave_0_agent_rdata_fifo_src_ready                       : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> channel_1_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	signal cmd_mux_src_valid                                                                   : std_logic;                      -- cmd_mux:src_valid -> channel_1_avalon_universal_slave_0_agent:cp_valid
	signal cmd_mux_src_data                                                                    : std_logic_vector(116 downto 0); -- cmd_mux:src_data -> channel_1_avalon_universal_slave_0_agent:cp_data
	signal cmd_mux_src_ready                                                                   : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:cp_ready -> cmd_mux:src_ready
	signal cmd_mux_src_channel                                                                 : std_logic_vector(11 downto 0);  -- cmd_mux:src_channel -> channel_1_avalon_universal_slave_0_agent:cp_channel
	signal cmd_mux_src_startofpacket                                                           : std_logic;                      -- cmd_mux:src_startofpacket -> channel_1_avalon_universal_slave_0_agent:cp_startofpacket
	signal cmd_mux_src_endofpacket                                                             : std_logic;                      -- cmd_mux:src_endofpacket -> channel_1_avalon_universal_slave_0_agent:cp_endofpacket
	signal channel_0_avalon_universal_slave_0_agent_m0_readdata                                : std_logic_vector(31 downto 0);  -- channel_0_avalon_universal_slave_0_translator:uav_readdata -> channel_0_avalon_universal_slave_0_agent:m0_readdata
	signal channel_0_avalon_universal_slave_0_agent_m0_waitrequest                             : std_logic;                      -- channel_0_avalon_universal_slave_0_translator:uav_waitrequest -> channel_0_avalon_universal_slave_0_agent:m0_waitrequest
	signal channel_0_avalon_universal_slave_0_agent_m0_debugaccess                             : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:m0_debugaccess -> channel_0_avalon_universal_slave_0_translator:uav_debugaccess
	signal channel_0_avalon_universal_slave_0_agent_m0_address                                 : std_logic_vector(31 downto 0);  -- channel_0_avalon_universal_slave_0_agent:m0_address -> channel_0_avalon_universal_slave_0_translator:uav_address
	signal channel_0_avalon_universal_slave_0_agent_m0_byteenable                              : std_logic_vector(3 downto 0);   -- channel_0_avalon_universal_slave_0_agent:m0_byteenable -> channel_0_avalon_universal_slave_0_translator:uav_byteenable
	signal channel_0_avalon_universal_slave_0_agent_m0_read                                    : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:m0_read -> channel_0_avalon_universal_slave_0_translator:uav_read
	signal channel_0_avalon_universal_slave_0_agent_m0_readdatavalid                           : std_logic;                      -- channel_0_avalon_universal_slave_0_translator:uav_readdatavalid -> channel_0_avalon_universal_slave_0_agent:m0_readdatavalid
	signal channel_0_avalon_universal_slave_0_agent_m0_lock                                    : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:m0_lock -> channel_0_avalon_universal_slave_0_translator:uav_lock
	signal channel_0_avalon_universal_slave_0_agent_m0_writedata                               : std_logic_vector(31 downto 0);  -- channel_0_avalon_universal_slave_0_agent:m0_writedata -> channel_0_avalon_universal_slave_0_translator:uav_writedata
	signal channel_0_avalon_universal_slave_0_agent_m0_write                                   : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:m0_write -> channel_0_avalon_universal_slave_0_translator:uav_write
	signal channel_0_avalon_universal_slave_0_agent_m0_burstcount                              : std_logic_vector(2 downto 0);   -- channel_0_avalon_universal_slave_0_agent:m0_burstcount -> channel_0_avalon_universal_slave_0_translator:uav_burstcount
	signal channel_0_avalon_universal_slave_0_agent_rf_source_valid                            : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:rf_source_valid -> channel_0_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	signal channel_0_avalon_universal_slave_0_agent_rf_source_data                             : std_logic_vector(117 downto 0); -- channel_0_avalon_universal_slave_0_agent:rf_source_data -> channel_0_avalon_universal_slave_0_agent_rsp_fifo:in_data
	signal channel_0_avalon_universal_slave_0_agent_rf_source_ready                            : std_logic;                      -- channel_0_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> channel_0_avalon_universal_slave_0_agent:rf_source_ready
	signal channel_0_avalon_universal_slave_0_agent_rf_source_startofpacket                    : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:rf_source_startofpacket -> channel_0_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	signal channel_0_avalon_universal_slave_0_agent_rf_source_endofpacket                      : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:rf_source_endofpacket -> channel_0_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	signal channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_valid                         : std_logic;                      -- channel_0_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> channel_0_avalon_universal_slave_0_agent:rf_sink_valid
	signal channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_data                          : std_logic_vector(117 downto 0); -- channel_0_avalon_universal_slave_0_agent_rsp_fifo:out_data -> channel_0_avalon_universal_slave_0_agent:rf_sink_data
	signal channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_ready                         : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:rf_sink_ready -> channel_0_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	signal channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket                 : std_logic;                      -- channel_0_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> channel_0_avalon_universal_slave_0_agent:rf_sink_startofpacket
	signal channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket                   : std_logic;                      -- channel_0_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> channel_0_avalon_universal_slave_0_agent:rf_sink_endofpacket
	signal channel_0_avalon_universal_slave_0_agent_rdata_fifo_src_valid                       : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> channel_0_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	signal channel_0_avalon_universal_slave_0_agent_rdata_fifo_src_data                        : std_logic_vector(33 downto 0);  -- channel_0_avalon_universal_slave_0_agent:rdata_fifo_src_data -> channel_0_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	signal channel_0_avalon_universal_slave_0_agent_rdata_fifo_src_ready                       : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> channel_0_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	signal cmd_mux_001_src_valid                                                               : std_logic;                      -- cmd_mux_001:src_valid -> channel_0_avalon_universal_slave_0_agent:cp_valid
	signal cmd_mux_001_src_data                                                                : std_logic_vector(116 downto 0); -- cmd_mux_001:src_data -> channel_0_avalon_universal_slave_0_agent:cp_data
	signal cmd_mux_001_src_ready                                                               : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_001:src_ready
	signal cmd_mux_001_src_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_mux_001:src_channel -> channel_0_avalon_universal_slave_0_agent:cp_channel
	signal cmd_mux_001_src_startofpacket                                                       : std_logic;                      -- cmd_mux_001:src_startofpacket -> channel_0_avalon_universal_slave_0_agent:cp_startofpacket
	signal cmd_mux_001_src_endofpacket                                                         : std_logic;                      -- cmd_mux_001:src_endofpacket -> channel_0_avalon_universal_slave_0_agent:cp_endofpacket
	signal channel_2_avalon_universal_slave_0_agent_m0_readdata                                : std_logic_vector(31 downto 0);  -- channel_2_avalon_universal_slave_0_translator:uav_readdata -> channel_2_avalon_universal_slave_0_agent:m0_readdata
	signal channel_2_avalon_universal_slave_0_agent_m0_waitrequest                             : std_logic;                      -- channel_2_avalon_universal_slave_0_translator:uav_waitrequest -> channel_2_avalon_universal_slave_0_agent:m0_waitrequest
	signal channel_2_avalon_universal_slave_0_agent_m0_debugaccess                             : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:m0_debugaccess -> channel_2_avalon_universal_slave_0_translator:uav_debugaccess
	signal channel_2_avalon_universal_slave_0_agent_m0_address                                 : std_logic_vector(31 downto 0);  -- channel_2_avalon_universal_slave_0_agent:m0_address -> channel_2_avalon_universal_slave_0_translator:uav_address
	signal channel_2_avalon_universal_slave_0_agent_m0_byteenable                              : std_logic_vector(3 downto 0);   -- channel_2_avalon_universal_slave_0_agent:m0_byteenable -> channel_2_avalon_universal_slave_0_translator:uav_byteenable
	signal channel_2_avalon_universal_slave_0_agent_m0_read                                    : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:m0_read -> channel_2_avalon_universal_slave_0_translator:uav_read
	signal channel_2_avalon_universal_slave_0_agent_m0_readdatavalid                           : std_logic;                      -- channel_2_avalon_universal_slave_0_translator:uav_readdatavalid -> channel_2_avalon_universal_slave_0_agent:m0_readdatavalid
	signal channel_2_avalon_universal_slave_0_agent_m0_lock                                    : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:m0_lock -> channel_2_avalon_universal_slave_0_translator:uav_lock
	signal channel_2_avalon_universal_slave_0_agent_m0_writedata                               : std_logic_vector(31 downto 0);  -- channel_2_avalon_universal_slave_0_agent:m0_writedata -> channel_2_avalon_universal_slave_0_translator:uav_writedata
	signal channel_2_avalon_universal_slave_0_agent_m0_write                                   : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:m0_write -> channel_2_avalon_universal_slave_0_translator:uav_write
	signal channel_2_avalon_universal_slave_0_agent_m0_burstcount                              : std_logic_vector(2 downto 0);   -- channel_2_avalon_universal_slave_0_agent:m0_burstcount -> channel_2_avalon_universal_slave_0_translator:uav_burstcount
	signal channel_2_avalon_universal_slave_0_agent_rf_source_valid                            : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:rf_source_valid -> channel_2_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	signal channel_2_avalon_universal_slave_0_agent_rf_source_data                             : std_logic_vector(117 downto 0); -- channel_2_avalon_universal_slave_0_agent:rf_source_data -> channel_2_avalon_universal_slave_0_agent_rsp_fifo:in_data
	signal channel_2_avalon_universal_slave_0_agent_rf_source_ready                            : std_logic;                      -- channel_2_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> channel_2_avalon_universal_slave_0_agent:rf_source_ready
	signal channel_2_avalon_universal_slave_0_agent_rf_source_startofpacket                    : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:rf_source_startofpacket -> channel_2_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	signal channel_2_avalon_universal_slave_0_agent_rf_source_endofpacket                      : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:rf_source_endofpacket -> channel_2_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	signal channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_valid                         : std_logic;                      -- channel_2_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> channel_2_avalon_universal_slave_0_agent:rf_sink_valid
	signal channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_data                          : std_logic_vector(117 downto 0); -- channel_2_avalon_universal_slave_0_agent_rsp_fifo:out_data -> channel_2_avalon_universal_slave_0_agent:rf_sink_data
	signal channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_ready                         : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:rf_sink_ready -> channel_2_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	signal channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket                 : std_logic;                      -- channel_2_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> channel_2_avalon_universal_slave_0_agent:rf_sink_startofpacket
	signal channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket                   : std_logic;                      -- channel_2_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> channel_2_avalon_universal_slave_0_agent:rf_sink_endofpacket
	signal channel_2_avalon_universal_slave_0_agent_rdata_fifo_src_valid                       : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> channel_2_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	signal channel_2_avalon_universal_slave_0_agent_rdata_fifo_src_data                        : std_logic_vector(33 downto 0);  -- channel_2_avalon_universal_slave_0_agent:rdata_fifo_src_data -> channel_2_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	signal channel_2_avalon_universal_slave_0_agent_rdata_fifo_src_ready                       : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> channel_2_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	signal cmd_mux_002_src_valid                                                               : std_logic;                      -- cmd_mux_002:src_valid -> channel_2_avalon_universal_slave_0_agent:cp_valid
	signal cmd_mux_002_src_data                                                                : std_logic_vector(116 downto 0); -- cmd_mux_002:src_data -> channel_2_avalon_universal_slave_0_agent:cp_data
	signal cmd_mux_002_src_ready                                                               : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_002:src_ready
	signal cmd_mux_002_src_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_mux_002:src_channel -> channel_2_avalon_universal_slave_0_agent:cp_channel
	signal cmd_mux_002_src_startofpacket                                                       : std_logic;                      -- cmd_mux_002:src_startofpacket -> channel_2_avalon_universal_slave_0_agent:cp_startofpacket
	signal cmd_mux_002_src_endofpacket                                                         : std_logic;                      -- cmd_mux_002:src_endofpacket -> channel_2_avalon_universal_slave_0_agent:cp_endofpacket
	signal channel_3_avalon_universal_slave_0_agent_m0_readdata                                : std_logic_vector(31 downto 0);  -- channel_3_avalon_universal_slave_0_translator:uav_readdata -> channel_3_avalon_universal_slave_0_agent:m0_readdata
	signal channel_3_avalon_universal_slave_0_agent_m0_waitrequest                             : std_logic;                      -- channel_3_avalon_universal_slave_0_translator:uav_waitrequest -> channel_3_avalon_universal_slave_0_agent:m0_waitrequest
	signal channel_3_avalon_universal_slave_0_agent_m0_debugaccess                             : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:m0_debugaccess -> channel_3_avalon_universal_slave_0_translator:uav_debugaccess
	signal channel_3_avalon_universal_slave_0_agent_m0_address                                 : std_logic_vector(31 downto 0);  -- channel_3_avalon_universal_slave_0_agent:m0_address -> channel_3_avalon_universal_slave_0_translator:uav_address
	signal channel_3_avalon_universal_slave_0_agent_m0_byteenable                              : std_logic_vector(3 downto 0);   -- channel_3_avalon_universal_slave_0_agent:m0_byteenable -> channel_3_avalon_universal_slave_0_translator:uav_byteenable
	signal channel_3_avalon_universal_slave_0_agent_m0_read                                    : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:m0_read -> channel_3_avalon_universal_slave_0_translator:uav_read
	signal channel_3_avalon_universal_slave_0_agent_m0_readdatavalid                           : std_logic;                      -- channel_3_avalon_universal_slave_0_translator:uav_readdatavalid -> channel_3_avalon_universal_slave_0_agent:m0_readdatavalid
	signal channel_3_avalon_universal_slave_0_agent_m0_lock                                    : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:m0_lock -> channel_3_avalon_universal_slave_0_translator:uav_lock
	signal channel_3_avalon_universal_slave_0_agent_m0_writedata                               : std_logic_vector(31 downto 0);  -- channel_3_avalon_universal_slave_0_agent:m0_writedata -> channel_3_avalon_universal_slave_0_translator:uav_writedata
	signal channel_3_avalon_universal_slave_0_agent_m0_write                                   : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:m0_write -> channel_3_avalon_universal_slave_0_translator:uav_write
	signal channel_3_avalon_universal_slave_0_agent_m0_burstcount                              : std_logic_vector(2 downto 0);   -- channel_3_avalon_universal_slave_0_agent:m0_burstcount -> channel_3_avalon_universal_slave_0_translator:uav_burstcount
	signal channel_3_avalon_universal_slave_0_agent_rf_source_valid                            : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:rf_source_valid -> channel_3_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	signal channel_3_avalon_universal_slave_0_agent_rf_source_data                             : std_logic_vector(117 downto 0); -- channel_3_avalon_universal_slave_0_agent:rf_source_data -> channel_3_avalon_universal_slave_0_agent_rsp_fifo:in_data
	signal channel_3_avalon_universal_slave_0_agent_rf_source_ready                            : std_logic;                      -- channel_3_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> channel_3_avalon_universal_slave_0_agent:rf_source_ready
	signal channel_3_avalon_universal_slave_0_agent_rf_source_startofpacket                    : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:rf_source_startofpacket -> channel_3_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	signal channel_3_avalon_universal_slave_0_agent_rf_source_endofpacket                      : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:rf_source_endofpacket -> channel_3_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	signal channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_valid                         : std_logic;                      -- channel_3_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> channel_3_avalon_universal_slave_0_agent:rf_sink_valid
	signal channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_data                          : std_logic_vector(117 downto 0); -- channel_3_avalon_universal_slave_0_agent_rsp_fifo:out_data -> channel_3_avalon_universal_slave_0_agent:rf_sink_data
	signal channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_ready                         : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:rf_sink_ready -> channel_3_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	signal channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket                 : std_logic;                      -- channel_3_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> channel_3_avalon_universal_slave_0_agent:rf_sink_startofpacket
	signal channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket                   : std_logic;                      -- channel_3_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> channel_3_avalon_universal_slave_0_agent:rf_sink_endofpacket
	signal channel_3_avalon_universal_slave_0_agent_rdata_fifo_src_valid                       : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> channel_3_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	signal channel_3_avalon_universal_slave_0_agent_rdata_fifo_src_data                        : std_logic_vector(33 downto 0);  -- channel_3_avalon_universal_slave_0_agent:rdata_fifo_src_data -> channel_3_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	signal channel_3_avalon_universal_slave_0_agent_rdata_fifo_src_ready                       : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> channel_3_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	signal cmd_mux_003_src_valid                                                               : std_logic;                      -- cmd_mux_003:src_valid -> channel_3_avalon_universal_slave_0_agent:cp_valid
	signal cmd_mux_003_src_data                                                                : std_logic_vector(116 downto 0); -- cmd_mux_003:src_data -> channel_3_avalon_universal_slave_0_agent:cp_data
	signal cmd_mux_003_src_ready                                                               : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_003:src_ready
	signal cmd_mux_003_src_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_mux_003:src_channel -> channel_3_avalon_universal_slave_0_agent:cp_channel
	signal cmd_mux_003_src_startofpacket                                                       : std_logic;                      -- cmd_mux_003:src_startofpacket -> channel_3_avalon_universal_slave_0_agent:cp_startofpacket
	signal cmd_mux_003_src_endofpacket                                                         : std_logic;                      -- cmd_mux_003:src_endofpacket -> channel_3_avalon_universal_slave_0_agent:cp_endofpacket
	signal channel_4_avalon_universal_slave_0_agent_m0_readdata                                : std_logic_vector(31 downto 0);  -- channel_4_avalon_universal_slave_0_translator:uav_readdata -> channel_4_avalon_universal_slave_0_agent:m0_readdata
	signal channel_4_avalon_universal_slave_0_agent_m0_waitrequest                             : std_logic;                      -- channel_4_avalon_universal_slave_0_translator:uav_waitrequest -> channel_4_avalon_universal_slave_0_agent:m0_waitrequest
	signal channel_4_avalon_universal_slave_0_agent_m0_debugaccess                             : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:m0_debugaccess -> channel_4_avalon_universal_slave_0_translator:uav_debugaccess
	signal channel_4_avalon_universal_slave_0_agent_m0_address                                 : std_logic_vector(31 downto 0);  -- channel_4_avalon_universal_slave_0_agent:m0_address -> channel_4_avalon_universal_slave_0_translator:uav_address
	signal channel_4_avalon_universal_slave_0_agent_m0_byteenable                              : std_logic_vector(3 downto 0);   -- channel_4_avalon_universal_slave_0_agent:m0_byteenable -> channel_4_avalon_universal_slave_0_translator:uav_byteenable
	signal channel_4_avalon_universal_slave_0_agent_m0_read                                    : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:m0_read -> channel_4_avalon_universal_slave_0_translator:uav_read
	signal channel_4_avalon_universal_slave_0_agent_m0_readdatavalid                           : std_logic;                      -- channel_4_avalon_universal_slave_0_translator:uav_readdatavalid -> channel_4_avalon_universal_slave_0_agent:m0_readdatavalid
	signal channel_4_avalon_universal_slave_0_agent_m0_lock                                    : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:m0_lock -> channel_4_avalon_universal_slave_0_translator:uav_lock
	signal channel_4_avalon_universal_slave_0_agent_m0_writedata                               : std_logic_vector(31 downto 0);  -- channel_4_avalon_universal_slave_0_agent:m0_writedata -> channel_4_avalon_universal_slave_0_translator:uav_writedata
	signal channel_4_avalon_universal_slave_0_agent_m0_write                                   : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:m0_write -> channel_4_avalon_universal_slave_0_translator:uav_write
	signal channel_4_avalon_universal_slave_0_agent_m0_burstcount                              : std_logic_vector(2 downto 0);   -- channel_4_avalon_universal_slave_0_agent:m0_burstcount -> channel_4_avalon_universal_slave_0_translator:uav_burstcount
	signal channel_4_avalon_universal_slave_0_agent_rf_source_valid                            : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:rf_source_valid -> channel_4_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	signal channel_4_avalon_universal_slave_0_agent_rf_source_data                             : std_logic_vector(117 downto 0); -- channel_4_avalon_universal_slave_0_agent:rf_source_data -> channel_4_avalon_universal_slave_0_agent_rsp_fifo:in_data
	signal channel_4_avalon_universal_slave_0_agent_rf_source_ready                            : std_logic;                      -- channel_4_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> channel_4_avalon_universal_slave_0_agent:rf_source_ready
	signal channel_4_avalon_universal_slave_0_agent_rf_source_startofpacket                    : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:rf_source_startofpacket -> channel_4_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	signal channel_4_avalon_universal_slave_0_agent_rf_source_endofpacket                      : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:rf_source_endofpacket -> channel_4_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	signal channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_valid                         : std_logic;                      -- channel_4_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> channel_4_avalon_universal_slave_0_agent:rf_sink_valid
	signal channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_data                          : std_logic_vector(117 downto 0); -- channel_4_avalon_universal_slave_0_agent_rsp_fifo:out_data -> channel_4_avalon_universal_slave_0_agent:rf_sink_data
	signal channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_ready                         : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:rf_sink_ready -> channel_4_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	signal channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket                 : std_logic;                      -- channel_4_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> channel_4_avalon_universal_slave_0_agent:rf_sink_startofpacket
	signal channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket                   : std_logic;                      -- channel_4_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> channel_4_avalon_universal_slave_0_agent:rf_sink_endofpacket
	signal channel_4_avalon_universal_slave_0_agent_rdata_fifo_src_valid                       : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> channel_4_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	signal channel_4_avalon_universal_slave_0_agent_rdata_fifo_src_data                        : std_logic_vector(33 downto 0);  -- channel_4_avalon_universal_slave_0_agent:rdata_fifo_src_data -> channel_4_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	signal channel_4_avalon_universal_slave_0_agent_rdata_fifo_src_ready                       : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> channel_4_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	signal cmd_mux_004_src_valid                                                               : std_logic;                      -- cmd_mux_004:src_valid -> channel_4_avalon_universal_slave_0_agent:cp_valid
	signal cmd_mux_004_src_data                                                                : std_logic_vector(116 downto 0); -- cmd_mux_004:src_data -> channel_4_avalon_universal_slave_0_agent:cp_data
	signal cmd_mux_004_src_ready                                                               : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_004:src_ready
	signal cmd_mux_004_src_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_mux_004:src_channel -> channel_4_avalon_universal_slave_0_agent:cp_channel
	signal cmd_mux_004_src_startofpacket                                                       : std_logic;                      -- cmd_mux_004:src_startofpacket -> channel_4_avalon_universal_slave_0_agent:cp_startofpacket
	signal cmd_mux_004_src_endofpacket                                                         : std_logic;                      -- cmd_mux_004:src_endofpacket -> channel_4_avalon_universal_slave_0_agent:cp_endofpacket
	signal channel_5_avalon_universal_slave_0_agent_m0_readdata                                : std_logic_vector(31 downto 0);  -- channel_5_avalon_universal_slave_0_translator:uav_readdata -> channel_5_avalon_universal_slave_0_agent:m0_readdata
	signal channel_5_avalon_universal_slave_0_agent_m0_waitrequest                             : std_logic;                      -- channel_5_avalon_universal_slave_0_translator:uav_waitrequest -> channel_5_avalon_universal_slave_0_agent:m0_waitrequest
	signal channel_5_avalon_universal_slave_0_agent_m0_debugaccess                             : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:m0_debugaccess -> channel_5_avalon_universal_slave_0_translator:uav_debugaccess
	signal channel_5_avalon_universal_slave_0_agent_m0_address                                 : std_logic_vector(31 downto 0);  -- channel_5_avalon_universal_slave_0_agent:m0_address -> channel_5_avalon_universal_slave_0_translator:uav_address
	signal channel_5_avalon_universal_slave_0_agent_m0_byteenable                              : std_logic_vector(3 downto 0);   -- channel_5_avalon_universal_slave_0_agent:m0_byteenable -> channel_5_avalon_universal_slave_0_translator:uav_byteenable
	signal channel_5_avalon_universal_slave_0_agent_m0_read                                    : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:m0_read -> channel_5_avalon_universal_slave_0_translator:uav_read
	signal channel_5_avalon_universal_slave_0_agent_m0_readdatavalid                           : std_logic;                      -- channel_5_avalon_universal_slave_0_translator:uav_readdatavalid -> channel_5_avalon_universal_slave_0_agent:m0_readdatavalid
	signal channel_5_avalon_universal_slave_0_agent_m0_lock                                    : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:m0_lock -> channel_5_avalon_universal_slave_0_translator:uav_lock
	signal channel_5_avalon_universal_slave_0_agent_m0_writedata                               : std_logic_vector(31 downto 0);  -- channel_5_avalon_universal_slave_0_agent:m0_writedata -> channel_5_avalon_universal_slave_0_translator:uav_writedata
	signal channel_5_avalon_universal_slave_0_agent_m0_write                                   : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:m0_write -> channel_5_avalon_universal_slave_0_translator:uav_write
	signal channel_5_avalon_universal_slave_0_agent_m0_burstcount                              : std_logic_vector(2 downto 0);   -- channel_5_avalon_universal_slave_0_agent:m0_burstcount -> channel_5_avalon_universal_slave_0_translator:uav_burstcount
	signal channel_5_avalon_universal_slave_0_agent_rf_source_valid                            : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:rf_source_valid -> channel_5_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	signal channel_5_avalon_universal_slave_0_agent_rf_source_data                             : std_logic_vector(117 downto 0); -- channel_5_avalon_universal_slave_0_agent:rf_source_data -> channel_5_avalon_universal_slave_0_agent_rsp_fifo:in_data
	signal channel_5_avalon_universal_slave_0_agent_rf_source_ready                            : std_logic;                      -- channel_5_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> channel_5_avalon_universal_slave_0_agent:rf_source_ready
	signal channel_5_avalon_universal_slave_0_agent_rf_source_startofpacket                    : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:rf_source_startofpacket -> channel_5_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	signal channel_5_avalon_universal_slave_0_agent_rf_source_endofpacket                      : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:rf_source_endofpacket -> channel_5_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	signal channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_valid                         : std_logic;                      -- channel_5_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> channel_5_avalon_universal_slave_0_agent:rf_sink_valid
	signal channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_data                          : std_logic_vector(117 downto 0); -- channel_5_avalon_universal_slave_0_agent_rsp_fifo:out_data -> channel_5_avalon_universal_slave_0_agent:rf_sink_data
	signal channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_ready                         : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:rf_sink_ready -> channel_5_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	signal channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket                 : std_logic;                      -- channel_5_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> channel_5_avalon_universal_slave_0_agent:rf_sink_startofpacket
	signal channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket                   : std_logic;                      -- channel_5_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> channel_5_avalon_universal_slave_0_agent:rf_sink_endofpacket
	signal channel_5_avalon_universal_slave_0_agent_rdata_fifo_src_valid                       : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> channel_5_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	signal channel_5_avalon_universal_slave_0_agent_rdata_fifo_src_data                        : std_logic_vector(33 downto 0);  -- channel_5_avalon_universal_slave_0_agent:rdata_fifo_src_data -> channel_5_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	signal channel_5_avalon_universal_slave_0_agent_rdata_fifo_src_ready                       : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> channel_5_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	signal cmd_mux_005_src_valid                                                               : std_logic;                      -- cmd_mux_005:src_valid -> channel_5_avalon_universal_slave_0_agent:cp_valid
	signal cmd_mux_005_src_data                                                                : std_logic_vector(116 downto 0); -- cmd_mux_005:src_data -> channel_5_avalon_universal_slave_0_agent:cp_data
	signal cmd_mux_005_src_ready                                                               : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_005:src_ready
	signal cmd_mux_005_src_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_mux_005:src_channel -> channel_5_avalon_universal_slave_0_agent:cp_channel
	signal cmd_mux_005_src_startofpacket                                                       : std_logic;                      -- cmd_mux_005:src_startofpacket -> channel_5_avalon_universal_slave_0_agent:cp_startofpacket
	signal cmd_mux_005_src_endofpacket                                                         : std_logic;                      -- cmd_mux_005:src_endofpacket -> channel_5_avalon_universal_slave_0_agent:cp_endofpacket
	signal channel_6_avalon_universal_slave_0_agent_m0_readdata                                : std_logic_vector(31 downto 0);  -- channel_6_avalon_universal_slave_0_translator:uav_readdata -> channel_6_avalon_universal_slave_0_agent:m0_readdata
	signal channel_6_avalon_universal_slave_0_agent_m0_waitrequest                             : std_logic;                      -- channel_6_avalon_universal_slave_0_translator:uav_waitrequest -> channel_6_avalon_universal_slave_0_agent:m0_waitrequest
	signal channel_6_avalon_universal_slave_0_agent_m0_debugaccess                             : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:m0_debugaccess -> channel_6_avalon_universal_slave_0_translator:uav_debugaccess
	signal channel_6_avalon_universal_slave_0_agent_m0_address                                 : std_logic_vector(31 downto 0);  -- channel_6_avalon_universal_slave_0_agent:m0_address -> channel_6_avalon_universal_slave_0_translator:uav_address
	signal channel_6_avalon_universal_slave_0_agent_m0_byteenable                              : std_logic_vector(3 downto 0);   -- channel_6_avalon_universal_slave_0_agent:m0_byteenable -> channel_6_avalon_universal_slave_0_translator:uav_byteenable
	signal channel_6_avalon_universal_slave_0_agent_m0_read                                    : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:m0_read -> channel_6_avalon_universal_slave_0_translator:uav_read
	signal channel_6_avalon_universal_slave_0_agent_m0_readdatavalid                           : std_logic;                      -- channel_6_avalon_universal_slave_0_translator:uav_readdatavalid -> channel_6_avalon_universal_slave_0_agent:m0_readdatavalid
	signal channel_6_avalon_universal_slave_0_agent_m0_lock                                    : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:m0_lock -> channel_6_avalon_universal_slave_0_translator:uav_lock
	signal channel_6_avalon_universal_slave_0_agent_m0_writedata                               : std_logic_vector(31 downto 0);  -- channel_6_avalon_universal_slave_0_agent:m0_writedata -> channel_6_avalon_universal_slave_0_translator:uav_writedata
	signal channel_6_avalon_universal_slave_0_agent_m0_write                                   : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:m0_write -> channel_6_avalon_universal_slave_0_translator:uav_write
	signal channel_6_avalon_universal_slave_0_agent_m0_burstcount                              : std_logic_vector(2 downto 0);   -- channel_6_avalon_universal_slave_0_agent:m0_burstcount -> channel_6_avalon_universal_slave_0_translator:uav_burstcount
	signal channel_6_avalon_universal_slave_0_agent_rf_source_valid                            : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:rf_source_valid -> channel_6_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	signal channel_6_avalon_universal_slave_0_agent_rf_source_data                             : std_logic_vector(117 downto 0); -- channel_6_avalon_universal_slave_0_agent:rf_source_data -> channel_6_avalon_universal_slave_0_agent_rsp_fifo:in_data
	signal channel_6_avalon_universal_slave_0_agent_rf_source_ready                            : std_logic;                      -- channel_6_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> channel_6_avalon_universal_slave_0_agent:rf_source_ready
	signal channel_6_avalon_universal_slave_0_agent_rf_source_startofpacket                    : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:rf_source_startofpacket -> channel_6_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	signal channel_6_avalon_universal_slave_0_agent_rf_source_endofpacket                      : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:rf_source_endofpacket -> channel_6_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	signal channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_valid                         : std_logic;                      -- channel_6_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> channel_6_avalon_universal_slave_0_agent:rf_sink_valid
	signal channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_data                          : std_logic_vector(117 downto 0); -- channel_6_avalon_universal_slave_0_agent_rsp_fifo:out_data -> channel_6_avalon_universal_slave_0_agent:rf_sink_data
	signal channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_ready                         : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:rf_sink_ready -> channel_6_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	signal channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket                 : std_logic;                      -- channel_6_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> channel_6_avalon_universal_slave_0_agent:rf_sink_startofpacket
	signal channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket                   : std_logic;                      -- channel_6_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> channel_6_avalon_universal_slave_0_agent:rf_sink_endofpacket
	signal channel_6_avalon_universal_slave_0_agent_rdata_fifo_src_valid                       : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> channel_6_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	signal channel_6_avalon_universal_slave_0_agent_rdata_fifo_src_data                        : std_logic_vector(33 downto 0);  -- channel_6_avalon_universal_slave_0_agent:rdata_fifo_src_data -> channel_6_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	signal channel_6_avalon_universal_slave_0_agent_rdata_fifo_src_ready                       : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> channel_6_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	signal cmd_mux_006_src_valid                                                               : std_logic;                      -- cmd_mux_006:src_valid -> channel_6_avalon_universal_slave_0_agent:cp_valid
	signal cmd_mux_006_src_data                                                                : std_logic_vector(116 downto 0); -- cmd_mux_006:src_data -> channel_6_avalon_universal_slave_0_agent:cp_data
	signal cmd_mux_006_src_ready                                                               : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_006:src_ready
	signal cmd_mux_006_src_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_mux_006:src_channel -> channel_6_avalon_universal_slave_0_agent:cp_channel
	signal cmd_mux_006_src_startofpacket                                                       : std_logic;                      -- cmd_mux_006:src_startofpacket -> channel_6_avalon_universal_slave_0_agent:cp_startofpacket
	signal cmd_mux_006_src_endofpacket                                                         : std_logic;                      -- cmd_mux_006:src_endofpacket -> channel_6_avalon_universal_slave_0_agent:cp_endofpacket
	signal channel_7_avalon_universal_slave_0_agent_m0_readdata                                : std_logic_vector(31 downto 0);  -- channel_7_avalon_universal_slave_0_translator:uav_readdata -> channel_7_avalon_universal_slave_0_agent:m0_readdata
	signal channel_7_avalon_universal_slave_0_agent_m0_waitrequest                             : std_logic;                      -- channel_7_avalon_universal_slave_0_translator:uav_waitrequest -> channel_7_avalon_universal_slave_0_agent:m0_waitrequest
	signal channel_7_avalon_universal_slave_0_agent_m0_debugaccess                             : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:m0_debugaccess -> channel_7_avalon_universal_slave_0_translator:uav_debugaccess
	signal channel_7_avalon_universal_slave_0_agent_m0_address                                 : std_logic_vector(31 downto 0);  -- channel_7_avalon_universal_slave_0_agent:m0_address -> channel_7_avalon_universal_slave_0_translator:uav_address
	signal channel_7_avalon_universal_slave_0_agent_m0_byteenable                              : std_logic_vector(3 downto 0);   -- channel_7_avalon_universal_slave_0_agent:m0_byteenable -> channel_7_avalon_universal_slave_0_translator:uav_byteenable
	signal channel_7_avalon_universal_slave_0_agent_m0_read                                    : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:m0_read -> channel_7_avalon_universal_slave_0_translator:uav_read
	signal channel_7_avalon_universal_slave_0_agent_m0_readdatavalid                           : std_logic;                      -- channel_7_avalon_universal_slave_0_translator:uav_readdatavalid -> channel_7_avalon_universal_slave_0_agent:m0_readdatavalid
	signal channel_7_avalon_universal_slave_0_agent_m0_lock                                    : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:m0_lock -> channel_7_avalon_universal_slave_0_translator:uav_lock
	signal channel_7_avalon_universal_slave_0_agent_m0_writedata                               : std_logic_vector(31 downto 0);  -- channel_7_avalon_universal_slave_0_agent:m0_writedata -> channel_7_avalon_universal_slave_0_translator:uav_writedata
	signal channel_7_avalon_universal_slave_0_agent_m0_write                                   : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:m0_write -> channel_7_avalon_universal_slave_0_translator:uav_write
	signal channel_7_avalon_universal_slave_0_agent_m0_burstcount                              : std_logic_vector(2 downto 0);   -- channel_7_avalon_universal_slave_0_agent:m0_burstcount -> channel_7_avalon_universal_slave_0_translator:uav_burstcount
	signal channel_7_avalon_universal_slave_0_agent_rf_source_valid                            : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:rf_source_valid -> channel_7_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	signal channel_7_avalon_universal_slave_0_agent_rf_source_data                             : std_logic_vector(117 downto 0); -- channel_7_avalon_universal_slave_0_agent:rf_source_data -> channel_7_avalon_universal_slave_0_agent_rsp_fifo:in_data
	signal channel_7_avalon_universal_slave_0_agent_rf_source_ready                            : std_logic;                      -- channel_7_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> channel_7_avalon_universal_slave_0_agent:rf_source_ready
	signal channel_7_avalon_universal_slave_0_agent_rf_source_startofpacket                    : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:rf_source_startofpacket -> channel_7_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	signal channel_7_avalon_universal_slave_0_agent_rf_source_endofpacket                      : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:rf_source_endofpacket -> channel_7_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	signal channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_valid                         : std_logic;                      -- channel_7_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> channel_7_avalon_universal_slave_0_agent:rf_sink_valid
	signal channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_data                          : std_logic_vector(117 downto 0); -- channel_7_avalon_universal_slave_0_agent_rsp_fifo:out_data -> channel_7_avalon_universal_slave_0_agent:rf_sink_data
	signal channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_ready                         : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:rf_sink_ready -> channel_7_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	signal channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket                 : std_logic;                      -- channel_7_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> channel_7_avalon_universal_slave_0_agent:rf_sink_startofpacket
	signal channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket                   : std_logic;                      -- channel_7_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> channel_7_avalon_universal_slave_0_agent:rf_sink_endofpacket
	signal channel_7_avalon_universal_slave_0_agent_rdata_fifo_src_valid                       : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> channel_7_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	signal channel_7_avalon_universal_slave_0_agent_rdata_fifo_src_data                        : std_logic_vector(33 downto 0);  -- channel_7_avalon_universal_slave_0_agent:rdata_fifo_src_data -> channel_7_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	signal channel_7_avalon_universal_slave_0_agent_rdata_fifo_src_ready                       : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> channel_7_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	signal cmd_mux_007_src_valid                                                               : std_logic;                      -- cmd_mux_007:src_valid -> channel_7_avalon_universal_slave_0_agent:cp_valid
	signal cmd_mux_007_src_data                                                                : std_logic_vector(116 downto 0); -- cmd_mux_007:src_data -> channel_7_avalon_universal_slave_0_agent:cp_data
	signal cmd_mux_007_src_ready                                                               : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_007:src_ready
	signal cmd_mux_007_src_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_mux_007:src_channel -> channel_7_avalon_universal_slave_0_agent:cp_channel
	signal cmd_mux_007_src_startofpacket                                                       : std_logic;                      -- cmd_mux_007:src_startofpacket -> channel_7_avalon_universal_slave_0_agent:cp_startofpacket
	signal cmd_mux_007_src_endofpacket                                                         : std_logic;                      -- cmd_mux_007:src_endofpacket -> channel_7_avalon_universal_slave_0_agent:cp_endofpacket
	signal channel_8_avalon_universal_slave_0_agent_m0_readdata                                : std_logic_vector(31 downto 0);  -- channel_8_avalon_universal_slave_0_translator:uav_readdata -> channel_8_avalon_universal_slave_0_agent:m0_readdata
	signal channel_8_avalon_universal_slave_0_agent_m0_waitrequest                             : std_logic;                      -- channel_8_avalon_universal_slave_0_translator:uav_waitrequest -> channel_8_avalon_universal_slave_0_agent:m0_waitrequest
	signal channel_8_avalon_universal_slave_0_agent_m0_debugaccess                             : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:m0_debugaccess -> channel_8_avalon_universal_slave_0_translator:uav_debugaccess
	signal channel_8_avalon_universal_slave_0_agent_m0_address                                 : std_logic_vector(31 downto 0);  -- channel_8_avalon_universal_slave_0_agent:m0_address -> channel_8_avalon_universal_slave_0_translator:uav_address
	signal channel_8_avalon_universal_slave_0_agent_m0_byteenable                              : std_logic_vector(3 downto 0);   -- channel_8_avalon_universal_slave_0_agent:m0_byteenable -> channel_8_avalon_universal_slave_0_translator:uav_byteenable
	signal channel_8_avalon_universal_slave_0_agent_m0_read                                    : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:m0_read -> channel_8_avalon_universal_slave_0_translator:uav_read
	signal channel_8_avalon_universal_slave_0_agent_m0_readdatavalid                           : std_logic;                      -- channel_8_avalon_universal_slave_0_translator:uav_readdatavalid -> channel_8_avalon_universal_slave_0_agent:m0_readdatavalid
	signal channel_8_avalon_universal_slave_0_agent_m0_lock                                    : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:m0_lock -> channel_8_avalon_universal_slave_0_translator:uav_lock
	signal channel_8_avalon_universal_slave_0_agent_m0_writedata                               : std_logic_vector(31 downto 0);  -- channel_8_avalon_universal_slave_0_agent:m0_writedata -> channel_8_avalon_universal_slave_0_translator:uav_writedata
	signal channel_8_avalon_universal_slave_0_agent_m0_write                                   : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:m0_write -> channel_8_avalon_universal_slave_0_translator:uav_write
	signal channel_8_avalon_universal_slave_0_agent_m0_burstcount                              : std_logic_vector(2 downto 0);   -- channel_8_avalon_universal_slave_0_agent:m0_burstcount -> channel_8_avalon_universal_slave_0_translator:uav_burstcount
	signal channel_8_avalon_universal_slave_0_agent_rf_source_valid                            : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:rf_source_valid -> channel_8_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	signal channel_8_avalon_universal_slave_0_agent_rf_source_data                             : std_logic_vector(117 downto 0); -- channel_8_avalon_universal_slave_0_agent:rf_source_data -> channel_8_avalon_universal_slave_0_agent_rsp_fifo:in_data
	signal channel_8_avalon_universal_slave_0_agent_rf_source_ready                            : std_logic;                      -- channel_8_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> channel_8_avalon_universal_slave_0_agent:rf_source_ready
	signal channel_8_avalon_universal_slave_0_agent_rf_source_startofpacket                    : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:rf_source_startofpacket -> channel_8_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	signal channel_8_avalon_universal_slave_0_agent_rf_source_endofpacket                      : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:rf_source_endofpacket -> channel_8_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	signal channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_valid                         : std_logic;                      -- channel_8_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> channel_8_avalon_universal_slave_0_agent:rf_sink_valid
	signal channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_data                          : std_logic_vector(117 downto 0); -- channel_8_avalon_universal_slave_0_agent_rsp_fifo:out_data -> channel_8_avalon_universal_slave_0_agent:rf_sink_data
	signal channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_ready                         : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:rf_sink_ready -> channel_8_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	signal channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket                 : std_logic;                      -- channel_8_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> channel_8_avalon_universal_slave_0_agent:rf_sink_startofpacket
	signal channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket                   : std_logic;                      -- channel_8_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> channel_8_avalon_universal_slave_0_agent:rf_sink_endofpacket
	signal channel_8_avalon_universal_slave_0_agent_rdata_fifo_src_valid                       : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> channel_8_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	signal channel_8_avalon_universal_slave_0_agent_rdata_fifo_src_data                        : std_logic_vector(33 downto 0);  -- channel_8_avalon_universal_slave_0_agent:rdata_fifo_src_data -> channel_8_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	signal channel_8_avalon_universal_slave_0_agent_rdata_fifo_src_ready                       : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> channel_8_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	signal cmd_mux_008_src_valid                                                               : std_logic;                      -- cmd_mux_008:src_valid -> channel_8_avalon_universal_slave_0_agent:cp_valid
	signal cmd_mux_008_src_data                                                                : std_logic_vector(116 downto 0); -- cmd_mux_008:src_data -> channel_8_avalon_universal_slave_0_agent:cp_data
	signal cmd_mux_008_src_ready                                                               : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_008:src_ready
	signal cmd_mux_008_src_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_mux_008:src_channel -> channel_8_avalon_universal_slave_0_agent:cp_channel
	signal cmd_mux_008_src_startofpacket                                                       : std_logic;                      -- cmd_mux_008:src_startofpacket -> channel_8_avalon_universal_slave_0_agent:cp_startofpacket
	signal cmd_mux_008_src_endofpacket                                                         : std_logic;                      -- cmd_mux_008:src_endofpacket -> channel_8_avalon_universal_slave_0_agent:cp_endofpacket
	signal channel_9_avalon_universal_slave_0_agent_m0_readdata                                : std_logic_vector(31 downto 0);  -- channel_9_avalon_universal_slave_0_translator:uav_readdata -> channel_9_avalon_universal_slave_0_agent:m0_readdata
	signal channel_9_avalon_universal_slave_0_agent_m0_waitrequest                             : std_logic;                      -- channel_9_avalon_universal_slave_0_translator:uav_waitrequest -> channel_9_avalon_universal_slave_0_agent:m0_waitrequest
	signal channel_9_avalon_universal_slave_0_agent_m0_debugaccess                             : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:m0_debugaccess -> channel_9_avalon_universal_slave_0_translator:uav_debugaccess
	signal channel_9_avalon_universal_slave_0_agent_m0_address                                 : std_logic_vector(31 downto 0);  -- channel_9_avalon_universal_slave_0_agent:m0_address -> channel_9_avalon_universal_slave_0_translator:uav_address
	signal channel_9_avalon_universal_slave_0_agent_m0_byteenable                              : std_logic_vector(3 downto 0);   -- channel_9_avalon_universal_slave_0_agent:m0_byteenable -> channel_9_avalon_universal_slave_0_translator:uav_byteenable
	signal channel_9_avalon_universal_slave_0_agent_m0_read                                    : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:m0_read -> channel_9_avalon_universal_slave_0_translator:uav_read
	signal channel_9_avalon_universal_slave_0_agent_m0_readdatavalid                           : std_logic;                      -- channel_9_avalon_universal_slave_0_translator:uav_readdatavalid -> channel_9_avalon_universal_slave_0_agent:m0_readdatavalid
	signal channel_9_avalon_universal_slave_0_agent_m0_lock                                    : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:m0_lock -> channel_9_avalon_universal_slave_0_translator:uav_lock
	signal channel_9_avalon_universal_slave_0_agent_m0_writedata                               : std_logic_vector(31 downto 0);  -- channel_9_avalon_universal_slave_0_agent:m0_writedata -> channel_9_avalon_universal_slave_0_translator:uav_writedata
	signal channel_9_avalon_universal_slave_0_agent_m0_write                                   : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:m0_write -> channel_9_avalon_universal_slave_0_translator:uav_write
	signal channel_9_avalon_universal_slave_0_agent_m0_burstcount                              : std_logic_vector(2 downto 0);   -- channel_9_avalon_universal_slave_0_agent:m0_burstcount -> channel_9_avalon_universal_slave_0_translator:uav_burstcount
	signal channel_9_avalon_universal_slave_0_agent_rf_source_valid                            : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:rf_source_valid -> channel_9_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	signal channel_9_avalon_universal_slave_0_agent_rf_source_data                             : std_logic_vector(117 downto 0); -- channel_9_avalon_universal_slave_0_agent:rf_source_data -> channel_9_avalon_universal_slave_0_agent_rsp_fifo:in_data
	signal channel_9_avalon_universal_slave_0_agent_rf_source_ready                            : std_logic;                      -- channel_9_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> channel_9_avalon_universal_slave_0_agent:rf_source_ready
	signal channel_9_avalon_universal_slave_0_agent_rf_source_startofpacket                    : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:rf_source_startofpacket -> channel_9_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	signal channel_9_avalon_universal_slave_0_agent_rf_source_endofpacket                      : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:rf_source_endofpacket -> channel_9_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	signal channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_valid                         : std_logic;                      -- channel_9_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> channel_9_avalon_universal_slave_0_agent:rf_sink_valid
	signal channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_data                          : std_logic_vector(117 downto 0); -- channel_9_avalon_universal_slave_0_agent_rsp_fifo:out_data -> channel_9_avalon_universal_slave_0_agent:rf_sink_data
	signal channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_ready                         : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:rf_sink_ready -> channel_9_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	signal channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket                 : std_logic;                      -- channel_9_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> channel_9_avalon_universal_slave_0_agent:rf_sink_startofpacket
	signal channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket                   : std_logic;                      -- channel_9_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> channel_9_avalon_universal_slave_0_agent:rf_sink_endofpacket
	signal channel_9_avalon_universal_slave_0_agent_rdata_fifo_src_valid                       : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> channel_9_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	signal channel_9_avalon_universal_slave_0_agent_rdata_fifo_src_data                        : std_logic_vector(33 downto 0);  -- channel_9_avalon_universal_slave_0_agent:rdata_fifo_src_data -> channel_9_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	signal channel_9_avalon_universal_slave_0_agent_rdata_fifo_src_ready                       : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> channel_9_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	signal cmd_mux_009_src_valid                                                               : std_logic;                      -- cmd_mux_009:src_valid -> channel_9_avalon_universal_slave_0_agent:cp_valid
	signal cmd_mux_009_src_data                                                                : std_logic_vector(116 downto 0); -- cmd_mux_009:src_data -> channel_9_avalon_universal_slave_0_agent:cp_data
	signal cmd_mux_009_src_ready                                                               : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_009:src_ready
	signal cmd_mux_009_src_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_mux_009:src_channel -> channel_9_avalon_universal_slave_0_agent:cp_channel
	signal cmd_mux_009_src_startofpacket                                                       : std_logic;                      -- cmd_mux_009:src_startofpacket -> channel_9_avalon_universal_slave_0_agent:cp_startofpacket
	signal cmd_mux_009_src_endofpacket                                                         : std_logic;                      -- cmd_mux_009:src_endofpacket -> channel_9_avalon_universal_slave_0_agent:cp_endofpacket
	signal channel_10_avalon_universal_slave_0_agent_m0_readdata                               : std_logic_vector(31 downto 0);  -- channel_10_avalon_universal_slave_0_translator:uav_readdata -> channel_10_avalon_universal_slave_0_agent:m0_readdata
	signal channel_10_avalon_universal_slave_0_agent_m0_waitrequest                            : std_logic;                      -- channel_10_avalon_universal_slave_0_translator:uav_waitrequest -> channel_10_avalon_universal_slave_0_agent:m0_waitrequest
	signal channel_10_avalon_universal_slave_0_agent_m0_debugaccess                            : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:m0_debugaccess -> channel_10_avalon_universal_slave_0_translator:uav_debugaccess
	signal channel_10_avalon_universal_slave_0_agent_m0_address                                : std_logic_vector(31 downto 0);  -- channel_10_avalon_universal_slave_0_agent:m0_address -> channel_10_avalon_universal_slave_0_translator:uav_address
	signal channel_10_avalon_universal_slave_0_agent_m0_byteenable                             : std_logic_vector(3 downto 0);   -- channel_10_avalon_universal_slave_0_agent:m0_byteenable -> channel_10_avalon_universal_slave_0_translator:uav_byteenable
	signal channel_10_avalon_universal_slave_0_agent_m0_read                                   : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:m0_read -> channel_10_avalon_universal_slave_0_translator:uav_read
	signal channel_10_avalon_universal_slave_0_agent_m0_readdatavalid                          : std_logic;                      -- channel_10_avalon_universal_slave_0_translator:uav_readdatavalid -> channel_10_avalon_universal_slave_0_agent:m0_readdatavalid
	signal channel_10_avalon_universal_slave_0_agent_m0_lock                                   : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:m0_lock -> channel_10_avalon_universal_slave_0_translator:uav_lock
	signal channel_10_avalon_universal_slave_0_agent_m0_writedata                              : std_logic_vector(31 downto 0);  -- channel_10_avalon_universal_slave_0_agent:m0_writedata -> channel_10_avalon_universal_slave_0_translator:uav_writedata
	signal channel_10_avalon_universal_slave_0_agent_m0_write                                  : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:m0_write -> channel_10_avalon_universal_slave_0_translator:uav_write
	signal channel_10_avalon_universal_slave_0_agent_m0_burstcount                             : std_logic_vector(2 downto 0);   -- channel_10_avalon_universal_slave_0_agent:m0_burstcount -> channel_10_avalon_universal_slave_0_translator:uav_burstcount
	signal channel_10_avalon_universal_slave_0_agent_rf_source_valid                           : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:rf_source_valid -> channel_10_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	signal channel_10_avalon_universal_slave_0_agent_rf_source_data                            : std_logic_vector(117 downto 0); -- channel_10_avalon_universal_slave_0_agent:rf_source_data -> channel_10_avalon_universal_slave_0_agent_rsp_fifo:in_data
	signal channel_10_avalon_universal_slave_0_agent_rf_source_ready                           : std_logic;                      -- channel_10_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> channel_10_avalon_universal_slave_0_agent:rf_source_ready
	signal channel_10_avalon_universal_slave_0_agent_rf_source_startofpacket                   : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:rf_source_startofpacket -> channel_10_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	signal channel_10_avalon_universal_slave_0_agent_rf_source_endofpacket                     : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:rf_source_endofpacket -> channel_10_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	signal channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_valid                        : std_logic;                      -- channel_10_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> channel_10_avalon_universal_slave_0_agent:rf_sink_valid
	signal channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_data                         : std_logic_vector(117 downto 0); -- channel_10_avalon_universal_slave_0_agent_rsp_fifo:out_data -> channel_10_avalon_universal_slave_0_agent:rf_sink_data
	signal channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_ready                        : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:rf_sink_ready -> channel_10_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	signal channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket                : std_logic;                      -- channel_10_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> channel_10_avalon_universal_slave_0_agent:rf_sink_startofpacket
	signal channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket                  : std_logic;                      -- channel_10_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> channel_10_avalon_universal_slave_0_agent:rf_sink_endofpacket
	signal channel_10_avalon_universal_slave_0_agent_rdata_fifo_src_valid                      : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> channel_10_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	signal channel_10_avalon_universal_slave_0_agent_rdata_fifo_src_data                       : std_logic_vector(33 downto 0);  -- channel_10_avalon_universal_slave_0_agent:rdata_fifo_src_data -> channel_10_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	signal channel_10_avalon_universal_slave_0_agent_rdata_fifo_src_ready                      : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> channel_10_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	signal cmd_mux_010_src_valid                                                               : std_logic;                      -- cmd_mux_010:src_valid -> channel_10_avalon_universal_slave_0_agent:cp_valid
	signal cmd_mux_010_src_data                                                                : std_logic_vector(116 downto 0); -- cmd_mux_010:src_data -> channel_10_avalon_universal_slave_0_agent:cp_data
	signal cmd_mux_010_src_ready                                                               : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_010:src_ready
	signal cmd_mux_010_src_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_mux_010:src_channel -> channel_10_avalon_universal_slave_0_agent:cp_channel
	signal cmd_mux_010_src_startofpacket                                                       : std_logic;                      -- cmd_mux_010:src_startofpacket -> channel_10_avalon_universal_slave_0_agent:cp_startofpacket
	signal cmd_mux_010_src_endofpacket                                                         : std_logic;                      -- cmd_mux_010:src_endofpacket -> channel_10_avalon_universal_slave_0_agent:cp_endofpacket
	signal channel_11_avalon_universal_slave_0_agent_m0_readdata                               : std_logic_vector(31 downto 0);  -- channel_11_avalon_universal_slave_0_translator:uav_readdata -> channel_11_avalon_universal_slave_0_agent:m0_readdata
	signal channel_11_avalon_universal_slave_0_agent_m0_waitrequest                            : std_logic;                      -- channel_11_avalon_universal_slave_0_translator:uav_waitrequest -> channel_11_avalon_universal_slave_0_agent:m0_waitrequest
	signal channel_11_avalon_universal_slave_0_agent_m0_debugaccess                            : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:m0_debugaccess -> channel_11_avalon_universal_slave_0_translator:uav_debugaccess
	signal channel_11_avalon_universal_slave_0_agent_m0_address                                : std_logic_vector(31 downto 0);  -- channel_11_avalon_universal_slave_0_agent:m0_address -> channel_11_avalon_universal_slave_0_translator:uav_address
	signal channel_11_avalon_universal_slave_0_agent_m0_byteenable                             : std_logic_vector(3 downto 0);   -- channel_11_avalon_universal_slave_0_agent:m0_byteenable -> channel_11_avalon_universal_slave_0_translator:uav_byteenable
	signal channel_11_avalon_universal_slave_0_agent_m0_read                                   : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:m0_read -> channel_11_avalon_universal_slave_0_translator:uav_read
	signal channel_11_avalon_universal_slave_0_agent_m0_readdatavalid                          : std_logic;                      -- channel_11_avalon_universal_slave_0_translator:uav_readdatavalid -> channel_11_avalon_universal_slave_0_agent:m0_readdatavalid
	signal channel_11_avalon_universal_slave_0_agent_m0_lock                                   : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:m0_lock -> channel_11_avalon_universal_slave_0_translator:uav_lock
	signal channel_11_avalon_universal_slave_0_agent_m0_writedata                              : std_logic_vector(31 downto 0);  -- channel_11_avalon_universal_slave_0_agent:m0_writedata -> channel_11_avalon_universal_slave_0_translator:uav_writedata
	signal channel_11_avalon_universal_slave_0_agent_m0_write                                  : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:m0_write -> channel_11_avalon_universal_slave_0_translator:uav_write
	signal channel_11_avalon_universal_slave_0_agent_m0_burstcount                             : std_logic_vector(2 downto 0);   -- channel_11_avalon_universal_slave_0_agent:m0_burstcount -> channel_11_avalon_universal_slave_0_translator:uav_burstcount
	signal channel_11_avalon_universal_slave_0_agent_rf_source_valid                           : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:rf_source_valid -> channel_11_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	signal channel_11_avalon_universal_slave_0_agent_rf_source_data                            : std_logic_vector(117 downto 0); -- channel_11_avalon_universal_slave_0_agent:rf_source_data -> channel_11_avalon_universal_slave_0_agent_rsp_fifo:in_data
	signal channel_11_avalon_universal_slave_0_agent_rf_source_ready                           : std_logic;                      -- channel_11_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> channel_11_avalon_universal_slave_0_agent:rf_source_ready
	signal channel_11_avalon_universal_slave_0_agent_rf_source_startofpacket                   : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:rf_source_startofpacket -> channel_11_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	signal channel_11_avalon_universal_slave_0_agent_rf_source_endofpacket                     : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:rf_source_endofpacket -> channel_11_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	signal channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_valid                        : std_logic;                      -- channel_11_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> channel_11_avalon_universal_slave_0_agent:rf_sink_valid
	signal channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_data                         : std_logic_vector(117 downto 0); -- channel_11_avalon_universal_slave_0_agent_rsp_fifo:out_data -> channel_11_avalon_universal_slave_0_agent:rf_sink_data
	signal channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_ready                        : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:rf_sink_ready -> channel_11_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	signal channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket                : std_logic;                      -- channel_11_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> channel_11_avalon_universal_slave_0_agent:rf_sink_startofpacket
	signal channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket                  : std_logic;                      -- channel_11_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> channel_11_avalon_universal_slave_0_agent:rf_sink_endofpacket
	signal channel_11_avalon_universal_slave_0_agent_rdata_fifo_src_valid                      : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> channel_11_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	signal channel_11_avalon_universal_slave_0_agent_rdata_fifo_src_data                       : std_logic_vector(33 downto 0);  -- channel_11_avalon_universal_slave_0_agent:rdata_fifo_src_data -> channel_11_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	signal channel_11_avalon_universal_slave_0_agent_rdata_fifo_src_ready                      : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> channel_11_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	signal cmd_mux_011_src_valid                                                               : std_logic;                      -- cmd_mux_011:src_valid -> channel_11_avalon_universal_slave_0_agent:cp_valid
	signal cmd_mux_011_src_data                                                                : std_logic_vector(116 downto 0); -- cmd_mux_011:src_data -> channel_11_avalon_universal_slave_0_agent:cp_data
	signal cmd_mux_011_src_ready                                                               : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_011:src_ready
	signal cmd_mux_011_src_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_mux_011:src_channel -> channel_11_avalon_universal_slave_0_agent:cp_channel
	signal cmd_mux_011_src_startofpacket                                                       : std_logic;                      -- cmd_mux_011:src_startofpacket -> channel_11_avalon_universal_slave_0_agent:cp_startofpacket
	signal cmd_mux_011_src_endofpacket                                                         : std_logic;                      -- cmd_mux_011:src_endofpacket -> channel_11_avalon_universal_slave_0_agent:cp_endofpacket
	signal master_avalon_universal_master_0_agent_cp_valid                                     : std_logic;                      -- master_avalon_universal_master_0_agent:cp_valid -> router:sink_valid
	signal master_avalon_universal_master_0_agent_cp_data                                      : std_logic_vector(116 downto 0); -- master_avalon_universal_master_0_agent:cp_data -> router:sink_data
	signal master_avalon_universal_master_0_agent_cp_ready                                     : std_logic;                      -- router:sink_ready -> master_avalon_universal_master_0_agent:cp_ready
	signal master_avalon_universal_master_0_agent_cp_startofpacket                             : std_logic;                      -- master_avalon_universal_master_0_agent:cp_startofpacket -> router:sink_startofpacket
	signal master_avalon_universal_master_0_agent_cp_endofpacket                               : std_logic;                      -- master_avalon_universal_master_0_agent:cp_endofpacket -> router:sink_endofpacket
	signal channel_1_avalon_universal_slave_0_agent_rp_valid                                   : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:rp_valid -> router_001:sink_valid
	signal channel_1_avalon_universal_slave_0_agent_rp_data                                    : std_logic_vector(116 downto 0); -- channel_1_avalon_universal_slave_0_agent:rp_data -> router_001:sink_data
	signal channel_1_avalon_universal_slave_0_agent_rp_ready                                   : std_logic;                      -- router_001:sink_ready -> channel_1_avalon_universal_slave_0_agent:rp_ready
	signal channel_1_avalon_universal_slave_0_agent_rp_startofpacket                           : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:rp_startofpacket -> router_001:sink_startofpacket
	signal channel_1_avalon_universal_slave_0_agent_rp_endofpacket                             : std_logic;                      -- channel_1_avalon_universal_slave_0_agent:rp_endofpacket -> router_001:sink_endofpacket
	signal router_001_src_valid                                                                : std_logic;                      -- router_001:src_valid -> rsp_demux:sink_valid
	signal router_001_src_data                                                                 : std_logic_vector(116 downto 0); -- router_001:src_data -> rsp_demux:sink_data
	signal router_001_src_ready                                                                : std_logic;                      -- rsp_demux:sink_ready -> router_001:src_ready
	signal router_001_src_channel                                                              : std_logic_vector(11 downto 0);  -- router_001:src_channel -> rsp_demux:sink_channel
	signal router_001_src_startofpacket                                                        : std_logic;                      -- router_001:src_startofpacket -> rsp_demux:sink_startofpacket
	signal router_001_src_endofpacket                                                          : std_logic;                      -- router_001:src_endofpacket -> rsp_demux:sink_endofpacket
	signal channel_0_avalon_universal_slave_0_agent_rp_valid                                   : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:rp_valid -> router_002:sink_valid
	signal channel_0_avalon_universal_slave_0_agent_rp_data                                    : std_logic_vector(116 downto 0); -- channel_0_avalon_universal_slave_0_agent:rp_data -> router_002:sink_data
	signal channel_0_avalon_universal_slave_0_agent_rp_ready                                   : std_logic;                      -- router_002:sink_ready -> channel_0_avalon_universal_slave_0_agent:rp_ready
	signal channel_0_avalon_universal_slave_0_agent_rp_startofpacket                           : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:rp_startofpacket -> router_002:sink_startofpacket
	signal channel_0_avalon_universal_slave_0_agent_rp_endofpacket                             : std_logic;                      -- channel_0_avalon_universal_slave_0_agent:rp_endofpacket -> router_002:sink_endofpacket
	signal router_002_src_valid                                                                : std_logic;                      -- router_002:src_valid -> rsp_demux_001:sink_valid
	signal router_002_src_data                                                                 : std_logic_vector(116 downto 0); -- router_002:src_data -> rsp_demux_001:sink_data
	signal router_002_src_ready                                                                : std_logic;                      -- rsp_demux_001:sink_ready -> router_002:src_ready
	signal router_002_src_channel                                                              : std_logic_vector(11 downto 0);  -- router_002:src_channel -> rsp_demux_001:sink_channel
	signal router_002_src_startofpacket                                                        : std_logic;                      -- router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
	signal router_002_src_endofpacket                                                          : std_logic;                      -- router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
	signal channel_2_avalon_universal_slave_0_agent_rp_valid                                   : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:rp_valid -> router_003:sink_valid
	signal channel_2_avalon_universal_slave_0_agent_rp_data                                    : std_logic_vector(116 downto 0); -- channel_2_avalon_universal_slave_0_agent:rp_data -> router_003:sink_data
	signal channel_2_avalon_universal_slave_0_agent_rp_ready                                   : std_logic;                      -- router_003:sink_ready -> channel_2_avalon_universal_slave_0_agent:rp_ready
	signal channel_2_avalon_universal_slave_0_agent_rp_startofpacket                           : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:rp_startofpacket -> router_003:sink_startofpacket
	signal channel_2_avalon_universal_slave_0_agent_rp_endofpacket                             : std_logic;                      -- channel_2_avalon_universal_slave_0_agent:rp_endofpacket -> router_003:sink_endofpacket
	signal router_003_src_valid                                                                : std_logic;                      -- router_003:src_valid -> rsp_demux_002:sink_valid
	signal router_003_src_data                                                                 : std_logic_vector(116 downto 0); -- router_003:src_data -> rsp_demux_002:sink_data
	signal router_003_src_ready                                                                : std_logic;                      -- rsp_demux_002:sink_ready -> router_003:src_ready
	signal router_003_src_channel                                                              : std_logic_vector(11 downto 0);  -- router_003:src_channel -> rsp_demux_002:sink_channel
	signal router_003_src_startofpacket                                                        : std_logic;                      -- router_003:src_startofpacket -> rsp_demux_002:sink_startofpacket
	signal router_003_src_endofpacket                                                          : std_logic;                      -- router_003:src_endofpacket -> rsp_demux_002:sink_endofpacket
	signal channel_3_avalon_universal_slave_0_agent_rp_valid                                   : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:rp_valid -> router_004:sink_valid
	signal channel_3_avalon_universal_slave_0_agent_rp_data                                    : std_logic_vector(116 downto 0); -- channel_3_avalon_universal_slave_0_agent:rp_data -> router_004:sink_data
	signal channel_3_avalon_universal_slave_0_agent_rp_ready                                   : std_logic;                      -- router_004:sink_ready -> channel_3_avalon_universal_slave_0_agent:rp_ready
	signal channel_3_avalon_universal_slave_0_agent_rp_startofpacket                           : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:rp_startofpacket -> router_004:sink_startofpacket
	signal channel_3_avalon_universal_slave_0_agent_rp_endofpacket                             : std_logic;                      -- channel_3_avalon_universal_slave_0_agent:rp_endofpacket -> router_004:sink_endofpacket
	signal router_004_src_valid                                                                : std_logic;                      -- router_004:src_valid -> rsp_demux_003:sink_valid
	signal router_004_src_data                                                                 : std_logic_vector(116 downto 0); -- router_004:src_data -> rsp_demux_003:sink_data
	signal router_004_src_ready                                                                : std_logic;                      -- rsp_demux_003:sink_ready -> router_004:src_ready
	signal router_004_src_channel                                                              : std_logic_vector(11 downto 0);  -- router_004:src_channel -> rsp_demux_003:sink_channel
	signal router_004_src_startofpacket                                                        : std_logic;                      -- router_004:src_startofpacket -> rsp_demux_003:sink_startofpacket
	signal router_004_src_endofpacket                                                          : std_logic;                      -- router_004:src_endofpacket -> rsp_demux_003:sink_endofpacket
	signal channel_4_avalon_universal_slave_0_agent_rp_valid                                   : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:rp_valid -> router_005:sink_valid
	signal channel_4_avalon_universal_slave_0_agent_rp_data                                    : std_logic_vector(116 downto 0); -- channel_4_avalon_universal_slave_0_agent:rp_data -> router_005:sink_data
	signal channel_4_avalon_universal_slave_0_agent_rp_ready                                   : std_logic;                      -- router_005:sink_ready -> channel_4_avalon_universal_slave_0_agent:rp_ready
	signal channel_4_avalon_universal_slave_0_agent_rp_startofpacket                           : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:rp_startofpacket -> router_005:sink_startofpacket
	signal channel_4_avalon_universal_slave_0_agent_rp_endofpacket                             : std_logic;                      -- channel_4_avalon_universal_slave_0_agent:rp_endofpacket -> router_005:sink_endofpacket
	signal router_005_src_valid                                                                : std_logic;                      -- router_005:src_valid -> rsp_demux_004:sink_valid
	signal router_005_src_data                                                                 : std_logic_vector(116 downto 0); -- router_005:src_data -> rsp_demux_004:sink_data
	signal router_005_src_ready                                                                : std_logic;                      -- rsp_demux_004:sink_ready -> router_005:src_ready
	signal router_005_src_channel                                                              : std_logic_vector(11 downto 0);  -- router_005:src_channel -> rsp_demux_004:sink_channel
	signal router_005_src_startofpacket                                                        : std_logic;                      -- router_005:src_startofpacket -> rsp_demux_004:sink_startofpacket
	signal router_005_src_endofpacket                                                          : std_logic;                      -- router_005:src_endofpacket -> rsp_demux_004:sink_endofpacket
	signal channel_5_avalon_universal_slave_0_agent_rp_valid                                   : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:rp_valid -> router_006:sink_valid
	signal channel_5_avalon_universal_slave_0_agent_rp_data                                    : std_logic_vector(116 downto 0); -- channel_5_avalon_universal_slave_0_agent:rp_data -> router_006:sink_data
	signal channel_5_avalon_universal_slave_0_agent_rp_ready                                   : std_logic;                      -- router_006:sink_ready -> channel_5_avalon_universal_slave_0_agent:rp_ready
	signal channel_5_avalon_universal_slave_0_agent_rp_startofpacket                           : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:rp_startofpacket -> router_006:sink_startofpacket
	signal channel_5_avalon_universal_slave_0_agent_rp_endofpacket                             : std_logic;                      -- channel_5_avalon_universal_slave_0_agent:rp_endofpacket -> router_006:sink_endofpacket
	signal router_006_src_valid                                                                : std_logic;                      -- router_006:src_valid -> rsp_demux_005:sink_valid
	signal router_006_src_data                                                                 : std_logic_vector(116 downto 0); -- router_006:src_data -> rsp_demux_005:sink_data
	signal router_006_src_ready                                                                : std_logic;                      -- rsp_demux_005:sink_ready -> router_006:src_ready
	signal router_006_src_channel                                                              : std_logic_vector(11 downto 0);  -- router_006:src_channel -> rsp_demux_005:sink_channel
	signal router_006_src_startofpacket                                                        : std_logic;                      -- router_006:src_startofpacket -> rsp_demux_005:sink_startofpacket
	signal router_006_src_endofpacket                                                          : std_logic;                      -- router_006:src_endofpacket -> rsp_demux_005:sink_endofpacket
	signal channel_6_avalon_universal_slave_0_agent_rp_valid                                   : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:rp_valid -> router_007:sink_valid
	signal channel_6_avalon_universal_slave_0_agent_rp_data                                    : std_logic_vector(116 downto 0); -- channel_6_avalon_universal_slave_0_agent:rp_data -> router_007:sink_data
	signal channel_6_avalon_universal_slave_0_agent_rp_ready                                   : std_logic;                      -- router_007:sink_ready -> channel_6_avalon_universal_slave_0_agent:rp_ready
	signal channel_6_avalon_universal_slave_0_agent_rp_startofpacket                           : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:rp_startofpacket -> router_007:sink_startofpacket
	signal channel_6_avalon_universal_slave_0_agent_rp_endofpacket                             : std_logic;                      -- channel_6_avalon_universal_slave_0_agent:rp_endofpacket -> router_007:sink_endofpacket
	signal router_007_src_valid                                                                : std_logic;                      -- router_007:src_valid -> rsp_demux_006:sink_valid
	signal router_007_src_data                                                                 : std_logic_vector(116 downto 0); -- router_007:src_data -> rsp_demux_006:sink_data
	signal router_007_src_ready                                                                : std_logic;                      -- rsp_demux_006:sink_ready -> router_007:src_ready
	signal router_007_src_channel                                                              : std_logic_vector(11 downto 0);  -- router_007:src_channel -> rsp_demux_006:sink_channel
	signal router_007_src_startofpacket                                                        : std_logic;                      -- router_007:src_startofpacket -> rsp_demux_006:sink_startofpacket
	signal router_007_src_endofpacket                                                          : std_logic;                      -- router_007:src_endofpacket -> rsp_demux_006:sink_endofpacket
	signal channel_7_avalon_universal_slave_0_agent_rp_valid                                   : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:rp_valid -> router_008:sink_valid
	signal channel_7_avalon_universal_slave_0_agent_rp_data                                    : std_logic_vector(116 downto 0); -- channel_7_avalon_universal_slave_0_agent:rp_data -> router_008:sink_data
	signal channel_7_avalon_universal_slave_0_agent_rp_ready                                   : std_logic;                      -- router_008:sink_ready -> channel_7_avalon_universal_slave_0_agent:rp_ready
	signal channel_7_avalon_universal_slave_0_agent_rp_startofpacket                           : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:rp_startofpacket -> router_008:sink_startofpacket
	signal channel_7_avalon_universal_slave_0_agent_rp_endofpacket                             : std_logic;                      -- channel_7_avalon_universal_slave_0_agent:rp_endofpacket -> router_008:sink_endofpacket
	signal router_008_src_valid                                                                : std_logic;                      -- router_008:src_valid -> rsp_demux_007:sink_valid
	signal router_008_src_data                                                                 : std_logic_vector(116 downto 0); -- router_008:src_data -> rsp_demux_007:sink_data
	signal router_008_src_ready                                                                : std_logic;                      -- rsp_demux_007:sink_ready -> router_008:src_ready
	signal router_008_src_channel                                                              : std_logic_vector(11 downto 0);  -- router_008:src_channel -> rsp_demux_007:sink_channel
	signal router_008_src_startofpacket                                                        : std_logic;                      -- router_008:src_startofpacket -> rsp_demux_007:sink_startofpacket
	signal router_008_src_endofpacket                                                          : std_logic;                      -- router_008:src_endofpacket -> rsp_demux_007:sink_endofpacket
	signal channel_8_avalon_universal_slave_0_agent_rp_valid                                   : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:rp_valid -> router_009:sink_valid
	signal channel_8_avalon_universal_slave_0_agent_rp_data                                    : std_logic_vector(116 downto 0); -- channel_8_avalon_universal_slave_0_agent:rp_data -> router_009:sink_data
	signal channel_8_avalon_universal_slave_0_agent_rp_ready                                   : std_logic;                      -- router_009:sink_ready -> channel_8_avalon_universal_slave_0_agent:rp_ready
	signal channel_8_avalon_universal_slave_0_agent_rp_startofpacket                           : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:rp_startofpacket -> router_009:sink_startofpacket
	signal channel_8_avalon_universal_slave_0_agent_rp_endofpacket                             : std_logic;                      -- channel_8_avalon_universal_slave_0_agent:rp_endofpacket -> router_009:sink_endofpacket
	signal router_009_src_valid                                                                : std_logic;                      -- router_009:src_valid -> rsp_demux_008:sink_valid
	signal router_009_src_data                                                                 : std_logic_vector(116 downto 0); -- router_009:src_data -> rsp_demux_008:sink_data
	signal router_009_src_ready                                                                : std_logic;                      -- rsp_demux_008:sink_ready -> router_009:src_ready
	signal router_009_src_channel                                                              : std_logic_vector(11 downto 0);  -- router_009:src_channel -> rsp_demux_008:sink_channel
	signal router_009_src_startofpacket                                                        : std_logic;                      -- router_009:src_startofpacket -> rsp_demux_008:sink_startofpacket
	signal router_009_src_endofpacket                                                          : std_logic;                      -- router_009:src_endofpacket -> rsp_demux_008:sink_endofpacket
	signal channel_9_avalon_universal_slave_0_agent_rp_valid                                   : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:rp_valid -> router_010:sink_valid
	signal channel_9_avalon_universal_slave_0_agent_rp_data                                    : std_logic_vector(116 downto 0); -- channel_9_avalon_universal_slave_0_agent:rp_data -> router_010:sink_data
	signal channel_9_avalon_universal_slave_0_agent_rp_ready                                   : std_logic;                      -- router_010:sink_ready -> channel_9_avalon_universal_slave_0_agent:rp_ready
	signal channel_9_avalon_universal_slave_0_agent_rp_startofpacket                           : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:rp_startofpacket -> router_010:sink_startofpacket
	signal channel_9_avalon_universal_slave_0_agent_rp_endofpacket                             : std_logic;                      -- channel_9_avalon_universal_slave_0_agent:rp_endofpacket -> router_010:sink_endofpacket
	signal router_010_src_valid                                                                : std_logic;                      -- router_010:src_valid -> rsp_demux_009:sink_valid
	signal router_010_src_data                                                                 : std_logic_vector(116 downto 0); -- router_010:src_data -> rsp_demux_009:sink_data
	signal router_010_src_ready                                                                : std_logic;                      -- rsp_demux_009:sink_ready -> router_010:src_ready
	signal router_010_src_channel                                                              : std_logic_vector(11 downto 0);  -- router_010:src_channel -> rsp_demux_009:sink_channel
	signal router_010_src_startofpacket                                                        : std_logic;                      -- router_010:src_startofpacket -> rsp_demux_009:sink_startofpacket
	signal router_010_src_endofpacket                                                          : std_logic;                      -- router_010:src_endofpacket -> rsp_demux_009:sink_endofpacket
	signal channel_10_avalon_universal_slave_0_agent_rp_valid                                  : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:rp_valid -> router_011:sink_valid
	signal channel_10_avalon_universal_slave_0_agent_rp_data                                   : std_logic_vector(116 downto 0); -- channel_10_avalon_universal_slave_0_agent:rp_data -> router_011:sink_data
	signal channel_10_avalon_universal_slave_0_agent_rp_ready                                  : std_logic;                      -- router_011:sink_ready -> channel_10_avalon_universal_slave_0_agent:rp_ready
	signal channel_10_avalon_universal_slave_0_agent_rp_startofpacket                          : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:rp_startofpacket -> router_011:sink_startofpacket
	signal channel_10_avalon_universal_slave_0_agent_rp_endofpacket                            : std_logic;                      -- channel_10_avalon_universal_slave_0_agent:rp_endofpacket -> router_011:sink_endofpacket
	signal router_011_src_valid                                                                : std_logic;                      -- router_011:src_valid -> rsp_demux_010:sink_valid
	signal router_011_src_data                                                                 : std_logic_vector(116 downto 0); -- router_011:src_data -> rsp_demux_010:sink_data
	signal router_011_src_ready                                                                : std_logic;                      -- rsp_demux_010:sink_ready -> router_011:src_ready
	signal router_011_src_channel                                                              : std_logic_vector(11 downto 0);  -- router_011:src_channel -> rsp_demux_010:sink_channel
	signal router_011_src_startofpacket                                                        : std_logic;                      -- router_011:src_startofpacket -> rsp_demux_010:sink_startofpacket
	signal router_011_src_endofpacket                                                          : std_logic;                      -- router_011:src_endofpacket -> rsp_demux_010:sink_endofpacket
	signal channel_11_avalon_universal_slave_0_agent_rp_valid                                  : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:rp_valid -> router_012:sink_valid
	signal channel_11_avalon_universal_slave_0_agent_rp_data                                   : std_logic_vector(116 downto 0); -- channel_11_avalon_universal_slave_0_agent:rp_data -> router_012:sink_data
	signal channel_11_avalon_universal_slave_0_agent_rp_ready                                  : std_logic;                      -- router_012:sink_ready -> channel_11_avalon_universal_slave_0_agent:rp_ready
	signal channel_11_avalon_universal_slave_0_agent_rp_startofpacket                          : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:rp_startofpacket -> router_012:sink_startofpacket
	signal channel_11_avalon_universal_slave_0_agent_rp_endofpacket                            : std_logic;                      -- channel_11_avalon_universal_slave_0_agent:rp_endofpacket -> router_012:sink_endofpacket
	signal router_012_src_valid                                                                : std_logic;                      -- router_012:src_valid -> rsp_demux_011:sink_valid
	signal router_012_src_data                                                                 : std_logic_vector(116 downto 0); -- router_012:src_data -> rsp_demux_011:sink_data
	signal router_012_src_ready                                                                : std_logic;                      -- rsp_demux_011:sink_ready -> router_012:src_ready
	signal router_012_src_channel                                                              : std_logic_vector(11 downto 0);  -- router_012:src_channel -> rsp_demux_011:sink_channel
	signal router_012_src_startofpacket                                                        : std_logic;                      -- router_012:src_startofpacket -> rsp_demux_011:sink_startofpacket
	signal router_012_src_endofpacket                                                          : std_logic;                      -- router_012:src_endofpacket -> rsp_demux_011:sink_endofpacket
	signal router_src_valid                                                                    : std_logic;                      -- router:src_valid -> master_avalon_universal_master_0_limiter:cmd_sink_valid
	signal router_src_data                                                                     : std_logic_vector(116 downto 0); -- router:src_data -> master_avalon_universal_master_0_limiter:cmd_sink_data
	signal router_src_ready                                                                    : std_logic;                      -- master_avalon_universal_master_0_limiter:cmd_sink_ready -> router:src_ready
	signal router_src_channel                                                                  : std_logic_vector(11 downto 0);  -- router:src_channel -> master_avalon_universal_master_0_limiter:cmd_sink_channel
	signal router_src_startofpacket                                                            : std_logic;                      -- router:src_startofpacket -> master_avalon_universal_master_0_limiter:cmd_sink_startofpacket
	signal router_src_endofpacket                                                              : std_logic;                      -- router:src_endofpacket -> master_avalon_universal_master_0_limiter:cmd_sink_endofpacket
	signal master_avalon_universal_master_0_limiter_cmd_src_data                               : std_logic_vector(116 downto 0); -- master_avalon_universal_master_0_limiter:cmd_src_data -> cmd_demux:sink_data
	signal master_avalon_universal_master_0_limiter_cmd_src_ready                              : std_logic;                      -- cmd_demux:sink_ready -> master_avalon_universal_master_0_limiter:cmd_src_ready
	signal master_avalon_universal_master_0_limiter_cmd_src_channel                            : std_logic_vector(11 downto 0);  -- master_avalon_universal_master_0_limiter:cmd_src_channel -> cmd_demux:sink_channel
	signal master_avalon_universal_master_0_limiter_cmd_src_startofpacket                      : std_logic;                      -- master_avalon_universal_master_0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
	signal master_avalon_universal_master_0_limiter_cmd_src_endofpacket                        : std_logic;                      -- master_avalon_universal_master_0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
	signal rsp_mux_src_valid                                                                   : std_logic;                      -- rsp_mux:src_valid -> master_avalon_universal_master_0_limiter:rsp_sink_valid
	signal rsp_mux_src_data                                                                    : std_logic_vector(116 downto 0); -- rsp_mux:src_data -> master_avalon_universal_master_0_limiter:rsp_sink_data
	signal rsp_mux_src_ready                                                                   : std_logic;                      -- master_avalon_universal_master_0_limiter:rsp_sink_ready -> rsp_mux:src_ready
	signal rsp_mux_src_channel                                                                 : std_logic_vector(11 downto 0);  -- rsp_mux:src_channel -> master_avalon_universal_master_0_limiter:rsp_sink_channel
	signal rsp_mux_src_startofpacket                                                           : std_logic;                      -- rsp_mux:src_startofpacket -> master_avalon_universal_master_0_limiter:rsp_sink_startofpacket
	signal rsp_mux_src_endofpacket                                                             : std_logic;                      -- rsp_mux:src_endofpacket -> master_avalon_universal_master_0_limiter:rsp_sink_endofpacket
	signal master_avalon_universal_master_0_limiter_rsp_src_valid                              : std_logic;                      -- master_avalon_universal_master_0_limiter:rsp_src_valid -> master_avalon_universal_master_0_agent:rp_valid
	signal master_avalon_universal_master_0_limiter_rsp_src_data                               : std_logic_vector(116 downto 0); -- master_avalon_universal_master_0_limiter:rsp_src_data -> master_avalon_universal_master_0_agent:rp_data
	signal master_avalon_universal_master_0_limiter_rsp_src_ready                              : std_logic;                      -- master_avalon_universal_master_0_agent:rp_ready -> master_avalon_universal_master_0_limiter:rsp_src_ready
	signal master_avalon_universal_master_0_limiter_rsp_src_channel                            : std_logic_vector(11 downto 0);  -- master_avalon_universal_master_0_limiter:rsp_src_channel -> master_avalon_universal_master_0_agent:rp_channel
	signal master_avalon_universal_master_0_limiter_rsp_src_startofpacket                      : std_logic;                      -- master_avalon_universal_master_0_limiter:rsp_src_startofpacket -> master_avalon_universal_master_0_agent:rp_startofpacket
	signal master_avalon_universal_master_0_limiter_rsp_src_endofpacket                        : std_logic;                      -- master_avalon_universal_master_0_limiter:rsp_src_endofpacket -> master_avalon_universal_master_0_agent:rp_endofpacket
	signal cmd_demux_src0_valid                                                                : std_logic;                      -- cmd_demux:src0_valid -> cmd_mux:sink0_valid
	signal cmd_demux_src0_data                                                                 : std_logic_vector(116 downto 0); -- cmd_demux:src0_data -> cmd_mux:sink0_data
	signal cmd_demux_src0_ready                                                                : std_logic;                      -- cmd_mux:sink0_ready -> cmd_demux:src0_ready
	signal cmd_demux_src0_channel                                                              : std_logic_vector(11 downto 0);  -- cmd_demux:src0_channel -> cmd_mux:sink0_channel
	signal cmd_demux_src0_startofpacket                                                        : std_logic;                      -- cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	signal cmd_demux_src0_endofpacket                                                          : std_logic;                      -- cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	signal cmd_demux_src1_valid                                                                : std_logic;                      -- cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	signal cmd_demux_src1_data                                                                 : std_logic_vector(116 downto 0); -- cmd_demux:src1_data -> cmd_mux_001:sink0_data
	signal cmd_demux_src1_ready                                                                : std_logic;                      -- cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	signal cmd_demux_src1_channel                                                              : std_logic_vector(11 downto 0);  -- cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	signal cmd_demux_src1_startofpacket                                                        : std_logic;                      -- cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	signal cmd_demux_src1_endofpacket                                                          : std_logic;                      -- cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	signal cmd_demux_src2_valid                                                                : std_logic;                      -- cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
	signal cmd_demux_src2_data                                                                 : std_logic_vector(116 downto 0); -- cmd_demux:src2_data -> cmd_mux_002:sink0_data
	signal cmd_demux_src2_ready                                                                : std_logic;                      -- cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
	signal cmd_demux_src2_channel                                                              : std_logic_vector(11 downto 0);  -- cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
	signal cmd_demux_src2_startofpacket                                                        : std_logic;                      -- cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	signal cmd_demux_src2_endofpacket                                                          : std_logic;                      -- cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	signal cmd_demux_src3_valid                                                                : std_logic;                      -- cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
	signal cmd_demux_src3_data                                                                 : std_logic_vector(116 downto 0); -- cmd_demux:src3_data -> cmd_mux_003:sink0_data
	signal cmd_demux_src3_ready                                                                : std_logic;                      -- cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
	signal cmd_demux_src3_channel                                                              : std_logic_vector(11 downto 0);  -- cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
	signal cmd_demux_src3_startofpacket                                                        : std_logic;                      -- cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
	signal cmd_demux_src3_endofpacket                                                          : std_logic;                      -- cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
	signal cmd_demux_src4_valid                                                                : std_logic;                      -- cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
	signal cmd_demux_src4_data                                                                 : std_logic_vector(116 downto 0); -- cmd_demux:src4_data -> cmd_mux_004:sink0_data
	signal cmd_demux_src4_ready                                                                : std_logic;                      -- cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
	signal cmd_demux_src4_channel                                                              : std_logic_vector(11 downto 0);  -- cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
	signal cmd_demux_src4_startofpacket                                                        : std_logic;                      -- cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
	signal cmd_demux_src4_endofpacket                                                          : std_logic;                      -- cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
	signal cmd_demux_src5_valid                                                                : std_logic;                      -- cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
	signal cmd_demux_src5_data                                                                 : std_logic_vector(116 downto 0); -- cmd_demux:src5_data -> cmd_mux_005:sink0_data
	signal cmd_demux_src5_ready                                                                : std_logic;                      -- cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
	signal cmd_demux_src5_channel                                                              : std_logic_vector(11 downto 0);  -- cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
	signal cmd_demux_src5_startofpacket                                                        : std_logic;                      -- cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
	signal cmd_demux_src5_endofpacket                                                          : std_logic;                      -- cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
	signal cmd_demux_src6_valid                                                                : std_logic;                      -- cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
	signal cmd_demux_src6_data                                                                 : std_logic_vector(116 downto 0); -- cmd_demux:src6_data -> cmd_mux_006:sink0_data
	signal cmd_demux_src6_ready                                                                : std_logic;                      -- cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
	signal cmd_demux_src6_channel                                                              : std_logic_vector(11 downto 0);  -- cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
	signal cmd_demux_src6_startofpacket                                                        : std_logic;                      -- cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
	signal cmd_demux_src6_endofpacket                                                          : std_logic;                      -- cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
	signal cmd_demux_src7_valid                                                                : std_logic;                      -- cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
	signal cmd_demux_src7_data                                                                 : std_logic_vector(116 downto 0); -- cmd_demux:src7_data -> cmd_mux_007:sink0_data
	signal cmd_demux_src7_ready                                                                : std_logic;                      -- cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
	signal cmd_demux_src7_channel                                                              : std_logic_vector(11 downto 0);  -- cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
	signal cmd_demux_src7_startofpacket                                                        : std_logic;                      -- cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
	signal cmd_demux_src7_endofpacket                                                          : std_logic;                      -- cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
	signal cmd_demux_src8_valid                                                                : std_logic;                      -- cmd_demux:src8_valid -> cmd_mux_008:sink0_valid
	signal cmd_demux_src8_data                                                                 : std_logic_vector(116 downto 0); -- cmd_demux:src8_data -> cmd_mux_008:sink0_data
	signal cmd_demux_src8_ready                                                                : std_logic;                      -- cmd_mux_008:sink0_ready -> cmd_demux:src8_ready
	signal cmd_demux_src8_channel                                                              : std_logic_vector(11 downto 0);  -- cmd_demux:src8_channel -> cmd_mux_008:sink0_channel
	signal cmd_demux_src8_startofpacket                                                        : std_logic;                      -- cmd_demux:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
	signal cmd_demux_src8_endofpacket                                                          : std_logic;                      -- cmd_demux:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
	signal cmd_demux_src9_valid                                                                : std_logic;                      -- cmd_demux:src9_valid -> cmd_mux_009:sink0_valid
	signal cmd_demux_src9_data                                                                 : std_logic_vector(116 downto 0); -- cmd_demux:src9_data -> cmd_mux_009:sink0_data
	signal cmd_demux_src9_ready                                                                : std_logic;                      -- cmd_mux_009:sink0_ready -> cmd_demux:src9_ready
	signal cmd_demux_src9_channel                                                              : std_logic_vector(11 downto 0);  -- cmd_demux:src9_channel -> cmd_mux_009:sink0_channel
	signal cmd_demux_src9_startofpacket                                                        : std_logic;                      -- cmd_demux:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
	signal cmd_demux_src9_endofpacket                                                          : std_logic;                      -- cmd_demux:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
	signal cmd_demux_src10_valid                                                               : std_logic;                      -- cmd_demux:src10_valid -> cmd_mux_010:sink0_valid
	signal cmd_demux_src10_data                                                                : std_logic_vector(116 downto 0); -- cmd_demux:src10_data -> cmd_mux_010:sink0_data
	signal cmd_demux_src10_ready                                                               : std_logic;                      -- cmd_mux_010:sink0_ready -> cmd_demux:src10_ready
	signal cmd_demux_src10_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_demux:src10_channel -> cmd_mux_010:sink0_channel
	signal cmd_demux_src10_startofpacket                                                       : std_logic;                      -- cmd_demux:src10_startofpacket -> cmd_mux_010:sink0_startofpacket
	signal cmd_demux_src10_endofpacket                                                         : std_logic;                      -- cmd_demux:src10_endofpacket -> cmd_mux_010:sink0_endofpacket
	signal cmd_demux_src11_valid                                                               : std_logic;                      -- cmd_demux:src11_valid -> cmd_mux_011:sink0_valid
	signal cmd_demux_src11_data                                                                : std_logic_vector(116 downto 0); -- cmd_demux:src11_data -> cmd_mux_011:sink0_data
	signal cmd_demux_src11_ready                                                               : std_logic;                      -- cmd_mux_011:sink0_ready -> cmd_demux:src11_ready
	signal cmd_demux_src11_channel                                                             : std_logic_vector(11 downto 0);  -- cmd_demux:src11_channel -> cmd_mux_011:sink0_channel
	signal cmd_demux_src11_startofpacket                                                       : std_logic;                      -- cmd_demux:src11_startofpacket -> cmd_mux_011:sink0_startofpacket
	signal cmd_demux_src11_endofpacket                                                         : std_logic;                      -- cmd_demux:src11_endofpacket -> cmd_mux_011:sink0_endofpacket
	signal rsp_demux_src0_valid                                                                : std_logic;                      -- rsp_demux:src0_valid -> rsp_mux:sink0_valid
	signal rsp_demux_src0_data                                                                 : std_logic_vector(116 downto 0); -- rsp_demux:src0_data -> rsp_mux:sink0_data
	signal rsp_demux_src0_ready                                                                : std_logic;                      -- rsp_mux:sink0_ready -> rsp_demux:src0_ready
	signal rsp_demux_src0_channel                                                              : std_logic_vector(11 downto 0);  -- rsp_demux:src0_channel -> rsp_mux:sink0_channel
	signal rsp_demux_src0_startofpacket                                                        : std_logic;                      -- rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	signal rsp_demux_src0_endofpacket                                                          : std_logic;                      -- rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	signal rsp_demux_001_src0_valid                                                            : std_logic;                      -- rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	signal rsp_demux_001_src0_data                                                             : std_logic_vector(116 downto 0); -- rsp_demux_001:src0_data -> rsp_mux:sink1_data
	signal rsp_demux_001_src0_ready                                                            : std_logic;                      -- rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	signal rsp_demux_001_src0_channel                                                          : std_logic_vector(11 downto 0);  -- rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	signal rsp_demux_001_src0_startofpacket                                                    : std_logic;                      -- rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	signal rsp_demux_001_src0_endofpacket                                                      : std_logic;                      -- rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	signal rsp_demux_002_src0_valid                                                            : std_logic;                      -- rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
	signal rsp_demux_002_src0_data                                                             : std_logic_vector(116 downto 0); -- rsp_demux_002:src0_data -> rsp_mux:sink2_data
	signal rsp_demux_002_src0_ready                                                            : std_logic;                      -- rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
	signal rsp_demux_002_src0_channel                                                          : std_logic_vector(11 downto 0);  -- rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
	signal rsp_demux_002_src0_startofpacket                                                    : std_logic;                      -- rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
	signal rsp_demux_002_src0_endofpacket                                                      : std_logic;                      -- rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
	signal rsp_demux_003_src0_valid                                                            : std_logic;                      -- rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
	signal rsp_demux_003_src0_data                                                             : std_logic_vector(116 downto 0); -- rsp_demux_003:src0_data -> rsp_mux:sink3_data
	signal rsp_demux_003_src0_ready                                                            : std_logic;                      -- rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
	signal rsp_demux_003_src0_channel                                                          : std_logic_vector(11 downto 0);  -- rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
	signal rsp_demux_003_src0_startofpacket                                                    : std_logic;                      -- rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
	signal rsp_demux_003_src0_endofpacket                                                      : std_logic;                      -- rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
	signal rsp_demux_004_src0_valid                                                            : std_logic;                      -- rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
	signal rsp_demux_004_src0_data                                                             : std_logic_vector(116 downto 0); -- rsp_demux_004:src0_data -> rsp_mux:sink4_data
	signal rsp_demux_004_src0_ready                                                            : std_logic;                      -- rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
	signal rsp_demux_004_src0_channel                                                          : std_logic_vector(11 downto 0);  -- rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
	signal rsp_demux_004_src0_startofpacket                                                    : std_logic;                      -- rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
	signal rsp_demux_004_src0_endofpacket                                                      : std_logic;                      -- rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
	signal rsp_demux_005_src0_valid                                                            : std_logic;                      -- rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
	signal rsp_demux_005_src0_data                                                             : std_logic_vector(116 downto 0); -- rsp_demux_005:src0_data -> rsp_mux:sink5_data
	signal rsp_demux_005_src0_ready                                                            : std_logic;                      -- rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
	signal rsp_demux_005_src0_channel                                                          : std_logic_vector(11 downto 0);  -- rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
	signal rsp_demux_005_src0_startofpacket                                                    : std_logic;                      -- rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
	signal rsp_demux_005_src0_endofpacket                                                      : std_logic;                      -- rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
	signal rsp_demux_006_src0_valid                                                            : std_logic;                      -- rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
	signal rsp_demux_006_src0_data                                                             : std_logic_vector(116 downto 0); -- rsp_demux_006:src0_data -> rsp_mux:sink6_data
	signal rsp_demux_006_src0_ready                                                            : std_logic;                      -- rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
	signal rsp_demux_006_src0_channel                                                          : std_logic_vector(11 downto 0);  -- rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
	signal rsp_demux_006_src0_startofpacket                                                    : std_logic;                      -- rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
	signal rsp_demux_006_src0_endofpacket                                                      : std_logic;                      -- rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
	signal rsp_demux_007_src0_valid                                                            : std_logic;                      -- rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
	signal rsp_demux_007_src0_data                                                             : std_logic_vector(116 downto 0); -- rsp_demux_007:src0_data -> rsp_mux:sink7_data
	signal rsp_demux_007_src0_ready                                                            : std_logic;                      -- rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
	signal rsp_demux_007_src0_channel                                                          : std_logic_vector(11 downto 0);  -- rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
	signal rsp_demux_007_src0_startofpacket                                                    : std_logic;                      -- rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
	signal rsp_demux_007_src0_endofpacket                                                      : std_logic;                      -- rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
	signal rsp_demux_008_src0_valid                                                            : std_logic;                      -- rsp_demux_008:src0_valid -> rsp_mux:sink8_valid
	signal rsp_demux_008_src0_data                                                             : std_logic_vector(116 downto 0); -- rsp_demux_008:src0_data -> rsp_mux:sink8_data
	signal rsp_demux_008_src0_ready                                                            : std_logic;                      -- rsp_mux:sink8_ready -> rsp_demux_008:src0_ready
	signal rsp_demux_008_src0_channel                                                          : std_logic_vector(11 downto 0);  -- rsp_demux_008:src0_channel -> rsp_mux:sink8_channel
	signal rsp_demux_008_src0_startofpacket                                                    : std_logic;                      -- rsp_demux_008:src0_startofpacket -> rsp_mux:sink8_startofpacket
	signal rsp_demux_008_src0_endofpacket                                                      : std_logic;                      -- rsp_demux_008:src0_endofpacket -> rsp_mux:sink8_endofpacket
	signal rsp_demux_009_src0_valid                                                            : std_logic;                      -- rsp_demux_009:src0_valid -> rsp_mux:sink9_valid
	signal rsp_demux_009_src0_data                                                             : std_logic_vector(116 downto 0); -- rsp_demux_009:src0_data -> rsp_mux:sink9_data
	signal rsp_demux_009_src0_ready                                                            : std_logic;                      -- rsp_mux:sink9_ready -> rsp_demux_009:src0_ready
	signal rsp_demux_009_src0_channel                                                          : std_logic_vector(11 downto 0);  -- rsp_demux_009:src0_channel -> rsp_mux:sink9_channel
	signal rsp_demux_009_src0_startofpacket                                                    : std_logic;                      -- rsp_demux_009:src0_startofpacket -> rsp_mux:sink9_startofpacket
	signal rsp_demux_009_src0_endofpacket                                                      : std_logic;                      -- rsp_demux_009:src0_endofpacket -> rsp_mux:sink9_endofpacket
	signal rsp_demux_010_src0_valid                                                            : std_logic;                      -- rsp_demux_010:src0_valid -> rsp_mux:sink10_valid
	signal rsp_demux_010_src0_data                                                             : std_logic_vector(116 downto 0); -- rsp_demux_010:src0_data -> rsp_mux:sink10_data
	signal rsp_demux_010_src0_ready                                                            : std_logic;                      -- rsp_mux:sink10_ready -> rsp_demux_010:src0_ready
	signal rsp_demux_010_src0_channel                                                          : std_logic_vector(11 downto 0);  -- rsp_demux_010:src0_channel -> rsp_mux:sink10_channel
	signal rsp_demux_010_src0_startofpacket                                                    : std_logic;                      -- rsp_demux_010:src0_startofpacket -> rsp_mux:sink10_startofpacket
	signal rsp_demux_010_src0_endofpacket                                                      : std_logic;                      -- rsp_demux_010:src0_endofpacket -> rsp_mux:sink10_endofpacket
	signal rsp_demux_011_src0_valid                                                            : std_logic;                      -- rsp_demux_011:src0_valid -> rsp_mux:sink11_valid
	signal rsp_demux_011_src0_data                                                             : std_logic_vector(116 downto 0); -- rsp_demux_011:src0_data -> rsp_mux:sink11_data
	signal rsp_demux_011_src0_ready                                                            : std_logic;                      -- rsp_mux:sink11_ready -> rsp_demux_011:src0_ready
	signal rsp_demux_011_src0_channel                                                          : std_logic_vector(11 downto 0);  -- rsp_demux_011:src0_channel -> rsp_mux:sink11_channel
	signal rsp_demux_011_src0_startofpacket                                                    : std_logic;                      -- rsp_demux_011:src0_startofpacket -> rsp_mux:sink11_startofpacket
	signal rsp_demux_011_src0_endofpacket                                                      : std_logic;                      -- rsp_demux_011:src0_endofpacket -> rsp_mux:sink11_endofpacket
	signal master_avalon_universal_master_0_limiter_cmd_valid_data                             : std_logic_vector(11 downto 0);  -- master_avalon_universal_master_0_limiter:cmd_src_valid -> cmd_demux:sink_valid

	for master_avalon_universal_master_0_translator : address_decoder_multi_channel_altera_merlin_master_translator_191_g7h47bq_cmp
		use entity altera_merlin_master_translator_191.address_decoder_multi_channel_altera_merlin_master_translator_191_g7h47bq;
	for channel_1_avalon_universal_slave_0_translator : address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		use entity altera_merlin_slave_translator_191.address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki;
	for channel_0_avalon_universal_slave_0_translator : address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		use entity altera_merlin_slave_translator_191.address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki;
	for channel_2_avalon_universal_slave_0_translator : address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		use entity altera_merlin_slave_translator_191.address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki;
	for channel_3_avalon_universal_slave_0_translator : address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		use entity altera_merlin_slave_translator_191.address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki;
	for channel_4_avalon_universal_slave_0_translator : address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		use entity altera_merlin_slave_translator_191.address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki;
	for channel_5_avalon_universal_slave_0_translator : address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		use entity altera_merlin_slave_translator_191.address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki;
	for channel_6_avalon_universal_slave_0_translator : address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		use entity altera_merlin_slave_translator_191.address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki;
	for channel_7_avalon_universal_slave_0_translator : address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		use entity altera_merlin_slave_translator_191.address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki;
	for channel_8_avalon_universal_slave_0_translator : address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		use entity altera_merlin_slave_translator_191.address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki;
	for channel_9_avalon_universal_slave_0_translator : address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		use entity altera_merlin_slave_translator_191.address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki;
	for channel_10_avalon_universal_slave_0_translator : address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		use entity altera_merlin_slave_translator_191.address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki;
	for channel_11_avalon_universal_slave_0_translator : address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		use entity altera_merlin_slave_translator_191.address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki;
	for master_avalon_universal_master_0_agent : address_decoder_multi_channel_altera_merlin_master_agent_191_mpbm6tq_cmp
		use entity altera_merlin_master_agent_191.address_decoder_multi_channel_altera_merlin_master_agent_191_mpbm6tq;
	for channel_1_avalon_universal_slave_0_agent : address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		use entity altera_merlin_slave_agent_191.address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri;
	for channel_0_avalon_universal_slave_0_agent : address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		use entity altera_merlin_slave_agent_191.address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri;
	for channel_2_avalon_universal_slave_0_agent : address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		use entity altera_merlin_slave_agent_191.address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri;
	for channel_3_avalon_universal_slave_0_agent : address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		use entity altera_merlin_slave_agent_191.address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri;
	for channel_4_avalon_universal_slave_0_agent : address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		use entity altera_merlin_slave_agent_191.address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri;
	for channel_5_avalon_universal_slave_0_agent : address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		use entity altera_merlin_slave_agent_191.address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri;
	for channel_6_avalon_universal_slave_0_agent : address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		use entity altera_merlin_slave_agent_191.address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri;
	for channel_7_avalon_universal_slave_0_agent : address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		use entity altera_merlin_slave_agent_191.address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri;
	for channel_8_avalon_universal_slave_0_agent : address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		use entity altera_merlin_slave_agent_191.address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri;
	for channel_9_avalon_universal_slave_0_agent : address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		use entity altera_merlin_slave_agent_191.address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri;
	for channel_10_avalon_universal_slave_0_agent : address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		use entity altera_merlin_slave_agent_191.address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri;
	for channel_11_avalon_universal_slave_0_agent : address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		use entity altera_merlin_slave_agent_191.address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri;
	for channel_1_avalon_universal_slave_0_agent_rsp_fifo : address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq;
	for channel_0_avalon_universal_slave_0_agent_rsp_fifo : address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq;
	for channel_2_avalon_universal_slave_0_agent_rsp_fifo : address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq;
	for channel_3_avalon_universal_slave_0_agent_rsp_fifo : address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq;
	for channel_4_avalon_universal_slave_0_agent_rsp_fifo : address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq;
	for channel_5_avalon_universal_slave_0_agent_rsp_fifo : address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq;
	for channel_6_avalon_universal_slave_0_agent_rsp_fifo : address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq;
	for channel_7_avalon_universal_slave_0_agent_rsp_fifo : address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq;
	for channel_8_avalon_universal_slave_0_agent_rsp_fifo : address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq;
	for channel_9_avalon_universal_slave_0_agent_rsp_fifo : address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq;
	for channel_10_avalon_universal_slave_0_agent_rsp_fifo : address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq;
	for channel_11_avalon_universal_slave_0_agent_rsp_fifo : address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		use entity altera_avalon_sc_fifo_191.address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq;
	for router : address_decoder_multi_channel_altera_merlin_router_191_32egg6a_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_32egg6a;
	for router_001 : address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_4vwofdq;
	for router_002 : address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_4vwofdq;
	for router_003 : address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_4vwofdq;
	for router_004 : address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_4vwofdq;
	for router_005 : address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_4vwofdq;
	for router_006 : address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_4vwofdq;
	for router_007 : address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_4vwofdq;
	for router_008 : address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_4vwofdq;
	for router_009 : address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_4vwofdq;
	for router_010 : address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_4vwofdq;
	for router_011 : address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_4vwofdq;
	for router_012 : address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		use entity altera_merlin_router_191.address_decoder_multi_channel_altera_merlin_router_191_4vwofdq;
	for master_avalon_universal_master_0_limiter : address_decoder_multi_channel_altera_merlin_traffic_limiter_191_kcba44q_cmp
		use entity altera_merlin_traffic_limiter_191.address_decoder_multi_channel_altera_merlin_traffic_limiter_191_kcba44q;
	for cmd_demux : address_decoder_multi_channel_altera_merlin_demultiplexer_191_vs5t6hy_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_vs5t6hy;
	for cmd_mux : address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q;
	for cmd_mux_001 : address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q;
	for cmd_mux_002 : address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q;
	for cmd_mux_003 : address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q;
	for cmd_mux_004 : address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q;
	for cmd_mux_005 : address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q;
	for cmd_mux_006 : address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q;
	for cmd_mux_007 : address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q;
	for cmd_mux_008 : address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q;
	for cmd_mux_009 : address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q;
	for cmd_mux_010 : address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q;
	for cmd_mux_011 : address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q;
	for rsp_demux : address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi;
	for rsp_demux_001 : address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi;
	for rsp_demux_002 : address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi;
	for rsp_demux_003 : address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi;
	for rsp_demux_004 : address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi;
	for rsp_demux_005 : address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi;
	for rsp_demux_006 : address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi;
	for rsp_demux_007 : address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi;
	for rsp_demux_008 : address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi;
	for rsp_demux_009 : address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi;
	for rsp_demux_010 : address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi;
	for rsp_demux_011 : address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		use entity altera_merlin_demultiplexer_191.address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi;
	for rsp_mux : address_decoder_multi_channel_altera_merlin_multiplexer_191_qznn4dq_cmp
		use entity altera_merlin_multiplexer_191.address_decoder_multi_channel_altera_merlin_multiplexer_191_qznn4dq;
begin

	master_avalon_universal_master_0_translator : component address_decoder_multi_channel_altera_merlin_master_translator_191_g7h47bq_cmp
		generic map (
			AV_ADDRESS_W                => 32,
			AV_DATA_W                   => 32,
			AV_BURSTCOUNT_W             => 3,
			AV_BYTEENABLE_W             => 4,
			UAV_ADDRESS_W               => 32,
			UAV_BURSTCOUNT_W            => 3,
			USE_READ                    => 1,
			USE_WRITE                   => 1,
			USE_BEGINBURSTTRANSFER      => 0,
			USE_BEGINTRANSFER           => 0,
			USE_CHIPSELECT              => 0,
			USE_BURSTCOUNT              => 1,
			USE_READDATAVALID           => 1,
			USE_WAITREQUEST             => 1,
			USE_READRESPONSE            => 0,
			USE_WRITERESPONSE           => 0,
			AV_SYMBOLS_PER_WORD         => 4,
			AV_ADDRESS_SYMBOLS          => 1,
			AV_BURSTCOUNT_SYMBOLS       => 1,
			AV_CONSTANT_BURST_BEHAVIOR  => 0,
			UAV_CONSTANT_BURST_BEHAVIOR => 0,
			AV_LINEWRAPBURSTS           => 0,
			AV_REGISTERINCOMINGSIGNALS  => 0,
			SYNC_RESET                  => 0,
			WAITREQUEST_ALLOWANCE       => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                                                     --                       clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                                            --                     reset.reset
			uav_address            => master_avalon_universal_master_0_translator_avalon_universal_master_0_address,       -- avalon_universal_master_0.address
			uav_burstcount         => master_avalon_universal_master_0_translator_avalon_universal_master_0_burstcount,    --                          .burstcount
			uav_read               => master_avalon_universal_master_0_translator_avalon_universal_master_0_read,          --                          .read
			uav_write              => master_avalon_universal_master_0_translator_avalon_universal_master_0_write,         --                          .write
			uav_waitrequest        => master_avalon_universal_master_0_translator_avalon_universal_master_0_waitrequest,   --                          .waitrequest
			uav_readdatavalid      => master_avalon_universal_master_0_translator_avalon_universal_master_0_readdatavalid, --                          .readdatavalid
			uav_byteenable         => master_avalon_universal_master_0_translator_avalon_universal_master_0_byteenable,    --                          .byteenable
			uav_readdata           => master_avalon_universal_master_0_translator_avalon_universal_master_0_readdata,      --                          .readdata
			uav_writedata          => master_avalon_universal_master_0_translator_avalon_universal_master_0_writedata,     --                          .writedata
			uav_lock               => master_avalon_universal_master_0_translator_avalon_universal_master_0_lock,          --                          .lock
			uav_debugaccess        => master_avalon_universal_master_0_translator_avalon_universal_master_0_debugaccess,   --                          .debugaccess
			av_address             => master_avalon_universal_master_0_address,                                            --      avalon_anti_master_0.address
			av_waitrequest         => master_avalon_universal_master_0_waitrequest,                                        --                          .waitrequest
			av_burstcount          => master_avalon_universal_master_0_burstcount,                                         --                          .burstcount
			av_byteenable          => master_avalon_universal_master_0_byteenable,                                         --                          .byteenable
			av_read                => master_avalon_universal_master_0_read,                                               --                          .read
			av_readdata            => master_avalon_universal_master_0_readdata,                                           --                          .readdata
			av_readdatavalid       => master_avalon_universal_master_0_readdatavalid,                                      --                          .readdatavalid
			av_write               => master_avalon_universal_master_0_write,                                              --                          .write
			av_writedata           => master_avalon_universal_master_0_writedata,                                          --                          .writedata
			av_lock                => master_avalon_universal_master_0_lock,                                               --                          .lock
			av_debugaccess         => master_avalon_universal_master_0_debugaccess,                                        --                          .debugaccess
			av_beginbursttransfer  => '0',                                                                                 --               (terminated)
			av_begintransfer       => '0',                                                                                 --               (terminated)
			av_chipselect          => '0',                                                                                 --               (terminated)
			uav_clken              => open,                                                                                --               (terminated)
			av_clken               => '1',                                                                                 --               (terminated)
			uav_response           => "00",                                                                                --               (terminated)
			av_response            => open,                                                                                --               (terminated)
			uav_writeresponsevalid => '0',                                                                                 --               (terminated)
			av_writeresponsevalid  => open                                                                                 --               (terminated)
		);

	channel_1_avalon_universal_slave_0_translator : component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 3,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 1,
			AV_BURSTCOUNT_SYMBOLS          => 1,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 0,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0,
			WAITREQUEST_ALLOWANCE          => 0,
			SYNC_RESET                     => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                           --                      clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                  --                    reset.reset
			uav_address            => channel_1_avalon_universal_slave_0_agent_m0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => channel_1_avalon_universal_slave_0_agent_m0_burstcount,    --                         .burstcount
			uav_read               => channel_1_avalon_universal_slave_0_agent_m0_read,          --                         .read
			uav_write              => channel_1_avalon_universal_slave_0_agent_m0_write,         --                         .write
			uav_waitrequest        => channel_1_avalon_universal_slave_0_agent_m0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => channel_1_avalon_universal_slave_0_agent_m0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => channel_1_avalon_universal_slave_0_agent_m0_byteenable,    --                         .byteenable
			uav_readdata           => channel_1_avalon_universal_slave_0_agent_m0_readdata,      --                         .readdata
			uav_writedata          => channel_1_avalon_universal_slave_0_agent_m0_writedata,     --                         .writedata
			uav_lock               => channel_1_avalon_universal_slave_0_agent_m0_lock,          --                         .lock
			uav_debugaccess        => channel_1_avalon_universal_slave_0_agent_m0_debugaccess,   --                         .debugaccess
			av_address             => channel_1_avalon_universal_slave_0_address,                --      avalon_anti_slave_0.address
			av_write               => channel_1_avalon_universal_slave_0_write,                  --                         .write
			av_read                => channel_1_avalon_universal_slave_0_read,                   --                         .read
			av_readdata            => channel_1_avalon_universal_slave_0_readdata,               --                         .readdata
			av_writedata           => channel_1_avalon_universal_slave_0_writedata,              --                         .writedata
			av_burstcount          => channel_1_avalon_universal_slave_0_burstcount,             --                         .burstcount
			av_byteenable          => channel_1_avalon_universal_slave_0_byteenable,             --                         .byteenable
			av_readdatavalid       => channel_1_avalon_universal_slave_0_readdatavalid,          --                         .readdatavalid
			av_waitrequest         => channel_1_avalon_universal_slave_0_waitrequest,            --                         .waitrequest
			av_lock                => channel_1_avalon_universal_slave_0_lock,                   --                         .lock
			av_debugaccess         => channel_1_avalon_universal_slave_0_debugaccess,            --                         .debugaccess
			av_begintransfer       => open,                                                      --              (terminated)
			av_beginbursttransfer  => open,                                                      --              (terminated)
			av_writebyteenable     => open,                                                      --              (terminated)
			av_chipselect          => open,                                                      --              (terminated)
			av_clken               => open,                                                      --              (terminated)
			uav_clken              => '0',                                                       --              (terminated)
			av_outputenable        => open,                                                      --              (terminated)
			uav_response           => open,                                                      --              (terminated)
			av_response            => "00",                                                      --              (terminated)
			uav_writeresponsevalid => open,                                                      --              (terminated)
			av_writeresponsevalid  => '0'                                                        --              (terminated)
		);

	channel_0_avalon_universal_slave_0_translator : component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 3,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 1,
			AV_BURSTCOUNT_SYMBOLS          => 1,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 0,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0,
			WAITREQUEST_ALLOWANCE          => 0,
			SYNC_RESET                     => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                           --                      clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                  --                    reset.reset
			uav_address            => channel_0_avalon_universal_slave_0_agent_m0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => channel_0_avalon_universal_slave_0_agent_m0_burstcount,    --                         .burstcount
			uav_read               => channel_0_avalon_universal_slave_0_agent_m0_read,          --                         .read
			uav_write              => channel_0_avalon_universal_slave_0_agent_m0_write,         --                         .write
			uav_waitrequest        => channel_0_avalon_universal_slave_0_agent_m0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => channel_0_avalon_universal_slave_0_agent_m0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => channel_0_avalon_universal_slave_0_agent_m0_byteenable,    --                         .byteenable
			uav_readdata           => channel_0_avalon_universal_slave_0_agent_m0_readdata,      --                         .readdata
			uav_writedata          => channel_0_avalon_universal_slave_0_agent_m0_writedata,     --                         .writedata
			uav_lock               => channel_0_avalon_universal_slave_0_agent_m0_lock,          --                         .lock
			uav_debugaccess        => channel_0_avalon_universal_slave_0_agent_m0_debugaccess,   --                         .debugaccess
			av_address             => channel_0_avalon_universal_slave_0_address,                --      avalon_anti_slave_0.address
			av_write               => channel_0_avalon_universal_slave_0_write,                  --                         .write
			av_read                => channel_0_avalon_universal_slave_0_read,                   --                         .read
			av_readdata            => channel_0_avalon_universal_slave_0_readdata,               --                         .readdata
			av_writedata           => channel_0_avalon_universal_slave_0_writedata,              --                         .writedata
			av_burstcount          => channel_0_avalon_universal_slave_0_burstcount,             --                         .burstcount
			av_byteenable          => channel_0_avalon_universal_slave_0_byteenable,             --                         .byteenable
			av_readdatavalid       => channel_0_avalon_universal_slave_0_readdatavalid,          --                         .readdatavalid
			av_waitrequest         => channel_0_avalon_universal_slave_0_waitrequest,            --                         .waitrequest
			av_lock                => channel_0_avalon_universal_slave_0_lock,                   --                         .lock
			av_debugaccess         => channel_0_avalon_universal_slave_0_debugaccess,            --                         .debugaccess
			av_begintransfer       => open,                                                      --              (terminated)
			av_beginbursttransfer  => open,                                                      --              (terminated)
			av_writebyteenable     => open,                                                      --              (terminated)
			av_chipselect          => open,                                                      --              (terminated)
			av_clken               => open,                                                      --              (terminated)
			uav_clken              => '0',                                                       --              (terminated)
			av_outputenable        => open,                                                      --              (terminated)
			uav_response           => open,                                                      --              (terminated)
			av_response            => "00",                                                      --              (terminated)
			uav_writeresponsevalid => open,                                                      --              (terminated)
			av_writeresponsevalid  => '0'                                                        --              (terminated)
		);

	channel_2_avalon_universal_slave_0_translator : component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 3,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 1,
			AV_BURSTCOUNT_SYMBOLS          => 1,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 0,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0,
			WAITREQUEST_ALLOWANCE          => 0,
			SYNC_RESET                     => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                           --                      clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                  --                    reset.reset
			uav_address            => channel_2_avalon_universal_slave_0_agent_m0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => channel_2_avalon_universal_slave_0_agent_m0_burstcount,    --                         .burstcount
			uav_read               => channel_2_avalon_universal_slave_0_agent_m0_read,          --                         .read
			uav_write              => channel_2_avalon_universal_slave_0_agent_m0_write,         --                         .write
			uav_waitrequest        => channel_2_avalon_universal_slave_0_agent_m0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => channel_2_avalon_universal_slave_0_agent_m0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => channel_2_avalon_universal_slave_0_agent_m0_byteenable,    --                         .byteenable
			uav_readdata           => channel_2_avalon_universal_slave_0_agent_m0_readdata,      --                         .readdata
			uav_writedata          => channel_2_avalon_universal_slave_0_agent_m0_writedata,     --                         .writedata
			uav_lock               => channel_2_avalon_universal_slave_0_agent_m0_lock,          --                         .lock
			uav_debugaccess        => channel_2_avalon_universal_slave_0_agent_m0_debugaccess,   --                         .debugaccess
			av_address             => channel_2_avalon_universal_slave_0_address,                --      avalon_anti_slave_0.address
			av_write               => channel_2_avalon_universal_slave_0_write,                  --                         .write
			av_read                => channel_2_avalon_universal_slave_0_read,                   --                         .read
			av_readdata            => channel_2_avalon_universal_slave_0_readdata,               --                         .readdata
			av_writedata           => channel_2_avalon_universal_slave_0_writedata,              --                         .writedata
			av_burstcount          => channel_2_avalon_universal_slave_0_burstcount,             --                         .burstcount
			av_byteenable          => channel_2_avalon_universal_slave_0_byteenable,             --                         .byteenable
			av_readdatavalid       => channel_2_avalon_universal_slave_0_readdatavalid,          --                         .readdatavalid
			av_waitrequest         => channel_2_avalon_universal_slave_0_waitrequest,            --                         .waitrequest
			av_lock                => channel_2_avalon_universal_slave_0_lock,                   --                         .lock
			av_debugaccess         => channel_2_avalon_universal_slave_0_debugaccess,            --                         .debugaccess
			av_begintransfer       => open,                                                      --              (terminated)
			av_beginbursttransfer  => open,                                                      --              (terminated)
			av_writebyteenable     => open,                                                      --              (terminated)
			av_chipselect          => open,                                                      --              (terminated)
			av_clken               => open,                                                      --              (terminated)
			uav_clken              => '0',                                                       --              (terminated)
			av_outputenable        => open,                                                      --              (terminated)
			uav_response           => open,                                                      --              (terminated)
			av_response            => "00",                                                      --              (terminated)
			uav_writeresponsevalid => open,                                                      --              (terminated)
			av_writeresponsevalid  => '0'                                                        --              (terminated)
		);

	channel_3_avalon_universal_slave_0_translator : component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 3,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 1,
			AV_BURSTCOUNT_SYMBOLS          => 1,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 0,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0,
			WAITREQUEST_ALLOWANCE          => 0,
			SYNC_RESET                     => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                           --                      clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                  --                    reset.reset
			uav_address            => channel_3_avalon_universal_slave_0_agent_m0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => channel_3_avalon_universal_slave_0_agent_m0_burstcount,    --                         .burstcount
			uav_read               => channel_3_avalon_universal_slave_0_agent_m0_read,          --                         .read
			uav_write              => channel_3_avalon_universal_slave_0_agent_m0_write,         --                         .write
			uav_waitrequest        => channel_3_avalon_universal_slave_0_agent_m0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => channel_3_avalon_universal_slave_0_agent_m0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => channel_3_avalon_universal_slave_0_agent_m0_byteenable,    --                         .byteenable
			uav_readdata           => channel_3_avalon_universal_slave_0_agent_m0_readdata,      --                         .readdata
			uav_writedata          => channel_3_avalon_universal_slave_0_agent_m0_writedata,     --                         .writedata
			uav_lock               => channel_3_avalon_universal_slave_0_agent_m0_lock,          --                         .lock
			uav_debugaccess        => channel_3_avalon_universal_slave_0_agent_m0_debugaccess,   --                         .debugaccess
			av_address             => channel_3_avalon_universal_slave_0_address,                --      avalon_anti_slave_0.address
			av_write               => channel_3_avalon_universal_slave_0_write,                  --                         .write
			av_read                => channel_3_avalon_universal_slave_0_read,                   --                         .read
			av_readdata            => channel_3_avalon_universal_slave_0_readdata,               --                         .readdata
			av_writedata           => channel_3_avalon_universal_slave_0_writedata,              --                         .writedata
			av_burstcount          => channel_3_avalon_universal_slave_0_burstcount,             --                         .burstcount
			av_byteenable          => channel_3_avalon_universal_slave_0_byteenable,             --                         .byteenable
			av_readdatavalid       => channel_3_avalon_universal_slave_0_readdatavalid,          --                         .readdatavalid
			av_waitrequest         => channel_3_avalon_universal_slave_0_waitrequest,            --                         .waitrequest
			av_lock                => channel_3_avalon_universal_slave_0_lock,                   --                         .lock
			av_debugaccess         => channel_3_avalon_universal_slave_0_debugaccess,            --                         .debugaccess
			av_begintransfer       => open,                                                      --              (terminated)
			av_beginbursttransfer  => open,                                                      --              (terminated)
			av_writebyteenable     => open,                                                      --              (terminated)
			av_chipselect          => open,                                                      --              (terminated)
			av_clken               => open,                                                      --              (terminated)
			uav_clken              => '0',                                                       --              (terminated)
			av_outputenable        => open,                                                      --              (terminated)
			uav_response           => open,                                                      --              (terminated)
			av_response            => "00",                                                      --              (terminated)
			uav_writeresponsevalid => open,                                                      --              (terminated)
			av_writeresponsevalid  => '0'                                                        --              (terminated)
		);

	channel_4_avalon_universal_slave_0_translator : component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 3,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 1,
			AV_BURSTCOUNT_SYMBOLS          => 1,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 0,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0,
			WAITREQUEST_ALLOWANCE          => 0,
			SYNC_RESET                     => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                           --                      clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                  --                    reset.reset
			uav_address            => channel_4_avalon_universal_slave_0_agent_m0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => channel_4_avalon_universal_slave_0_agent_m0_burstcount,    --                         .burstcount
			uav_read               => channel_4_avalon_universal_slave_0_agent_m0_read,          --                         .read
			uav_write              => channel_4_avalon_universal_slave_0_agent_m0_write,         --                         .write
			uav_waitrequest        => channel_4_avalon_universal_slave_0_agent_m0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => channel_4_avalon_universal_slave_0_agent_m0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => channel_4_avalon_universal_slave_0_agent_m0_byteenable,    --                         .byteenable
			uav_readdata           => channel_4_avalon_universal_slave_0_agent_m0_readdata,      --                         .readdata
			uav_writedata          => channel_4_avalon_universal_slave_0_agent_m0_writedata,     --                         .writedata
			uav_lock               => channel_4_avalon_universal_slave_0_agent_m0_lock,          --                         .lock
			uav_debugaccess        => channel_4_avalon_universal_slave_0_agent_m0_debugaccess,   --                         .debugaccess
			av_address             => channel_4_avalon_universal_slave_0_address,                --      avalon_anti_slave_0.address
			av_write               => channel_4_avalon_universal_slave_0_write,                  --                         .write
			av_read                => channel_4_avalon_universal_slave_0_read,                   --                         .read
			av_readdata            => channel_4_avalon_universal_slave_0_readdata,               --                         .readdata
			av_writedata           => channel_4_avalon_universal_slave_0_writedata,              --                         .writedata
			av_burstcount          => channel_4_avalon_universal_slave_0_burstcount,             --                         .burstcount
			av_byteenable          => channel_4_avalon_universal_slave_0_byteenable,             --                         .byteenable
			av_readdatavalid       => channel_4_avalon_universal_slave_0_readdatavalid,          --                         .readdatavalid
			av_waitrequest         => channel_4_avalon_universal_slave_0_waitrequest,            --                         .waitrequest
			av_lock                => channel_4_avalon_universal_slave_0_lock,                   --                         .lock
			av_debugaccess         => channel_4_avalon_universal_slave_0_debugaccess,            --                         .debugaccess
			av_begintransfer       => open,                                                      --              (terminated)
			av_beginbursttransfer  => open,                                                      --              (terminated)
			av_writebyteenable     => open,                                                      --              (terminated)
			av_chipselect          => open,                                                      --              (terminated)
			av_clken               => open,                                                      --              (terminated)
			uav_clken              => '0',                                                       --              (terminated)
			av_outputenable        => open,                                                      --              (terminated)
			uav_response           => open,                                                      --              (terminated)
			av_response            => "00",                                                      --              (terminated)
			uav_writeresponsevalid => open,                                                      --              (terminated)
			av_writeresponsevalid  => '0'                                                        --              (terminated)
		);

	channel_5_avalon_universal_slave_0_translator : component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 3,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 1,
			AV_BURSTCOUNT_SYMBOLS          => 1,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 0,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0,
			WAITREQUEST_ALLOWANCE          => 0,
			SYNC_RESET                     => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                           --                      clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                  --                    reset.reset
			uav_address            => channel_5_avalon_universal_slave_0_agent_m0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => channel_5_avalon_universal_slave_0_agent_m0_burstcount,    --                         .burstcount
			uav_read               => channel_5_avalon_universal_slave_0_agent_m0_read,          --                         .read
			uav_write              => channel_5_avalon_universal_slave_0_agent_m0_write,         --                         .write
			uav_waitrequest        => channel_5_avalon_universal_slave_0_agent_m0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => channel_5_avalon_universal_slave_0_agent_m0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => channel_5_avalon_universal_slave_0_agent_m0_byteenable,    --                         .byteenable
			uav_readdata           => channel_5_avalon_universal_slave_0_agent_m0_readdata,      --                         .readdata
			uav_writedata          => channel_5_avalon_universal_slave_0_agent_m0_writedata,     --                         .writedata
			uav_lock               => channel_5_avalon_universal_slave_0_agent_m0_lock,          --                         .lock
			uav_debugaccess        => channel_5_avalon_universal_slave_0_agent_m0_debugaccess,   --                         .debugaccess
			av_address             => channel_5_avalon_universal_slave_0_address,                --      avalon_anti_slave_0.address
			av_write               => channel_5_avalon_universal_slave_0_write,                  --                         .write
			av_read                => channel_5_avalon_universal_slave_0_read,                   --                         .read
			av_readdata            => channel_5_avalon_universal_slave_0_readdata,               --                         .readdata
			av_writedata           => channel_5_avalon_universal_slave_0_writedata,              --                         .writedata
			av_burstcount          => channel_5_avalon_universal_slave_0_burstcount,             --                         .burstcount
			av_byteenable          => channel_5_avalon_universal_slave_0_byteenable,             --                         .byteenable
			av_readdatavalid       => channel_5_avalon_universal_slave_0_readdatavalid,          --                         .readdatavalid
			av_waitrequest         => channel_5_avalon_universal_slave_0_waitrequest,            --                         .waitrequest
			av_lock                => channel_5_avalon_universal_slave_0_lock,                   --                         .lock
			av_debugaccess         => channel_5_avalon_universal_slave_0_debugaccess,            --                         .debugaccess
			av_begintransfer       => open,                                                      --              (terminated)
			av_beginbursttransfer  => open,                                                      --              (terminated)
			av_writebyteenable     => open,                                                      --              (terminated)
			av_chipselect          => open,                                                      --              (terminated)
			av_clken               => open,                                                      --              (terminated)
			uav_clken              => '0',                                                       --              (terminated)
			av_outputenable        => open,                                                      --              (terminated)
			uav_response           => open,                                                      --              (terminated)
			av_response            => "00",                                                      --              (terminated)
			uav_writeresponsevalid => open,                                                      --              (terminated)
			av_writeresponsevalid  => '0'                                                        --              (terminated)
		);

	channel_6_avalon_universal_slave_0_translator : component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 3,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 1,
			AV_BURSTCOUNT_SYMBOLS          => 1,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 0,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0,
			WAITREQUEST_ALLOWANCE          => 0,
			SYNC_RESET                     => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                           --                      clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                  --                    reset.reset
			uav_address            => channel_6_avalon_universal_slave_0_agent_m0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => channel_6_avalon_universal_slave_0_agent_m0_burstcount,    --                         .burstcount
			uav_read               => channel_6_avalon_universal_slave_0_agent_m0_read,          --                         .read
			uav_write              => channel_6_avalon_universal_slave_0_agent_m0_write,         --                         .write
			uav_waitrequest        => channel_6_avalon_universal_slave_0_agent_m0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => channel_6_avalon_universal_slave_0_agent_m0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => channel_6_avalon_universal_slave_0_agent_m0_byteenable,    --                         .byteenable
			uav_readdata           => channel_6_avalon_universal_slave_0_agent_m0_readdata,      --                         .readdata
			uav_writedata          => channel_6_avalon_universal_slave_0_agent_m0_writedata,     --                         .writedata
			uav_lock               => channel_6_avalon_universal_slave_0_agent_m0_lock,          --                         .lock
			uav_debugaccess        => channel_6_avalon_universal_slave_0_agent_m0_debugaccess,   --                         .debugaccess
			av_address             => channel_6_avalon_universal_slave_0_address,                --      avalon_anti_slave_0.address
			av_write               => channel_6_avalon_universal_slave_0_write,                  --                         .write
			av_read                => channel_6_avalon_universal_slave_0_read,                   --                         .read
			av_readdata            => channel_6_avalon_universal_slave_0_readdata,               --                         .readdata
			av_writedata           => channel_6_avalon_universal_slave_0_writedata,              --                         .writedata
			av_burstcount          => channel_6_avalon_universal_slave_0_burstcount,             --                         .burstcount
			av_byteenable          => channel_6_avalon_universal_slave_0_byteenable,             --                         .byteenable
			av_readdatavalid       => channel_6_avalon_universal_slave_0_readdatavalid,          --                         .readdatavalid
			av_waitrequest         => channel_6_avalon_universal_slave_0_waitrequest,            --                         .waitrequest
			av_lock                => channel_6_avalon_universal_slave_0_lock,                   --                         .lock
			av_debugaccess         => channel_6_avalon_universal_slave_0_debugaccess,            --                         .debugaccess
			av_begintransfer       => open,                                                      --              (terminated)
			av_beginbursttransfer  => open,                                                      --              (terminated)
			av_writebyteenable     => open,                                                      --              (terminated)
			av_chipselect          => open,                                                      --              (terminated)
			av_clken               => open,                                                      --              (terminated)
			uav_clken              => '0',                                                       --              (terminated)
			av_outputenable        => open,                                                      --              (terminated)
			uav_response           => open,                                                      --              (terminated)
			av_response            => "00",                                                      --              (terminated)
			uav_writeresponsevalid => open,                                                      --              (terminated)
			av_writeresponsevalid  => '0'                                                        --              (terminated)
		);

	channel_7_avalon_universal_slave_0_translator : component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 3,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 1,
			AV_BURSTCOUNT_SYMBOLS          => 1,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 0,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0,
			WAITREQUEST_ALLOWANCE          => 0,
			SYNC_RESET                     => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                           --                      clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                  --                    reset.reset
			uav_address            => channel_7_avalon_universal_slave_0_agent_m0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => channel_7_avalon_universal_slave_0_agent_m0_burstcount,    --                         .burstcount
			uav_read               => channel_7_avalon_universal_slave_0_agent_m0_read,          --                         .read
			uav_write              => channel_7_avalon_universal_slave_0_agent_m0_write,         --                         .write
			uav_waitrequest        => channel_7_avalon_universal_slave_0_agent_m0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => channel_7_avalon_universal_slave_0_agent_m0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => channel_7_avalon_universal_slave_0_agent_m0_byteenable,    --                         .byteenable
			uav_readdata           => channel_7_avalon_universal_slave_0_agent_m0_readdata,      --                         .readdata
			uav_writedata          => channel_7_avalon_universal_slave_0_agent_m0_writedata,     --                         .writedata
			uav_lock               => channel_7_avalon_universal_slave_0_agent_m0_lock,          --                         .lock
			uav_debugaccess        => channel_7_avalon_universal_slave_0_agent_m0_debugaccess,   --                         .debugaccess
			av_address             => channel_7_avalon_universal_slave_0_address,                --      avalon_anti_slave_0.address
			av_write               => channel_7_avalon_universal_slave_0_write,                  --                         .write
			av_read                => channel_7_avalon_universal_slave_0_read,                   --                         .read
			av_readdata            => channel_7_avalon_universal_slave_0_readdata,               --                         .readdata
			av_writedata           => channel_7_avalon_universal_slave_0_writedata,              --                         .writedata
			av_burstcount          => channel_7_avalon_universal_slave_0_burstcount,             --                         .burstcount
			av_byteenable          => channel_7_avalon_universal_slave_0_byteenable,             --                         .byteenable
			av_readdatavalid       => channel_7_avalon_universal_slave_0_readdatavalid,          --                         .readdatavalid
			av_waitrequest         => channel_7_avalon_universal_slave_0_waitrequest,            --                         .waitrequest
			av_lock                => channel_7_avalon_universal_slave_0_lock,                   --                         .lock
			av_debugaccess         => channel_7_avalon_universal_slave_0_debugaccess,            --                         .debugaccess
			av_begintransfer       => open,                                                      --              (terminated)
			av_beginbursttransfer  => open,                                                      --              (terminated)
			av_writebyteenable     => open,                                                      --              (terminated)
			av_chipselect          => open,                                                      --              (terminated)
			av_clken               => open,                                                      --              (terminated)
			uav_clken              => '0',                                                       --              (terminated)
			av_outputenable        => open,                                                      --              (terminated)
			uav_response           => open,                                                      --              (terminated)
			av_response            => "00",                                                      --              (terminated)
			uav_writeresponsevalid => open,                                                      --              (terminated)
			av_writeresponsevalid  => '0'                                                        --              (terminated)
		);

	channel_8_avalon_universal_slave_0_translator : component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 3,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 1,
			AV_BURSTCOUNT_SYMBOLS          => 1,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 0,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0,
			WAITREQUEST_ALLOWANCE          => 0,
			SYNC_RESET                     => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                           --                      clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                  --                    reset.reset
			uav_address            => channel_8_avalon_universal_slave_0_agent_m0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => channel_8_avalon_universal_slave_0_agent_m0_burstcount,    --                         .burstcount
			uav_read               => channel_8_avalon_universal_slave_0_agent_m0_read,          --                         .read
			uav_write              => channel_8_avalon_universal_slave_0_agent_m0_write,         --                         .write
			uav_waitrequest        => channel_8_avalon_universal_slave_0_agent_m0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => channel_8_avalon_universal_slave_0_agent_m0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => channel_8_avalon_universal_slave_0_agent_m0_byteenable,    --                         .byteenable
			uav_readdata           => channel_8_avalon_universal_slave_0_agent_m0_readdata,      --                         .readdata
			uav_writedata          => channel_8_avalon_universal_slave_0_agent_m0_writedata,     --                         .writedata
			uav_lock               => channel_8_avalon_universal_slave_0_agent_m0_lock,          --                         .lock
			uav_debugaccess        => channel_8_avalon_universal_slave_0_agent_m0_debugaccess,   --                         .debugaccess
			av_address             => channel_8_avalon_universal_slave_0_address,                --      avalon_anti_slave_0.address
			av_write               => channel_8_avalon_universal_slave_0_write,                  --                         .write
			av_read                => channel_8_avalon_universal_slave_0_read,                   --                         .read
			av_readdata            => channel_8_avalon_universal_slave_0_readdata,               --                         .readdata
			av_writedata           => channel_8_avalon_universal_slave_0_writedata,              --                         .writedata
			av_burstcount          => channel_8_avalon_universal_slave_0_burstcount,             --                         .burstcount
			av_byteenable          => channel_8_avalon_universal_slave_0_byteenable,             --                         .byteenable
			av_readdatavalid       => channel_8_avalon_universal_slave_0_readdatavalid,          --                         .readdatavalid
			av_waitrequest         => channel_8_avalon_universal_slave_0_waitrequest,            --                         .waitrequest
			av_lock                => channel_8_avalon_universal_slave_0_lock,                   --                         .lock
			av_debugaccess         => channel_8_avalon_universal_slave_0_debugaccess,            --                         .debugaccess
			av_begintransfer       => open,                                                      --              (terminated)
			av_beginbursttransfer  => open,                                                      --              (terminated)
			av_writebyteenable     => open,                                                      --              (terminated)
			av_chipselect          => open,                                                      --              (terminated)
			av_clken               => open,                                                      --              (terminated)
			uav_clken              => '0',                                                       --              (terminated)
			av_outputenable        => open,                                                      --              (terminated)
			uav_response           => open,                                                      --              (terminated)
			av_response            => "00",                                                      --              (terminated)
			uav_writeresponsevalid => open,                                                      --              (terminated)
			av_writeresponsevalid  => '0'                                                        --              (terminated)
		);

	channel_9_avalon_universal_slave_0_translator : component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 3,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 1,
			AV_BURSTCOUNT_SYMBOLS          => 1,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 0,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0,
			WAITREQUEST_ALLOWANCE          => 0,
			SYNC_RESET                     => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                           --                      clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                  --                    reset.reset
			uav_address            => channel_9_avalon_universal_slave_0_agent_m0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => channel_9_avalon_universal_slave_0_agent_m0_burstcount,    --                         .burstcount
			uav_read               => channel_9_avalon_universal_slave_0_agent_m0_read,          --                         .read
			uav_write              => channel_9_avalon_universal_slave_0_agent_m0_write,         --                         .write
			uav_waitrequest        => channel_9_avalon_universal_slave_0_agent_m0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => channel_9_avalon_universal_slave_0_agent_m0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => channel_9_avalon_universal_slave_0_agent_m0_byteenable,    --                         .byteenable
			uav_readdata           => channel_9_avalon_universal_slave_0_agent_m0_readdata,      --                         .readdata
			uav_writedata          => channel_9_avalon_universal_slave_0_agent_m0_writedata,     --                         .writedata
			uav_lock               => channel_9_avalon_universal_slave_0_agent_m0_lock,          --                         .lock
			uav_debugaccess        => channel_9_avalon_universal_slave_0_agent_m0_debugaccess,   --                         .debugaccess
			av_address             => channel_9_avalon_universal_slave_0_address,                --      avalon_anti_slave_0.address
			av_write               => channel_9_avalon_universal_slave_0_write,                  --                         .write
			av_read                => channel_9_avalon_universal_slave_0_read,                   --                         .read
			av_readdata            => channel_9_avalon_universal_slave_0_readdata,               --                         .readdata
			av_writedata           => channel_9_avalon_universal_slave_0_writedata,              --                         .writedata
			av_burstcount          => channel_9_avalon_universal_slave_0_burstcount,             --                         .burstcount
			av_byteenable          => channel_9_avalon_universal_slave_0_byteenable,             --                         .byteenable
			av_readdatavalid       => channel_9_avalon_universal_slave_0_readdatavalid,          --                         .readdatavalid
			av_waitrequest         => channel_9_avalon_universal_slave_0_waitrequest,            --                         .waitrequest
			av_lock                => channel_9_avalon_universal_slave_0_lock,                   --                         .lock
			av_debugaccess         => channel_9_avalon_universal_slave_0_debugaccess,            --                         .debugaccess
			av_begintransfer       => open,                                                      --              (terminated)
			av_beginbursttransfer  => open,                                                      --              (terminated)
			av_writebyteenable     => open,                                                      --              (terminated)
			av_chipselect          => open,                                                      --              (terminated)
			av_clken               => open,                                                      --              (terminated)
			uav_clken              => '0',                                                       --              (terminated)
			av_outputenable        => open,                                                      --              (terminated)
			uav_response           => open,                                                      --              (terminated)
			av_response            => "00",                                                      --              (terminated)
			uav_writeresponsevalid => open,                                                      --              (terminated)
			av_writeresponsevalid  => '0'                                                        --              (terminated)
		);

	channel_10_avalon_universal_slave_0_translator : component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 3,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 1,
			AV_BURSTCOUNT_SYMBOLS          => 1,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 0,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0,
			WAITREQUEST_ALLOWANCE          => 0,
			SYNC_RESET                     => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                            --                      clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                   --                    reset.reset
			uav_address            => channel_10_avalon_universal_slave_0_agent_m0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => channel_10_avalon_universal_slave_0_agent_m0_burstcount,    --                         .burstcount
			uav_read               => channel_10_avalon_universal_slave_0_agent_m0_read,          --                         .read
			uav_write              => channel_10_avalon_universal_slave_0_agent_m0_write,         --                         .write
			uav_waitrequest        => channel_10_avalon_universal_slave_0_agent_m0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => channel_10_avalon_universal_slave_0_agent_m0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => channel_10_avalon_universal_slave_0_agent_m0_byteenable,    --                         .byteenable
			uav_readdata           => channel_10_avalon_universal_slave_0_agent_m0_readdata,      --                         .readdata
			uav_writedata          => channel_10_avalon_universal_slave_0_agent_m0_writedata,     --                         .writedata
			uav_lock               => channel_10_avalon_universal_slave_0_agent_m0_lock,          --                         .lock
			uav_debugaccess        => channel_10_avalon_universal_slave_0_agent_m0_debugaccess,   --                         .debugaccess
			av_address             => channel_10_avalon_universal_slave_0_address,                --      avalon_anti_slave_0.address
			av_write               => channel_10_avalon_universal_slave_0_write,                  --                         .write
			av_read                => channel_10_avalon_universal_slave_0_read,                   --                         .read
			av_readdata            => channel_10_avalon_universal_slave_0_readdata,               --                         .readdata
			av_writedata           => channel_10_avalon_universal_slave_0_writedata,              --                         .writedata
			av_burstcount          => channel_10_avalon_universal_slave_0_burstcount,             --                         .burstcount
			av_byteenable          => channel_10_avalon_universal_slave_0_byteenable,             --                         .byteenable
			av_readdatavalid       => channel_10_avalon_universal_slave_0_readdatavalid,          --                         .readdatavalid
			av_waitrequest         => channel_10_avalon_universal_slave_0_waitrequest,            --                         .waitrequest
			av_lock                => channel_10_avalon_universal_slave_0_lock,                   --                         .lock
			av_debugaccess         => channel_10_avalon_universal_slave_0_debugaccess,            --                         .debugaccess
			av_begintransfer       => open,                                                       --              (terminated)
			av_beginbursttransfer  => open,                                                       --              (terminated)
			av_writebyteenable     => open,                                                       --              (terminated)
			av_chipselect          => open,                                                       --              (terminated)
			av_clken               => open,                                                       --              (terminated)
			uav_clken              => '0',                                                        --              (terminated)
			av_outputenable        => open,                                                       --              (terminated)
			uav_response           => open,                                                       --              (terminated)
			av_response            => "00",                                                       --              (terminated)
			uav_writeresponsevalid => open,                                                       --              (terminated)
			av_writeresponsevalid  => '0'                                                         --              (terminated)
		);

	channel_11_avalon_universal_slave_0_translator : component address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki_cmp
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 3,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 1,
			AV_BURSTCOUNT_SYMBOLS          => 1,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 0,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0,
			WAITREQUEST_ALLOWANCE          => 0,
			SYNC_RESET                     => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                            --                      clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                   --                    reset.reset
			uav_address            => channel_11_avalon_universal_slave_0_agent_m0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => channel_11_avalon_universal_slave_0_agent_m0_burstcount,    --                         .burstcount
			uav_read               => channel_11_avalon_universal_slave_0_agent_m0_read,          --                         .read
			uav_write              => channel_11_avalon_universal_slave_0_agent_m0_write,         --                         .write
			uav_waitrequest        => channel_11_avalon_universal_slave_0_agent_m0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => channel_11_avalon_universal_slave_0_agent_m0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => channel_11_avalon_universal_slave_0_agent_m0_byteenable,    --                         .byteenable
			uav_readdata           => channel_11_avalon_universal_slave_0_agent_m0_readdata,      --                         .readdata
			uav_writedata          => channel_11_avalon_universal_slave_0_agent_m0_writedata,     --                         .writedata
			uav_lock               => channel_11_avalon_universal_slave_0_agent_m0_lock,          --                         .lock
			uav_debugaccess        => channel_11_avalon_universal_slave_0_agent_m0_debugaccess,   --                         .debugaccess
			av_address             => channel_11_avalon_universal_slave_0_address,                --      avalon_anti_slave_0.address
			av_write               => channel_11_avalon_universal_slave_0_write,                  --                         .write
			av_read                => channel_11_avalon_universal_slave_0_read,                   --                         .read
			av_readdata            => channel_11_avalon_universal_slave_0_readdata,               --                         .readdata
			av_writedata           => channel_11_avalon_universal_slave_0_writedata,              --                         .writedata
			av_burstcount          => channel_11_avalon_universal_slave_0_burstcount,             --                         .burstcount
			av_byteenable          => channel_11_avalon_universal_slave_0_byteenable,             --                         .byteenable
			av_readdatavalid       => channel_11_avalon_universal_slave_0_readdatavalid,          --                         .readdatavalid
			av_waitrequest         => channel_11_avalon_universal_slave_0_waitrequest,            --                         .waitrequest
			av_lock                => channel_11_avalon_universal_slave_0_lock,                   --                         .lock
			av_debugaccess         => channel_11_avalon_universal_slave_0_debugaccess,            --                         .debugaccess
			av_begintransfer       => open,                                                       --              (terminated)
			av_beginbursttransfer  => open,                                                       --              (terminated)
			av_writebyteenable     => open,                                                       --              (terminated)
			av_chipselect          => open,                                                       --              (terminated)
			av_clken               => open,                                                       --              (terminated)
			uav_clken              => '0',                                                        --              (terminated)
			av_outputenable        => open,                                                       --              (terminated)
			uav_response           => open,                                                       --              (terminated)
			av_response            => "00",                                                       --              (terminated)
			uav_writeresponsevalid => open,                                                       --              (terminated)
			av_writeresponsevalid  => '0'                                                         --              (terminated)
		);

	master_avalon_universal_master_0_agent : component address_decoder_multi_channel_altera_merlin_master_agent_191_mpbm6tq_cmp
		generic map (
			PKT_WUNIQUE               => 116,
			PKT_DOMAIN_H              => 115,
			PKT_DOMAIN_L              => 114,
			PKT_SNOOP_H               => 113,
			PKT_SNOOP_L               => 110,
			PKT_BARRIER_H             => 109,
			PKT_BARRIER_L             => 108,
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_QOS_H                 => 86,
			PKT_QOS_L                 => 86,
			PKT_DATA_SIDEBAND_H       => 84,
			PKT_DATA_SIDEBAND_L       => 84,
			PKT_ADDR_SIDEBAND_H       => 83,
			PKT_ADDR_SIDEBAND_L       => 83,
			PKT_BURST_TYPE_H          => 82,
			PKT_BURST_TYPE_L          => 81,
			PKT_CACHE_H               => 102,
			PKT_CACHE_L               => 99,
			PKT_THREAD_ID_H           => 95,
			PKT_THREAD_ID_L           => 95,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_EXCLUSIVE       => 73,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			ST_DATA_W                 => 117,
			ST_CHANNEL_W              => 12,
			AV_BURSTCOUNT_W           => 3,
			SUPPRESS_0_BYTEEN_RSP     => 0,
			ID                        => 0,
			BURSTWRAP_VALUE           => 1,
			CACHE_VALUE               => 0,
			SECURE_ACCESS_BIT         => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			DOMAIN_VALUE              => 3,
			BARRIER_VALUE             => 0,
			SNOOP_VALUE               => 0,
			WUNIQUE_VALUE             => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                   => csr_clk_clk_clk,                                                                     --       clk.clk
			reset                 => master_reset_reset_bridge_in_reset_reset,                                            -- clk_reset.reset
			av_address            => master_avalon_universal_master_0_translator_avalon_universal_master_0_address,       --        av.address
			av_write              => master_avalon_universal_master_0_translator_avalon_universal_master_0_write,         --          .write
			av_read               => master_avalon_universal_master_0_translator_avalon_universal_master_0_read,          --          .read
			av_writedata          => master_avalon_universal_master_0_translator_avalon_universal_master_0_writedata,     --          .writedata
			av_readdata           => master_avalon_universal_master_0_translator_avalon_universal_master_0_readdata,      --          .readdata
			av_waitrequest        => master_avalon_universal_master_0_translator_avalon_universal_master_0_waitrequest,   --          .waitrequest
			av_readdatavalid      => master_avalon_universal_master_0_translator_avalon_universal_master_0_readdatavalid, --          .readdatavalid
			av_byteenable         => master_avalon_universal_master_0_translator_avalon_universal_master_0_byteenable,    --          .byteenable
			av_burstcount         => master_avalon_universal_master_0_translator_avalon_universal_master_0_burstcount,    --          .burstcount
			av_debugaccess        => master_avalon_universal_master_0_translator_avalon_universal_master_0_debugaccess,   --          .debugaccess
			av_lock               => master_avalon_universal_master_0_translator_avalon_universal_master_0_lock,          --          .lock
			cp_valid              => master_avalon_universal_master_0_agent_cp_valid,                                     --        cp.valid
			cp_data               => master_avalon_universal_master_0_agent_cp_data,                                      --          .data
			cp_startofpacket      => master_avalon_universal_master_0_agent_cp_startofpacket,                             --          .startofpacket
			cp_endofpacket        => master_avalon_universal_master_0_agent_cp_endofpacket,                               --          .endofpacket
			cp_ready              => master_avalon_universal_master_0_agent_cp_ready,                                     --          .ready
			rp_valid              => master_avalon_universal_master_0_limiter_rsp_src_valid,                              --        rp.valid
			rp_data               => master_avalon_universal_master_0_limiter_rsp_src_data,                               --          .data
			rp_channel            => master_avalon_universal_master_0_limiter_rsp_src_channel,                            --          .channel
			rp_startofpacket      => master_avalon_universal_master_0_limiter_rsp_src_startofpacket,                      --          .startofpacket
			rp_endofpacket        => master_avalon_universal_master_0_limiter_rsp_src_endofpacket,                        --          .endofpacket
			rp_ready              => master_avalon_universal_master_0_limiter_rsp_src_ready,                              --          .ready
			av_response           => open,                                                                                -- (terminated)
			av_writeresponsevalid => open                                                                                 -- (terminated)
		);

	channel_1_avalon_universal_slave_0_agent : component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		generic map (
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 12,
			ST_DATA_W                 => 117,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                     => csr_clk_clk_clk,                                                     --             clk.clk
			reset                   => master_reset_reset_bridge_in_reset_reset,                            --       clk_reset.reset
			m0_address              => channel_1_avalon_universal_slave_0_agent_m0_address,                 --              m0.address
			m0_burstcount           => channel_1_avalon_universal_slave_0_agent_m0_burstcount,              --                .burstcount
			m0_byteenable           => channel_1_avalon_universal_slave_0_agent_m0_byteenable,              --                .byteenable
			m0_debugaccess          => channel_1_avalon_universal_slave_0_agent_m0_debugaccess,             --                .debugaccess
			m0_lock                 => channel_1_avalon_universal_slave_0_agent_m0_lock,                    --                .lock
			m0_readdata             => channel_1_avalon_universal_slave_0_agent_m0_readdata,                --                .readdata
			m0_readdatavalid        => channel_1_avalon_universal_slave_0_agent_m0_readdatavalid,           --                .readdatavalid
			m0_read                 => channel_1_avalon_universal_slave_0_agent_m0_read,                    --                .read
			m0_waitrequest          => channel_1_avalon_universal_slave_0_agent_m0_waitrequest,             --                .waitrequest
			m0_writedata            => channel_1_avalon_universal_slave_0_agent_m0_writedata,               --                .writedata
			m0_write                => channel_1_avalon_universal_slave_0_agent_m0_write,                   --                .write
			rp_endofpacket          => channel_1_avalon_universal_slave_0_agent_rp_endofpacket,             --              rp.endofpacket
			rp_ready                => channel_1_avalon_universal_slave_0_agent_rp_ready,                   --                .ready
			rp_valid                => channel_1_avalon_universal_slave_0_agent_rp_valid,                   --                .valid
			rp_data                 => channel_1_avalon_universal_slave_0_agent_rp_data,                    --                .data
			rp_startofpacket        => channel_1_avalon_universal_slave_0_agent_rp_startofpacket,           --                .startofpacket
			cp_ready                => cmd_mux_src_ready,                                                   --              cp.ready
			cp_valid                => cmd_mux_src_valid,                                                   --                .valid
			cp_data                 => cmd_mux_src_data,                                                    --                .data
			cp_startofpacket        => cmd_mux_src_startofpacket,                                           --                .startofpacket
			cp_endofpacket          => cmd_mux_src_endofpacket,                                             --                .endofpacket
			cp_channel              => cmd_mux_src_channel,                                                 --                .channel
			rf_sink_ready           => channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --         rf_sink.ready
			rf_sink_valid           => channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --                .valid
			rf_sink_startofpacket   => channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --                .startofpacket
			rf_sink_endofpacket     => channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --                .endofpacket
			rf_sink_data            => channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --                .data
			rf_source_ready         => channel_1_avalon_universal_slave_0_agent_rf_source_ready,            --       rf_source.ready
			rf_source_valid         => channel_1_avalon_universal_slave_0_agent_rf_source_valid,            --                .valid
			rf_source_startofpacket => channel_1_avalon_universal_slave_0_agent_rf_source_startofpacket,    --                .startofpacket
			rf_source_endofpacket   => channel_1_avalon_universal_slave_0_agent_rf_source_endofpacket,      --                .endofpacket
			rf_source_data          => channel_1_avalon_universal_slave_0_agent_rf_source_data,             --                .data
			rdata_fifo_sink_ready   => channel_1_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => channel_1_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_sink_data    => channel_1_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			rdata_fifo_src_ready    => channel_1_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => channel_1_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_src_data     => channel_1_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			m0_response             => "00",                                                                --     (terminated)
			m0_writeresponsevalid   => '0',                                                                 --     (terminated)
			rdata_fifo_sink_error   => '0'                                                                  --     (terminated)
		);

	channel_1_avalon_universal_slave_0_agent_rsp_fifo : component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 118,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => csr_clk_clk_clk,                                                     --       clk.clk
			reset             => master_reset_reset_bridge_in_reset_reset,                            -- clk_reset.reset
			in_data           => channel_1_avalon_universal_slave_0_agent_rf_source_data,             --        in.data
			in_valid          => channel_1_avalon_universal_slave_0_agent_rf_source_valid,            --          .valid
			in_ready          => channel_1_avalon_universal_slave_0_agent_rf_source_ready,            --          .ready
			in_startofpacket  => channel_1_avalon_universal_slave_0_agent_rf_source_startofpacket,    --          .startofpacket
			in_endofpacket    => channel_1_avalon_universal_slave_0_agent_rf_source_endofpacket,      --          .endofpacket
			out_data          => channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --       out.data
			out_valid         => channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --          .valid
			out_ready         => channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --          .ready
			out_startofpacket => channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --          .startofpacket
			out_endofpacket   => channel_1_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --          .endofpacket
			csr_address       => "00",                                                                -- (terminated)
			csr_read          => '0',                                                                 -- (terminated)
			csr_write         => '0',                                                                 -- (terminated)
			csr_readdata      => open,                                                                -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                                  -- (terminated)
			almost_full_data  => open,                                                                -- (terminated)
			almost_empty_data => open,                                                                -- (terminated)
			in_empty          => "0",                                                                 -- (terminated)
			out_empty         => open,                                                                -- (terminated)
			in_error          => "0",                                                                 -- (terminated)
			out_error         => open,                                                                -- (terminated)
			in_channel        => "0",                                                                 -- (terminated)
			out_channel       => open                                                                 -- (terminated)
		);

	channel_0_avalon_universal_slave_0_agent : component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		generic map (
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 12,
			ST_DATA_W                 => 117,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                     => csr_clk_clk_clk,                                                     --             clk.clk
			reset                   => master_reset_reset_bridge_in_reset_reset,                            --       clk_reset.reset
			m0_address              => channel_0_avalon_universal_slave_0_agent_m0_address,                 --              m0.address
			m0_burstcount           => channel_0_avalon_universal_slave_0_agent_m0_burstcount,              --                .burstcount
			m0_byteenable           => channel_0_avalon_universal_slave_0_agent_m0_byteenable,              --                .byteenable
			m0_debugaccess          => channel_0_avalon_universal_slave_0_agent_m0_debugaccess,             --                .debugaccess
			m0_lock                 => channel_0_avalon_universal_slave_0_agent_m0_lock,                    --                .lock
			m0_readdata             => channel_0_avalon_universal_slave_0_agent_m0_readdata,                --                .readdata
			m0_readdatavalid        => channel_0_avalon_universal_slave_0_agent_m0_readdatavalid,           --                .readdatavalid
			m0_read                 => channel_0_avalon_universal_slave_0_agent_m0_read,                    --                .read
			m0_waitrequest          => channel_0_avalon_universal_slave_0_agent_m0_waitrequest,             --                .waitrequest
			m0_writedata            => channel_0_avalon_universal_slave_0_agent_m0_writedata,               --                .writedata
			m0_write                => channel_0_avalon_universal_slave_0_agent_m0_write,                   --                .write
			rp_endofpacket          => channel_0_avalon_universal_slave_0_agent_rp_endofpacket,             --              rp.endofpacket
			rp_ready                => channel_0_avalon_universal_slave_0_agent_rp_ready,                   --                .ready
			rp_valid                => channel_0_avalon_universal_slave_0_agent_rp_valid,                   --                .valid
			rp_data                 => channel_0_avalon_universal_slave_0_agent_rp_data,                    --                .data
			rp_startofpacket        => channel_0_avalon_universal_slave_0_agent_rp_startofpacket,           --                .startofpacket
			cp_ready                => cmd_mux_001_src_ready,                                               --              cp.ready
			cp_valid                => cmd_mux_001_src_valid,                                               --                .valid
			cp_data                 => cmd_mux_001_src_data,                                                --                .data
			cp_startofpacket        => cmd_mux_001_src_startofpacket,                                       --                .startofpacket
			cp_endofpacket          => cmd_mux_001_src_endofpacket,                                         --                .endofpacket
			cp_channel              => cmd_mux_001_src_channel,                                             --                .channel
			rf_sink_ready           => channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --         rf_sink.ready
			rf_sink_valid           => channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --                .valid
			rf_sink_startofpacket   => channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --                .startofpacket
			rf_sink_endofpacket     => channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --                .endofpacket
			rf_sink_data            => channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --                .data
			rf_source_ready         => channel_0_avalon_universal_slave_0_agent_rf_source_ready,            --       rf_source.ready
			rf_source_valid         => channel_0_avalon_universal_slave_0_agent_rf_source_valid,            --                .valid
			rf_source_startofpacket => channel_0_avalon_universal_slave_0_agent_rf_source_startofpacket,    --                .startofpacket
			rf_source_endofpacket   => channel_0_avalon_universal_slave_0_agent_rf_source_endofpacket,      --                .endofpacket
			rf_source_data          => channel_0_avalon_universal_slave_0_agent_rf_source_data,             --                .data
			rdata_fifo_sink_ready   => channel_0_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => channel_0_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_sink_data    => channel_0_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			rdata_fifo_src_ready    => channel_0_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => channel_0_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_src_data     => channel_0_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			m0_response             => "00",                                                                --     (terminated)
			m0_writeresponsevalid   => '0',                                                                 --     (terminated)
			rdata_fifo_sink_error   => '0'                                                                  --     (terminated)
		);

	channel_0_avalon_universal_slave_0_agent_rsp_fifo : component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 118,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => csr_clk_clk_clk,                                                     --       clk.clk
			reset             => master_reset_reset_bridge_in_reset_reset,                            -- clk_reset.reset
			in_data           => channel_0_avalon_universal_slave_0_agent_rf_source_data,             --        in.data
			in_valid          => channel_0_avalon_universal_slave_0_agent_rf_source_valid,            --          .valid
			in_ready          => channel_0_avalon_universal_slave_0_agent_rf_source_ready,            --          .ready
			in_startofpacket  => channel_0_avalon_universal_slave_0_agent_rf_source_startofpacket,    --          .startofpacket
			in_endofpacket    => channel_0_avalon_universal_slave_0_agent_rf_source_endofpacket,      --          .endofpacket
			out_data          => channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --       out.data
			out_valid         => channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --          .valid
			out_ready         => channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --          .ready
			out_startofpacket => channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --          .startofpacket
			out_endofpacket   => channel_0_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --          .endofpacket
			csr_address       => "00",                                                                -- (terminated)
			csr_read          => '0',                                                                 -- (terminated)
			csr_write         => '0',                                                                 -- (terminated)
			csr_readdata      => open,                                                                -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                                  -- (terminated)
			almost_full_data  => open,                                                                -- (terminated)
			almost_empty_data => open,                                                                -- (terminated)
			in_empty          => "0",                                                                 -- (terminated)
			out_empty         => open,                                                                -- (terminated)
			in_error          => "0",                                                                 -- (terminated)
			out_error         => open,                                                                -- (terminated)
			in_channel        => "0",                                                                 -- (terminated)
			out_channel       => open                                                                 -- (terminated)
		);

	channel_2_avalon_universal_slave_0_agent : component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		generic map (
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 12,
			ST_DATA_W                 => 117,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                     => csr_clk_clk_clk,                                                     --             clk.clk
			reset                   => master_reset_reset_bridge_in_reset_reset,                            --       clk_reset.reset
			m0_address              => channel_2_avalon_universal_slave_0_agent_m0_address,                 --              m0.address
			m0_burstcount           => channel_2_avalon_universal_slave_0_agent_m0_burstcount,              --                .burstcount
			m0_byteenable           => channel_2_avalon_universal_slave_0_agent_m0_byteenable,              --                .byteenable
			m0_debugaccess          => channel_2_avalon_universal_slave_0_agent_m0_debugaccess,             --                .debugaccess
			m0_lock                 => channel_2_avalon_universal_slave_0_agent_m0_lock,                    --                .lock
			m0_readdata             => channel_2_avalon_universal_slave_0_agent_m0_readdata,                --                .readdata
			m0_readdatavalid        => channel_2_avalon_universal_slave_0_agent_m0_readdatavalid,           --                .readdatavalid
			m0_read                 => channel_2_avalon_universal_slave_0_agent_m0_read,                    --                .read
			m0_waitrequest          => channel_2_avalon_universal_slave_0_agent_m0_waitrequest,             --                .waitrequest
			m0_writedata            => channel_2_avalon_universal_slave_0_agent_m0_writedata,               --                .writedata
			m0_write                => channel_2_avalon_universal_slave_0_agent_m0_write,                   --                .write
			rp_endofpacket          => channel_2_avalon_universal_slave_0_agent_rp_endofpacket,             --              rp.endofpacket
			rp_ready                => channel_2_avalon_universal_slave_0_agent_rp_ready,                   --                .ready
			rp_valid                => channel_2_avalon_universal_slave_0_agent_rp_valid,                   --                .valid
			rp_data                 => channel_2_avalon_universal_slave_0_agent_rp_data,                    --                .data
			rp_startofpacket        => channel_2_avalon_universal_slave_0_agent_rp_startofpacket,           --                .startofpacket
			cp_ready                => cmd_mux_002_src_ready,                                               --              cp.ready
			cp_valid                => cmd_mux_002_src_valid,                                               --                .valid
			cp_data                 => cmd_mux_002_src_data,                                                --                .data
			cp_startofpacket        => cmd_mux_002_src_startofpacket,                                       --                .startofpacket
			cp_endofpacket          => cmd_mux_002_src_endofpacket,                                         --                .endofpacket
			cp_channel              => cmd_mux_002_src_channel,                                             --                .channel
			rf_sink_ready           => channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --         rf_sink.ready
			rf_sink_valid           => channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --                .valid
			rf_sink_startofpacket   => channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --                .startofpacket
			rf_sink_endofpacket     => channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --                .endofpacket
			rf_sink_data            => channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --                .data
			rf_source_ready         => channel_2_avalon_universal_slave_0_agent_rf_source_ready,            --       rf_source.ready
			rf_source_valid         => channel_2_avalon_universal_slave_0_agent_rf_source_valid,            --                .valid
			rf_source_startofpacket => channel_2_avalon_universal_slave_0_agent_rf_source_startofpacket,    --                .startofpacket
			rf_source_endofpacket   => channel_2_avalon_universal_slave_0_agent_rf_source_endofpacket,      --                .endofpacket
			rf_source_data          => channel_2_avalon_universal_slave_0_agent_rf_source_data,             --                .data
			rdata_fifo_sink_ready   => channel_2_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => channel_2_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_sink_data    => channel_2_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			rdata_fifo_src_ready    => channel_2_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => channel_2_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_src_data     => channel_2_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			m0_response             => "00",                                                                --     (terminated)
			m0_writeresponsevalid   => '0',                                                                 --     (terminated)
			rdata_fifo_sink_error   => '0'                                                                  --     (terminated)
		);

	channel_2_avalon_universal_slave_0_agent_rsp_fifo : component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 118,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => csr_clk_clk_clk,                                                     --       clk.clk
			reset             => master_reset_reset_bridge_in_reset_reset,                            -- clk_reset.reset
			in_data           => channel_2_avalon_universal_slave_0_agent_rf_source_data,             --        in.data
			in_valid          => channel_2_avalon_universal_slave_0_agent_rf_source_valid,            --          .valid
			in_ready          => channel_2_avalon_universal_slave_0_agent_rf_source_ready,            --          .ready
			in_startofpacket  => channel_2_avalon_universal_slave_0_agent_rf_source_startofpacket,    --          .startofpacket
			in_endofpacket    => channel_2_avalon_universal_slave_0_agent_rf_source_endofpacket,      --          .endofpacket
			out_data          => channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --       out.data
			out_valid         => channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --          .valid
			out_ready         => channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --          .ready
			out_startofpacket => channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --          .startofpacket
			out_endofpacket   => channel_2_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --          .endofpacket
			csr_address       => "00",                                                                -- (terminated)
			csr_read          => '0',                                                                 -- (terminated)
			csr_write         => '0',                                                                 -- (terminated)
			csr_readdata      => open,                                                                -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                                  -- (terminated)
			almost_full_data  => open,                                                                -- (terminated)
			almost_empty_data => open,                                                                -- (terminated)
			in_empty          => "0",                                                                 -- (terminated)
			out_empty         => open,                                                                -- (terminated)
			in_error          => "0",                                                                 -- (terminated)
			out_error         => open,                                                                -- (terminated)
			in_channel        => "0",                                                                 -- (terminated)
			out_channel       => open                                                                 -- (terminated)
		);

	channel_3_avalon_universal_slave_0_agent : component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		generic map (
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 12,
			ST_DATA_W                 => 117,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                     => csr_clk_clk_clk,                                                     --             clk.clk
			reset                   => master_reset_reset_bridge_in_reset_reset,                            --       clk_reset.reset
			m0_address              => channel_3_avalon_universal_slave_0_agent_m0_address,                 --              m0.address
			m0_burstcount           => channel_3_avalon_universal_slave_0_agent_m0_burstcount,              --                .burstcount
			m0_byteenable           => channel_3_avalon_universal_slave_0_agent_m0_byteenable,              --                .byteenable
			m0_debugaccess          => channel_3_avalon_universal_slave_0_agent_m0_debugaccess,             --                .debugaccess
			m0_lock                 => channel_3_avalon_universal_slave_0_agent_m0_lock,                    --                .lock
			m0_readdata             => channel_3_avalon_universal_slave_0_agent_m0_readdata,                --                .readdata
			m0_readdatavalid        => channel_3_avalon_universal_slave_0_agent_m0_readdatavalid,           --                .readdatavalid
			m0_read                 => channel_3_avalon_universal_slave_0_agent_m0_read,                    --                .read
			m0_waitrequest          => channel_3_avalon_universal_slave_0_agent_m0_waitrequest,             --                .waitrequest
			m0_writedata            => channel_3_avalon_universal_slave_0_agent_m0_writedata,               --                .writedata
			m0_write                => channel_3_avalon_universal_slave_0_agent_m0_write,                   --                .write
			rp_endofpacket          => channel_3_avalon_universal_slave_0_agent_rp_endofpacket,             --              rp.endofpacket
			rp_ready                => channel_3_avalon_universal_slave_0_agent_rp_ready,                   --                .ready
			rp_valid                => channel_3_avalon_universal_slave_0_agent_rp_valid,                   --                .valid
			rp_data                 => channel_3_avalon_universal_slave_0_agent_rp_data,                    --                .data
			rp_startofpacket        => channel_3_avalon_universal_slave_0_agent_rp_startofpacket,           --                .startofpacket
			cp_ready                => cmd_mux_003_src_ready,                                               --              cp.ready
			cp_valid                => cmd_mux_003_src_valid,                                               --                .valid
			cp_data                 => cmd_mux_003_src_data,                                                --                .data
			cp_startofpacket        => cmd_mux_003_src_startofpacket,                                       --                .startofpacket
			cp_endofpacket          => cmd_mux_003_src_endofpacket,                                         --                .endofpacket
			cp_channel              => cmd_mux_003_src_channel,                                             --                .channel
			rf_sink_ready           => channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --         rf_sink.ready
			rf_sink_valid           => channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --                .valid
			rf_sink_startofpacket   => channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --                .startofpacket
			rf_sink_endofpacket     => channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --                .endofpacket
			rf_sink_data            => channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --                .data
			rf_source_ready         => channel_3_avalon_universal_slave_0_agent_rf_source_ready,            --       rf_source.ready
			rf_source_valid         => channel_3_avalon_universal_slave_0_agent_rf_source_valid,            --                .valid
			rf_source_startofpacket => channel_3_avalon_universal_slave_0_agent_rf_source_startofpacket,    --                .startofpacket
			rf_source_endofpacket   => channel_3_avalon_universal_slave_0_agent_rf_source_endofpacket,      --                .endofpacket
			rf_source_data          => channel_3_avalon_universal_slave_0_agent_rf_source_data,             --                .data
			rdata_fifo_sink_ready   => channel_3_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => channel_3_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_sink_data    => channel_3_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			rdata_fifo_src_ready    => channel_3_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => channel_3_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_src_data     => channel_3_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			m0_response             => "00",                                                                --     (terminated)
			m0_writeresponsevalid   => '0',                                                                 --     (terminated)
			rdata_fifo_sink_error   => '0'                                                                  --     (terminated)
		);

	channel_3_avalon_universal_slave_0_agent_rsp_fifo : component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 118,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => csr_clk_clk_clk,                                                     --       clk.clk
			reset             => master_reset_reset_bridge_in_reset_reset,                            -- clk_reset.reset
			in_data           => channel_3_avalon_universal_slave_0_agent_rf_source_data,             --        in.data
			in_valid          => channel_3_avalon_universal_slave_0_agent_rf_source_valid,            --          .valid
			in_ready          => channel_3_avalon_universal_slave_0_agent_rf_source_ready,            --          .ready
			in_startofpacket  => channel_3_avalon_universal_slave_0_agent_rf_source_startofpacket,    --          .startofpacket
			in_endofpacket    => channel_3_avalon_universal_slave_0_agent_rf_source_endofpacket,      --          .endofpacket
			out_data          => channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --       out.data
			out_valid         => channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --          .valid
			out_ready         => channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --          .ready
			out_startofpacket => channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --          .startofpacket
			out_endofpacket   => channel_3_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --          .endofpacket
			csr_address       => "00",                                                                -- (terminated)
			csr_read          => '0',                                                                 -- (terminated)
			csr_write         => '0',                                                                 -- (terminated)
			csr_readdata      => open,                                                                -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                                  -- (terminated)
			almost_full_data  => open,                                                                -- (terminated)
			almost_empty_data => open,                                                                -- (terminated)
			in_empty          => "0",                                                                 -- (terminated)
			out_empty         => open,                                                                -- (terminated)
			in_error          => "0",                                                                 -- (terminated)
			out_error         => open,                                                                -- (terminated)
			in_channel        => "0",                                                                 -- (terminated)
			out_channel       => open                                                                 -- (terminated)
		);

	channel_4_avalon_universal_slave_0_agent : component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		generic map (
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 12,
			ST_DATA_W                 => 117,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                     => csr_clk_clk_clk,                                                     --             clk.clk
			reset                   => master_reset_reset_bridge_in_reset_reset,                            --       clk_reset.reset
			m0_address              => channel_4_avalon_universal_slave_0_agent_m0_address,                 --              m0.address
			m0_burstcount           => channel_4_avalon_universal_slave_0_agent_m0_burstcount,              --                .burstcount
			m0_byteenable           => channel_4_avalon_universal_slave_0_agent_m0_byteenable,              --                .byteenable
			m0_debugaccess          => channel_4_avalon_universal_slave_0_agent_m0_debugaccess,             --                .debugaccess
			m0_lock                 => channel_4_avalon_universal_slave_0_agent_m0_lock,                    --                .lock
			m0_readdata             => channel_4_avalon_universal_slave_0_agent_m0_readdata,                --                .readdata
			m0_readdatavalid        => channel_4_avalon_universal_slave_0_agent_m0_readdatavalid,           --                .readdatavalid
			m0_read                 => channel_4_avalon_universal_slave_0_agent_m0_read,                    --                .read
			m0_waitrequest          => channel_4_avalon_universal_slave_0_agent_m0_waitrequest,             --                .waitrequest
			m0_writedata            => channel_4_avalon_universal_slave_0_agent_m0_writedata,               --                .writedata
			m0_write                => channel_4_avalon_universal_slave_0_agent_m0_write,                   --                .write
			rp_endofpacket          => channel_4_avalon_universal_slave_0_agent_rp_endofpacket,             --              rp.endofpacket
			rp_ready                => channel_4_avalon_universal_slave_0_agent_rp_ready,                   --                .ready
			rp_valid                => channel_4_avalon_universal_slave_0_agent_rp_valid,                   --                .valid
			rp_data                 => channel_4_avalon_universal_slave_0_agent_rp_data,                    --                .data
			rp_startofpacket        => channel_4_avalon_universal_slave_0_agent_rp_startofpacket,           --                .startofpacket
			cp_ready                => cmd_mux_004_src_ready,                                               --              cp.ready
			cp_valid                => cmd_mux_004_src_valid,                                               --                .valid
			cp_data                 => cmd_mux_004_src_data,                                                --                .data
			cp_startofpacket        => cmd_mux_004_src_startofpacket,                                       --                .startofpacket
			cp_endofpacket          => cmd_mux_004_src_endofpacket,                                         --                .endofpacket
			cp_channel              => cmd_mux_004_src_channel,                                             --                .channel
			rf_sink_ready           => channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --         rf_sink.ready
			rf_sink_valid           => channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --                .valid
			rf_sink_startofpacket   => channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --                .startofpacket
			rf_sink_endofpacket     => channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --                .endofpacket
			rf_sink_data            => channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --                .data
			rf_source_ready         => channel_4_avalon_universal_slave_0_agent_rf_source_ready,            --       rf_source.ready
			rf_source_valid         => channel_4_avalon_universal_slave_0_agent_rf_source_valid,            --                .valid
			rf_source_startofpacket => channel_4_avalon_universal_slave_0_agent_rf_source_startofpacket,    --                .startofpacket
			rf_source_endofpacket   => channel_4_avalon_universal_slave_0_agent_rf_source_endofpacket,      --                .endofpacket
			rf_source_data          => channel_4_avalon_universal_slave_0_agent_rf_source_data,             --                .data
			rdata_fifo_sink_ready   => channel_4_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => channel_4_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_sink_data    => channel_4_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			rdata_fifo_src_ready    => channel_4_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => channel_4_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_src_data     => channel_4_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			m0_response             => "00",                                                                --     (terminated)
			m0_writeresponsevalid   => '0',                                                                 --     (terminated)
			rdata_fifo_sink_error   => '0'                                                                  --     (terminated)
		);

	channel_4_avalon_universal_slave_0_agent_rsp_fifo : component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 118,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => csr_clk_clk_clk,                                                     --       clk.clk
			reset             => master_reset_reset_bridge_in_reset_reset,                            -- clk_reset.reset
			in_data           => channel_4_avalon_universal_slave_0_agent_rf_source_data,             --        in.data
			in_valid          => channel_4_avalon_universal_slave_0_agent_rf_source_valid,            --          .valid
			in_ready          => channel_4_avalon_universal_slave_0_agent_rf_source_ready,            --          .ready
			in_startofpacket  => channel_4_avalon_universal_slave_0_agent_rf_source_startofpacket,    --          .startofpacket
			in_endofpacket    => channel_4_avalon_universal_slave_0_agent_rf_source_endofpacket,      --          .endofpacket
			out_data          => channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --       out.data
			out_valid         => channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --          .valid
			out_ready         => channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --          .ready
			out_startofpacket => channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --          .startofpacket
			out_endofpacket   => channel_4_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --          .endofpacket
			csr_address       => "00",                                                                -- (terminated)
			csr_read          => '0',                                                                 -- (terminated)
			csr_write         => '0',                                                                 -- (terminated)
			csr_readdata      => open,                                                                -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                                  -- (terminated)
			almost_full_data  => open,                                                                -- (terminated)
			almost_empty_data => open,                                                                -- (terminated)
			in_empty          => "0",                                                                 -- (terminated)
			out_empty         => open,                                                                -- (terminated)
			in_error          => "0",                                                                 -- (terminated)
			out_error         => open,                                                                -- (terminated)
			in_channel        => "0",                                                                 -- (terminated)
			out_channel       => open                                                                 -- (terminated)
		);

	channel_5_avalon_universal_slave_0_agent : component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		generic map (
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 12,
			ST_DATA_W                 => 117,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                     => csr_clk_clk_clk,                                                     --             clk.clk
			reset                   => master_reset_reset_bridge_in_reset_reset,                            --       clk_reset.reset
			m0_address              => channel_5_avalon_universal_slave_0_agent_m0_address,                 --              m0.address
			m0_burstcount           => channel_5_avalon_universal_slave_0_agent_m0_burstcount,              --                .burstcount
			m0_byteenable           => channel_5_avalon_universal_slave_0_agent_m0_byteenable,              --                .byteenable
			m0_debugaccess          => channel_5_avalon_universal_slave_0_agent_m0_debugaccess,             --                .debugaccess
			m0_lock                 => channel_5_avalon_universal_slave_0_agent_m0_lock,                    --                .lock
			m0_readdata             => channel_5_avalon_universal_slave_0_agent_m0_readdata,                --                .readdata
			m0_readdatavalid        => channel_5_avalon_universal_slave_0_agent_m0_readdatavalid,           --                .readdatavalid
			m0_read                 => channel_5_avalon_universal_slave_0_agent_m0_read,                    --                .read
			m0_waitrequest          => channel_5_avalon_universal_slave_0_agent_m0_waitrequest,             --                .waitrequest
			m0_writedata            => channel_5_avalon_universal_slave_0_agent_m0_writedata,               --                .writedata
			m0_write                => channel_5_avalon_universal_slave_0_agent_m0_write,                   --                .write
			rp_endofpacket          => channel_5_avalon_universal_slave_0_agent_rp_endofpacket,             --              rp.endofpacket
			rp_ready                => channel_5_avalon_universal_slave_0_agent_rp_ready,                   --                .ready
			rp_valid                => channel_5_avalon_universal_slave_0_agent_rp_valid,                   --                .valid
			rp_data                 => channel_5_avalon_universal_slave_0_agent_rp_data,                    --                .data
			rp_startofpacket        => channel_5_avalon_universal_slave_0_agent_rp_startofpacket,           --                .startofpacket
			cp_ready                => cmd_mux_005_src_ready,                                               --              cp.ready
			cp_valid                => cmd_mux_005_src_valid,                                               --                .valid
			cp_data                 => cmd_mux_005_src_data,                                                --                .data
			cp_startofpacket        => cmd_mux_005_src_startofpacket,                                       --                .startofpacket
			cp_endofpacket          => cmd_mux_005_src_endofpacket,                                         --                .endofpacket
			cp_channel              => cmd_mux_005_src_channel,                                             --                .channel
			rf_sink_ready           => channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --         rf_sink.ready
			rf_sink_valid           => channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --                .valid
			rf_sink_startofpacket   => channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --                .startofpacket
			rf_sink_endofpacket     => channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --                .endofpacket
			rf_sink_data            => channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --                .data
			rf_source_ready         => channel_5_avalon_universal_slave_0_agent_rf_source_ready,            --       rf_source.ready
			rf_source_valid         => channel_5_avalon_universal_slave_0_agent_rf_source_valid,            --                .valid
			rf_source_startofpacket => channel_5_avalon_universal_slave_0_agent_rf_source_startofpacket,    --                .startofpacket
			rf_source_endofpacket   => channel_5_avalon_universal_slave_0_agent_rf_source_endofpacket,      --                .endofpacket
			rf_source_data          => channel_5_avalon_universal_slave_0_agent_rf_source_data,             --                .data
			rdata_fifo_sink_ready   => channel_5_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => channel_5_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_sink_data    => channel_5_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			rdata_fifo_src_ready    => channel_5_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => channel_5_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_src_data     => channel_5_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			m0_response             => "00",                                                                --     (terminated)
			m0_writeresponsevalid   => '0',                                                                 --     (terminated)
			rdata_fifo_sink_error   => '0'                                                                  --     (terminated)
		);

	channel_5_avalon_universal_slave_0_agent_rsp_fifo : component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 118,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => csr_clk_clk_clk,                                                     --       clk.clk
			reset             => master_reset_reset_bridge_in_reset_reset,                            -- clk_reset.reset
			in_data           => channel_5_avalon_universal_slave_0_agent_rf_source_data,             --        in.data
			in_valid          => channel_5_avalon_universal_slave_0_agent_rf_source_valid,            --          .valid
			in_ready          => channel_5_avalon_universal_slave_0_agent_rf_source_ready,            --          .ready
			in_startofpacket  => channel_5_avalon_universal_slave_0_agent_rf_source_startofpacket,    --          .startofpacket
			in_endofpacket    => channel_5_avalon_universal_slave_0_agent_rf_source_endofpacket,      --          .endofpacket
			out_data          => channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --       out.data
			out_valid         => channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --          .valid
			out_ready         => channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --          .ready
			out_startofpacket => channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --          .startofpacket
			out_endofpacket   => channel_5_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --          .endofpacket
			csr_address       => "00",                                                                -- (terminated)
			csr_read          => '0',                                                                 -- (terminated)
			csr_write         => '0',                                                                 -- (terminated)
			csr_readdata      => open,                                                                -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                                  -- (terminated)
			almost_full_data  => open,                                                                -- (terminated)
			almost_empty_data => open,                                                                -- (terminated)
			in_empty          => "0",                                                                 -- (terminated)
			out_empty         => open,                                                                -- (terminated)
			in_error          => "0",                                                                 -- (terminated)
			out_error         => open,                                                                -- (terminated)
			in_channel        => "0",                                                                 -- (terminated)
			out_channel       => open                                                                 -- (terminated)
		);

	channel_6_avalon_universal_slave_0_agent : component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		generic map (
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 12,
			ST_DATA_W                 => 117,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                     => csr_clk_clk_clk,                                                     --             clk.clk
			reset                   => master_reset_reset_bridge_in_reset_reset,                            --       clk_reset.reset
			m0_address              => channel_6_avalon_universal_slave_0_agent_m0_address,                 --              m0.address
			m0_burstcount           => channel_6_avalon_universal_slave_0_agent_m0_burstcount,              --                .burstcount
			m0_byteenable           => channel_6_avalon_universal_slave_0_agent_m0_byteenable,              --                .byteenable
			m0_debugaccess          => channel_6_avalon_universal_slave_0_agent_m0_debugaccess,             --                .debugaccess
			m0_lock                 => channel_6_avalon_universal_slave_0_agent_m0_lock,                    --                .lock
			m0_readdata             => channel_6_avalon_universal_slave_0_agent_m0_readdata,                --                .readdata
			m0_readdatavalid        => channel_6_avalon_universal_slave_0_agent_m0_readdatavalid,           --                .readdatavalid
			m0_read                 => channel_6_avalon_universal_slave_0_agent_m0_read,                    --                .read
			m0_waitrequest          => channel_6_avalon_universal_slave_0_agent_m0_waitrequest,             --                .waitrequest
			m0_writedata            => channel_6_avalon_universal_slave_0_agent_m0_writedata,               --                .writedata
			m0_write                => channel_6_avalon_universal_slave_0_agent_m0_write,                   --                .write
			rp_endofpacket          => channel_6_avalon_universal_slave_0_agent_rp_endofpacket,             --              rp.endofpacket
			rp_ready                => channel_6_avalon_universal_slave_0_agent_rp_ready,                   --                .ready
			rp_valid                => channel_6_avalon_universal_slave_0_agent_rp_valid,                   --                .valid
			rp_data                 => channel_6_avalon_universal_slave_0_agent_rp_data,                    --                .data
			rp_startofpacket        => channel_6_avalon_universal_slave_0_agent_rp_startofpacket,           --                .startofpacket
			cp_ready                => cmd_mux_006_src_ready,                                               --              cp.ready
			cp_valid                => cmd_mux_006_src_valid,                                               --                .valid
			cp_data                 => cmd_mux_006_src_data,                                                --                .data
			cp_startofpacket        => cmd_mux_006_src_startofpacket,                                       --                .startofpacket
			cp_endofpacket          => cmd_mux_006_src_endofpacket,                                         --                .endofpacket
			cp_channel              => cmd_mux_006_src_channel,                                             --                .channel
			rf_sink_ready           => channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --         rf_sink.ready
			rf_sink_valid           => channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --                .valid
			rf_sink_startofpacket   => channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --                .startofpacket
			rf_sink_endofpacket     => channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --                .endofpacket
			rf_sink_data            => channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --                .data
			rf_source_ready         => channel_6_avalon_universal_slave_0_agent_rf_source_ready,            --       rf_source.ready
			rf_source_valid         => channel_6_avalon_universal_slave_0_agent_rf_source_valid,            --                .valid
			rf_source_startofpacket => channel_6_avalon_universal_slave_0_agent_rf_source_startofpacket,    --                .startofpacket
			rf_source_endofpacket   => channel_6_avalon_universal_slave_0_agent_rf_source_endofpacket,      --                .endofpacket
			rf_source_data          => channel_6_avalon_universal_slave_0_agent_rf_source_data,             --                .data
			rdata_fifo_sink_ready   => channel_6_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => channel_6_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_sink_data    => channel_6_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			rdata_fifo_src_ready    => channel_6_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => channel_6_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_src_data     => channel_6_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			m0_response             => "00",                                                                --     (terminated)
			m0_writeresponsevalid   => '0',                                                                 --     (terminated)
			rdata_fifo_sink_error   => '0'                                                                  --     (terminated)
		);

	channel_6_avalon_universal_slave_0_agent_rsp_fifo : component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 118,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => csr_clk_clk_clk,                                                     --       clk.clk
			reset             => master_reset_reset_bridge_in_reset_reset,                            -- clk_reset.reset
			in_data           => channel_6_avalon_universal_slave_0_agent_rf_source_data,             --        in.data
			in_valid          => channel_6_avalon_universal_slave_0_agent_rf_source_valid,            --          .valid
			in_ready          => channel_6_avalon_universal_slave_0_agent_rf_source_ready,            --          .ready
			in_startofpacket  => channel_6_avalon_universal_slave_0_agent_rf_source_startofpacket,    --          .startofpacket
			in_endofpacket    => channel_6_avalon_universal_slave_0_agent_rf_source_endofpacket,      --          .endofpacket
			out_data          => channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --       out.data
			out_valid         => channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --          .valid
			out_ready         => channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --          .ready
			out_startofpacket => channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --          .startofpacket
			out_endofpacket   => channel_6_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --          .endofpacket
			csr_address       => "00",                                                                -- (terminated)
			csr_read          => '0',                                                                 -- (terminated)
			csr_write         => '0',                                                                 -- (terminated)
			csr_readdata      => open,                                                                -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                                  -- (terminated)
			almost_full_data  => open,                                                                -- (terminated)
			almost_empty_data => open,                                                                -- (terminated)
			in_empty          => "0",                                                                 -- (terminated)
			out_empty         => open,                                                                -- (terminated)
			in_error          => "0",                                                                 -- (terminated)
			out_error         => open,                                                                -- (terminated)
			in_channel        => "0",                                                                 -- (terminated)
			out_channel       => open                                                                 -- (terminated)
		);

	channel_7_avalon_universal_slave_0_agent : component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		generic map (
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 12,
			ST_DATA_W                 => 117,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                     => csr_clk_clk_clk,                                                     --             clk.clk
			reset                   => master_reset_reset_bridge_in_reset_reset,                            --       clk_reset.reset
			m0_address              => channel_7_avalon_universal_slave_0_agent_m0_address,                 --              m0.address
			m0_burstcount           => channel_7_avalon_universal_slave_0_agent_m0_burstcount,              --                .burstcount
			m0_byteenable           => channel_7_avalon_universal_slave_0_agent_m0_byteenable,              --                .byteenable
			m0_debugaccess          => channel_7_avalon_universal_slave_0_agent_m0_debugaccess,             --                .debugaccess
			m0_lock                 => channel_7_avalon_universal_slave_0_agent_m0_lock,                    --                .lock
			m0_readdata             => channel_7_avalon_universal_slave_0_agent_m0_readdata,                --                .readdata
			m0_readdatavalid        => channel_7_avalon_universal_slave_0_agent_m0_readdatavalid,           --                .readdatavalid
			m0_read                 => channel_7_avalon_universal_slave_0_agent_m0_read,                    --                .read
			m0_waitrequest          => channel_7_avalon_universal_slave_0_agent_m0_waitrequest,             --                .waitrequest
			m0_writedata            => channel_7_avalon_universal_slave_0_agent_m0_writedata,               --                .writedata
			m0_write                => channel_7_avalon_universal_slave_0_agent_m0_write,                   --                .write
			rp_endofpacket          => channel_7_avalon_universal_slave_0_agent_rp_endofpacket,             --              rp.endofpacket
			rp_ready                => channel_7_avalon_universal_slave_0_agent_rp_ready,                   --                .ready
			rp_valid                => channel_7_avalon_universal_slave_0_agent_rp_valid,                   --                .valid
			rp_data                 => channel_7_avalon_universal_slave_0_agent_rp_data,                    --                .data
			rp_startofpacket        => channel_7_avalon_universal_slave_0_agent_rp_startofpacket,           --                .startofpacket
			cp_ready                => cmd_mux_007_src_ready,                                               --              cp.ready
			cp_valid                => cmd_mux_007_src_valid,                                               --                .valid
			cp_data                 => cmd_mux_007_src_data,                                                --                .data
			cp_startofpacket        => cmd_mux_007_src_startofpacket,                                       --                .startofpacket
			cp_endofpacket          => cmd_mux_007_src_endofpacket,                                         --                .endofpacket
			cp_channel              => cmd_mux_007_src_channel,                                             --                .channel
			rf_sink_ready           => channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --         rf_sink.ready
			rf_sink_valid           => channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --                .valid
			rf_sink_startofpacket   => channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --                .startofpacket
			rf_sink_endofpacket     => channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --                .endofpacket
			rf_sink_data            => channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --                .data
			rf_source_ready         => channel_7_avalon_universal_slave_0_agent_rf_source_ready,            --       rf_source.ready
			rf_source_valid         => channel_7_avalon_universal_slave_0_agent_rf_source_valid,            --                .valid
			rf_source_startofpacket => channel_7_avalon_universal_slave_0_agent_rf_source_startofpacket,    --                .startofpacket
			rf_source_endofpacket   => channel_7_avalon_universal_slave_0_agent_rf_source_endofpacket,      --                .endofpacket
			rf_source_data          => channel_7_avalon_universal_slave_0_agent_rf_source_data,             --                .data
			rdata_fifo_sink_ready   => channel_7_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => channel_7_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_sink_data    => channel_7_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			rdata_fifo_src_ready    => channel_7_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => channel_7_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_src_data     => channel_7_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			m0_response             => "00",                                                                --     (terminated)
			m0_writeresponsevalid   => '0',                                                                 --     (terminated)
			rdata_fifo_sink_error   => '0'                                                                  --     (terminated)
		);

	channel_7_avalon_universal_slave_0_agent_rsp_fifo : component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 118,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => csr_clk_clk_clk,                                                     --       clk.clk
			reset             => master_reset_reset_bridge_in_reset_reset,                            -- clk_reset.reset
			in_data           => channel_7_avalon_universal_slave_0_agent_rf_source_data,             --        in.data
			in_valid          => channel_7_avalon_universal_slave_0_agent_rf_source_valid,            --          .valid
			in_ready          => channel_7_avalon_universal_slave_0_agent_rf_source_ready,            --          .ready
			in_startofpacket  => channel_7_avalon_universal_slave_0_agent_rf_source_startofpacket,    --          .startofpacket
			in_endofpacket    => channel_7_avalon_universal_slave_0_agent_rf_source_endofpacket,      --          .endofpacket
			out_data          => channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --       out.data
			out_valid         => channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --          .valid
			out_ready         => channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --          .ready
			out_startofpacket => channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --          .startofpacket
			out_endofpacket   => channel_7_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --          .endofpacket
			csr_address       => "00",                                                                -- (terminated)
			csr_read          => '0',                                                                 -- (terminated)
			csr_write         => '0',                                                                 -- (terminated)
			csr_readdata      => open,                                                                -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                                  -- (terminated)
			almost_full_data  => open,                                                                -- (terminated)
			almost_empty_data => open,                                                                -- (terminated)
			in_empty          => "0",                                                                 -- (terminated)
			out_empty         => open,                                                                -- (terminated)
			in_error          => "0",                                                                 -- (terminated)
			out_error         => open,                                                                -- (terminated)
			in_channel        => "0",                                                                 -- (terminated)
			out_channel       => open                                                                 -- (terminated)
		);

	channel_8_avalon_universal_slave_0_agent : component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		generic map (
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 12,
			ST_DATA_W                 => 117,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                     => csr_clk_clk_clk,                                                     --             clk.clk
			reset                   => master_reset_reset_bridge_in_reset_reset,                            --       clk_reset.reset
			m0_address              => channel_8_avalon_universal_slave_0_agent_m0_address,                 --              m0.address
			m0_burstcount           => channel_8_avalon_universal_slave_0_agent_m0_burstcount,              --                .burstcount
			m0_byteenable           => channel_8_avalon_universal_slave_0_agent_m0_byteenable,              --                .byteenable
			m0_debugaccess          => channel_8_avalon_universal_slave_0_agent_m0_debugaccess,             --                .debugaccess
			m0_lock                 => channel_8_avalon_universal_slave_0_agent_m0_lock,                    --                .lock
			m0_readdata             => channel_8_avalon_universal_slave_0_agent_m0_readdata,                --                .readdata
			m0_readdatavalid        => channel_8_avalon_universal_slave_0_agent_m0_readdatavalid,           --                .readdatavalid
			m0_read                 => channel_8_avalon_universal_slave_0_agent_m0_read,                    --                .read
			m0_waitrequest          => channel_8_avalon_universal_slave_0_agent_m0_waitrequest,             --                .waitrequest
			m0_writedata            => channel_8_avalon_universal_slave_0_agent_m0_writedata,               --                .writedata
			m0_write                => channel_8_avalon_universal_slave_0_agent_m0_write,                   --                .write
			rp_endofpacket          => channel_8_avalon_universal_slave_0_agent_rp_endofpacket,             --              rp.endofpacket
			rp_ready                => channel_8_avalon_universal_slave_0_agent_rp_ready,                   --                .ready
			rp_valid                => channel_8_avalon_universal_slave_0_agent_rp_valid,                   --                .valid
			rp_data                 => channel_8_avalon_universal_slave_0_agent_rp_data,                    --                .data
			rp_startofpacket        => channel_8_avalon_universal_slave_0_agent_rp_startofpacket,           --                .startofpacket
			cp_ready                => cmd_mux_008_src_ready,                                               --              cp.ready
			cp_valid                => cmd_mux_008_src_valid,                                               --                .valid
			cp_data                 => cmd_mux_008_src_data,                                                --                .data
			cp_startofpacket        => cmd_mux_008_src_startofpacket,                                       --                .startofpacket
			cp_endofpacket          => cmd_mux_008_src_endofpacket,                                         --                .endofpacket
			cp_channel              => cmd_mux_008_src_channel,                                             --                .channel
			rf_sink_ready           => channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --         rf_sink.ready
			rf_sink_valid           => channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --                .valid
			rf_sink_startofpacket   => channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --                .startofpacket
			rf_sink_endofpacket     => channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --                .endofpacket
			rf_sink_data            => channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --                .data
			rf_source_ready         => channel_8_avalon_universal_slave_0_agent_rf_source_ready,            --       rf_source.ready
			rf_source_valid         => channel_8_avalon_universal_slave_0_agent_rf_source_valid,            --                .valid
			rf_source_startofpacket => channel_8_avalon_universal_slave_0_agent_rf_source_startofpacket,    --                .startofpacket
			rf_source_endofpacket   => channel_8_avalon_universal_slave_0_agent_rf_source_endofpacket,      --                .endofpacket
			rf_source_data          => channel_8_avalon_universal_slave_0_agent_rf_source_data,             --                .data
			rdata_fifo_sink_ready   => channel_8_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => channel_8_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_sink_data    => channel_8_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			rdata_fifo_src_ready    => channel_8_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => channel_8_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_src_data     => channel_8_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			m0_response             => "00",                                                                --     (terminated)
			m0_writeresponsevalid   => '0',                                                                 --     (terminated)
			rdata_fifo_sink_error   => '0'                                                                  --     (terminated)
		);

	channel_8_avalon_universal_slave_0_agent_rsp_fifo : component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 118,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => csr_clk_clk_clk,                                                     --       clk.clk
			reset             => master_reset_reset_bridge_in_reset_reset,                            -- clk_reset.reset
			in_data           => channel_8_avalon_universal_slave_0_agent_rf_source_data,             --        in.data
			in_valid          => channel_8_avalon_universal_slave_0_agent_rf_source_valid,            --          .valid
			in_ready          => channel_8_avalon_universal_slave_0_agent_rf_source_ready,            --          .ready
			in_startofpacket  => channel_8_avalon_universal_slave_0_agent_rf_source_startofpacket,    --          .startofpacket
			in_endofpacket    => channel_8_avalon_universal_slave_0_agent_rf_source_endofpacket,      --          .endofpacket
			out_data          => channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --       out.data
			out_valid         => channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --          .valid
			out_ready         => channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --          .ready
			out_startofpacket => channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --          .startofpacket
			out_endofpacket   => channel_8_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --          .endofpacket
			csr_address       => "00",                                                                -- (terminated)
			csr_read          => '0',                                                                 -- (terminated)
			csr_write         => '0',                                                                 -- (terminated)
			csr_readdata      => open,                                                                -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                                  -- (terminated)
			almost_full_data  => open,                                                                -- (terminated)
			almost_empty_data => open,                                                                -- (terminated)
			in_empty          => "0",                                                                 -- (terminated)
			out_empty         => open,                                                                -- (terminated)
			in_error          => "0",                                                                 -- (terminated)
			out_error         => open,                                                                -- (terminated)
			in_channel        => "0",                                                                 -- (terminated)
			out_channel       => open                                                                 -- (terminated)
		);

	channel_9_avalon_universal_slave_0_agent : component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		generic map (
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 12,
			ST_DATA_W                 => 117,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                     => csr_clk_clk_clk,                                                     --             clk.clk
			reset                   => master_reset_reset_bridge_in_reset_reset,                            --       clk_reset.reset
			m0_address              => channel_9_avalon_universal_slave_0_agent_m0_address,                 --              m0.address
			m0_burstcount           => channel_9_avalon_universal_slave_0_agent_m0_burstcount,              --                .burstcount
			m0_byteenable           => channel_9_avalon_universal_slave_0_agent_m0_byteenable,              --                .byteenable
			m0_debugaccess          => channel_9_avalon_universal_slave_0_agent_m0_debugaccess,             --                .debugaccess
			m0_lock                 => channel_9_avalon_universal_slave_0_agent_m0_lock,                    --                .lock
			m0_readdata             => channel_9_avalon_universal_slave_0_agent_m0_readdata,                --                .readdata
			m0_readdatavalid        => channel_9_avalon_universal_slave_0_agent_m0_readdatavalid,           --                .readdatavalid
			m0_read                 => channel_9_avalon_universal_slave_0_agent_m0_read,                    --                .read
			m0_waitrequest          => channel_9_avalon_universal_slave_0_agent_m0_waitrequest,             --                .waitrequest
			m0_writedata            => channel_9_avalon_universal_slave_0_agent_m0_writedata,               --                .writedata
			m0_write                => channel_9_avalon_universal_slave_0_agent_m0_write,                   --                .write
			rp_endofpacket          => channel_9_avalon_universal_slave_0_agent_rp_endofpacket,             --              rp.endofpacket
			rp_ready                => channel_9_avalon_universal_slave_0_agent_rp_ready,                   --                .ready
			rp_valid                => channel_9_avalon_universal_slave_0_agent_rp_valid,                   --                .valid
			rp_data                 => channel_9_avalon_universal_slave_0_agent_rp_data,                    --                .data
			rp_startofpacket        => channel_9_avalon_universal_slave_0_agent_rp_startofpacket,           --                .startofpacket
			cp_ready                => cmd_mux_009_src_ready,                                               --              cp.ready
			cp_valid                => cmd_mux_009_src_valid,                                               --                .valid
			cp_data                 => cmd_mux_009_src_data,                                                --                .data
			cp_startofpacket        => cmd_mux_009_src_startofpacket,                                       --                .startofpacket
			cp_endofpacket          => cmd_mux_009_src_endofpacket,                                         --                .endofpacket
			cp_channel              => cmd_mux_009_src_channel,                                             --                .channel
			rf_sink_ready           => channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --         rf_sink.ready
			rf_sink_valid           => channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --                .valid
			rf_sink_startofpacket   => channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --                .startofpacket
			rf_sink_endofpacket     => channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --                .endofpacket
			rf_sink_data            => channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --                .data
			rf_source_ready         => channel_9_avalon_universal_slave_0_agent_rf_source_ready,            --       rf_source.ready
			rf_source_valid         => channel_9_avalon_universal_slave_0_agent_rf_source_valid,            --                .valid
			rf_source_startofpacket => channel_9_avalon_universal_slave_0_agent_rf_source_startofpacket,    --                .startofpacket
			rf_source_endofpacket   => channel_9_avalon_universal_slave_0_agent_rf_source_endofpacket,      --                .endofpacket
			rf_source_data          => channel_9_avalon_universal_slave_0_agent_rf_source_data,             --                .data
			rdata_fifo_sink_ready   => channel_9_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => channel_9_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_sink_data    => channel_9_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			rdata_fifo_src_ready    => channel_9_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => channel_9_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_src_data     => channel_9_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			m0_response             => "00",                                                                --     (terminated)
			m0_writeresponsevalid   => '0',                                                                 --     (terminated)
			rdata_fifo_sink_error   => '0'                                                                  --     (terminated)
		);

	channel_9_avalon_universal_slave_0_agent_rsp_fifo : component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 118,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => csr_clk_clk_clk,                                                     --       clk.clk
			reset             => master_reset_reset_bridge_in_reset_reset,                            -- clk_reset.reset
			in_data           => channel_9_avalon_universal_slave_0_agent_rf_source_data,             --        in.data
			in_valid          => channel_9_avalon_universal_slave_0_agent_rf_source_valid,            --          .valid
			in_ready          => channel_9_avalon_universal_slave_0_agent_rf_source_ready,            --          .ready
			in_startofpacket  => channel_9_avalon_universal_slave_0_agent_rf_source_startofpacket,    --          .startofpacket
			in_endofpacket    => channel_9_avalon_universal_slave_0_agent_rf_source_endofpacket,      --          .endofpacket
			out_data          => channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --       out.data
			out_valid         => channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --          .valid
			out_ready         => channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --          .ready
			out_startofpacket => channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --          .startofpacket
			out_endofpacket   => channel_9_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --          .endofpacket
			csr_address       => "00",                                                                -- (terminated)
			csr_read          => '0',                                                                 -- (terminated)
			csr_write         => '0',                                                                 -- (terminated)
			csr_readdata      => open,                                                                -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                                  -- (terminated)
			almost_full_data  => open,                                                                -- (terminated)
			almost_empty_data => open,                                                                -- (terminated)
			in_empty          => "0",                                                                 -- (terminated)
			out_empty         => open,                                                                -- (terminated)
			in_error          => "0",                                                                 -- (terminated)
			out_error         => open,                                                                -- (terminated)
			in_channel        => "0",                                                                 -- (terminated)
			out_channel       => open                                                                 -- (terminated)
		);

	channel_10_avalon_universal_slave_0_agent : component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		generic map (
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 12,
			ST_DATA_W                 => 117,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                     => csr_clk_clk_clk,                                                      --             clk.clk
			reset                   => master_reset_reset_bridge_in_reset_reset,                             --       clk_reset.reset
			m0_address              => channel_10_avalon_universal_slave_0_agent_m0_address,                 --              m0.address
			m0_burstcount           => channel_10_avalon_universal_slave_0_agent_m0_burstcount,              --                .burstcount
			m0_byteenable           => channel_10_avalon_universal_slave_0_agent_m0_byteenable,              --                .byteenable
			m0_debugaccess          => channel_10_avalon_universal_slave_0_agent_m0_debugaccess,             --                .debugaccess
			m0_lock                 => channel_10_avalon_universal_slave_0_agent_m0_lock,                    --                .lock
			m0_readdata             => channel_10_avalon_universal_slave_0_agent_m0_readdata,                --                .readdata
			m0_readdatavalid        => channel_10_avalon_universal_slave_0_agent_m0_readdatavalid,           --                .readdatavalid
			m0_read                 => channel_10_avalon_universal_slave_0_agent_m0_read,                    --                .read
			m0_waitrequest          => channel_10_avalon_universal_slave_0_agent_m0_waitrequest,             --                .waitrequest
			m0_writedata            => channel_10_avalon_universal_slave_0_agent_m0_writedata,               --                .writedata
			m0_write                => channel_10_avalon_universal_slave_0_agent_m0_write,                   --                .write
			rp_endofpacket          => channel_10_avalon_universal_slave_0_agent_rp_endofpacket,             --              rp.endofpacket
			rp_ready                => channel_10_avalon_universal_slave_0_agent_rp_ready,                   --                .ready
			rp_valid                => channel_10_avalon_universal_slave_0_agent_rp_valid,                   --                .valid
			rp_data                 => channel_10_avalon_universal_slave_0_agent_rp_data,                    --                .data
			rp_startofpacket        => channel_10_avalon_universal_slave_0_agent_rp_startofpacket,           --                .startofpacket
			cp_ready                => cmd_mux_010_src_ready,                                                --              cp.ready
			cp_valid                => cmd_mux_010_src_valid,                                                --                .valid
			cp_data                 => cmd_mux_010_src_data,                                                 --                .data
			cp_startofpacket        => cmd_mux_010_src_startofpacket,                                        --                .startofpacket
			cp_endofpacket          => cmd_mux_010_src_endofpacket,                                          --                .endofpacket
			cp_channel              => cmd_mux_010_src_channel,                                              --                .channel
			rf_sink_ready           => channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --         rf_sink.ready
			rf_sink_valid           => channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --                .valid
			rf_sink_startofpacket   => channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --                .startofpacket
			rf_sink_endofpacket     => channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --                .endofpacket
			rf_sink_data            => channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --                .data
			rf_source_ready         => channel_10_avalon_universal_slave_0_agent_rf_source_ready,            --       rf_source.ready
			rf_source_valid         => channel_10_avalon_universal_slave_0_agent_rf_source_valid,            --                .valid
			rf_source_startofpacket => channel_10_avalon_universal_slave_0_agent_rf_source_startofpacket,    --                .startofpacket
			rf_source_endofpacket   => channel_10_avalon_universal_slave_0_agent_rf_source_endofpacket,      --                .endofpacket
			rf_source_data          => channel_10_avalon_universal_slave_0_agent_rf_source_data,             --                .data
			rdata_fifo_sink_ready   => channel_10_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => channel_10_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_sink_data    => channel_10_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			rdata_fifo_src_ready    => channel_10_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => channel_10_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_src_data     => channel_10_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			m0_response             => "00",                                                                 --     (terminated)
			m0_writeresponsevalid   => '0',                                                                  --     (terminated)
			rdata_fifo_sink_error   => '0'                                                                   --     (terminated)
		);

	channel_10_avalon_universal_slave_0_agent_rsp_fifo : component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 118,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => csr_clk_clk_clk,                                                      --       clk.clk
			reset             => master_reset_reset_bridge_in_reset_reset,                             -- clk_reset.reset
			in_data           => channel_10_avalon_universal_slave_0_agent_rf_source_data,             --        in.data
			in_valid          => channel_10_avalon_universal_slave_0_agent_rf_source_valid,            --          .valid
			in_ready          => channel_10_avalon_universal_slave_0_agent_rf_source_ready,            --          .ready
			in_startofpacket  => channel_10_avalon_universal_slave_0_agent_rf_source_startofpacket,    --          .startofpacket
			in_endofpacket    => channel_10_avalon_universal_slave_0_agent_rf_source_endofpacket,      --          .endofpacket
			out_data          => channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --       out.data
			out_valid         => channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --          .valid
			out_ready         => channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --          .ready
			out_startofpacket => channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --          .startofpacket
			out_endofpacket   => channel_10_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --          .endofpacket
			csr_address       => "00",                                                                 -- (terminated)
			csr_read          => '0',                                                                  -- (terminated)
			csr_write         => '0',                                                                  -- (terminated)
			csr_readdata      => open,                                                                 -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                                   -- (terminated)
			almost_full_data  => open,                                                                 -- (terminated)
			almost_empty_data => open,                                                                 -- (terminated)
			in_empty          => "0",                                                                  -- (terminated)
			out_empty         => open,                                                                 -- (terminated)
			in_error          => "0",                                                                  -- (terminated)
			out_error         => open,                                                                 -- (terminated)
			in_channel        => "0",                                                                  -- (terminated)
			out_channel       => open                                                                  -- (terminated)
		);

	channel_11_avalon_universal_slave_0_agent : component address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri_cmp
		generic map (
			PKT_ORI_BURST_SIZE_H      => 107,
			PKT_ORI_BURST_SIZE_L      => 105,
			PKT_RESPONSE_STATUS_H     => 104,
			PKT_RESPONSE_STATUS_L     => 103,
			PKT_BURST_SIZE_H          => 80,
			PKT_BURST_SIZE_L          => 78,
			PKT_TRANS_LOCK            => 72,
			PKT_BEGIN_BURST           => 85,
			PKT_PROTECTION_H          => 98,
			PKT_PROTECTION_L          => 96,
			PKT_BURSTWRAP_H           => 77,
			PKT_BURSTWRAP_L           => 77,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_ADDR_H                => 67,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 68,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			PKT_TRANS_READ            => 71,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 12,
			ST_DATA_W                 => 117,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0,
			SYNC_RESET                => 0
		)
		port map (
			clk                     => csr_clk_clk_clk,                                                      --             clk.clk
			reset                   => master_reset_reset_bridge_in_reset_reset,                             --       clk_reset.reset
			m0_address              => channel_11_avalon_universal_slave_0_agent_m0_address,                 --              m0.address
			m0_burstcount           => channel_11_avalon_universal_slave_0_agent_m0_burstcount,              --                .burstcount
			m0_byteenable           => channel_11_avalon_universal_slave_0_agent_m0_byteenable,              --                .byteenable
			m0_debugaccess          => channel_11_avalon_universal_slave_0_agent_m0_debugaccess,             --                .debugaccess
			m0_lock                 => channel_11_avalon_universal_slave_0_agent_m0_lock,                    --                .lock
			m0_readdata             => channel_11_avalon_universal_slave_0_agent_m0_readdata,                --                .readdata
			m0_readdatavalid        => channel_11_avalon_universal_slave_0_agent_m0_readdatavalid,           --                .readdatavalid
			m0_read                 => channel_11_avalon_universal_slave_0_agent_m0_read,                    --                .read
			m0_waitrequest          => channel_11_avalon_universal_slave_0_agent_m0_waitrequest,             --                .waitrequest
			m0_writedata            => channel_11_avalon_universal_slave_0_agent_m0_writedata,               --                .writedata
			m0_write                => channel_11_avalon_universal_slave_0_agent_m0_write,                   --                .write
			rp_endofpacket          => channel_11_avalon_universal_slave_0_agent_rp_endofpacket,             --              rp.endofpacket
			rp_ready                => channel_11_avalon_universal_slave_0_agent_rp_ready,                   --                .ready
			rp_valid                => channel_11_avalon_universal_slave_0_agent_rp_valid,                   --                .valid
			rp_data                 => channel_11_avalon_universal_slave_0_agent_rp_data,                    --                .data
			rp_startofpacket        => channel_11_avalon_universal_slave_0_agent_rp_startofpacket,           --                .startofpacket
			cp_ready                => cmd_mux_011_src_ready,                                                --              cp.ready
			cp_valid                => cmd_mux_011_src_valid,                                                --                .valid
			cp_data                 => cmd_mux_011_src_data,                                                 --                .data
			cp_startofpacket        => cmd_mux_011_src_startofpacket,                                        --                .startofpacket
			cp_endofpacket          => cmd_mux_011_src_endofpacket,                                          --                .endofpacket
			cp_channel              => cmd_mux_011_src_channel,                                              --                .channel
			rf_sink_ready           => channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --         rf_sink.ready
			rf_sink_valid           => channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --                .valid
			rf_sink_startofpacket   => channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --                .startofpacket
			rf_sink_endofpacket     => channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --                .endofpacket
			rf_sink_data            => channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --                .data
			rf_source_ready         => channel_11_avalon_universal_slave_0_agent_rf_source_ready,            --       rf_source.ready
			rf_source_valid         => channel_11_avalon_universal_slave_0_agent_rf_source_valid,            --                .valid
			rf_source_startofpacket => channel_11_avalon_universal_slave_0_agent_rf_source_startofpacket,    --                .startofpacket
			rf_source_endofpacket   => channel_11_avalon_universal_slave_0_agent_rf_source_endofpacket,      --                .endofpacket
			rf_source_data          => channel_11_avalon_universal_slave_0_agent_rf_source_data,             --                .data
			rdata_fifo_sink_ready   => channel_11_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => channel_11_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_sink_data    => channel_11_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			rdata_fifo_src_ready    => channel_11_avalon_universal_slave_0_agent_rdata_fifo_src_ready,       --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => channel_11_avalon_universal_slave_0_agent_rdata_fifo_src_valid,       --                .valid
			rdata_fifo_src_data     => channel_11_avalon_universal_slave_0_agent_rdata_fifo_src_data,        --                .data
			m0_response             => "00",                                                                 --     (terminated)
			m0_writeresponsevalid   => '0',                                                                  --     (terminated)
			rdata_fifo_sink_error   => '0'                                                                   --     (terminated)
		);

	channel_11_avalon_universal_slave_0_agent_rsp_fifo : component address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq_cmp
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 118,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0,
			EMPTY_WIDTH         => 1,
			SYNC_RESET          => 0
		)
		port map (
			clk               => csr_clk_clk_clk,                                                      --       clk.clk
			reset             => master_reset_reset_bridge_in_reset_reset,                             -- clk_reset.reset
			in_data           => channel_11_avalon_universal_slave_0_agent_rf_source_data,             --        in.data
			in_valid          => channel_11_avalon_universal_slave_0_agent_rf_source_valid,            --          .valid
			in_ready          => channel_11_avalon_universal_slave_0_agent_rf_source_ready,            --          .ready
			in_startofpacket  => channel_11_avalon_universal_slave_0_agent_rf_source_startofpacket,    --          .startofpacket
			in_endofpacket    => channel_11_avalon_universal_slave_0_agent_rf_source_endofpacket,      --          .endofpacket
			out_data          => channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_data,          --       out.data
			out_valid         => channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_valid,         --          .valid
			out_ready         => channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_ready,         --          .ready
			out_startofpacket => channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, --          .startofpacket
			out_endofpacket   => channel_11_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket,   --          .endofpacket
			csr_address       => "00",                                                                 -- (terminated)
			csr_read          => '0',                                                                  -- (terminated)
			csr_write         => '0',                                                                  -- (terminated)
			csr_readdata      => open,                                                                 -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                                   -- (terminated)
			almost_full_data  => open,                                                                 -- (terminated)
			almost_empty_data => open,                                                                 -- (terminated)
			in_empty          => "0",                                                                  -- (terminated)
			out_empty         => open,                                                                 -- (terminated)
			in_error          => "0",                                                                  -- (terminated)
			out_error         => open,                                                                 -- (terminated)
			in_channel        => "0",                                                                  -- (terminated)
			out_channel       => open                                                                  -- (terminated)
		);

	router : component address_decoder_multi_channel_altera_merlin_router_191_32egg6a_cmp
		port map (
			sink_ready         => master_avalon_universal_master_0_agent_cp_ready,         --      sink.ready
			sink_valid         => master_avalon_universal_master_0_agent_cp_valid,         --          .valid
			sink_data          => master_avalon_universal_master_0_agent_cp_data,          --          .data
			sink_startofpacket => master_avalon_universal_master_0_agent_cp_startofpacket, --          .startofpacket
			sink_endofpacket   => master_avalon_universal_master_0_agent_cp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                         --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                -- clk_reset.reset
			src_ready          => router_src_ready,                                        --       src.ready
			src_valid          => router_src_valid,                                        --          .valid
			src_data           => router_src_data,                                         --          .data
			src_channel        => router_src_channel,                                      --          .channel
			src_startofpacket  => router_src_startofpacket,                                --          .startofpacket
			src_endofpacket    => router_src_endofpacket                                   --          .endofpacket
		);

	router_001 : component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		port map (
			sink_ready         => channel_1_avalon_universal_slave_0_agent_rp_ready,         --      sink.ready
			sink_valid         => channel_1_avalon_universal_slave_0_agent_rp_valid,         --          .valid
			sink_data          => channel_1_avalon_universal_slave_0_agent_rp_data,          --          .data
			sink_startofpacket => channel_1_avalon_universal_slave_0_agent_rp_startofpacket, --          .startofpacket
			sink_endofpacket   => channel_1_avalon_universal_slave_0_agent_rp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                           --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                  -- clk_reset.reset
			src_ready          => router_001_src_ready,                                      --       src.ready
			src_valid          => router_001_src_valid,                                      --          .valid
			src_data           => router_001_src_data,                                       --          .data
			src_channel        => router_001_src_channel,                                    --          .channel
			src_startofpacket  => router_001_src_startofpacket,                              --          .startofpacket
			src_endofpacket    => router_001_src_endofpacket                                 --          .endofpacket
		);

	router_002 : component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		port map (
			sink_ready         => channel_0_avalon_universal_slave_0_agent_rp_ready,         --      sink.ready
			sink_valid         => channel_0_avalon_universal_slave_0_agent_rp_valid,         --          .valid
			sink_data          => channel_0_avalon_universal_slave_0_agent_rp_data,          --          .data
			sink_startofpacket => channel_0_avalon_universal_slave_0_agent_rp_startofpacket, --          .startofpacket
			sink_endofpacket   => channel_0_avalon_universal_slave_0_agent_rp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                           --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                  -- clk_reset.reset
			src_ready          => router_002_src_ready,                                      --       src.ready
			src_valid          => router_002_src_valid,                                      --          .valid
			src_data           => router_002_src_data,                                       --          .data
			src_channel        => router_002_src_channel,                                    --          .channel
			src_startofpacket  => router_002_src_startofpacket,                              --          .startofpacket
			src_endofpacket    => router_002_src_endofpacket                                 --          .endofpacket
		);

	router_003 : component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		port map (
			sink_ready         => channel_2_avalon_universal_slave_0_agent_rp_ready,         --      sink.ready
			sink_valid         => channel_2_avalon_universal_slave_0_agent_rp_valid,         --          .valid
			sink_data          => channel_2_avalon_universal_slave_0_agent_rp_data,          --          .data
			sink_startofpacket => channel_2_avalon_universal_slave_0_agent_rp_startofpacket, --          .startofpacket
			sink_endofpacket   => channel_2_avalon_universal_slave_0_agent_rp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                           --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                  -- clk_reset.reset
			src_ready          => router_003_src_ready,                                      --       src.ready
			src_valid          => router_003_src_valid,                                      --          .valid
			src_data           => router_003_src_data,                                       --          .data
			src_channel        => router_003_src_channel,                                    --          .channel
			src_startofpacket  => router_003_src_startofpacket,                              --          .startofpacket
			src_endofpacket    => router_003_src_endofpacket                                 --          .endofpacket
		);

	router_004 : component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		port map (
			sink_ready         => channel_3_avalon_universal_slave_0_agent_rp_ready,         --      sink.ready
			sink_valid         => channel_3_avalon_universal_slave_0_agent_rp_valid,         --          .valid
			sink_data          => channel_3_avalon_universal_slave_0_agent_rp_data,          --          .data
			sink_startofpacket => channel_3_avalon_universal_slave_0_agent_rp_startofpacket, --          .startofpacket
			sink_endofpacket   => channel_3_avalon_universal_slave_0_agent_rp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                           --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                  -- clk_reset.reset
			src_ready          => router_004_src_ready,                                      --       src.ready
			src_valid          => router_004_src_valid,                                      --          .valid
			src_data           => router_004_src_data,                                       --          .data
			src_channel        => router_004_src_channel,                                    --          .channel
			src_startofpacket  => router_004_src_startofpacket,                              --          .startofpacket
			src_endofpacket    => router_004_src_endofpacket                                 --          .endofpacket
		);

	router_005 : component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		port map (
			sink_ready         => channel_4_avalon_universal_slave_0_agent_rp_ready,         --      sink.ready
			sink_valid         => channel_4_avalon_universal_slave_0_agent_rp_valid,         --          .valid
			sink_data          => channel_4_avalon_universal_slave_0_agent_rp_data,          --          .data
			sink_startofpacket => channel_4_avalon_universal_slave_0_agent_rp_startofpacket, --          .startofpacket
			sink_endofpacket   => channel_4_avalon_universal_slave_0_agent_rp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                           --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                  -- clk_reset.reset
			src_ready          => router_005_src_ready,                                      --       src.ready
			src_valid          => router_005_src_valid,                                      --          .valid
			src_data           => router_005_src_data,                                       --          .data
			src_channel        => router_005_src_channel,                                    --          .channel
			src_startofpacket  => router_005_src_startofpacket,                              --          .startofpacket
			src_endofpacket    => router_005_src_endofpacket                                 --          .endofpacket
		);

	router_006 : component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		port map (
			sink_ready         => channel_5_avalon_universal_slave_0_agent_rp_ready,         --      sink.ready
			sink_valid         => channel_5_avalon_universal_slave_0_agent_rp_valid,         --          .valid
			sink_data          => channel_5_avalon_universal_slave_0_agent_rp_data,          --          .data
			sink_startofpacket => channel_5_avalon_universal_slave_0_agent_rp_startofpacket, --          .startofpacket
			sink_endofpacket   => channel_5_avalon_universal_slave_0_agent_rp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                           --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                  -- clk_reset.reset
			src_ready          => router_006_src_ready,                                      --       src.ready
			src_valid          => router_006_src_valid,                                      --          .valid
			src_data           => router_006_src_data,                                       --          .data
			src_channel        => router_006_src_channel,                                    --          .channel
			src_startofpacket  => router_006_src_startofpacket,                              --          .startofpacket
			src_endofpacket    => router_006_src_endofpacket                                 --          .endofpacket
		);

	router_007 : component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		port map (
			sink_ready         => channel_6_avalon_universal_slave_0_agent_rp_ready,         --      sink.ready
			sink_valid         => channel_6_avalon_universal_slave_0_agent_rp_valid,         --          .valid
			sink_data          => channel_6_avalon_universal_slave_0_agent_rp_data,          --          .data
			sink_startofpacket => channel_6_avalon_universal_slave_0_agent_rp_startofpacket, --          .startofpacket
			sink_endofpacket   => channel_6_avalon_universal_slave_0_agent_rp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                           --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                  -- clk_reset.reset
			src_ready          => router_007_src_ready,                                      --       src.ready
			src_valid          => router_007_src_valid,                                      --          .valid
			src_data           => router_007_src_data,                                       --          .data
			src_channel        => router_007_src_channel,                                    --          .channel
			src_startofpacket  => router_007_src_startofpacket,                              --          .startofpacket
			src_endofpacket    => router_007_src_endofpacket                                 --          .endofpacket
		);

	router_008 : component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		port map (
			sink_ready         => channel_7_avalon_universal_slave_0_agent_rp_ready,         --      sink.ready
			sink_valid         => channel_7_avalon_universal_slave_0_agent_rp_valid,         --          .valid
			sink_data          => channel_7_avalon_universal_slave_0_agent_rp_data,          --          .data
			sink_startofpacket => channel_7_avalon_universal_slave_0_agent_rp_startofpacket, --          .startofpacket
			sink_endofpacket   => channel_7_avalon_universal_slave_0_agent_rp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                           --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                  -- clk_reset.reset
			src_ready          => router_008_src_ready,                                      --       src.ready
			src_valid          => router_008_src_valid,                                      --          .valid
			src_data           => router_008_src_data,                                       --          .data
			src_channel        => router_008_src_channel,                                    --          .channel
			src_startofpacket  => router_008_src_startofpacket,                              --          .startofpacket
			src_endofpacket    => router_008_src_endofpacket                                 --          .endofpacket
		);

	router_009 : component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		port map (
			sink_ready         => channel_8_avalon_universal_slave_0_agent_rp_ready,         --      sink.ready
			sink_valid         => channel_8_avalon_universal_slave_0_agent_rp_valid,         --          .valid
			sink_data          => channel_8_avalon_universal_slave_0_agent_rp_data,          --          .data
			sink_startofpacket => channel_8_avalon_universal_slave_0_agent_rp_startofpacket, --          .startofpacket
			sink_endofpacket   => channel_8_avalon_universal_slave_0_agent_rp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                           --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                  -- clk_reset.reset
			src_ready          => router_009_src_ready,                                      --       src.ready
			src_valid          => router_009_src_valid,                                      --          .valid
			src_data           => router_009_src_data,                                       --          .data
			src_channel        => router_009_src_channel,                                    --          .channel
			src_startofpacket  => router_009_src_startofpacket,                              --          .startofpacket
			src_endofpacket    => router_009_src_endofpacket                                 --          .endofpacket
		);

	router_010 : component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		port map (
			sink_ready         => channel_9_avalon_universal_slave_0_agent_rp_ready,         --      sink.ready
			sink_valid         => channel_9_avalon_universal_slave_0_agent_rp_valid,         --          .valid
			sink_data          => channel_9_avalon_universal_slave_0_agent_rp_data,          --          .data
			sink_startofpacket => channel_9_avalon_universal_slave_0_agent_rp_startofpacket, --          .startofpacket
			sink_endofpacket   => channel_9_avalon_universal_slave_0_agent_rp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                           --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                  -- clk_reset.reset
			src_ready          => router_010_src_ready,                                      --       src.ready
			src_valid          => router_010_src_valid,                                      --          .valid
			src_data           => router_010_src_data,                                       --          .data
			src_channel        => router_010_src_channel,                                    --          .channel
			src_startofpacket  => router_010_src_startofpacket,                              --          .startofpacket
			src_endofpacket    => router_010_src_endofpacket                                 --          .endofpacket
		);

	router_011 : component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		port map (
			sink_ready         => channel_10_avalon_universal_slave_0_agent_rp_ready,         --      sink.ready
			sink_valid         => channel_10_avalon_universal_slave_0_agent_rp_valid,         --          .valid
			sink_data          => channel_10_avalon_universal_slave_0_agent_rp_data,          --          .data
			sink_startofpacket => channel_10_avalon_universal_slave_0_agent_rp_startofpacket, --          .startofpacket
			sink_endofpacket   => channel_10_avalon_universal_slave_0_agent_rp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                            --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                   -- clk_reset.reset
			src_ready          => router_011_src_ready,                                       --       src.ready
			src_valid          => router_011_src_valid,                                       --          .valid
			src_data           => router_011_src_data,                                        --          .data
			src_channel        => router_011_src_channel,                                     --          .channel
			src_startofpacket  => router_011_src_startofpacket,                               --          .startofpacket
			src_endofpacket    => router_011_src_endofpacket                                  --          .endofpacket
		);

	router_012 : component address_decoder_multi_channel_altera_merlin_router_191_4vwofdq_cmp
		port map (
			sink_ready         => channel_11_avalon_universal_slave_0_agent_rp_ready,         --      sink.ready
			sink_valid         => channel_11_avalon_universal_slave_0_agent_rp_valid,         --          .valid
			sink_data          => channel_11_avalon_universal_slave_0_agent_rp_data,          --          .data
			sink_startofpacket => channel_11_avalon_universal_slave_0_agent_rp_startofpacket, --          .startofpacket
			sink_endofpacket   => channel_11_avalon_universal_slave_0_agent_rp_endofpacket,   --          .endofpacket
			clk                => csr_clk_clk_clk,                                            --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset,                   -- clk_reset.reset
			src_ready          => router_012_src_ready,                                       --       src.ready
			src_valid          => router_012_src_valid,                                       --          .valid
			src_data           => router_012_src_data,                                        --          .data
			src_channel        => router_012_src_channel,                                     --          .channel
			src_startofpacket  => router_012_src_startofpacket,                               --          .startofpacket
			src_endofpacket    => router_012_src_endofpacket                                  --          .endofpacket
		);

	master_avalon_universal_master_0_limiter : component address_decoder_multi_channel_altera_merlin_traffic_limiter_191_kcba44q_cmp
		generic map (
			SYNC_RESET                => 0,
			PKT_DEST_ID_H             => 94,
			PKT_DEST_ID_L             => 91,
			PKT_SRC_ID_H              => 90,
			PKT_SRC_ID_L              => 87,
			PKT_BYTE_CNT_H            => 76,
			PKT_BYTE_CNT_L            => 74,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_TRANS_POSTED          => 69,
			PKT_TRANS_WRITE           => 70,
			MAX_OUTSTANDING_RESPONSES => 2,
			PIPELINED                 => 0,
			ST_DATA_W                 => 117,
			ST_CHANNEL_W              => 12,
			VALID_WIDTH               => 12,
			ENFORCE_ORDER             => 1,
			PREVENT_HAZARDS           => 0,
			SUPPORTS_POSTED_WRITES    => 1,
			SUPPORTS_NONPOSTED_WRITES => 0,
			REORDER                   => 0
		)
		port map (
			clk                    => csr_clk_clk_clk,                                                --       clk.clk
			reset                  => master_reset_reset_bridge_in_reset_reset,                       -- clk_reset.reset
			cmd_sink_ready         => router_src_ready,                                               --  cmd_sink.ready
			cmd_sink_valid         => router_src_valid,                                               --          .valid
			cmd_sink_data          => router_src_data,                                                --          .data
			cmd_sink_channel       => router_src_channel,                                             --          .channel
			cmd_sink_startofpacket => router_src_startofpacket,                                       --          .startofpacket
			cmd_sink_endofpacket   => router_src_endofpacket,                                         --          .endofpacket
			cmd_src_ready          => master_avalon_universal_master_0_limiter_cmd_src_ready,         --   cmd_src.ready
			cmd_src_data           => master_avalon_universal_master_0_limiter_cmd_src_data,          --          .data
			cmd_src_channel        => master_avalon_universal_master_0_limiter_cmd_src_channel,       --          .channel
			cmd_src_startofpacket  => master_avalon_universal_master_0_limiter_cmd_src_startofpacket, --          .startofpacket
			cmd_src_endofpacket    => master_avalon_universal_master_0_limiter_cmd_src_endofpacket,   --          .endofpacket
			rsp_sink_ready         => rsp_mux_src_ready,                                              --  rsp_sink.ready
			rsp_sink_valid         => rsp_mux_src_valid,                                              --          .valid
			rsp_sink_channel       => rsp_mux_src_channel,                                            --          .channel
			rsp_sink_data          => rsp_mux_src_data,                                               --          .data
			rsp_sink_startofpacket => rsp_mux_src_startofpacket,                                      --          .startofpacket
			rsp_sink_endofpacket   => rsp_mux_src_endofpacket,                                        --          .endofpacket
			rsp_src_ready          => master_avalon_universal_master_0_limiter_rsp_src_ready,         --   rsp_src.ready
			rsp_src_valid          => master_avalon_universal_master_0_limiter_rsp_src_valid,         --          .valid
			rsp_src_data           => master_avalon_universal_master_0_limiter_rsp_src_data,          --          .data
			rsp_src_channel        => master_avalon_universal_master_0_limiter_rsp_src_channel,       --          .channel
			rsp_src_startofpacket  => master_avalon_universal_master_0_limiter_rsp_src_startofpacket, --          .startofpacket
			rsp_src_endofpacket    => master_avalon_universal_master_0_limiter_rsp_src_endofpacket,   --          .endofpacket
			cmd_src_valid          => master_avalon_universal_master_0_limiter_cmd_valid_data         -- cmd_valid.data
		);

	cmd_demux : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_vs5t6hy_cmp
		port map (
			clk                 => csr_clk_clk_clk,                                                --        clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset,                       --  clk_reset.reset
			sink_ready          => master_avalon_universal_master_0_limiter_cmd_src_ready,         --       sink.ready
			sink_channel        => master_avalon_universal_master_0_limiter_cmd_src_channel,       --           .channel
			sink_data           => master_avalon_universal_master_0_limiter_cmd_src_data,          --           .data
			sink_startofpacket  => master_avalon_universal_master_0_limiter_cmd_src_startofpacket, --           .startofpacket
			sink_endofpacket    => master_avalon_universal_master_0_limiter_cmd_src_endofpacket,   --           .endofpacket
			sink_valid          => master_avalon_universal_master_0_limiter_cmd_valid_data,        -- sink_valid.data
			src0_ready          => cmd_demux_src0_ready,                                           --       src0.ready
			src0_valid          => cmd_demux_src0_valid,                                           --           .valid
			src0_data           => cmd_demux_src0_data,                                            --           .data
			src0_channel        => cmd_demux_src0_channel,                                         --           .channel
			src0_startofpacket  => cmd_demux_src0_startofpacket,                                   --           .startofpacket
			src0_endofpacket    => cmd_demux_src0_endofpacket,                                     --           .endofpacket
			src1_ready          => cmd_demux_src1_ready,                                           --       src1.ready
			src1_valid          => cmd_demux_src1_valid,                                           --           .valid
			src1_data           => cmd_demux_src1_data,                                            --           .data
			src1_channel        => cmd_demux_src1_channel,                                         --           .channel
			src1_startofpacket  => cmd_demux_src1_startofpacket,                                   --           .startofpacket
			src1_endofpacket    => cmd_demux_src1_endofpacket,                                     --           .endofpacket
			src2_ready          => cmd_demux_src2_ready,                                           --       src2.ready
			src2_valid          => cmd_demux_src2_valid,                                           --           .valid
			src2_data           => cmd_demux_src2_data,                                            --           .data
			src2_channel        => cmd_demux_src2_channel,                                         --           .channel
			src2_startofpacket  => cmd_demux_src2_startofpacket,                                   --           .startofpacket
			src2_endofpacket    => cmd_demux_src2_endofpacket,                                     --           .endofpacket
			src3_ready          => cmd_demux_src3_ready,                                           --       src3.ready
			src3_valid          => cmd_demux_src3_valid,                                           --           .valid
			src3_data           => cmd_demux_src3_data,                                            --           .data
			src3_channel        => cmd_demux_src3_channel,                                         --           .channel
			src3_startofpacket  => cmd_demux_src3_startofpacket,                                   --           .startofpacket
			src3_endofpacket    => cmd_demux_src3_endofpacket,                                     --           .endofpacket
			src4_ready          => cmd_demux_src4_ready,                                           --       src4.ready
			src4_valid          => cmd_demux_src4_valid,                                           --           .valid
			src4_data           => cmd_demux_src4_data,                                            --           .data
			src4_channel        => cmd_demux_src4_channel,                                         --           .channel
			src4_startofpacket  => cmd_demux_src4_startofpacket,                                   --           .startofpacket
			src4_endofpacket    => cmd_demux_src4_endofpacket,                                     --           .endofpacket
			src5_ready          => cmd_demux_src5_ready,                                           --       src5.ready
			src5_valid          => cmd_demux_src5_valid,                                           --           .valid
			src5_data           => cmd_demux_src5_data,                                            --           .data
			src5_channel        => cmd_demux_src5_channel,                                         --           .channel
			src5_startofpacket  => cmd_demux_src5_startofpacket,                                   --           .startofpacket
			src5_endofpacket    => cmd_demux_src5_endofpacket,                                     --           .endofpacket
			src6_ready          => cmd_demux_src6_ready,                                           --       src6.ready
			src6_valid          => cmd_demux_src6_valid,                                           --           .valid
			src6_data           => cmd_demux_src6_data,                                            --           .data
			src6_channel        => cmd_demux_src6_channel,                                         --           .channel
			src6_startofpacket  => cmd_demux_src6_startofpacket,                                   --           .startofpacket
			src6_endofpacket    => cmd_demux_src6_endofpacket,                                     --           .endofpacket
			src7_ready          => cmd_demux_src7_ready,                                           --       src7.ready
			src7_valid          => cmd_demux_src7_valid,                                           --           .valid
			src7_data           => cmd_demux_src7_data,                                            --           .data
			src7_channel        => cmd_demux_src7_channel,                                         --           .channel
			src7_startofpacket  => cmd_demux_src7_startofpacket,                                   --           .startofpacket
			src7_endofpacket    => cmd_demux_src7_endofpacket,                                     --           .endofpacket
			src8_ready          => cmd_demux_src8_ready,                                           --       src8.ready
			src8_valid          => cmd_demux_src8_valid,                                           --           .valid
			src8_data           => cmd_demux_src8_data,                                            --           .data
			src8_channel        => cmd_demux_src8_channel,                                         --           .channel
			src8_startofpacket  => cmd_demux_src8_startofpacket,                                   --           .startofpacket
			src8_endofpacket    => cmd_demux_src8_endofpacket,                                     --           .endofpacket
			src9_ready          => cmd_demux_src9_ready,                                           --       src9.ready
			src9_valid          => cmd_demux_src9_valid,                                           --           .valid
			src9_data           => cmd_demux_src9_data,                                            --           .data
			src9_channel        => cmd_demux_src9_channel,                                         --           .channel
			src9_startofpacket  => cmd_demux_src9_startofpacket,                                   --           .startofpacket
			src9_endofpacket    => cmd_demux_src9_endofpacket,                                     --           .endofpacket
			src10_ready         => cmd_demux_src10_ready,                                          --      src10.ready
			src10_valid         => cmd_demux_src10_valid,                                          --           .valid
			src10_data          => cmd_demux_src10_data,                                           --           .data
			src10_channel       => cmd_demux_src10_channel,                                        --           .channel
			src10_startofpacket => cmd_demux_src10_startofpacket,                                  --           .startofpacket
			src10_endofpacket   => cmd_demux_src10_endofpacket,                                    --           .endofpacket
			src11_ready         => cmd_demux_src11_ready,                                          --      src11.ready
			src11_valid         => cmd_demux_src11_valid,                                          --           .valid
			src11_data          => cmd_demux_src11_data,                                           --           .data
			src11_channel       => cmd_demux_src11_channel,                                        --           .channel
			src11_startofpacket => cmd_demux_src11_startofpacket,                                  --           .startofpacket
			src11_endofpacket   => cmd_demux_src11_endofpacket                                     --           .endofpacket
		);

	cmd_mux : component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		port map (
			clk                 => csr_clk_clk_clk,                          --       clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_src_ready,                        --       src.ready
			src_valid           => cmd_mux_src_valid,                        --          .valid
			src_data            => cmd_mux_src_data,                         --          .data
			src_channel         => cmd_mux_src_channel,                      --          .channel
			src_startofpacket   => cmd_mux_src_startofpacket,                --          .startofpacket
			src_endofpacket     => cmd_mux_src_endofpacket,                  --          .endofpacket
			sink0_ready         => cmd_demux_src0_ready,                     --     sink0.ready
			sink0_valid         => cmd_demux_src0_valid,                     --          .valid
			sink0_channel       => cmd_demux_src0_channel,                   --          .channel
			sink0_data          => cmd_demux_src0_data,                      --          .data
			sink0_startofpacket => cmd_demux_src0_startofpacket,             --          .startofpacket
			sink0_endofpacket   => cmd_demux_src0_endofpacket                --          .endofpacket
		);

	cmd_mux_001 : component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		port map (
			clk                 => csr_clk_clk_clk,                          --       clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_001_src_ready,                    --       src.ready
			src_valid           => cmd_mux_001_src_valid,                    --          .valid
			src_data            => cmd_mux_001_src_data,                     --          .data
			src_channel         => cmd_mux_001_src_channel,                  --          .channel
			src_startofpacket   => cmd_mux_001_src_startofpacket,            --          .startofpacket
			src_endofpacket     => cmd_mux_001_src_endofpacket,              --          .endofpacket
			sink0_ready         => cmd_demux_src1_ready,                     --     sink0.ready
			sink0_valid         => cmd_demux_src1_valid,                     --          .valid
			sink0_channel       => cmd_demux_src1_channel,                   --          .channel
			sink0_data          => cmd_demux_src1_data,                      --          .data
			sink0_startofpacket => cmd_demux_src1_startofpacket,             --          .startofpacket
			sink0_endofpacket   => cmd_demux_src1_endofpacket                --          .endofpacket
		);

	cmd_mux_002 : component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		port map (
			clk                 => csr_clk_clk_clk,                          --       clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_002_src_ready,                    --       src.ready
			src_valid           => cmd_mux_002_src_valid,                    --          .valid
			src_data            => cmd_mux_002_src_data,                     --          .data
			src_channel         => cmd_mux_002_src_channel,                  --          .channel
			src_startofpacket   => cmd_mux_002_src_startofpacket,            --          .startofpacket
			src_endofpacket     => cmd_mux_002_src_endofpacket,              --          .endofpacket
			sink0_ready         => cmd_demux_src2_ready,                     --     sink0.ready
			sink0_valid         => cmd_demux_src2_valid,                     --          .valid
			sink0_channel       => cmd_demux_src2_channel,                   --          .channel
			sink0_data          => cmd_demux_src2_data,                      --          .data
			sink0_startofpacket => cmd_demux_src2_startofpacket,             --          .startofpacket
			sink0_endofpacket   => cmd_demux_src2_endofpacket                --          .endofpacket
		);

	cmd_mux_003 : component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		port map (
			clk                 => csr_clk_clk_clk,                          --       clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_003_src_ready,                    --       src.ready
			src_valid           => cmd_mux_003_src_valid,                    --          .valid
			src_data            => cmd_mux_003_src_data,                     --          .data
			src_channel         => cmd_mux_003_src_channel,                  --          .channel
			src_startofpacket   => cmd_mux_003_src_startofpacket,            --          .startofpacket
			src_endofpacket     => cmd_mux_003_src_endofpacket,              --          .endofpacket
			sink0_ready         => cmd_demux_src3_ready,                     --     sink0.ready
			sink0_valid         => cmd_demux_src3_valid,                     --          .valid
			sink0_channel       => cmd_demux_src3_channel,                   --          .channel
			sink0_data          => cmd_demux_src3_data,                      --          .data
			sink0_startofpacket => cmd_demux_src3_startofpacket,             --          .startofpacket
			sink0_endofpacket   => cmd_demux_src3_endofpacket                --          .endofpacket
		);

	cmd_mux_004 : component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		port map (
			clk                 => csr_clk_clk_clk,                          --       clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_004_src_ready,                    --       src.ready
			src_valid           => cmd_mux_004_src_valid,                    --          .valid
			src_data            => cmd_mux_004_src_data,                     --          .data
			src_channel         => cmd_mux_004_src_channel,                  --          .channel
			src_startofpacket   => cmd_mux_004_src_startofpacket,            --          .startofpacket
			src_endofpacket     => cmd_mux_004_src_endofpacket,              --          .endofpacket
			sink0_ready         => cmd_demux_src4_ready,                     --     sink0.ready
			sink0_valid         => cmd_demux_src4_valid,                     --          .valid
			sink0_channel       => cmd_demux_src4_channel,                   --          .channel
			sink0_data          => cmd_demux_src4_data,                      --          .data
			sink0_startofpacket => cmd_demux_src4_startofpacket,             --          .startofpacket
			sink0_endofpacket   => cmd_demux_src4_endofpacket                --          .endofpacket
		);

	cmd_mux_005 : component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		port map (
			clk                 => csr_clk_clk_clk,                          --       clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_005_src_ready,                    --       src.ready
			src_valid           => cmd_mux_005_src_valid,                    --          .valid
			src_data            => cmd_mux_005_src_data,                     --          .data
			src_channel         => cmd_mux_005_src_channel,                  --          .channel
			src_startofpacket   => cmd_mux_005_src_startofpacket,            --          .startofpacket
			src_endofpacket     => cmd_mux_005_src_endofpacket,              --          .endofpacket
			sink0_ready         => cmd_demux_src5_ready,                     --     sink0.ready
			sink0_valid         => cmd_demux_src5_valid,                     --          .valid
			sink0_channel       => cmd_demux_src5_channel,                   --          .channel
			sink0_data          => cmd_demux_src5_data,                      --          .data
			sink0_startofpacket => cmd_demux_src5_startofpacket,             --          .startofpacket
			sink0_endofpacket   => cmd_demux_src5_endofpacket                --          .endofpacket
		);

	cmd_mux_006 : component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		port map (
			clk                 => csr_clk_clk_clk,                          --       clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_006_src_ready,                    --       src.ready
			src_valid           => cmd_mux_006_src_valid,                    --          .valid
			src_data            => cmd_mux_006_src_data,                     --          .data
			src_channel         => cmd_mux_006_src_channel,                  --          .channel
			src_startofpacket   => cmd_mux_006_src_startofpacket,            --          .startofpacket
			src_endofpacket     => cmd_mux_006_src_endofpacket,              --          .endofpacket
			sink0_ready         => cmd_demux_src6_ready,                     --     sink0.ready
			sink0_valid         => cmd_demux_src6_valid,                     --          .valid
			sink0_channel       => cmd_demux_src6_channel,                   --          .channel
			sink0_data          => cmd_demux_src6_data,                      --          .data
			sink0_startofpacket => cmd_demux_src6_startofpacket,             --          .startofpacket
			sink0_endofpacket   => cmd_demux_src6_endofpacket                --          .endofpacket
		);

	cmd_mux_007 : component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		port map (
			clk                 => csr_clk_clk_clk,                          --       clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_007_src_ready,                    --       src.ready
			src_valid           => cmd_mux_007_src_valid,                    --          .valid
			src_data            => cmd_mux_007_src_data,                     --          .data
			src_channel         => cmd_mux_007_src_channel,                  --          .channel
			src_startofpacket   => cmd_mux_007_src_startofpacket,            --          .startofpacket
			src_endofpacket     => cmd_mux_007_src_endofpacket,              --          .endofpacket
			sink0_ready         => cmd_demux_src7_ready,                     --     sink0.ready
			sink0_valid         => cmd_demux_src7_valid,                     --          .valid
			sink0_channel       => cmd_demux_src7_channel,                   --          .channel
			sink0_data          => cmd_demux_src7_data,                      --          .data
			sink0_startofpacket => cmd_demux_src7_startofpacket,             --          .startofpacket
			sink0_endofpacket   => cmd_demux_src7_endofpacket                --          .endofpacket
		);

	cmd_mux_008 : component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		port map (
			clk                 => csr_clk_clk_clk,                          --       clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_008_src_ready,                    --       src.ready
			src_valid           => cmd_mux_008_src_valid,                    --          .valid
			src_data            => cmd_mux_008_src_data,                     --          .data
			src_channel         => cmd_mux_008_src_channel,                  --          .channel
			src_startofpacket   => cmd_mux_008_src_startofpacket,            --          .startofpacket
			src_endofpacket     => cmd_mux_008_src_endofpacket,              --          .endofpacket
			sink0_ready         => cmd_demux_src8_ready,                     --     sink0.ready
			sink0_valid         => cmd_demux_src8_valid,                     --          .valid
			sink0_channel       => cmd_demux_src8_channel,                   --          .channel
			sink0_data          => cmd_demux_src8_data,                      --          .data
			sink0_startofpacket => cmd_demux_src8_startofpacket,             --          .startofpacket
			sink0_endofpacket   => cmd_demux_src8_endofpacket                --          .endofpacket
		);

	cmd_mux_009 : component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		port map (
			clk                 => csr_clk_clk_clk,                          --       clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_009_src_ready,                    --       src.ready
			src_valid           => cmd_mux_009_src_valid,                    --          .valid
			src_data            => cmd_mux_009_src_data,                     --          .data
			src_channel         => cmd_mux_009_src_channel,                  --          .channel
			src_startofpacket   => cmd_mux_009_src_startofpacket,            --          .startofpacket
			src_endofpacket     => cmd_mux_009_src_endofpacket,              --          .endofpacket
			sink0_ready         => cmd_demux_src9_ready,                     --     sink0.ready
			sink0_valid         => cmd_demux_src9_valid,                     --          .valid
			sink0_channel       => cmd_demux_src9_channel,                   --          .channel
			sink0_data          => cmd_demux_src9_data,                      --          .data
			sink0_startofpacket => cmd_demux_src9_startofpacket,             --          .startofpacket
			sink0_endofpacket   => cmd_demux_src9_endofpacket                --          .endofpacket
		);

	cmd_mux_010 : component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		port map (
			clk                 => csr_clk_clk_clk,                          --       clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_010_src_ready,                    --       src.ready
			src_valid           => cmd_mux_010_src_valid,                    --          .valid
			src_data            => cmd_mux_010_src_data,                     --          .data
			src_channel         => cmd_mux_010_src_channel,                  --          .channel
			src_startofpacket   => cmd_mux_010_src_startofpacket,            --          .startofpacket
			src_endofpacket     => cmd_mux_010_src_endofpacket,              --          .endofpacket
			sink0_ready         => cmd_demux_src10_ready,                    --     sink0.ready
			sink0_valid         => cmd_demux_src10_valid,                    --          .valid
			sink0_channel       => cmd_demux_src10_channel,                  --          .channel
			sink0_data          => cmd_demux_src10_data,                     --          .data
			sink0_startofpacket => cmd_demux_src10_startofpacket,            --          .startofpacket
			sink0_endofpacket   => cmd_demux_src10_endofpacket               --          .endofpacket
		);

	cmd_mux_011 : component address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q_cmp
		port map (
			clk                 => csr_clk_clk_clk,                          --       clk.clk
			reset               => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_011_src_ready,                    --       src.ready
			src_valid           => cmd_mux_011_src_valid,                    --          .valid
			src_data            => cmd_mux_011_src_data,                     --          .data
			src_channel         => cmd_mux_011_src_channel,                  --          .channel
			src_startofpacket   => cmd_mux_011_src_startofpacket,            --          .startofpacket
			src_endofpacket     => cmd_mux_011_src_endofpacket,              --          .endofpacket
			sink0_ready         => cmd_demux_src11_ready,                    --     sink0.ready
			sink0_valid         => cmd_demux_src11_valid,                    --          .valid
			sink0_channel       => cmd_demux_src11_channel,                  --          .channel
			sink0_data          => cmd_demux_src11_data,                     --          .data
			sink0_startofpacket => cmd_demux_src11_startofpacket,            --          .startofpacket
			sink0_endofpacket   => cmd_demux_src11_endofpacket               --          .endofpacket
		);

	rsp_demux : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		port map (
			clk                => csr_clk_clk_clk,                          --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_001_src_ready,                     --      sink.ready
			sink_channel       => router_001_src_channel,                   --          .channel
			sink_data          => router_001_src_data,                      --          .data
			sink_startofpacket => router_001_src_startofpacket,             --          .startofpacket
			sink_endofpacket   => router_001_src_endofpacket,               --          .endofpacket
			sink_valid(0)      => router_001_src_valid,                     --          .valid
			src0_ready         => rsp_demux_src0_ready,                     --      src0.ready
			src0_valid         => rsp_demux_src0_valid,                     --          .valid
			src0_data          => rsp_demux_src0_data,                      --          .data
			src0_channel       => rsp_demux_src0_channel,                   --          .channel
			src0_startofpacket => rsp_demux_src0_startofpacket,             --          .startofpacket
			src0_endofpacket   => rsp_demux_src0_endofpacket                --          .endofpacket
		);

	rsp_demux_001 : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		port map (
			clk                => csr_clk_clk_clk,                          --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_002_src_ready,                     --      sink.ready
			sink_channel       => router_002_src_channel,                   --          .channel
			sink_data          => router_002_src_data,                      --          .data
			sink_startofpacket => router_002_src_startofpacket,             --          .startofpacket
			sink_endofpacket   => router_002_src_endofpacket,               --          .endofpacket
			sink_valid(0)      => router_002_src_valid,                     --          .valid
			src0_ready         => rsp_demux_001_src0_ready,                 --      src0.ready
			src0_valid         => rsp_demux_001_src0_valid,                 --          .valid
			src0_data          => rsp_demux_001_src0_data,                  --          .data
			src0_channel       => rsp_demux_001_src0_channel,               --          .channel
			src0_startofpacket => rsp_demux_001_src0_startofpacket,         --          .startofpacket
			src0_endofpacket   => rsp_demux_001_src0_endofpacket            --          .endofpacket
		);

	rsp_demux_002 : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		port map (
			clk                => csr_clk_clk_clk,                          --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_003_src_ready,                     --      sink.ready
			sink_channel       => router_003_src_channel,                   --          .channel
			sink_data          => router_003_src_data,                      --          .data
			sink_startofpacket => router_003_src_startofpacket,             --          .startofpacket
			sink_endofpacket   => router_003_src_endofpacket,               --          .endofpacket
			sink_valid(0)      => router_003_src_valid,                     --          .valid
			src0_ready         => rsp_demux_002_src0_ready,                 --      src0.ready
			src0_valid         => rsp_demux_002_src0_valid,                 --          .valid
			src0_data          => rsp_demux_002_src0_data,                  --          .data
			src0_channel       => rsp_demux_002_src0_channel,               --          .channel
			src0_startofpacket => rsp_demux_002_src0_startofpacket,         --          .startofpacket
			src0_endofpacket   => rsp_demux_002_src0_endofpacket            --          .endofpacket
		);

	rsp_demux_003 : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		port map (
			clk                => csr_clk_clk_clk,                          --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_004_src_ready,                     --      sink.ready
			sink_channel       => router_004_src_channel,                   --          .channel
			sink_data          => router_004_src_data,                      --          .data
			sink_startofpacket => router_004_src_startofpacket,             --          .startofpacket
			sink_endofpacket   => router_004_src_endofpacket,               --          .endofpacket
			sink_valid(0)      => router_004_src_valid,                     --          .valid
			src0_ready         => rsp_demux_003_src0_ready,                 --      src0.ready
			src0_valid         => rsp_demux_003_src0_valid,                 --          .valid
			src0_data          => rsp_demux_003_src0_data,                  --          .data
			src0_channel       => rsp_demux_003_src0_channel,               --          .channel
			src0_startofpacket => rsp_demux_003_src0_startofpacket,         --          .startofpacket
			src0_endofpacket   => rsp_demux_003_src0_endofpacket            --          .endofpacket
		);

	rsp_demux_004 : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		port map (
			clk                => csr_clk_clk_clk,                          --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_005_src_ready,                     --      sink.ready
			sink_channel       => router_005_src_channel,                   --          .channel
			sink_data          => router_005_src_data,                      --          .data
			sink_startofpacket => router_005_src_startofpacket,             --          .startofpacket
			sink_endofpacket   => router_005_src_endofpacket,               --          .endofpacket
			sink_valid(0)      => router_005_src_valid,                     --          .valid
			src0_ready         => rsp_demux_004_src0_ready,                 --      src0.ready
			src0_valid         => rsp_demux_004_src0_valid,                 --          .valid
			src0_data          => rsp_demux_004_src0_data,                  --          .data
			src0_channel       => rsp_demux_004_src0_channel,               --          .channel
			src0_startofpacket => rsp_demux_004_src0_startofpacket,         --          .startofpacket
			src0_endofpacket   => rsp_demux_004_src0_endofpacket            --          .endofpacket
		);

	rsp_demux_005 : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		port map (
			clk                => csr_clk_clk_clk,                          --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_006_src_ready,                     --      sink.ready
			sink_channel       => router_006_src_channel,                   --          .channel
			sink_data          => router_006_src_data,                      --          .data
			sink_startofpacket => router_006_src_startofpacket,             --          .startofpacket
			sink_endofpacket   => router_006_src_endofpacket,               --          .endofpacket
			sink_valid(0)      => router_006_src_valid,                     --          .valid
			src0_ready         => rsp_demux_005_src0_ready,                 --      src0.ready
			src0_valid         => rsp_demux_005_src0_valid,                 --          .valid
			src0_data          => rsp_demux_005_src0_data,                  --          .data
			src0_channel       => rsp_demux_005_src0_channel,               --          .channel
			src0_startofpacket => rsp_demux_005_src0_startofpacket,         --          .startofpacket
			src0_endofpacket   => rsp_demux_005_src0_endofpacket            --          .endofpacket
		);

	rsp_demux_006 : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		port map (
			clk                => csr_clk_clk_clk,                          --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_007_src_ready,                     --      sink.ready
			sink_channel       => router_007_src_channel,                   --          .channel
			sink_data          => router_007_src_data,                      --          .data
			sink_startofpacket => router_007_src_startofpacket,             --          .startofpacket
			sink_endofpacket   => router_007_src_endofpacket,               --          .endofpacket
			sink_valid(0)      => router_007_src_valid,                     --          .valid
			src0_ready         => rsp_demux_006_src0_ready,                 --      src0.ready
			src0_valid         => rsp_demux_006_src0_valid,                 --          .valid
			src0_data          => rsp_demux_006_src0_data,                  --          .data
			src0_channel       => rsp_demux_006_src0_channel,               --          .channel
			src0_startofpacket => rsp_demux_006_src0_startofpacket,         --          .startofpacket
			src0_endofpacket   => rsp_demux_006_src0_endofpacket            --          .endofpacket
		);

	rsp_demux_007 : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		port map (
			clk                => csr_clk_clk_clk,                          --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_008_src_ready,                     --      sink.ready
			sink_channel       => router_008_src_channel,                   --          .channel
			sink_data          => router_008_src_data,                      --          .data
			sink_startofpacket => router_008_src_startofpacket,             --          .startofpacket
			sink_endofpacket   => router_008_src_endofpacket,               --          .endofpacket
			sink_valid(0)      => router_008_src_valid,                     --          .valid
			src0_ready         => rsp_demux_007_src0_ready,                 --      src0.ready
			src0_valid         => rsp_demux_007_src0_valid,                 --          .valid
			src0_data          => rsp_demux_007_src0_data,                  --          .data
			src0_channel       => rsp_demux_007_src0_channel,               --          .channel
			src0_startofpacket => rsp_demux_007_src0_startofpacket,         --          .startofpacket
			src0_endofpacket   => rsp_demux_007_src0_endofpacket            --          .endofpacket
		);

	rsp_demux_008 : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		port map (
			clk                => csr_clk_clk_clk,                          --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_009_src_ready,                     --      sink.ready
			sink_channel       => router_009_src_channel,                   --          .channel
			sink_data          => router_009_src_data,                      --          .data
			sink_startofpacket => router_009_src_startofpacket,             --          .startofpacket
			sink_endofpacket   => router_009_src_endofpacket,               --          .endofpacket
			sink_valid(0)      => router_009_src_valid,                     --          .valid
			src0_ready         => rsp_demux_008_src0_ready,                 --      src0.ready
			src0_valid         => rsp_demux_008_src0_valid,                 --          .valid
			src0_data          => rsp_demux_008_src0_data,                  --          .data
			src0_channel       => rsp_demux_008_src0_channel,               --          .channel
			src0_startofpacket => rsp_demux_008_src0_startofpacket,         --          .startofpacket
			src0_endofpacket   => rsp_demux_008_src0_endofpacket            --          .endofpacket
		);

	rsp_demux_009 : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		port map (
			clk                => csr_clk_clk_clk,                          --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_010_src_ready,                     --      sink.ready
			sink_channel       => router_010_src_channel,                   --          .channel
			sink_data          => router_010_src_data,                      --          .data
			sink_startofpacket => router_010_src_startofpacket,             --          .startofpacket
			sink_endofpacket   => router_010_src_endofpacket,               --          .endofpacket
			sink_valid(0)      => router_010_src_valid,                     --          .valid
			src0_ready         => rsp_demux_009_src0_ready,                 --      src0.ready
			src0_valid         => rsp_demux_009_src0_valid,                 --          .valid
			src0_data          => rsp_demux_009_src0_data,                  --          .data
			src0_channel       => rsp_demux_009_src0_channel,               --          .channel
			src0_startofpacket => rsp_demux_009_src0_startofpacket,         --          .startofpacket
			src0_endofpacket   => rsp_demux_009_src0_endofpacket            --          .endofpacket
		);

	rsp_demux_010 : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		port map (
			clk                => csr_clk_clk_clk,                          --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_011_src_ready,                     --      sink.ready
			sink_channel       => router_011_src_channel,                   --          .channel
			sink_data          => router_011_src_data,                      --          .data
			sink_startofpacket => router_011_src_startofpacket,             --          .startofpacket
			sink_endofpacket   => router_011_src_endofpacket,               --          .endofpacket
			sink_valid(0)      => router_011_src_valid,                     --          .valid
			src0_ready         => rsp_demux_010_src0_ready,                 --      src0.ready
			src0_valid         => rsp_demux_010_src0_valid,                 --          .valid
			src0_data          => rsp_demux_010_src0_data,                  --          .data
			src0_channel       => rsp_demux_010_src0_channel,               --          .channel
			src0_startofpacket => rsp_demux_010_src0_startofpacket,         --          .startofpacket
			src0_endofpacket   => rsp_demux_010_src0_endofpacket            --          .endofpacket
		);

	rsp_demux_011 : component address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi_cmp
		port map (
			clk                => csr_clk_clk_clk,                          --       clk.clk
			reset              => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_012_src_ready,                     --      sink.ready
			sink_channel       => router_012_src_channel,                   --          .channel
			sink_data          => router_012_src_data,                      --          .data
			sink_startofpacket => router_012_src_startofpacket,             --          .startofpacket
			sink_endofpacket   => router_012_src_endofpacket,               --          .endofpacket
			sink_valid(0)      => router_012_src_valid,                     --          .valid
			src0_ready         => rsp_demux_011_src0_ready,                 --      src0.ready
			src0_valid         => rsp_demux_011_src0_valid,                 --          .valid
			src0_data          => rsp_demux_011_src0_data,                  --          .data
			src0_channel       => rsp_demux_011_src0_channel,               --          .channel
			src0_startofpacket => rsp_demux_011_src0_startofpacket,         --          .startofpacket
			src0_endofpacket   => rsp_demux_011_src0_endofpacket            --          .endofpacket
		);

	rsp_mux : component address_decoder_multi_channel_altera_merlin_multiplexer_191_qznn4dq_cmp
		port map (
			clk                  => csr_clk_clk_clk,                          --       clk.clk
			reset                => master_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready            => rsp_mux_src_ready,                        --       src.ready
			src_valid            => rsp_mux_src_valid,                        --          .valid
			src_data             => rsp_mux_src_data,                         --          .data
			src_channel          => rsp_mux_src_channel,                      --          .channel
			src_startofpacket    => rsp_mux_src_startofpacket,                --          .startofpacket
			src_endofpacket      => rsp_mux_src_endofpacket,                  --          .endofpacket
			sink0_ready          => rsp_demux_src0_ready,                     --     sink0.ready
			sink0_valid          => rsp_demux_src0_valid,                     --          .valid
			sink0_channel        => rsp_demux_src0_channel,                   --          .channel
			sink0_data           => rsp_demux_src0_data,                      --          .data
			sink0_startofpacket  => rsp_demux_src0_startofpacket,             --          .startofpacket
			sink0_endofpacket    => rsp_demux_src0_endofpacket,               --          .endofpacket
			sink1_ready          => rsp_demux_001_src0_ready,                 --     sink1.ready
			sink1_valid          => rsp_demux_001_src0_valid,                 --          .valid
			sink1_channel        => rsp_demux_001_src0_channel,               --          .channel
			sink1_data           => rsp_demux_001_src0_data,                  --          .data
			sink1_startofpacket  => rsp_demux_001_src0_startofpacket,         --          .startofpacket
			sink1_endofpacket    => rsp_demux_001_src0_endofpacket,           --          .endofpacket
			sink2_ready          => rsp_demux_002_src0_ready,                 --     sink2.ready
			sink2_valid          => rsp_demux_002_src0_valid,                 --          .valid
			sink2_channel        => rsp_demux_002_src0_channel,               --          .channel
			sink2_data           => rsp_demux_002_src0_data,                  --          .data
			sink2_startofpacket  => rsp_demux_002_src0_startofpacket,         --          .startofpacket
			sink2_endofpacket    => rsp_demux_002_src0_endofpacket,           --          .endofpacket
			sink3_ready          => rsp_demux_003_src0_ready,                 --     sink3.ready
			sink3_valid          => rsp_demux_003_src0_valid,                 --          .valid
			sink3_channel        => rsp_demux_003_src0_channel,               --          .channel
			sink3_data           => rsp_demux_003_src0_data,                  --          .data
			sink3_startofpacket  => rsp_demux_003_src0_startofpacket,         --          .startofpacket
			sink3_endofpacket    => rsp_demux_003_src0_endofpacket,           --          .endofpacket
			sink4_ready          => rsp_demux_004_src0_ready,                 --     sink4.ready
			sink4_valid          => rsp_demux_004_src0_valid,                 --          .valid
			sink4_channel        => rsp_demux_004_src0_channel,               --          .channel
			sink4_data           => rsp_demux_004_src0_data,                  --          .data
			sink4_startofpacket  => rsp_demux_004_src0_startofpacket,         --          .startofpacket
			sink4_endofpacket    => rsp_demux_004_src0_endofpacket,           --          .endofpacket
			sink5_ready          => rsp_demux_005_src0_ready,                 --     sink5.ready
			sink5_valid          => rsp_demux_005_src0_valid,                 --          .valid
			sink5_channel        => rsp_demux_005_src0_channel,               --          .channel
			sink5_data           => rsp_demux_005_src0_data,                  --          .data
			sink5_startofpacket  => rsp_demux_005_src0_startofpacket,         --          .startofpacket
			sink5_endofpacket    => rsp_demux_005_src0_endofpacket,           --          .endofpacket
			sink6_ready          => rsp_demux_006_src0_ready,                 --     sink6.ready
			sink6_valid          => rsp_demux_006_src0_valid,                 --          .valid
			sink6_channel        => rsp_demux_006_src0_channel,               --          .channel
			sink6_data           => rsp_demux_006_src0_data,                  --          .data
			sink6_startofpacket  => rsp_demux_006_src0_startofpacket,         --          .startofpacket
			sink6_endofpacket    => rsp_demux_006_src0_endofpacket,           --          .endofpacket
			sink7_ready          => rsp_demux_007_src0_ready,                 --     sink7.ready
			sink7_valid          => rsp_demux_007_src0_valid,                 --          .valid
			sink7_channel        => rsp_demux_007_src0_channel,               --          .channel
			sink7_data           => rsp_demux_007_src0_data,                  --          .data
			sink7_startofpacket  => rsp_demux_007_src0_startofpacket,         --          .startofpacket
			sink7_endofpacket    => rsp_demux_007_src0_endofpacket,           --          .endofpacket
			sink8_ready          => rsp_demux_008_src0_ready,                 --     sink8.ready
			sink8_valid          => rsp_demux_008_src0_valid,                 --          .valid
			sink8_channel        => rsp_demux_008_src0_channel,               --          .channel
			sink8_data           => rsp_demux_008_src0_data,                  --          .data
			sink8_startofpacket  => rsp_demux_008_src0_startofpacket,         --          .startofpacket
			sink8_endofpacket    => rsp_demux_008_src0_endofpacket,           --          .endofpacket
			sink9_ready          => rsp_demux_009_src0_ready,                 --     sink9.ready
			sink9_valid          => rsp_demux_009_src0_valid,                 --          .valid
			sink9_channel        => rsp_demux_009_src0_channel,               --          .channel
			sink9_data           => rsp_demux_009_src0_data,                  --          .data
			sink9_startofpacket  => rsp_demux_009_src0_startofpacket,         --          .startofpacket
			sink9_endofpacket    => rsp_demux_009_src0_endofpacket,           --          .endofpacket
			sink10_ready         => rsp_demux_010_src0_ready,                 --    sink10.ready
			sink10_valid         => rsp_demux_010_src0_valid,                 --          .valid
			sink10_channel       => rsp_demux_010_src0_channel,               --          .channel
			sink10_data          => rsp_demux_010_src0_data,                  --          .data
			sink10_startofpacket => rsp_demux_010_src0_startofpacket,         --          .startofpacket
			sink10_endofpacket   => rsp_demux_010_src0_endofpacket,           --          .endofpacket
			sink11_ready         => rsp_demux_011_src0_ready,                 --    sink11.ready
			sink11_valid         => rsp_demux_011_src0_valid,                 --          .valid
			sink11_channel       => rsp_demux_011_src0_channel,               --          .channel
			sink11_data          => rsp_demux_011_src0_data,                  --          .data
			sink11_startofpacket => rsp_demux_011_src0_startofpacket,         --          .startofpacket
			sink11_endofpacket   => rsp_demux_011_src0_endofpacket            --          .endofpacket
		);

end architecture rtl; -- of address_decoder_multi_channel_altera_mm_interconnect_191_yxycpgi
