NAME,DISPLAY_NAME,ALLOWED_RANGES,DEFAULT_VALUE,DESCRIPTION
"rcfg_enable","Enable dynamic reconfiguration","{0 1}","0","Enables the dynamic reconfiguration interface."
"rcfg_jtag_enable","Enable Native PHY Debug Master Endpoint","{0 1}","0","When enabled, the PLL IP includes an embedded Native PHY Debug Master Endpoint that connects internally Avalon-MM slave interface. The Native PHY Debug Master Endpoint can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the "Share reconfiguration interface" option for configurations using more than 1 channel and may also require that a jtag_debug link be included in the system."
"rcfg_separate_avmm_busy","Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE","{0 1}","0","When enabled, the reconfig_waitrequest will not indicate the status of AVMM arbitration with PreSICE.  The AVMM arbitration status will be reflected in a soft status register bit.  This feature requires that the "Enable control and status registers" feature under "Optional Reconfiguration Logic" be enabled.  For more information, please refer to the User Guide."
"rcfg_enable_avmm_busy_port","Enable avmm_busy port","{0 1}","0","Enable the port for avmm_busy"
"set_capability_reg_enable","Enable capability registers","{0 1}","0","Enables capability registers, which provide high level information about the transceiver PLL's configuration"
"set_csr_soft_logic_enable","Enable control and status registers","{0 1}","0","Enables soft registers for reading status signals and writing control signals on the phy interface through the embedded debug. Available signals include pll_cal_busy, pll_locked and pll_powerdown.  For more details, please refer to the User Guide."
"rcfg_file_prefix","Configuration file prefix","","altera_xcvr_rcfg_10","Specifies the file prefix to use for generated configuration files when enabled. Each variant of the IP should use a unique prefix for configuration files."
"rcfg_files_as_common_package","Declare SystemVerilog package file as common package file","{0 1}","0","Declares the SystemVerilog reconfig file as common package."
"rcfg_sv_file_enable","Generate SystemVerilog package file","{0 1}","0","When enabled, The IP will generate a SystemVerilog package file named "(Configuration file prefix)_reconfig_parameters.sv" containing parameters defined with the attribute values needed for reconfiguration."
"rcfg_h_file_enable","Generate C header file","{0 1}","0","When enabled, The IP will generate a C header file named "(Configuration file prefix)_reconfig_parameters.h" containing macros defined with the attribute values needed for reconfiguration."
"rcfg_mif_file_enable","Generate MIF (Memory Initialize File)","{0 1}","0","When enabled The IP will generate an Altera MIF (Memory Initialization File) named "(Configuration file prefix)_reconfig_parameters.mif". The MIF file contains the attribute values needed for reconfiguration in a data format."
"rcfg_multi_enable","Enable multiple reconfiguration profiles","{0 1}","0","When enabled, you can use the GUI to store multiple configurations. The IP will generate reconfiguration files for all of the stored profiles. The IP will also check your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them."
"set_rcfg_emb_strm_enable","Enable embedded reconfiguration streamer","{0 1}","0","Enables the embedded reconfiguration streamer, which automates the dynamic reconfiguration process between multiple predefined configuration profiles."
"rcfg_reduced_files_enable","Generate reduced reconfiguration files","{0 1}","0","When enabled, The Native PHY generates reconfiguration report files containing only the attributes or RAM data that are different between the multiple configured profiles."
"rcfg_profile_cnt","Number of reconfiguration profiles","1 2 3 4 5 6 7 8","2","Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled."
"rcfg_profile_select","Store current configuration to profile:","0","1","Selects which reconfiguration profile to store when clicking the "Store profile" button."
"device_family","device_family","","Stratix 10",""
"device","device","","Unknown",""
"base_device","base_device","","Unknown",""
"device_die_types","device_die_types","","Unknown",""
"device_die_revisions","device_die_revisions","","Unknown",""
"design_environment","design_environment","","NATIVE",""
"message_level","Message level for rule violations","error warning","error","Specifies the messaging level to use for parameter rule violations. Selecting "error" causes all rule violations to prevent IP generation. Selecting "warning" displays all rule violations as warnings and allows IP generation in spite of violations."
"reduced_reset_sim_time","Use fast reset for simulation","{0 1}","0","When enabled, the IP disables reset staggering in simulation. The reset behavior in simulation will be different from the reset behavior in hardware."
"channel_type","Transceiver channel type","GX GXT","GX","Specifies the transceiver channel variant."
"protocol_mode","Transceiver configuration rules","{basic_std:Basic/Custom (Standard PCS)} {basic_std_rm:Basic/Custom w/Rate Match (Standard PCS)} {cpri:CPRI (Auto)} {cpri_rx_tx:CPRI (Manual)} gige:GbE {gige_1588:GbE 1588} {pipe_g1:Gen 1 PIPE} {pipe_g2:Gen 2 PIPE} {pipe_g3:Gen 3 PIPE} {basic_enh:Basic (Enhanced PCS)} interlaken_mode:Interlaken teng_baser_mode:10GBASE-R {teng_1588_mode:10GBASE-R 1588} {teng_baser_krfec_mode:10GBASE-R w/KR FEC} {fortyg_basekr_krfec_mode:40GBASE-R w/KR FEC} {basic_krfec_mode:Basic w/KR FEC} {pcs_direct:PCS Direct}","basic_std","Selects the protocol configuration rules for the transceiver. This parameter governs the rules for correct settings of individual parameters within the PMA and PCS. Certain features of the transceiver are available only for specific protocol configuration rules. This parameter is not a "preset". You must still correctly set all other parameters for your specific protocol and application needs."
"pma_mode","PMA configuration rules","basic SATA:SATA/SAS GPON","basic","Selects the configuration rules for PMA. Options are SATA/SAS, GPON and basic. Basic should be selected for all modes other than SATA/SAS and GPON. SATA/SAS mode can be used only if "Transceiver configuration rules" is selected as Standard PCS. GPON mode can be used only if "Transceiver configuration rules" is selected as Standard or Enhanced PCS. This parameter is not a "preset". You must still correctly set other parameters and enable relavant ports for your specific application needs."
"duplex_mode","Transceiver mode","{duplex:TX/RX Duplex} {tx:TX Simplex} {rx:RX Simplex}","duplex","Selects the transceiver operation mode."
"channels","Number of data channels","1:144","1","Specifies the total number of data channels."
"set_data_rate","Data rate","","1250","Specifies the transceiver data rate in units of Mbps (megabits per second)."
"rcfg_iface_enable","Enable datapath and interface reconfiguration","{0 1}","0","Enables the ability to preconfigure and dynamically switch between the Standard PCS, Enhanced PCS, and PCS direct transceiver datapaths."
"enable_simple_interface","Enable simplified data interface","{0 1}","0","When selected the Native PHY presents a simplified data and control interface between the FPGA and transceiver. When not selected the Native PHY presents the full raw data interface to the transceiver. You need to understand the mapping of data and control signals within the interface. This option cannot be enabled if you want to perform dynamic interface reconfiguration as only a fixed subset of the data and control signals are provided."
"enable_transparent_pcs","Enable transparent PCS","{0 1}","0",""
"enable_double_rate_transfer","Enable double rate transfer mode","{0 1}","0","Enables the double rate transfer mode for RX and TX. Double rate transfer mode can be used to run the FPGA fabric at double clock speed and at half parallel data width."
"enable_background_cal_gui","Enable background calibration","{0 1}","0","Enable calibration running at background to improve performance, recommended for GT design."
"set_enable_eios_rx_protect","Enable PIPE EIOS RX Protection","{0 1}","0","Enable PCIe EIOS protection feature to improve fault-tolerance and compatibilty, may be used in PIPE Gen2/3 mode."
"bonded_mode","TX channel bonding mode","{not_bonded:Not bonded} {pma_only:PMA only bonding} {pma_pcs:PMA and PCS bonding}","not_bonded","Specifies the transceiver TX channel bonding mode to control channel-to-channel skew for the TX datapath. Refer to the user guide for bonding details. Options are no TX channel bonding (non-bonded); PMA only channel bonding; or PMA & PCS channel bonding."
"pcs_reset_sequencing_mode","PCS reset sequence","not_bonded:Independent bonded:Simultaneous","not_bonded","Specifies the mode of PCS reset release sequence. When "Independent" mode is selected, resets to the PCS channels will be released in a staggered pattern and each reset is controlled by a different digital reset input. When "Simultaneous" mode is selected, resets to the PCS channels will be released simultaneously and all the channels share the same digital reset input. Select "Simultaneous" mode if "PMA & PCS channel bonding" is enabled or soft PCS bonding in the core is desired."
"enable_manual_bonding_settings","Enable manual PCS bonding settings","{0 1}","0","Enables the ability to manually configure the PCS bonding mode settings."
"tx_pma_clk_div","TX local clock division factor","1 2 4 8","1","Specifies the TX serial clock division factor. The transceiver has the ability to further divide the TX serial clock from the TX PLL before use. This parameter specifies the division factor to use. Example: A PLL data rate of "10000 Mbps" and a local division factor of 8 results in a channel data rate of "1250 Mbps""
"plls","Number of TX PLL clock inputs per channel","1 2 3 4","1","Specifies the desired number of TX PLL clock inputs per channel. This is used when you intend to dynamically switch between TX PLL clock sources. The Native PHY presents up to 4 clock inputs per channel to allow dynamically input clock switching."
"pll_select","Initial TX PLL clock input selection","0","0","Specifies the initially selected TX PLL clock input. This indicates the starting clock input selection used for this configuration when dynamically switching between multiple TX PLL clock inputs."
"enable_port_tx_pma_iqtxrx_clkout","Enable tx_pma_iqtxrx_clkout port","{0 1}","0","Enables the optional tx_pma_iqtxrx_clkout output clock. This clock can be used to cascade the TX PMA output clock to the input of a PLL."
"enable_port_tx_pma_elecidle","Enable tx_pma_elecidle port","{0 1}","0","Enables the optional tx_pma_elecidle control input port. The assertion of this signal forces the transmitter into an electrical idle condition. Note that this port has no effect when the transceiver is configured for PCI express modes."
"cdr_refclk_cnt","Number of CDR reference clocks","1 2 3 4 5","1","Specifies the number of input reference clocks for the RX CDRs. The same bus of reference clocks feeds all RX CDRs in the netlist."
"cdr_refclk_select","Selected CDR reference clock","0","0","Specifies the initially selected reference clock input to the RX CDRs."
"set_cdr_refclk_freq","Selected CDR reference clock frequency","40.600394 40.922619 41.250000 41.582661 41.920732 42.264344 42.613636 42.968750 43.329832 43.697034 44.070513 44.450431 44.836957 45.230263 45.630531 46.037946 46.452703 46.875000 47.305046 47.743056 48.189252 48.643868 49.107143 49.579327 50.060680 50.551471 51.051980 51.562500 52.083333 52.614796 53.157216 53.710938 54.276316 54.853723 55.443548 56.046196 56.662088 57.291667 57.935393 58.593750 59.267241 59.956395 60.661765 61.383929 62.123494 62.881098 63.657407 64.453125 65.268987 66.105769 66.964286 67.845395 68.750000 69.679054 70.633562 71.614583 72.623239 73.660714 74.728261 75.827206 76.958955 78.125000 79.326923 80.566406 81.200787 81.845238 82.500000 83.165323 83.841463 84.528689 85.227273 85.937500 86.659664 87.394068 88.141026 88.900862 89.673913 90.460526 91.261062 92.075893 92.905405 93.750000 94.610092 95.486111 96.378505 97.287736 98.214286 99.158654 100.121359 101.102941 102.103960 103.125000 104.166667 105.229592 106.314433 107.421875 108.552632 109.707447 110.887097 112.092391 113.324176 114.583333 115.870787 117.187500 118.534483 119.912791 121.323529 122.767857 124.246988 125.762195 127.314815 128.906250 130.537975 132.211538 133.928571 135.690789 137.500000 139.358108 141.267123 143.229167 145.246479 147.321429 149.456522 151.654412 153.917910 156.250000 158.653846 161.132813 162.401575 163.690476 165.000000 166.330645 167.682927 169.057377 170.454545 171.875000 173.319328 174.788136 176.282051 177.801724 179.347826 180.921053 182.522124 184.151786 185.810811 187.500000 189.220183 190.972222 192.757009 194.575472 196.428571 198.317308 200.242718 202.205882 204.207921 206.250000 208.333333 210.459184 212.628866 214.843750 217.105263 219.414894 221.774194 224.184783 226.648352 229.166667 231.741573 234.375000 237.068966 239.825581 242.647059 245.535714 248.493976 251.524390 254.629630 257.812500 261.075949 264.423077 267.857143 271.381579 275.000000 278.716216 282.534247 286.458333 290.492958 294.642857 298.913043 303.308824 307.835821 312.500000 317.307692 322.265625 324.803150 327.380952 330.000000 332.661290 335.365854 338.114754 340.909091 343.750000 346.638655 349.576271 352.564103 355.603448 358.695652 361.842105 365.044248 368.303571 371.621622 375.000000 378.440367 381.944444 385.514019 389.150943 392.857143 396.634615 400.485437 404.411765 408.415842 412.500000 416.666667 420.918367 425.257732 429.687500 434.210526 438.829787 443.548387 448.369565 453.296703 458.333333 463.483146 468.750000 474.137931 479.651163 485.294118 491.071429 496.987952 503.048780 509.259259 515.625000 522.151899 528.846154 535.714286 542.763158 550.000000 557.432432 565.068493 572.916667 580.985915 589.285714 597.826087 606.617647 615.671642 625.000000 634.615385 644.531250 654.761905 665.322581 676.229508 687.500000 699.152542 711.206897 723.684211 736.607143 750.000000 763.888889 778.301887 793.269231 644.53125","125.000","Specifies the frequency in MHz of the selected reference clock input to the CDR."
"rx_ppm_detect_threshold","PPM detector threshold","100 300 500 1000","1000","Specifies the tolerable difference in PPM (parts per million) between the RX CDR reference clock and the recovered clock from the RX data input."
"set_cdr_refclk_receiver_detect_src","set_cdr_refclk_receiver_detect_src","iqclk coreclk","iqclk",""
"enable_port_rx_pma_iqtxrx_clkout","Enable rx_pma_iqtxrx_clkout port","{0 1}","0","Enables the optional rx_pma_iqtxrx_clkout output clock. This clock can be used to cascade the RX PMA output clock to the input of a PLL."
"enable_port_rx_pma_clkslip","Enable rx_pma_clkslip port","{0 1}","0","Enables the optional rx_pma_clkslip control input port. A rising edge on this signal causes the RX serializer to slip the serial data by one clock cycle (2 UI)."
"enable_port_rx_is_lockedtodata","Enable rx_is_lockedtodata port","{0 1}","1","Enables the optional rx_is_lockedtodata status output port. This signal indicates that the RX CDR is currently in lock to data mode or is attempting to lock to the incoming data stream. This is an asynchronous output signal."
"enable_port_rx_is_lockedtoref","Enable rx_is_lockedtoref port","{0 1}","1","Enables the optional rx_is_lockedtoref status output port. This signal indicates that the RX CDR is currently locked to the CDR reference clock. This is an asynchronous output signal."
"enable_ports_rx_manual_cdr_mode","Enable rx_set_locktodata and rx_set_locktoref ports","{0 1}","0","Enables the optional rx_set_locktodata and rx_set_locktoref control input ports. These ports are used to manually control the lock mode of the RX CDR. These are asynchonous input signals."
"enable_ports_rx_prbs","Enable PRBS verifier control and status ports","{0 1}","0","Enables the optional rx_prbs_err, rx_prbs_err_clr, and rx_prbs_done ports. These ports are used to control and collect status from the internal PRBS verifier."
"enable_port_rx_seriallpbken","Enable rx_seriallpbken port","{0 1}","0","Enables the optional rx_seriallpbken control input port. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This is an asynchronous input signal. This signal can be enabled in Duplex or Simplex mode. If enabled in Simplex mode, you must drive the signal on both the TX and RX instances from the same source. Otherwise the design fails compilation."
"enh_pcs_pma_width","Enhanced PCS / PMA interface width","32 40 64","40","Specifies the data interface width between the Enhanced PCS and the transceiver PMA."
"enh_pld_pcs_width","FPGA fabric / Enhanced PCS interface width","32 40 50 64 66 67","40","Specifies the data interface width between the Enhanced PCS and the FPGA fabric."
"enh_low_latency_enable","Enable 'Enhanced PCS' low latency mode","{0 1}","0","Enables the low latency path for the 'Enhanced PCS'. Enabling this option bypasses the individual functional blocks within the 'Enhanced PCS' to provide the lowest latency datapath from the PMA through the 'Enhanced PCS'."
"enh_tx_frmgen_enable","Enable Interlaken frame generator","{0 1}","0","Enables the Interlaken frame generator in the Enhanced PCS."
"enh_tx_frmgen_mfrm_length","Frame generator metaframe length","0:8192","2048","Specifies the Interlaken metaframe length for the frame generator."
"enh_tx_frmgen_burst_enable","Enable frame generator burst control","{0 1}","0","Enables burst control in the Interlaken frame generator. When enabled, the "tx_enh_frame_burst_en" port controls the burst behavior of the frame generator. Refer to the user guide for more details."
"enable_port_tx_enh_frame","Enable tx_enh_frame port","{0 1}","0","Enables the tx_enh_frame status output port. When the Interlaken frame generator is enabled this signal indicates the beginning of a new metaframe."
"enable_port_tx_enh_frame_diag_status","Enable tx_enh_frame_diag_status port","{0 1}","0","Enables the tx_enh_frame_diag_status control input port. When the Interlaken frame generator is enabled the value of this signal contains the 'Status Message' from the framing layer 'Diagnostic Word'. Refer to the user guide for more details."
"enable_port_tx_enh_frame_burst_en","Enable tx_enh_frame_burst_en port","{0 1}","0","Enables the tx_enh_frame_burst_en control input port. When burst control is enabled for the Interlaken frame generator, the assertion of this signal controls frame generator data reads from the TX FIFO. Refer to the user guide for more details."
"enh_rx_frmsync_enable","Enable Interlaken frame synchronizer","{0 1}","0","Enables the Interlaken frame synchronizer in the Enhanced PCS."
"enh_rx_frmsync_mfrm_length","Frame synchronizer metaframe length","0:8192","2048","Specifies the Interlaken metaframe length for the frame synchronizer."
"enable_port_rx_enh_frame","Enable rx_enh_frame port","{0 1}","0","Enables the rx_enh_frame status output port. When the Interlaken frame synchronizer is enabled this signal indicates the beginning of a new metaframe."
"enable_port_rx_enh_frame_lock","Enable rx_enh_frame_lock port","{0 1}","0","Enables the rx_enh_frame_lock status output port. When the Interlaken frame synchronizer is enabled the assertion of this signal indicates that the frame synchronizer has acheived metaframe delineation. This is an asynchronous output signal."
"enable_port_rx_enh_frame_diag_status","Enable rx_enh_frame_diag_status port","{0 1}","0","Enables the rx_enh_frame_diag_status status output port. When the Interlaken frame synchronizer is enabled This two-bit per lane output signal contains the value of the framing layer diagnostic word (bits[33:32]). This signal is latched when a valid diagnostic word is received."
"enh_tx_crcgen_enable","Enable Interlaken TX CRC-32 generator","{0 1}","0","Enables the Interlaken CRC-32 generator. This can be used as a dignostic tool. The CRC includes the entire metaframe including the diagnostic word."
"enh_tx_crcerr_enable","Enable Interlaken TX CRC-32 generator error insertion","{0 1}","0","Enables error insertion for the Interlaken CRC-32 generator. Error insertion is cycle-accurate. When enabled, the assertion of tx_control[8] inserts an error on that corresponding data word."
"enh_rx_crcchk_enable","Enable Interlaken RX CRC-32 checker","{0 1}","0","Enables the Interlaken CRC-32 checker."
"enable_port_rx_enh_crc32_err","Enable rx_enh_crc32_err port","{0 1}","0","Enables the optional rx_enh_crc32_err status output port. When the Interlaken CRC-32 checker is enabled the assertion of this signal indicates the detection of a CRC error in the metaframe."
"enable_port_rx_enh_highber","Enable rx_enh_highber port (10GBASE-R)","{0 1}","0","Enables the optional rx_enh_highber status output port. In 10GBASE-R mode the assertion of this signal indicates a bit-error rate higher then 10^-4. For the 10GBASE-R specification this occurs when there are at least 16 errors within 125us."
"enable_port_rx_enh_highber_clr_cnt","Enable rx_enh_highber_clr_cnt port (10GBASE-R)","{0 1}","0","Enables the optional rx_enh_highber_clr_cnt control input port. In 10GBASE-R mode the assertion of this signal clears the internal counter for the number of times the BER state machine has entered the "BER_BAD_SH" state."
"enable_port_rx_enh_clr_errblk_count","Enable rx_enh_clr_errblk_count port (10GBASE-R & FEC)","{0 1}","0","Enables the optional rx_enh_clr_errblk_count control input port. In 10GBASE-R mode, the assertion of this signal clears the internal counter for the number of times the RX state machine has entered the "RX_E" state. In modes where the FEC block is enabled, the assertion of this signal resets the status counters within the RX FEC block."
"enh_tx_64b66b_enable","Enable TX 64b/66b encoder","{0 1}","0","Enables the 64b/66b encoder."
"enh_rx_64b66b_enable","Enable RX 64b/66b decoder","{0 1}","0","Enables the 64b/66b decoder."
"enh_tx_sh_err","Enable TX sync header error insertion","{0 1}","0","Enables 64b/66b sync header error insertion for 10GBASE-R or Interlaken."
"enh_tx_scram_enable","Enable TX scrambler (10GBASE-R/Interlaken)","{0 1}","0","Enables the TX data scrambler for 10GBASE-R and Interlaken. Refer to the user guide for further details."
"enh_tx_scram_seed","TX scrambler seed (10GBASE-R/Interlaken)","","0","Specifies the initial seed for the 10GBASE-R / Interlaken scrambler."
"enh_rx_descram_enable","Enable RX descrambler (10GBASE-R/Interlaken)","{0 1}","0","Enables the RX data descrambler for 10GBASE-R and Interlaken. Refer to the user guide for further details."
"enh_tx_dispgen_enable","Enable Interlaken TX disparity generator","{0 1}","0","Enables the Interlaken disparity generator."
"enh_rx_dispchk_enable","Enable Interlaken RX disparity checker","{0 1}","0","Enables the Interlaken disparity checker."
"enh_tx_randomdispbit_enable","Enable Interlaken TX random disparity bit","{0 1}","0","Enables the Interlaken random disparity bit. When enabled a random number is used as disparity bit which saves 1 cycle of latency."
"enh_rx_blksync_enable","Enable RX block synchronizer","{0 1}","0","Enables the block synchronizer for the 10G RX PCS. Primariliy used in Interlaken and 10GBASE-R modes."
"enable_port_rx_enh_blk_lock","Enable rx_enh_blk_lock port","{0 1}","0","Enables the optional enable_port_rx_enh_blk_lock status output port. When the block synchronizer is enabled the assertion of this signal indicates that block delineation has been achieved. This is an asynchronous output signal."
"enh_tx_bitslip_enable","Enable TX data bitslip","{0 1}","0","Enables TX bitslip support for the Enhanced TX PCS datapath. When enabled, the tx_enh_bitslip port controls the number of bit locations to slip the TX parallel data before passing to the PMA."
"enh_tx_polinv_enable","Enable TX data polarity inversion","{0 1}","0","Enables TX bit polarity inversion for the Enhanced TX PCS datapath. When enabled, the TX parallel data bits are inverted before passing to the PMA."
"enh_rx_bitslip_enable","Enable RX data bitslip","{0 1}","0","Enables RX bitslip support for the Enhanced RX PCS datapath. When enabled, the rising edge assertion of the rx_bitslip port causes the RX parallel data from the PMA to slip by one bit before passing to the PCS."
"enh_rx_polinv_enable","Enable RX data polarity inversion","{0 1}","0","Enables RX bit polarity inversion for the Enhanced RX PCS datapath. When enabled, the RX parallel data bits are inverted before passing from the PMA to the PCS."
"enable_port_tx_enh_bitslip","Enable tx_enh_bitslip port","{0 1}","0","Enables the optional tx_enh_bitslip control input port. When TX bitslip support is enabled for the 10G PCS the value of this signal controls the number bit locations to slip the TX parallel data before passing to the PMA."
"enable_port_rx_enh_bitslip","Enable rx_bitslip port","{0 1}","0","Enables the optional rx_bitslip control input port. When RX bitslip support is enabled for the 10G PCS; a rising edge on this signal causes the RX parallel data to be slipped by one bit location after passing from the PMA. This is the shared RX bitslip control port for the Standard and Enhanced PCS datapaths."
"enh_rx_krfec_err_mark_enable","Enable RX KR-FEC error marking","{0 1}","0","Enables the optional error marking feature of the KR-FEC decoder. When enabled, if an uncorrectable error is detected by the decoder, both sync data bits are asserted (2'b11) to indicate the uncorrectable error. This feature increases latency through the KR-FEC decoder."
"enh_rx_krfec_err_mark_type","Error marking type","10G 40G","10G","Specifies the error marking type (10G or 40G)."
"enh_tx_krfec_burst_err_enable","Enable KR-FEC TX error insertion","{0 1}","0","Enables the optional error insertion feature of the KR-FEC encoder. This feature allows the user to insert errors by corrupting the data starting at bit 0 of the current word."
"enh_tx_krfec_burst_err_len","KR-FEC TX error insertion spacing","1:15","1","Specifies the spacing of the KR-FEC TX error insertions. KR-FEC can insert 1-bit to 15-bit spaced errors."
"enable_port_krfec_tx_enh_frame","Enable tx_enh_frame port","{0 1}","0","Enables the tx_enh_frame status output port. Asynchronous status flag output of TX KRFEC that signifies the beginning of generated KRFEC frame."
"enable_port_krfec_rx_enh_frame","Enable rx_enh_frame port","{0 1}","0","Enables the rx_enh_frame status output port. Asynchronous status flag output of RX KRFEC that signifies the beginning of a received KRFEC frame."
"enable_port_krfec_rx_enh_frame_diag_status","Enable rx_enh_frame_diag_status port","{0 1}","0","Enables the rx_enh_frame_diag_status status output port. Asynchronous status flag output of RX KRFEC that indicates the status of the current received frame. 00: No error 01 Correctable error 10: Uncorrectable error 11: Reset condition/pre-lock condition."
"enable_debug_ports","Enable PCS reset status ports","{0 1}","0","Enables the optional TX digital reset and RX digital reset release status output ports including tx_transfer_ready, rx_transfer_ready, tx_fifo_ready, rx_fifo_ready, tx_digitalreset_timeout and rx_digitalreset_timeout."
"tx_fifo_mode","TX Core Interface FIFO mode","{Phase compensation} Register Interlaken Basic","Phase compensation","Specifies the mode for the TX PCS-Core Interface FIFO."
"tx_fifo_pfull","TX FIFO partially full threshold","0:31","5","Specifies the partially full threshold for the TX PCS-Core Interface FIFO."
"tx_fifo_pempty","TX FIFO partially empty threshold","0:31","2","Specifies the partially empty threshold for the TX PCS-Core Interface FIFO."
"enable_port_tx_fifo_full","Enable tx_fifo_full port","{0 1}","0","Enables the optional tx_fifo_full status output port. This signal indicates when the TX core FIFO has reached the full threshold. This signal is synchronous with 'tx_clkout'."
"enable_port_tx_fifo_empty","Enable tx_fifo_empty port","{0 1}","0","Enables the optional tx_fifo_empty status output port. This signal indicates when the TX core FIFO has reached the empty threshold. This signal is synchronous with 'tx_clkout'."
"enable_port_tx_fifo_pfull","Enable tx_fifo_pfull port","{0 1}","0","Enables the optional tx_fifo_pfull status output port. This signal indicates when the TX core FIFO has reached the specified partially full threshold. "
"enable_port_tx_fifo_pempty","Enable tx_fifo_pempty port","{0 1}","0","Enables the optional tx_fifo_pempty status output port. This signal indicates when the TX core FIFO has reached the specified partially empty threshold."
"enable_port_tx_dll_lock","Enable tx_dll_lock port","{0 1}","0","Enables the optional tx_dll_lock status output port. This signal indicates when the TX DLL is locked for data transfer. Refer to the reset requirements for Basic/Interlaken FIFO mode in the user guide for more details about the usage of this signal."
"rx_fifo_mode","RX PCS-Core Interface FIFO mode (PCS FIFO-Core FIFO)","{Phase compensation} {Phase compensation-Register} {Phase compensation-Basic} Register {Register-Phase compensation} Register-Basic Interlaken 10GBase-R","Phase compensation","Specifies the mode for the RX PCS-Core Interface FIFO."
"rx_fifo_pfull","RX FIFO partially full threshold","0:63","5","Specifies the partially full threshold for the RX PCS-Core Interface FIFO."
"rx_fifo_pempty","RX FIFO partially empty threshold","0:63","2","Specifies the partially empty threshold for the RX PCS-Core Interface FIFO."
"rx_fifo_align_del","Enable RX FIFO alignment word deletion (Interlaken)","{0 1}","0","Enables Interlaken alignment word (sync word) removal. When the RX PCS-Core Interface FIFO is configured for Interlaken mode, enabling this option removes all alignment (sync) words once frame synchronization has occurred. This includes the first sync word. Enabling this option requires that you also enable control word deletion."
"rx_fifo_control_del","Enable RX FIFO control word deletion (Interlaken)","{0 1}","0","Enables Interlaken control word removal. When the Enhanced RX core FIFO is configured for Interlaken mode enabling this option removes all control words after frame synchronization has occurred. Enabling this option requires that you also enable alignment word deletion."
"enable_port_rx_data_valid","Enable rx_data_valid port","{0 1}","0","Enables the optional rx_data_valid status output port when simplified interface is enabled. This signal indicates when the RX core FIFO data is valid. This signal is synchronous with 'rx_clkout'."
"enable_port_rx_fifo_full","Enable rx_fifo_full port","{0 1}","0","Enables the optional rx_fifo_full status output port. This signal indicates when the RX core FIFO has reached the full threshold. This signal is synchronous with 'rx_clkout'."
"enable_port_rx_fifo_empty","Enable rx_fifo_empty port","{0 1}","0","Enables the optional rx_fifo_empty status output port. This signal indicates when the RX core FIFO has reached the empty threshold. This signal is synchronous with 'rx_clkout'."
"enable_port_rx_fifo_pfull","Enable rx_fifo_pfull port","{0 1}","0","Enables the optional rx_fifo_pfull status output port. This signal indicates when the RX core FIFO has reached the specified partially full threshold."
"enable_port_rx_fifo_pempty","Enable rx_fifo_pempty port","{0 1}","0","Enables the optional rx_fifo_pempty status output port. This signal indicates when the RX core FIFO has reached the specified partially empty threshold."
"enable_port_rx_fifo_del","Enable rx_fifo_del port (10GBASE-R)","{0 1}","0","Enables the optional rx_fifo_del status output port. This signal indicates when a word has been deleted from the rate-match FIFO. This signal is used in 10GBASE-R mode only."
"enable_port_rx_fifo_insert","Enable rx_fifo_insert port (10GBASE-R)","{0 1}","0","Enables the optional rx_fifo_insert status output port. This signal indicates when a word has been inserted into the rate-match FIFO. This signal is used in 10GBASE-R mode only."
"enable_port_rx_fifo_rd_en","Enable rx_fifo_rd_en port","{0 1}","0","Enables the optional rx_fifo_rd_en control input port. This port is used for Interlaken and Basic FIFO modes. Asserting this signal enables the read from RX core FIFO."
"enable_port_rx_fifo_align_clr","Enable rx_fifo_align_clr port (Interlaken)","{0 1}","0","Enables the optional rx_fifo_align_clr control input port. This port is used for Interlaken mode only."
"tx_clkout_sel","Selected tx_clkout clock source","{pcs_clkout:PCS clkout} {pcs_x2_clkout:PCS clkout x2} pma_div_clkout","pcs_clkout","Specifies the clock source for tx_clkout output clock. When "PCS clkout x2" is selected, the clock frequency of tx_clkout is 2x of TX PCS parallel clock frequency only when the TX PCS-Core Interface FIFO operates in full-rate  or double-rate transfer mode. However,  when PMA-PCS width is set to 20-bit for "Standard PCS" and byte-serializer is disabled, the clock frequency of tx_clkout is the same as TX PCS parallel clock frequency even though the FIFO operates in double-rate transfer mode. "
"enable_port_tx_clkout2","Enable tx_clkout2 port","{0 1}","0","Enables the optional tx_clkout2 output clock."
"enable_port_tx_clkout_hioint","Enable tx_clkout_hioint port","{0 1}","0","Enables the optional tx_clkout_hioint output clock."
"enable_port_tx_clkout2_hioint","Enable tx_clkout2_hioint port","{0 1}","0","Enables the optional tx_clkout2_hioint output clock."
"tx_coreclkin_clock_network","Selected tx_coreclkin clock network","{dedicated:Dedicated Clock} {rowclk:Global Clock}","dedicated","Specifies the type of clock network to use to route the clock signal to tx_coreclkin port. "Dedicated Clock" allows a higher maximum frequency (fmax) between the FPGA fabric and the TX PCS. The number of "Dedicated Clock" lines are limited."
"rx_clkout_sel","Selected rx_clkout clock source","{pcs_clkout:PCS clkout} {pcs_x2_clkout:PCS clkout x2} pma_div_clkout","pcs_clkout","Specifies the clock source for rx_clkout output clock. When "PCS clkout x2" is selected, the clock frequency of rx_clkout is 2x of RX PCS parallel clock frequency only when the RX PCS-Core Interface FIFO operates in full-rate or double-rate transfer mode."
"enable_port_rx_clkout2","Enable rx_clkout2 port","{0 1}","0","Enables the optional rx_clkout2 output clock."
"rx_clkout2_sel","Selected rx_clkout2 clock source","{pcs_clkout:PCS clkout} {pcs_x2_clkout:PCS clkout x2} pma_div_clkout","pcs_clkout","Specifies the clock source for rx_clkout2 output clock. When "PCS clkout x2" is selected, the clock frequency of rx_clkout2 is 2x of RX PCS parallel clock frequency only when the RX PCS-Core Interface FIFO operates in full-rate or double-rate transfer mode."
"enable_port_rx_clkout_hioint","Enable rx_clkout_hioint port","{0 1}","0","Enables the optional rx_clkout_hioint output clock."
"enable_port_rx_clkout2_hioint","Enable rx_clkout2_hioint port","{0 1}","0","Enables the optional rx_clkout2_hioint output clock."
"rx_pma_div_clkout_divider","RX pma_div_clkout division factor","0:Disabled 1 2 33 40 66","0","Specifies the divider value for the RX pma_div_clkout clock signal."
"rx_coreclkin_clock_network","Selected rx_coreclkin clock network","{dedicated:Dedicated Clock} {rowclk:Global Clock}","dedicated","Specifies the type of clock network to use to route the clock signal to rx_coreclkin port. "Dedicated Clock" allows a higher maximum frequency (fmax) between the FPGA fabric and the RX PCS. The number of "Dedicated Clock" lines are limited."
"enable_port_latency_measurement","Enable latency measurement ports","{0 1}","0","Enables the optional latency_sclk, tx_fifo_latency_pulse, tx_pcs_fifo_latency_pulse, rx_fifo_latency_pulse and rx_pcs_fifo_latency_pulse ports that are used to measure the FIFO latency for deterministic latency application."
"generate_docs","Generate parameter documentation file","{0 1}","1","When enabled, generation produces a Comma-Separated Value file (.csv) with descriptions of the Native PHY parameters."
"enable_tx_coreclkin2","Enable tx_coreclkin2 port","{0 1}","0","This clock port needs to be enabled to provide a fifo read clock when double rate transfer is enabled with a PMA width of 20 without byte serialization"
"ovrd_tx_dv_mode","Enable TX Data Valid Gen manual setting","{0 1}","0","Gives user control where TX Data Valid is generated, auto-resolve if not checked"
"ovrd_rx_dv_mode","Enable RX Data Valid Rcv manual setting","{0 1}","0","Gives user control where RX Data Valid is consumed, auto-resolve if not checked"
"rcfg_shared","Share reconfiguration interface","{0 1}","0","When enabled, the Native PHY presents a single Avalon-MM slave interface for dynamic reconfiguration of all channels. In this configuration the upper [n-1:11] address bits of the reconfiguration address bus specify the selected channel. Address bits [10:0] provide the register offset address within the reconfiguration space of the selected channel."
"rcfg_use_clk_reset_only","Use AVMM clock and reset ports only","{0 1}","0","When enabled, the Native PHY exposes only clcok and reset ports for Avalon-MM slave interface, other ports are terminated."
"set_embedded_debug_enable","Enable embedded debug","{0 1}","0","Enables the embedded debug logic in the transceiver channel and grants access to capability registers, soft prbs accumulators and control and status registers"
"set_prbs_soft_logic_enable","Enable prbs soft accumulators","{0 1}","0","Enables soft logic for doing prbs bit and error accumulation when using the hard prbs generator and checker."
"enable_rcfg_tx_digitalreset_release_ctrl","Enable rcfg_tx_digitalreset_release_ctrl port","{0 1}","0","Enables the rcfg_tx_digitalreset_release_ctrl port that dynamically controls the TX PCS reset release sequence. This port is mandatory when reconfiguring to/from TX PCS Gearbox ratio of *:67. Deassert this signal at least 30ns before deasserting tx_digitalreset when the TX PCS Gearbox ratio is configured to *:67. In other modes, assert this signal at least 30ns before deasserting tx_digitalreset."
"suppress_design_example_messages","suppress_design_example_messages","-2147483648:2147483647","0","This parameter is intended for a parent IP to supress the messages."
"tx_pll_type","Tx PLL type","ATX fPLL CMU","ATX","Selects the type of the TX PLL to be used in example design."
"tx_pll_refclk","Tx PLL reference clock frequency","","125.0","Tx PLL reference clock frequency. If an appropriate value is not specified, design example generation will fail."
"use_tx_clkout2","Use tx_clkout2 as source for tx_coreclkin","{0 1}","0","Determines whether tx_clkout or tx_clkout2 is used to clock tx_coreclkin and the TX data generator."
"use_rx_clkout2","Use rx_clkout2 as source for rx_coreclkin","{0 1}","0","Determines whether rx_clkout or rx_clkout2 is used to clock rx_coreclkin and the RX data generator."
"enable_de_hardware_debug","Enable soft register map for System Console","{0 1}","0","Enables a soft register map to be read out in system-console.  Allows the reading back of the design status.  Works in tandem with the transceiver ADME."
"tile_type_suffix","Xcvr Tile Type Suffix","{} _htile _etile","","TBD."
"design_example_filename","Design example filename","","top","Specifies the name of the design example. If design example generation succesful, filename.qsys and filename_tb.qsys files will be generated."
"anlg_voltage","VCCR_GXB and VCCT_GXB supply voltage for the Transceiver","1_1V 1_0V","1_0V","Selects the VCCR_GXB and VCCT_GXB supply voltage for the Transceiver."
"anlg_link","Tranceiver Link Type","sr lr","sr","Selects the type of transceiver link. SR-Short Reach (Chip-to-chip communication), LR-Long Reach (Backplane communication)"
"enable_ports_adaptation","Enable adaptation control ports","{0 1}","0","Enables the optional rx_adapt_reset, and rx_adapt_start ports. These ports are used to control the adaptation engine (adaptation engine can also be controlled through DPRIO interface). Even if they are exposed, the ports are not usable until they are activated through DPRIO interface. For adaptation engine control: user needs to apply the reset first, after releasing reset, assert the start. The adaptation status can be observed through DPRIO interface."
"qsf_assignments_enable","Provide sample QSF assignments","{0 1}","0","When enabled, the IP will display the sample Quartus Settings File assignments equivalent to the current IP settings. You do not normally need these QSF assignments as the analog settings are set by the IP in the design. However, depending on your system, you may want to override the IP settings using QSF assignments. One such case may be when you have different analog settings per channel in a multi-channel interface or if you want to use different analog settings assignments for different instances of an interface."
"tx_pma_analog_mode","TX PMA analog mode rules","analog_off cei_4976_lr cei_4976_sr cei_6375_lr cei_6375_sr cei_9950_lr cei_9950_sr cei_11100_lr cei_11100_sr cei_12500_lr cei_12500_sr cei_19000_vsr cei_28000_vsr cpri_12500 cpri_e6hv cpri_e6lv cpri_e6lvii cpri_e6lviii cpri_e12hv cpri_e12lv cpri_e12lvii cpri_e12lviii cpri_e24lv cpri_e24lvii cpri_e24lviii cpri_e30lv cpri_e30lvii cpri_e30lviii cpri_e48lvii cpri_e48lviii cpri_e60lvii cpri_e60lviii cpri_e96lviii cpri_e99lviii dp_1620 dp_2700 dp_5400 fc_400_df_ea_s fc_400_df_el_s fc_800_df_ea_s fc_800_df_el_s fc_1600_df_ea_s fc_1600_df_el_s gige_1250 gpon_155 gpon_622 gpon_1244 gpon_2488 hdmi_3400 hdmi_6000 higig_3125 higig_3750 higig_4062 higig_5000 higig_6250 higig_6562 hmc_10000 hmc_12500 hmc_15000 ieee_10g_base_cr_10312 ieee_10g_base_cx4 ieee_10g_base_kx4 ieee_10g_kr_10312 ieee_40g_base_cr4_10312 ieee_40g_base_kr_10312 ieee_100g_base_cr4_25781 ieee_100g_base_cr10_10312 ieee_100g_base_kr4_25781 ieee_1000_base_cx ieee_1000_base_kx ieee_itut_10g_gpon_epon infiniband_ddr_5000 infiniband_fdr_14000 infiniband_qdr_10000 infiniband_sdr_2500 interlaken_3125 interlaken_6375 interlaken_11100 interlaken_12500 interlaken_25781 jesd204_a_b_312 jesd204_a_b_3125 jesd204_a_b_6375 jesd204_a_b_12500 jesd204_b_16000 nppi_10312 otu2_10709 pcie_cable qsgmii_5000 sas_1500 sas_3000 sas_6000 sas_12000 sata_1500 sata_3000 sata_6000 sdi_270_sd sdi_1485_hd sdi_2970_3g sdi_6000 sdi_12000 serial_lite_iii_16400 serial_lite_iii_17400 sff_8431 sfi_2488 sfi_3125 sfi_s_6250 sfi_s_11200 sonet_oc12_622 sonet_oc48_2488 sonet_oc192_9953 srio_1250_lr srio_1250_sr srio_2500_lr srio_2500_sr srio_3125_lr srio_3125_sr srio_5000_lr srio_5000_mr srio_5000_sr srio_6250_lr srio_6250_mr srio_6250_sr srio_10312_lr srio_10312_sr upi user_custom xaui_3125 xfp_9950 xfp_10310 xfp_10520 xfp_10700 xfp_11320 xfp_12500","user_custom","Selects the analog protocol mode rules to pre-select the TX pin swing settings (VOD, Pre-emphasis, and Slew Rate). "
"rx_pma_analog_mode","RX PMA analog mode rules","analog_off dp_1620 dp_2700 dp_5400 dp_8100 gpon_622 gpon_1244 hdmi_3400 hdmi_6000 ieee_10g_base_kx4 ieee_10g_kr_10312 ieee_40g_base_cr4_10312 ieee_100g_base_cr10_10312 ieee_1000_base_kx infiniband_fdr_14000 nppi_10312 sas_12000 sonet_oc48_2488 upi user_custom","user_custom","Selects the analog protocol mode rules to pre-select the RX pin swing settings (VOD, Pre-emphasis, and Slew Rate). "
"tx_pma_optimal_settings","Use default TX PMA analog settings","{0 1}","1","When enabled, the TX PMA analog parameters will be configured using Intel specified default settings. When disabled, you must manually configure the TX PMA analog parameters. Your particular system or appliation may require custom settings."
"rx_pma_optimal_settings","Use default RX PMA analog settings","{0 1}","1","When enabled', the RX PMA analog parameters will be configured using Intel specified default settings. When disabled, you must manually configure the RX PMA analog parameters. Your particular system or appliation may require custom settings."
"rx_pma_adapt_mode","RX adaptation mode","{manual:Manual CTLE, Manual VGA, DFE Off} {ctle_only:Adaptive CTLE, Adaptive VGA, DFE Off} {ctle_dfe:Adaptive CTLE, Adaptive VGA, All-Tap Adaptive DFE} {ctle_dfe_tap1:Adaptive CTLE, Adaptive VGA, 1-Tap Adaptive DFE}","manual","Specifies the operation mode for the RX adaptation circuits."
