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module alt_st_fifo_empty
(
    input clk,
    input reset,

    input inc,
    input dec,
    
    output reg zero
);
    reg [1:0] ctr_low;
    reg [2:0] ctr_high;
    reg       ctr_low_overflow;
    reg       ctr_low_underflow;
    reg       sclr;
    reg       ctr_high_is_0;

    always @(posedge clk) begin
        sclr <= reset;
    end

    always @(posedge clk) begin
        if (sclr) begin
            ctr_low <= 2'h0;
        end else begin
            if (inc & (~dec | zero))
                ctr_low <= ctr_low + 1'b1;
            else if (dec & ~zero & ~inc)
                ctr_low <= ctr_low - 1'b1; 
        end
    end

    always @(posedge clk) begin
        ctr_low_overflow <= (ctr_low == 2'h3) & inc & ~dec;
        ctr_low_underflow <= (ctr_low == 2'h0) & dec & ~inc & ~zero;
    end

    always @(posedge clk) begin
        if (sclr)
            ctr_high_is_0 <= 1'b1;
        else if (ctr_low_overflow)
            ctr_high_is_0 <= 1'b0;
        else if (ctr_low_underflow & (ctr_high == 3'h1))
            ctr_high_is_0 <= 1'b1;
    end

    always @(posedge clk) begin
        if (sclr) begin
            ctr_high <= 3'h0;
        end else begin
            if (ctr_low_overflow) begin
                ctr_high <= ctr_high + 1'b1;
            end else if (ctr_low_underflow) begin
                ctr_high <= ctr_high - 1'b1;
            end
        end
    end

    always @(posedge clk) begin
        if (sclr)
            zero <= 1'b1;
        else if (inc)
            zero <= 1'b0;
        else if (ctr_high_is_0 & (ctr_low == 2'h1) & dec & ~inc)
            zero <= 1'b1;
    end

endmodule
