-- address_decoder_top.vhd

-- Generated using ACDS version 19.4 64

library IEEE;
library address_decoder_top_csr_clk;
library address_decoder_top_mac_clk;
library address_decoder_top_master;
library address_decoder_top_mm_clock_crossing_bridge;
library address_decoder_top_multi_channel;
library address_decoder_top_traffic_controller_ch_0_1;
library address_decoder_top_traffic_controller_ch_10_11;
library address_decoder_top_traffic_controller_ch_2_3;
library address_decoder_top_traffic_controller_ch_4_5;
library address_decoder_top_traffic_controller_ch_6_7;
library address_decoder_top_traffic_controller_ch_8_9;
library altera_mm_interconnect_191;
library altera_reset_controller_191;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity address_decoder_top is
	port (
		csr_clk_clk                             : in  std_logic                     := '0';             --                     csr_clk.clk
		csr_clk_reset_reset_n                   : in  std_logic                     := '0';             --               csr_clk_reset.reset_n
		mac_clk_clk                             : in  std_logic                     := '0';             --                     mac_clk.clk
		mac_clk_reset_reset_n                   : in  std_logic                     := '0';             --               mac_clk_reset.reset_n
		slave_address                           : in  std_logic_vector(31 downto 0) := (others => '0'); --                       slave.address
		slave_waitrequest                       : out std_logic;                                        --                            .waitrequest
		slave_read                              : in  std_logic                     := '0';             --                            .read
		slave_readdata                          : out std_logic_vector(31 downto 0);                    --                            .readdata
		slave_readdatavalid                     : out std_logic;                                        --                            .readdatavalid
		slave_write                             : in  std_logic                     := '0';             --                            .write
		slave_writedata                         : in  std_logic_vector(31 downto 0) := (others => '0'); --                            .writedata
		multi_channel_address                   : out std_logic_vector(19 downto 0);                    --               multi_channel.address
		multi_channel_write                     : out std_logic;                                        --                            .write
		multi_channel_read                      : out std_logic;                                        --                            .read
		multi_channel_readdata                  : in  std_logic_vector(31 downto 0) := (others => '0'); --                            .readdata
		multi_channel_writedata                 : out std_logic_vector(31 downto 0);                    --                            .writedata
		multi_channel_waitrequest               : in  std_logic                     := '0';             --                            .waitrequest
		traffic_controller_ch_0_1_address       : out std_logic_vector(13 downto 0);                    --   traffic_controller_ch_0_1.address
		traffic_controller_ch_0_1_write         : out std_logic;                                        --                            .write
		traffic_controller_ch_0_1_read          : out std_logic;                                        --                            .read
		traffic_controller_ch_0_1_readdata      : in  std_logic_vector(31 downto 0) := (others => '0'); --                            .readdata
		traffic_controller_ch_0_1_writedata     : out std_logic_vector(31 downto 0);                    --                            .writedata
		traffic_controller_ch_0_1_waitrequest   : in  std_logic                     := '0';             --                            .waitrequest
		traffic_controller_ch_10_11_address     : out std_logic_vector(13 downto 0);                    -- traffic_controller_ch_10_11.address
		traffic_controller_ch_10_11_write       : out std_logic;                                        --                            .write
		traffic_controller_ch_10_11_read        : out std_logic;                                        --                            .read
		traffic_controller_ch_10_11_readdata    : in  std_logic_vector(31 downto 0) := (others => '0'); --                            .readdata
		traffic_controller_ch_10_11_writedata   : out std_logic_vector(31 downto 0);                    --                            .writedata
		traffic_controller_ch_10_11_waitrequest : in  std_logic                     := '0';             --                            .waitrequest
		traffic_controller_ch_2_3_address       : out std_logic_vector(13 downto 0);                    --   traffic_controller_ch_2_3.address
		traffic_controller_ch_2_3_write         : out std_logic;                                        --                            .write
		traffic_controller_ch_2_3_read          : out std_logic;                                        --                            .read
		traffic_controller_ch_2_3_readdata      : in  std_logic_vector(31 downto 0) := (others => '0'); --                            .readdata
		traffic_controller_ch_2_3_writedata     : out std_logic_vector(31 downto 0);                    --                            .writedata
		traffic_controller_ch_2_3_waitrequest   : in  std_logic                     := '0';             --                            .waitrequest
		traffic_controller_ch_4_5_address       : out std_logic_vector(13 downto 0);                    --   traffic_controller_ch_4_5.address
		traffic_controller_ch_4_5_write         : out std_logic;                                        --                            .write
		traffic_controller_ch_4_5_read          : out std_logic;                                        --                            .read
		traffic_controller_ch_4_5_readdata      : in  std_logic_vector(31 downto 0) := (others => '0'); --                            .readdata
		traffic_controller_ch_4_5_writedata     : out std_logic_vector(31 downto 0);                    --                            .writedata
		traffic_controller_ch_4_5_waitrequest   : in  std_logic                     := '0';             --                            .waitrequest
		traffic_controller_ch_6_7_address       : out std_logic_vector(13 downto 0);                    --   traffic_controller_ch_6_7.address
		traffic_controller_ch_6_7_write         : out std_logic;                                        --                            .write
		traffic_controller_ch_6_7_read          : out std_logic;                                        --                            .read
		traffic_controller_ch_6_7_readdata      : in  std_logic_vector(31 downto 0) := (others => '0'); --                            .readdata
		traffic_controller_ch_6_7_writedata     : out std_logic_vector(31 downto 0);                    --                            .writedata
		traffic_controller_ch_6_7_waitrequest   : in  std_logic                     := '0';             --                            .waitrequest
		traffic_controller_ch_8_9_address       : out std_logic_vector(13 downto 0);                    --   traffic_controller_ch_8_9.address
		traffic_controller_ch_8_9_write         : out std_logic;                                        --                            .write
		traffic_controller_ch_8_9_read          : out std_logic;                                        --                            .read
		traffic_controller_ch_8_9_readdata      : in  std_logic_vector(31 downto 0) := (others => '0'); --                            .readdata
		traffic_controller_ch_8_9_writedata     : out std_logic_vector(31 downto 0);                    --                            .writedata
		traffic_controller_ch_8_9_waitrequest   : in  std_logic                     := '0'              --                            .waitrequest
	);
end entity address_decoder_top;

architecture rtl of address_decoder_top is
	component address_decoder_top_csr_clk_cmp is
		port (
			clk_out     : out std_logic;        -- clk
			in_clk      : in  std_logic := 'X'; -- clk
			reset_n     : in  std_logic := 'X'; -- reset_n
			reset_n_out : out std_logic         -- reset_n
		);
	end component address_decoder_top_csr_clk_cmp;

	component address_decoder_top_mac_clk_cmp is
		port (
			clk_out     : out std_logic;        -- clk
			in_clk      : in  std_logic := 'X'; -- clk
			reset_n     : in  std_logic := 'X'; -- reset_n
			reset_n_out : out std_logic         -- reset_n
		);
	end component address_decoder_top_mac_clk_cmp;

	component address_decoder_top_master_cmp is
		port (
			av_address        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- address
			av_waitrequest    : out std_logic;                                        -- waitrequest
			av_read           : in  std_logic                     := 'X';             -- read
			av_readdata       : out std_logic_vector(31 downto 0);                    -- readdata
			av_readdatavalid  : out std_logic;                                        -- readdatavalid
			av_write          : in  std_logic                     := 'X';             -- write
			av_writedata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_address       : out std_logic_vector(31 downto 0);                    -- address
			uav_burstcount    : out std_logic_vector(2 downto 0);                     -- burstcount
			uav_read          : out std_logic;                                        -- read
			uav_write         : out std_logic;                                        -- write
			uav_waitrequest   : in  std_logic                     := 'X';             -- waitrequest
			uav_readdatavalid : in  std_logic                     := 'X';             -- readdatavalid
			uav_byteenable    : out std_logic_vector(3 downto 0);                     -- byteenable
			uav_readdata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			uav_writedata     : out std_logic_vector(31 downto 0);                    -- writedata
			uav_lock          : out std_logic;                                        -- lock
			uav_debugaccess   : out std_logic;                                        -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_top_master_cmp;

	component address_decoder_top_mm_clock_crossing_bridge_cmp is
		port (
			m0_waitrequest   : in  std_logic                     := 'X';             -- waitrequest
			m0_readdata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			m0_readdatavalid : in  std_logic                     := 'X';             -- readdatavalid
			m0_burstcount    : out std_logic_vector(0 downto 0);                     -- burstcount
			m0_writedata     : out std_logic_vector(31 downto 0);                    -- writedata
			m0_address       : out std_logic_vector(16 downto 0);                    -- address
			m0_write         : out std_logic;                                        -- write
			m0_read          : out std_logic;                                        -- read
			m0_byteenable    : out std_logic_vector(3 downto 0);                     -- byteenable
			m0_debugaccess   : out std_logic;                                        -- debugaccess
			m0_clk           : in  std_logic                     := 'X';             -- clk
			m0_reset         : in  std_logic                     := 'X';             -- reset
			s0_waitrequest   : out std_logic;                                        -- waitrequest
			s0_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			s0_readdatavalid : out std_logic;                                        -- readdatavalid
			s0_burstcount    : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- burstcount
			s0_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			s0_address       : in  std_logic_vector(16 downto 0) := (others => 'X'); -- address
			s0_write         : in  std_logic                     := 'X';             -- write
			s0_read          : in  std_logic                     := 'X';             -- read
			s0_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			s0_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			s0_clk           : in  std_logic                     := 'X';             -- clk
			s0_reset         : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_top_mm_clock_crossing_bridge_cmp;

	component address_decoder_top_multi_channel_cmp is
		port (
			av_address        : out std_logic_vector(19 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(19 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_top_multi_channel_cmp;

	component address_decoder_top_traffic_controller_ch_0_1_cmp is
		port (
			av_address        : out std_logic_vector(13 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(13 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_top_traffic_controller_ch_0_1_cmp;

	component address_decoder_top_traffic_controller_ch_10_11_cmp is
		port (
			av_address        : out std_logic_vector(13 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(13 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_top_traffic_controller_ch_10_11_cmp;

	component address_decoder_top_traffic_controller_ch_2_3_cmp is
		port (
			av_address        : out std_logic_vector(13 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(13 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_top_traffic_controller_ch_2_3_cmp;

	component address_decoder_top_traffic_controller_ch_4_5_cmp is
		port (
			av_address        : out std_logic_vector(13 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(13 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_top_traffic_controller_ch_4_5_cmp;

	component address_decoder_top_traffic_controller_ch_6_7_cmp is
		port (
			av_address        : out std_logic_vector(13 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(13 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_top_traffic_controller_ch_6_7_cmp;

	component address_decoder_top_traffic_controller_ch_8_9_cmp is
		port (
			av_address        : out std_logic_vector(13 downto 0);                    -- address
			av_write          : out std_logic;                                        -- write
			av_read           : out std_logic;                                        -- read
			av_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			uav_address       : in  std_logic_vector(13 downto 0) := (others => 'X'); -- address
			uav_burstcount    : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read          : in  std_logic                     := 'X';             -- read
			uav_write         : in  std_logic                     := 'X';             -- write
			uav_waitrequest   : out std_logic;                                        -- waitrequest
			uav_readdatavalid : out std_logic;                                        -- readdatavalid
			uav_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock          : in  std_logic                     := 'X';             -- lock
			uav_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X'              -- reset
		);
	end component address_decoder_top_traffic_controller_ch_8_9_cmp;

	component address_decoder_top_altera_mm_interconnect_191_3kbf4ri_cmp is
		port (
			master_avalon_universal_master_0_address             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- address
			master_avalon_universal_master_0_waitrequest         : out std_logic;                                        -- waitrequest
			master_avalon_universal_master_0_burstcount          : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			master_avalon_universal_master_0_byteenable          : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			master_avalon_universal_master_0_read                : in  std_logic                     := 'X';             -- read
			master_avalon_universal_master_0_readdata            : out std_logic_vector(31 downto 0);                    -- readdata
			master_avalon_universal_master_0_readdatavalid       : out std_logic;                                        -- readdatavalid
			master_avalon_universal_master_0_write               : in  std_logic                     := 'X';             -- write
			master_avalon_universal_master_0_writedata           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			master_avalon_universal_master_0_lock                : in  std_logic                     := 'X';             -- lock
			master_avalon_universal_master_0_debugaccess         : in  std_logic                     := 'X';             -- debugaccess
			multi_channel_avalon_universal_slave_0_address       : out std_logic_vector(19 downto 0);                    -- address
			multi_channel_avalon_universal_slave_0_write         : out std_logic;                                        -- write
			multi_channel_avalon_universal_slave_0_read          : out std_logic;                                        -- read
			multi_channel_avalon_universal_slave_0_readdata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			multi_channel_avalon_universal_slave_0_writedata     : out std_logic_vector(31 downto 0);                    -- writedata
			multi_channel_avalon_universal_slave_0_burstcount    : out std_logic_vector(2 downto 0);                     -- burstcount
			multi_channel_avalon_universal_slave_0_byteenable    : out std_logic_vector(3 downto 0);                     -- byteenable
			multi_channel_avalon_universal_slave_0_readdatavalid : in  std_logic                     := 'X';             -- readdatavalid
			multi_channel_avalon_universal_slave_0_waitrequest   : in  std_logic                     := 'X';             -- waitrequest
			multi_channel_avalon_universal_slave_0_lock          : out std_logic;                                        -- lock
			multi_channel_avalon_universal_slave_0_debugaccess   : out std_logic;                                        -- debugaccess
			mm_clock_crossing_bridge_s0_address                  : out std_logic_vector(16 downto 0);                    -- address
			mm_clock_crossing_bridge_s0_write                    : out std_logic;                                        -- write
			mm_clock_crossing_bridge_s0_read                     : out std_logic;                                        -- read
			mm_clock_crossing_bridge_s0_readdata                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			mm_clock_crossing_bridge_s0_writedata                : out std_logic_vector(31 downto 0);                    -- writedata
			mm_clock_crossing_bridge_s0_burstcount               : out std_logic_vector(0 downto 0);                     -- burstcount
			mm_clock_crossing_bridge_s0_byteenable               : out std_logic_vector(3 downto 0);                     -- byteenable
			mm_clock_crossing_bridge_s0_readdatavalid            : in  std_logic                     := 'X';             -- readdatavalid
			mm_clock_crossing_bridge_s0_waitrequest              : in  std_logic                     := 'X';             -- waitrequest
			mm_clock_crossing_bridge_s0_debugaccess              : out std_logic;                                        -- debugaccess
			master_reset_reset_bridge_in_reset_reset             : in  std_logic                     := 'X';             -- reset
			csr_clk_clk_clk                                      : in  std_logic                     := 'X'              -- clk
		);
	end component address_decoder_top_altera_mm_interconnect_191_3kbf4ri_cmp;

	component address_decoder_top_altera_mm_interconnect_191_fv6bu5i_cmp is
		port (
			mm_clock_crossing_bridge_m0_address                                : in  std_logic_vector(16 downto 0) := (others => 'X'); -- address
			mm_clock_crossing_bridge_m0_waitrequest                            : out std_logic;                                        -- waitrequest
			mm_clock_crossing_bridge_m0_burstcount                             : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- burstcount
			mm_clock_crossing_bridge_m0_byteenable                             : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			mm_clock_crossing_bridge_m0_read                                   : in  std_logic                     := 'X';             -- read
			mm_clock_crossing_bridge_m0_readdata                               : out std_logic_vector(31 downto 0);                    -- readdata
			mm_clock_crossing_bridge_m0_readdatavalid                          : out std_logic;                                        -- readdatavalid
			mm_clock_crossing_bridge_m0_write                                  : in  std_logic                     := 'X';             -- write
			mm_clock_crossing_bridge_m0_writedata                              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			mm_clock_crossing_bridge_m0_debugaccess                            : in  std_logic                     := 'X';             -- debugaccess
			traffic_controller_ch_0_1_avalon_universal_slave_0_address         : out std_logic_vector(13 downto 0);                    -- address
			traffic_controller_ch_0_1_avalon_universal_slave_0_write           : out std_logic;                                        -- write
			traffic_controller_ch_0_1_avalon_universal_slave_0_read            : out std_logic;                                        -- read
			traffic_controller_ch_0_1_avalon_universal_slave_0_readdata        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			traffic_controller_ch_0_1_avalon_universal_slave_0_writedata       : out std_logic_vector(31 downto 0);                    -- writedata
			traffic_controller_ch_0_1_avalon_universal_slave_0_burstcount      : out std_logic_vector(2 downto 0);                     -- burstcount
			traffic_controller_ch_0_1_avalon_universal_slave_0_byteenable      : out std_logic_vector(3 downto 0);                     -- byteenable
			traffic_controller_ch_0_1_avalon_universal_slave_0_readdatavalid   : in  std_logic                     := 'X';             -- readdatavalid
			traffic_controller_ch_0_1_avalon_universal_slave_0_waitrequest     : in  std_logic                     := 'X';             -- waitrequest
			traffic_controller_ch_0_1_avalon_universal_slave_0_lock            : out std_logic;                                        -- lock
			traffic_controller_ch_0_1_avalon_universal_slave_0_debugaccess     : out std_logic;                                        -- debugaccess
			traffic_controller_ch_2_3_avalon_universal_slave_0_address         : out std_logic_vector(13 downto 0);                    -- address
			traffic_controller_ch_2_3_avalon_universal_slave_0_write           : out std_logic;                                        -- write
			traffic_controller_ch_2_3_avalon_universal_slave_0_read            : out std_logic;                                        -- read
			traffic_controller_ch_2_3_avalon_universal_slave_0_readdata        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			traffic_controller_ch_2_3_avalon_universal_slave_0_writedata       : out std_logic_vector(31 downto 0);                    -- writedata
			traffic_controller_ch_2_3_avalon_universal_slave_0_burstcount      : out std_logic_vector(2 downto 0);                     -- burstcount
			traffic_controller_ch_2_3_avalon_universal_slave_0_byteenable      : out std_logic_vector(3 downto 0);                     -- byteenable
			traffic_controller_ch_2_3_avalon_universal_slave_0_readdatavalid   : in  std_logic                     := 'X';             -- readdatavalid
			traffic_controller_ch_2_3_avalon_universal_slave_0_waitrequest     : in  std_logic                     := 'X';             -- waitrequest
			traffic_controller_ch_2_3_avalon_universal_slave_0_lock            : out std_logic;                                        -- lock
			traffic_controller_ch_2_3_avalon_universal_slave_0_debugaccess     : out std_logic;                                        -- debugaccess
			traffic_controller_ch_4_5_avalon_universal_slave_0_address         : out std_logic_vector(13 downto 0);                    -- address
			traffic_controller_ch_4_5_avalon_universal_slave_0_write           : out std_logic;                                        -- write
			traffic_controller_ch_4_5_avalon_universal_slave_0_read            : out std_logic;                                        -- read
			traffic_controller_ch_4_5_avalon_universal_slave_0_readdata        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			traffic_controller_ch_4_5_avalon_universal_slave_0_writedata       : out std_logic_vector(31 downto 0);                    -- writedata
			traffic_controller_ch_4_5_avalon_universal_slave_0_burstcount      : out std_logic_vector(2 downto 0);                     -- burstcount
			traffic_controller_ch_4_5_avalon_universal_slave_0_byteenable      : out std_logic_vector(3 downto 0);                     -- byteenable
			traffic_controller_ch_4_5_avalon_universal_slave_0_readdatavalid   : in  std_logic                     := 'X';             -- readdatavalid
			traffic_controller_ch_4_5_avalon_universal_slave_0_waitrequest     : in  std_logic                     := 'X';             -- waitrequest
			traffic_controller_ch_4_5_avalon_universal_slave_0_lock            : out std_logic;                                        -- lock
			traffic_controller_ch_4_5_avalon_universal_slave_0_debugaccess     : out std_logic;                                        -- debugaccess
			traffic_controller_ch_6_7_avalon_universal_slave_0_address         : out std_logic_vector(13 downto 0);                    -- address
			traffic_controller_ch_6_7_avalon_universal_slave_0_write           : out std_logic;                                        -- write
			traffic_controller_ch_6_7_avalon_universal_slave_0_read            : out std_logic;                                        -- read
			traffic_controller_ch_6_7_avalon_universal_slave_0_readdata        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			traffic_controller_ch_6_7_avalon_universal_slave_0_writedata       : out std_logic_vector(31 downto 0);                    -- writedata
			traffic_controller_ch_6_7_avalon_universal_slave_0_burstcount      : out std_logic_vector(2 downto 0);                     -- burstcount
			traffic_controller_ch_6_7_avalon_universal_slave_0_byteenable      : out std_logic_vector(3 downto 0);                     -- byteenable
			traffic_controller_ch_6_7_avalon_universal_slave_0_readdatavalid   : in  std_logic                     := 'X';             -- readdatavalid
			traffic_controller_ch_6_7_avalon_universal_slave_0_waitrequest     : in  std_logic                     := 'X';             -- waitrequest
			traffic_controller_ch_6_7_avalon_universal_slave_0_lock            : out std_logic;                                        -- lock
			traffic_controller_ch_6_7_avalon_universal_slave_0_debugaccess     : out std_logic;                                        -- debugaccess
			traffic_controller_ch_8_9_avalon_universal_slave_0_address         : out std_logic_vector(13 downto 0);                    -- address
			traffic_controller_ch_8_9_avalon_universal_slave_0_write           : out std_logic;                                        -- write
			traffic_controller_ch_8_9_avalon_universal_slave_0_read            : out std_logic;                                        -- read
			traffic_controller_ch_8_9_avalon_universal_slave_0_readdata        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			traffic_controller_ch_8_9_avalon_universal_slave_0_writedata       : out std_logic_vector(31 downto 0);                    -- writedata
			traffic_controller_ch_8_9_avalon_universal_slave_0_burstcount      : out std_logic_vector(2 downto 0);                     -- burstcount
			traffic_controller_ch_8_9_avalon_universal_slave_0_byteenable      : out std_logic_vector(3 downto 0);                     -- byteenable
			traffic_controller_ch_8_9_avalon_universal_slave_0_readdatavalid   : in  std_logic                     := 'X';             -- readdatavalid
			traffic_controller_ch_8_9_avalon_universal_slave_0_waitrequest     : in  std_logic                     := 'X';             -- waitrequest
			traffic_controller_ch_8_9_avalon_universal_slave_0_lock            : out std_logic;                                        -- lock
			traffic_controller_ch_8_9_avalon_universal_slave_0_debugaccess     : out std_logic;                                        -- debugaccess
			traffic_controller_ch_10_11_avalon_universal_slave_0_address       : out std_logic_vector(13 downto 0);                    -- address
			traffic_controller_ch_10_11_avalon_universal_slave_0_write         : out std_logic;                                        -- write
			traffic_controller_ch_10_11_avalon_universal_slave_0_read          : out std_logic;                                        -- read
			traffic_controller_ch_10_11_avalon_universal_slave_0_readdata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			traffic_controller_ch_10_11_avalon_universal_slave_0_writedata     : out std_logic_vector(31 downto 0);                    -- writedata
			traffic_controller_ch_10_11_avalon_universal_slave_0_burstcount    : out std_logic_vector(2 downto 0);                     -- burstcount
			traffic_controller_ch_10_11_avalon_universal_slave_0_byteenable    : out std_logic_vector(3 downto 0);                     -- byteenable
			traffic_controller_ch_10_11_avalon_universal_slave_0_readdatavalid : in  std_logic                     := 'X';             -- readdatavalid
			traffic_controller_ch_10_11_avalon_universal_slave_0_waitrequest   : in  std_logic                     := 'X';             -- waitrequest
			traffic_controller_ch_10_11_avalon_universal_slave_0_lock          : out std_logic;                                        -- lock
			traffic_controller_ch_10_11_avalon_universal_slave_0_debugaccess   : out std_logic;                                        -- debugaccess
			mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset      : in  std_logic                     := 'X';             -- reset
			mac_clk_clk_clk                                                    : in  std_logic                     := 'X'              -- clk
		);
	end component address_decoder_top_altera_mm_interconnect_191_fv6bu5i_cmp;

	component altera_reset_controller_cmp is
		generic (
			NUM_RESET_INPUTS          : integer := 6;
			OUTPUT_RESET_SYNC_EDGES   : string  := "deassert";
			SYNC_DEPTH                : integer := 2;
			RESET_REQUEST_PRESENT     : integer := 0;
			RESET_REQ_WAIT_TIME       : integer := 1;
			MIN_RST_ASSERTION_TIME    : integer := 3;
			RESET_REQ_EARLY_DSRT_TIME : integer := 1;
			USE_RESET_REQUEST_IN0     : integer := 0;
			USE_RESET_REQUEST_IN1     : integer := 0;
			USE_RESET_REQUEST_IN2     : integer := 0;
			USE_RESET_REQUEST_IN3     : integer := 0;
			USE_RESET_REQUEST_IN4     : integer := 0;
			USE_RESET_REQUEST_IN5     : integer := 0;
			USE_RESET_REQUEST_IN6     : integer := 0;
			USE_RESET_REQUEST_IN7     : integer := 0;
			USE_RESET_REQUEST_IN8     : integer := 0;
			USE_RESET_REQUEST_IN9     : integer := 0;
			USE_RESET_REQUEST_IN10    : integer := 0;
			USE_RESET_REQUEST_IN11    : integer := 0;
			USE_RESET_REQUEST_IN12    : integer := 0;
			USE_RESET_REQUEST_IN13    : integer := 0;
			USE_RESET_REQUEST_IN14    : integer := 0;
			USE_RESET_REQUEST_IN15    : integer := 0;
			ADAPT_RESET_REQUEST       : integer := 0
		);
		port (
			reset_in0      : in  std_logic := 'X'; -- reset
			clk            : in  std_logic := 'X'; -- clk
			reset_out      : out std_logic;        -- reset
			reset_req      : out std_logic;        -- reset_req
			reset_req_in0  : in  std_logic := 'X'; -- reset_req
			reset_in1      : in  std_logic := 'X'; -- reset
			reset_req_in1  : in  std_logic := 'X'; -- reset_req
			reset_in2      : in  std_logic := 'X'; -- reset
			reset_req_in2  : in  std_logic := 'X'; -- reset_req
			reset_in3      : in  std_logic := 'X'; -- reset
			reset_req_in3  : in  std_logic := 'X'; -- reset_req
			reset_in4      : in  std_logic := 'X'; -- reset
			reset_req_in4  : in  std_logic := 'X'; -- reset_req
			reset_in5      : in  std_logic := 'X'; -- reset
			reset_req_in5  : in  std_logic := 'X'; -- reset_req
			reset_in6      : in  std_logic := 'X'; -- reset
			reset_req_in6  : in  std_logic := 'X'; -- reset_req
			reset_in7      : in  std_logic := 'X'; -- reset
			reset_req_in7  : in  std_logic := 'X'; -- reset_req
			reset_in8      : in  std_logic := 'X'; -- reset
			reset_req_in8  : in  std_logic := 'X'; -- reset_req
			reset_in9      : in  std_logic := 'X'; -- reset
			reset_req_in9  : in  std_logic := 'X'; -- reset_req
			reset_in10     : in  std_logic := 'X'; -- reset
			reset_req_in10 : in  std_logic := 'X'; -- reset_req
			reset_in11     : in  std_logic := 'X'; -- reset
			reset_req_in11 : in  std_logic := 'X'; -- reset_req
			reset_in12     : in  std_logic := 'X'; -- reset
			reset_req_in12 : in  std_logic := 'X'; -- reset_req
			reset_in13     : in  std_logic := 'X'; -- reset
			reset_req_in13 : in  std_logic := 'X'; -- reset_req
			reset_in14     : in  std_logic := 'X'; -- reset
			reset_req_in14 : in  std_logic := 'X'; -- reset_req
			reset_in15     : in  std_logic := 'X'; -- reset
			reset_req_in15 : in  std_logic := 'X'  -- reset_req
		);
	end component altera_reset_controller_cmp;

	signal csr_clk_clk_clk                                                                      : std_logic;                     -- csr_clk:clk_out -> [master:clk, mm_clock_crossing_bridge:s0_clk, mm_interconnect_0:csr_clk_clk_clk, multi_channel:clk, rst_controller:clk]
	signal mac_clk_clk_clk                                                                      : std_logic;                     -- mac_clk:clk_out -> [mm_clock_crossing_bridge:m0_clk, mm_interconnect_1:mac_clk_clk_clk, rst_controller_001:clk, traffic_controller_ch_0_1:clk, traffic_controller_ch_10_11:clk, traffic_controller_ch_2_3:clk, traffic_controller_ch_4_5:clk, traffic_controller_ch_6_7:clk, traffic_controller_ch_8_9:clk]
	signal master_avalon_universal_master_0_waitrequest                                         : std_logic;                     -- mm_interconnect_0:master_avalon_universal_master_0_waitrequest -> master:uav_waitrequest
	signal master_avalon_universal_master_0_readdata                                            : std_logic_vector(31 downto 0); -- mm_interconnect_0:master_avalon_universal_master_0_readdata -> master:uav_readdata
	signal master_avalon_universal_master_0_debugaccess                                         : std_logic;                     -- master:uav_debugaccess -> mm_interconnect_0:master_avalon_universal_master_0_debugaccess
	signal master_avalon_universal_master_0_address                                             : std_logic_vector(31 downto 0); -- master:uav_address -> mm_interconnect_0:master_avalon_universal_master_0_address
	signal master_avalon_universal_master_0_read                                                : std_logic;                     -- master:uav_read -> mm_interconnect_0:master_avalon_universal_master_0_read
	signal master_avalon_universal_master_0_byteenable                                          : std_logic_vector(3 downto 0);  -- master:uav_byteenable -> mm_interconnect_0:master_avalon_universal_master_0_byteenable
	signal master_avalon_universal_master_0_readdatavalid                                       : std_logic;                     -- mm_interconnect_0:master_avalon_universal_master_0_readdatavalid -> master:uav_readdatavalid
	signal master_avalon_universal_master_0_lock                                                : std_logic;                     -- master:uav_lock -> mm_interconnect_0:master_avalon_universal_master_0_lock
	signal master_avalon_universal_master_0_write                                               : std_logic;                     -- master:uav_write -> mm_interconnect_0:master_avalon_universal_master_0_write
	signal master_avalon_universal_master_0_writedata                                           : std_logic_vector(31 downto 0); -- master:uav_writedata -> mm_interconnect_0:master_avalon_universal_master_0_writedata
	signal master_avalon_universal_master_0_burstcount                                          : std_logic_vector(2 downto 0);  -- master:uav_burstcount -> mm_interconnect_0:master_avalon_universal_master_0_burstcount
	signal mm_interconnect_0_multi_channel_avalon_universal_slave_0_readdata                    : std_logic_vector(31 downto 0); -- multi_channel:uav_readdata -> mm_interconnect_0:multi_channel_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_multi_channel_avalon_universal_slave_0_waitrequest                 : std_logic;                     -- multi_channel:uav_waitrequest -> mm_interconnect_0:multi_channel_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_multi_channel_avalon_universal_slave_0_debugaccess                 : std_logic;                     -- mm_interconnect_0:multi_channel_avalon_universal_slave_0_debugaccess -> multi_channel:uav_debugaccess
	signal mm_interconnect_0_multi_channel_avalon_universal_slave_0_address                     : std_logic_vector(19 downto 0); -- mm_interconnect_0:multi_channel_avalon_universal_slave_0_address -> multi_channel:uav_address
	signal mm_interconnect_0_multi_channel_avalon_universal_slave_0_read                        : std_logic;                     -- mm_interconnect_0:multi_channel_avalon_universal_slave_0_read -> multi_channel:uav_read
	signal mm_interconnect_0_multi_channel_avalon_universal_slave_0_byteenable                  : std_logic_vector(3 downto 0);  -- mm_interconnect_0:multi_channel_avalon_universal_slave_0_byteenable -> multi_channel:uav_byteenable
	signal mm_interconnect_0_multi_channel_avalon_universal_slave_0_readdatavalid               : std_logic;                     -- multi_channel:uav_readdatavalid -> mm_interconnect_0:multi_channel_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_multi_channel_avalon_universal_slave_0_lock                        : std_logic;                     -- mm_interconnect_0:multi_channel_avalon_universal_slave_0_lock -> multi_channel:uav_lock
	signal mm_interconnect_0_multi_channel_avalon_universal_slave_0_write                       : std_logic;                     -- mm_interconnect_0:multi_channel_avalon_universal_slave_0_write -> multi_channel:uav_write
	signal mm_interconnect_0_multi_channel_avalon_universal_slave_0_writedata                   : std_logic_vector(31 downto 0); -- mm_interconnect_0:multi_channel_avalon_universal_slave_0_writedata -> multi_channel:uav_writedata
	signal mm_interconnect_0_multi_channel_avalon_universal_slave_0_burstcount                  : std_logic_vector(2 downto 0);  -- mm_interconnect_0:multi_channel_avalon_universal_slave_0_burstcount -> multi_channel:uav_burstcount
	signal mm_interconnect_0_mm_clock_crossing_bridge_s0_readdata                               : std_logic_vector(31 downto 0); -- mm_clock_crossing_bridge:s0_readdata -> mm_interconnect_0:mm_clock_crossing_bridge_s0_readdata
	signal mm_interconnect_0_mm_clock_crossing_bridge_s0_waitrequest                            : std_logic;                     -- mm_clock_crossing_bridge:s0_waitrequest -> mm_interconnect_0:mm_clock_crossing_bridge_s0_waitrequest
	signal mm_interconnect_0_mm_clock_crossing_bridge_s0_debugaccess                            : std_logic;                     -- mm_interconnect_0:mm_clock_crossing_bridge_s0_debugaccess -> mm_clock_crossing_bridge:s0_debugaccess
	signal mm_interconnect_0_mm_clock_crossing_bridge_s0_address                                : std_logic_vector(16 downto 0); -- mm_interconnect_0:mm_clock_crossing_bridge_s0_address -> mm_clock_crossing_bridge:s0_address
	signal mm_interconnect_0_mm_clock_crossing_bridge_s0_read                                   : std_logic;                     -- mm_interconnect_0:mm_clock_crossing_bridge_s0_read -> mm_clock_crossing_bridge:s0_read
	signal mm_interconnect_0_mm_clock_crossing_bridge_s0_byteenable                             : std_logic_vector(3 downto 0);  -- mm_interconnect_0:mm_clock_crossing_bridge_s0_byteenable -> mm_clock_crossing_bridge:s0_byteenable
	signal mm_interconnect_0_mm_clock_crossing_bridge_s0_readdatavalid                          : std_logic;                     -- mm_clock_crossing_bridge:s0_readdatavalid -> mm_interconnect_0:mm_clock_crossing_bridge_s0_readdatavalid
	signal mm_interconnect_0_mm_clock_crossing_bridge_s0_write                                  : std_logic;                     -- mm_interconnect_0:mm_clock_crossing_bridge_s0_write -> mm_clock_crossing_bridge:s0_write
	signal mm_interconnect_0_mm_clock_crossing_bridge_s0_writedata                              : std_logic_vector(31 downto 0); -- mm_interconnect_0:mm_clock_crossing_bridge_s0_writedata -> mm_clock_crossing_bridge:s0_writedata
	signal mm_interconnect_0_mm_clock_crossing_bridge_s0_burstcount                             : std_logic_vector(0 downto 0);  -- mm_interconnect_0:mm_clock_crossing_bridge_s0_burstcount -> mm_clock_crossing_bridge:s0_burstcount
	signal mm_clock_crossing_bridge_m0_waitrequest                                              : std_logic;                     -- mm_interconnect_1:mm_clock_crossing_bridge_m0_waitrequest -> mm_clock_crossing_bridge:m0_waitrequest
	signal mm_clock_crossing_bridge_m0_readdata                                                 : std_logic_vector(31 downto 0); -- mm_interconnect_1:mm_clock_crossing_bridge_m0_readdata -> mm_clock_crossing_bridge:m0_readdata
	signal mm_clock_crossing_bridge_m0_debugaccess                                              : std_logic;                     -- mm_clock_crossing_bridge:m0_debugaccess -> mm_interconnect_1:mm_clock_crossing_bridge_m0_debugaccess
	signal mm_clock_crossing_bridge_m0_address                                                  : std_logic_vector(16 downto 0); -- mm_clock_crossing_bridge:m0_address -> mm_interconnect_1:mm_clock_crossing_bridge_m0_address
	signal mm_clock_crossing_bridge_m0_read                                                     : std_logic;                     -- mm_clock_crossing_bridge:m0_read -> mm_interconnect_1:mm_clock_crossing_bridge_m0_read
	signal mm_clock_crossing_bridge_m0_byteenable                                               : std_logic_vector(3 downto 0);  -- mm_clock_crossing_bridge:m0_byteenable -> mm_interconnect_1:mm_clock_crossing_bridge_m0_byteenable
	signal mm_clock_crossing_bridge_m0_readdatavalid                                            : std_logic;                     -- mm_interconnect_1:mm_clock_crossing_bridge_m0_readdatavalid -> mm_clock_crossing_bridge:m0_readdatavalid
	signal mm_clock_crossing_bridge_m0_writedata                                                : std_logic_vector(31 downto 0); -- mm_clock_crossing_bridge:m0_writedata -> mm_interconnect_1:mm_clock_crossing_bridge_m0_writedata
	signal mm_clock_crossing_bridge_m0_write                                                    : std_logic;                     -- mm_clock_crossing_bridge:m0_write -> mm_interconnect_1:mm_clock_crossing_bridge_m0_write
	signal mm_clock_crossing_bridge_m0_burstcount                                               : std_logic_vector(0 downto 0);  -- mm_clock_crossing_bridge:m0_burstcount -> mm_interconnect_1:mm_clock_crossing_bridge_m0_burstcount
	signal mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_readdata        : std_logic_vector(31 downto 0); -- traffic_controller_ch_0_1:uav_readdata -> mm_interconnect_1:traffic_controller_ch_0_1_avalon_universal_slave_0_readdata
	signal mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_waitrequest     : std_logic;                     -- traffic_controller_ch_0_1:uav_waitrequest -> mm_interconnect_1:traffic_controller_ch_0_1_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_debugaccess     : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_0_1_avalon_universal_slave_0_debugaccess -> traffic_controller_ch_0_1:uav_debugaccess
	signal mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_address         : std_logic_vector(13 downto 0); -- mm_interconnect_1:traffic_controller_ch_0_1_avalon_universal_slave_0_address -> traffic_controller_ch_0_1:uav_address
	signal mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_read            : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_0_1_avalon_universal_slave_0_read -> traffic_controller_ch_0_1:uav_read
	signal mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_byteenable      : std_logic_vector(3 downto 0);  -- mm_interconnect_1:traffic_controller_ch_0_1_avalon_universal_slave_0_byteenable -> traffic_controller_ch_0_1:uav_byteenable
	signal mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_readdatavalid   : std_logic;                     -- traffic_controller_ch_0_1:uav_readdatavalid -> mm_interconnect_1:traffic_controller_ch_0_1_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_lock            : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_0_1_avalon_universal_slave_0_lock -> traffic_controller_ch_0_1:uav_lock
	signal mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_write           : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_0_1_avalon_universal_slave_0_write -> traffic_controller_ch_0_1:uav_write
	signal mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_writedata       : std_logic_vector(31 downto 0); -- mm_interconnect_1:traffic_controller_ch_0_1_avalon_universal_slave_0_writedata -> traffic_controller_ch_0_1:uav_writedata
	signal mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_burstcount      : std_logic_vector(2 downto 0);  -- mm_interconnect_1:traffic_controller_ch_0_1_avalon_universal_slave_0_burstcount -> traffic_controller_ch_0_1:uav_burstcount
	signal mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_readdata        : std_logic_vector(31 downto 0); -- traffic_controller_ch_2_3:uav_readdata -> mm_interconnect_1:traffic_controller_ch_2_3_avalon_universal_slave_0_readdata
	signal mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_waitrequest     : std_logic;                     -- traffic_controller_ch_2_3:uav_waitrequest -> mm_interconnect_1:traffic_controller_ch_2_3_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_debugaccess     : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_2_3_avalon_universal_slave_0_debugaccess -> traffic_controller_ch_2_3:uav_debugaccess
	signal mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_address         : std_logic_vector(13 downto 0); -- mm_interconnect_1:traffic_controller_ch_2_3_avalon_universal_slave_0_address -> traffic_controller_ch_2_3:uav_address
	signal mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_read            : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_2_3_avalon_universal_slave_0_read -> traffic_controller_ch_2_3:uav_read
	signal mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_byteenable      : std_logic_vector(3 downto 0);  -- mm_interconnect_1:traffic_controller_ch_2_3_avalon_universal_slave_0_byteenable -> traffic_controller_ch_2_3:uav_byteenable
	signal mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_readdatavalid   : std_logic;                     -- traffic_controller_ch_2_3:uav_readdatavalid -> mm_interconnect_1:traffic_controller_ch_2_3_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_lock            : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_2_3_avalon_universal_slave_0_lock -> traffic_controller_ch_2_3:uav_lock
	signal mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_write           : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_2_3_avalon_universal_slave_0_write -> traffic_controller_ch_2_3:uav_write
	signal mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_writedata       : std_logic_vector(31 downto 0); -- mm_interconnect_1:traffic_controller_ch_2_3_avalon_universal_slave_0_writedata -> traffic_controller_ch_2_3:uav_writedata
	signal mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_burstcount      : std_logic_vector(2 downto 0);  -- mm_interconnect_1:traffic_controller_ch_2_3_avalon_universal_slave_0_burstcount -> traffic_controller_ch_2_3:uav_burstcount
	signal mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_readdata        : std_logic_vector(31 downto 0); -- traffic_controller_ch_4_5:uav_readdata -> mm_interconnect_1:traffic_controller_ch_4_5_avalon_universal_slave_0_readdata
	signal mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_waitrequest     : std_logic;                     -- traffic_controller_ch_4_5:uav_waitrequest -> mm_interconnect_1:traffic_controller_ch_4_5_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_debugaccess     : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_4_5_avalon_universal_slave_0_debugaccess -> traffic_controller_ch_4_5:uav_debugaccess
	signal mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_address         : std_logic_vector(13 downto 0); -- mm_interconnect_1:traffic_controller_ch_4_5_avalon_universal_slave_0_address -> traffic_controller_ch_4_5:uav_address
	signal mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_read            : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_4_5_avalon_universal_slave_0_read -> traffic_controller_ch_4_5:uav_read
	signal mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_byteenable      : std_logic_vector(3 downto 0);  -- mm_interconnect_1:traffic_controller_ch_4_5_avalon_universal_slave_0_byteenable -> traffic_controller_ch_4_5:uav_byteenable
	signal mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_readdatavalid   : std_logic;                     -- traffic_controller_ch_4_5:uav_readdatavalid -> mm_interconnect_1:traffic_controller_ch_4_5_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_lock            : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_4_5_avalon_universal_slave_0_lock -> traffic_controller_ch_4_5:uav_lock
	signal mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_write           : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_4_5_avalon_universal_slave_0_write -> traffic_controller_ch_4_5:uav_write
	signal mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_writedata       : std_logic_vector(31 downto 0); -- mm_interconnect_1:traffic_controller_ch_4_5_avalon_universal_slave_0_writedata -> traffic_controller_ch_4_5:uav_writedata
	signal mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_burstcount      : std_logic_vector(2 downto 0);  -- mm_interconnect_1:traffic_controller_ch_4_5_avalon_universal_slave_0_burstcount -> traffic_controller_ch_4_5:uav_burstcount
	signal mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_readdata        : std_logic_vector(31 downto 0); -- traffic_controller_ch_6_7:uav_readdata -> mm_interconnect_1:traffic_controller_ch_6_7_avalon_universal_slave_0_readdata
	signal mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_waitrequest     : std_logic;                     -- traffic_controller_ch_6_7:uav_waitrequest -> mm_interconnect_1:traffic_controller_ch_6_7_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_debugaccess     : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_6_7_avalon_universal_slave_0_debugaccess -> traffic_controller_ch_6_7:uav_debugaccess
	signal mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_address         : std_logic_vector(13 downto 0); -- mm_interconnect_1:traffic_controller_ch_6_7_avalon_universal_slave_0_address -> traffic_controller_ch_6_7:uav_address
	signal mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_read            : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_6_7_avalon_universal_slave_0_read -> traffic_controller_ch_6_7:uav_read
	signal mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_byteenable      : std_logic_vector(3 downto 0);  -- mm_interconnect_1:traffic_controller_ch_6_7_avalon_universal_slave_0_byteenable -> traffic_controller_ch_6_7:uav_byteenable
	signal mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_readdatavalid   : std_logic;                     -- traffic_controller_ch_6_7:uav_readdatavalid -> mm_interconnect_1:traffic_controller_ch_6_7_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_lock            : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_6_7_avalon_universal_slave_0_lock -> traffic_controller_ch_6_7:uav_lock
	signal mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_write           : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_6_7_avalon_universal_slave_0_write -> traffic_controller_ch_6_7:uav_write
	signal mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_writedata       : std_logic_vector(31 downto 0); -- mm_interconnect_1:traffic_controller_ch_6_7_avalon_universal_slave_0_writedata -> traffic_controller_ch_6_7:uav_writedata
	signal mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_burstcount      : std_logic_vector(2 downto 0);  -- mm_interconnect_1:traffic_controller_ch_6_7_avalon_universal_slave_0_burstcount -> traffic_controller_ch_6_7:uav_burstcount
	signal mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_readdata        : std_logic_vector(31 downto 0); -- traffic_controller_ch_8_9:uav_readdata -> mm_interconnect_1:traffic_controller_ch_8_9_avalon_universal_slave_0_readdata
	signal mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_waitrequest     : std_logic;                     -- traffic_controller_ch_8_9:uav_waitrequest -> mm_interconnect_1:traffic_controller_ch_8_9_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_debugaccess     : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_8_9_avalon_universal_slave_0_debugaccess -> traffic_controller_ch_8_9:uav_debugaccess
	signal mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_address         : std_logic_vector(13 downto 0); -- mm_interconnect_1:traffic_controller_ch_8_9_avalon_universal_slave_0_address -> traffic_controller_ch_8_9:uav_address
	signal mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_read            : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_8_9_avalon_universal_slave_0_read -> traffic_controller_ch_8_9:uav_read
	signal mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_byteenable      : std_logic_vector(3 downto 0);  -- mm_interconnect_1:traffic_controller_ch_8_9_avalon_universal_slave_0_byteenable -> traffic_controller_ch_8_9:uav_byteenable
	signal mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_readdatavalid   : std_logic;                     -- traffic_controller_ch_8_9:uav_readdatavalid -> mm_interconnect_1:traffic_controller_ch_8_9_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_lock            : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_8_9_avalon_universal_slave_0_lock -> traffic_controller_ch_8_9:uav_lock
	signal mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_write           : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_8_9_avalon_universal_slave_0_write -> traffic_controller_ch_8_9:uav_write
	signal mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_writedata       : std_logic_vector(31 downto 0); -- mm_interconnect_1:traffic_controller_ch_8_9_avalon_universal_slave_0_writedata -> traffic_controller_ch_8_9:uav_writedata
	signal mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_burstcount      : std_logic_vector(2 downto 0);  -- mm_interconnect_1:traffic_controller_ch_8_9_avalon_universal_slave_0_burstcount -> traffic_controller_ch_8_9:uav_burstcount
	signal mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_readdata      : std_logic_vector(31 downto 0); -- traffic_controller_ch_10_11:uav_readdata -> mm_interconnect_1:traffic_controller_ch_10_11_avalon_universal_slave_0_readdata
	signal mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_waitrequest   : std_logic;                     -- traffic_controller_ch_10_11:uav_waitrequest -> mm_interconnect_1:traffic_controller_ch_10_11_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_debugaccess   : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_10_11_avalon_universal_slave_0_debugaccess -> traffic_controller_ch_10_11:uav_debugaccess
	signal mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_address       : std_logic_vector(13 downto 0); -- mm_interconnect_1:traffic_controller_ch_10_11_avalon_universal_slave_0_address -> traffic_controller_ch_10_11:uav_address
	signal mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_read          : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_10_11_avalon_universal_slave_0_read -> traffic_controller_ch_10_11:uav_read
	signal mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_byteenable    : std_logic_vector(3 downto 0);  -- mm_interconnect_1:traffic_controller_ch_10_11_avalon_universal_slave_0_byteenable -> traffic_controller_ch_10_11:uav_byteenable
	signal mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_readdatavalid : std_logic;                     -- traffic_controller_ch_10_11:uav_readdatavalid -> mm_interconnect_1:traffic_controller_ch_10_11_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_lock          : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_10_11_avalon_universal_slave_0_lock -> traffic_controller_ch_10_11:uav_lock
	signal mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_write         : std_logic;                     -- mm_interconnect_1:traffic_controller_ch_10_11_avalon_universal_slave_0_write -> traffic_controller_ch_10_11:uav_write
	signal mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_writedata     : std_logic_vector(31 downto 0); -- mm_interconnect_1:traffic_controller_ch_10_11_avalon_universal_slave_0_writedata -> traffic_controller_ch_10_11:uav_writedata
	signal mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_burstcount    : std_logic_vector(2 downto 0);  -- mm_interconnect_1:traffic_controller_ch_10_11_avalon_universal_slave_0_burstcount -> traffic_controller_ch_10_11:uav_burstcount
	signal rst_controller_reset_out_reset                                                       : std_logic;                     -- rst_controller:reset_out -> [master:reset, mm_clock_crossing_bridge:s0_reset, mm_interconnect_0:master_reset_reset_bridge_in_reset_reset, multi_channel:reset]
	signal csr_clk_clk_reset_reset                                                              : std_logic;                     -- csr_clk:reset_n_out -> csr_clk_clk_reset_reset:in
	signal rst_controller_001_reset_out_reset                                                   : std_logic;                     -- rst_controller_001:reset_out -> [mm_clock_crossing_bridge:m0_reset, mm_interconnect_1:mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset, traffic_controller_ch_0_1:reset, traffic_controller_ch_10_11:reset, traffic_controller_ch_2_3:reset, traffic_controller_ch_4_5:reset, traffic_controller_ch_6_7:reset, traffic_controller_ch_8_9:reset]
	signal mac_clk_clk_reset_reset                                                              : std_logic;                     -- mac_clk:reset_n_out -> mac_clk_clk_reset_reset:in
	signal csr_clk_clk_reset_reset_ports_inv                                                    : std_logic;                     -- csr_clk_clk_reset_reset:inv -> rst_controller:reset_in0
	signal mac_clk_clk_reset_reset_ports_inv                                                    : std_logic;                     -- mac_clk_clk_reset_reset:inv -> rst_controller_001:reset_in0

	for csr_clk : address_decoder_top_csr_clk_cmp
		use entity address_decoder_top_csr_clk.address_decoder_top_csr_clk;
	for mac_clk : address_decoder_top_mac_clk_cmp
		use entity address_decoder_top_mac_clk.address_decoder_top_mac_clk;
	for master : address_decoder_top_master_cmp
		use entity address_decoder_top_master.address_decoder_top_master;
	for mm_clock_crossing_bridge : address_decoder_top_mm_clock_crossing_bridge_cmp
		use entity address_decoder_top_mm_clock_crossing_bridge.address_decoder_top_mm_clock_crossing_bridge;
	for multi_channel : address_decoder_top_multi_channel_cmp
		use entity address_decoder_top_multi_channel.address_decoder_top_multi_channel;
	for traffic_controller_ch_0_1 : address_decoder_top_traffic_controller_ch_0_1_cmp
		use entity address_decoder_top_traffic_controller_ch_0_1.address_decoder_top_traffic_controller_ch_0_1;
	for traffic_controller_ch_10_11 : address_decoder_top_traffic_controller_ch_10_11_cmp
		use entity address_decoder_top_traffic_controller_ch_10_11.address_decoder_top_traffic_controller_ch_10_11;
	for traffic_controller_ch_2_3 : address_decoder_top_traffic_controller_ch_2_3_cmp
		use entity address_decoder_top_traffic_controller_ch_2_3.address_decoder_top_traffic_controller_ch_2_3;
	for traffic_controller_ch_4_5 : address_decoder_top_traffic_controller_ch_4_5_cmp
		use entity address_decoder_top_traffic_controller_ch_4_5.address_decoder_top_traffic_controller_ch_4_5;
	for traffic_controller_ch_6_7 : address_decoder_top_traffic_controller_ch_6_7_cmp
		use entity address_decoder_top_traffic_controller_ch_6_7.address_decoder_top_traffic_controller_ch_6_7;
	for traffic_controller_ch_8_9 : address_decoder_top_traffic_controller_ch_8_9_cmp
		use entity address_decoder_top_traffic_controller_ch_8_9.address_decoder_top_traffic_controller_ch_8_9;
	for mm_interconnect_0 : address_decoder_top_altera_mm_interconnect_191_3kbf4ri_cmp
		use entity altera_mm_interconnect_191.address_decoder_top_altera_mm_interconnect_191_3kbf4ri;
	for mm_interconnect_1 : address_decoder_top_altera_mm_interconnect_191_fv6bu5i_cmp
		use entity altera_mm_interconnect_191.address_decoder_top_altera_mm_interconnect_191_fv6bu5i;
	for rst_controller : altera_reset_controller_cmp
		use entity altera_reset_controller_191.altera_reset_controller;
	for rst_controller_001 : altera_reset_controller_cmp
		use entity altera_reset_controller_191.altera_reset_controller;
begin

	csr_clk : component address_decoder_top_csr_clk_cmp
		port map (
			clk_out     => csr_clk_clk_clk,         --          clk.clk
			in_clk      => csr_clk_clk,             --       clk_in.clk
			reset_n     => csr_clk_reset_reset_n,   -- clk_in_reset.reset_n
			reset_n_out => csr_clk_clk_reset_reset  --    clk_reset.reset_n
		);

	mac_clk : component address_decoder_top_mac_clk_cmp
		port map (
			clk_out     => mac_clk_clk_clk,         --          clk.clk
			in_clk      => mac_clk_clk,             --       clk_in.clk
			reset_n     => mac_clk_reset_reset_n,   -- clk_in_reset.reset_n
			reset_n_out => mac_clk_clk_reset_reset  --    clk_reset.reset_n
		);

	master : component address_decoder_top_master_cmp
		port map (
			av_address        => slave_address,                                  --      avalon_anti_master_0.address
			av_waitrequest    => slave_waitrequest,                              --                          .waitrequest
			av_read           => slave_read,                                     --                          .read
			av_readdata       => slave_readdata,                                 --                          .readdata
			av_readdatavalid  => slave_readdatavalid,                            --                          .readdatavalid
			av_write          => slave_write,                                    --                          .write
			av_writedata      => slave_writedata,                                --                          .writedata
			uav_address       => master_avalon_universal_master_0_address,       -- avalon_universal_master_0.address
			uav_burstcount    => master_avalon_universal_master_0_burstcount,    --                          .burstcount
			uav_read          => master_avalon_universal_master_0_read,          --                          .read
			uav_write         => master_avalon_universal_master_0_write,         --                          .write
			uav_waitrequest   => master_avalon_universal_master_0_waitrequest,   --                          .waitrequest
			uav_readdatavalid => master_avalon_universal_master_0_readdatavalid, --                          .readdatavalid
			uav_byteenable    => master_avalon_universal_master_0_byteenable,    --                          .byteenable
			uav_readdata      => master_avalon_universal_master_0_readdata,      --                          .readdata
			uav_writedata     => master_avalon_universal_master_0_writedata,     --                          .writedata
			uav_lock          => master_avalon_universal_master_0_lock,          --                          .lock
			uav_debugaccess   => master_avalon_universal_master_0_debugaccess,   --                          .debugaccess
			clk               => csr_clk_clk_clk,                                --                       clk.clk
			reset             => rst_controller_reset_out_reset                  --                     reset.reset
		);

	mm_clock_crossing_bridge : component address_decoder_top_mm_clock_crossing_bridge_cmp
		port map (
			m0_waitrequest   => mm_clock_crossing_bridge_m0_waitrequest,                     --       m0.waitrequest
			m0_readdata      => mm_clock_crossing_bridge_m0_readdata,                        --         .readdata
			m0_readdatavalid => mm_clock_crossing_bridge_m0_readdatavalid,                   --         .readdatavalid
			m0_burstcount    => mm_clock_crossing_bridge_m0_burstcount,                      --         .burstcount
			m0_writedata     => mm_clock_crossing_bridge_m0_writedata,                       --         .writedata
			m0_address       => mm_clock_crossing_bridge_m0_address,                         --         .address
			m0_write         => mm_clock_crossing_bridge_m0_write,                           --         .write
			m0_read          => mm_clock_crossing_bridge_m0_read,                            --         .read
			m0_byteenable    => mm_clock_crossing_bridge_m0_byteenable,                      --         .byteenable
			m0_debugaccess   => mm_clock_crossing_bridge_m0_debugaccess,                     --         .debugaccess
			m0_clk           => mac_clk_clk_clk,                                             --   m0_clk.clk
			m0_reset         => rst_controller_001_reset_out_reset,                          -- m0_reset.reset
			s0_waitrequest   => mm_interconnect_0_mm_clock_crossing_bridge_s0_waitrequest,   --       s0.waitrequest
			s0_readdata      => mm_interconnect_0_mm_clock_crossing_bridge_s0_readdata,      --         .readdata
			s0_readdatavalid => mm_interconnect_0_mm_clock_crossing_bridge_s0_readdatavalid, --         .readdatavalid
			s0_burstcount    => mm_interconnect_0_mm_clock_crossing_bridge_s0_burstcount,    --         .burstcount
			s0_writedata     => mm_interconnect_0_mm_clock_crossing_bridge_s0_writedata,     --         .writedata
			s0_address       => mm_interconnect_0_mm_clock_crossing_bridge_s0_address,       --         .address
			s0_write         => mm_interconnect_0_mm_clock_crossing_bridge_s0_write,         --         .write
			s0_read          => mm_interconnect_0_mm_clock_crossing_bridge_s0_read,          --         .read
			s0_byteenable    => mm_interconnect_0_mm_clock_crossing_bridge_s0_byteenable,    --         .byteenable
			s0_debugaccess   => mm_interconnect_0_mm_clock_crossing_bridge_s0_debugaccess,   --         .debugaccess
			s0_clk           => csr_clk_clk_clk,                                             --   s0_clk.clk
			s0_reset         => rst_controller_reset_out_reset                               -- s0_reset.reset
		);

	multi_channel : component address_decoder_top_multi_channel_cmp
		port map (
			av_address        => multi_channel_address,                                                  --      avalon_anti_slave_0.address
			av_write          => multi_channel_write,                                                    --                         .write
			av_read           => multi_channel_read,                                                     --                         .read
			av_readdata       => multi_channel_readdata,                                                 --                         .readdata
			av_writedata      => multi_channel_writedata,                                                --                         .writedata
			av_waitrequest    => multi_channel_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_0_multi_channel_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_0_multi_channel_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_0_multi_channel_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_0_multi_channel_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_0_multi_channel_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_0_multi_channel_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_0_multi_channel_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_0_multi_channel_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_0_multi_channel_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_0_multi_channel_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_0_multi_channel_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => csr_clk_clk_clk,                                                        --                      clk.clk
			reset             => rst_controller_reset_out_reset                                          --                    reset.reset
		);

	traffic_controller_ch_0_1 : component address_decoder_top_traffic_controller_ch_0_1_cmp
		port map (
			av_address        => traffic_controller_ch_0_1_address,                                                  --      avalon_anti_slave_0.address
			av_write          => traffic_controller_ch_0_1_write,                                                    --                         .write
			av_read           => traffic_controller_ch_0_1_read,                                                     --                         .read
			av_readdata       => traffic_controller_ch_0_1_readdata,                                                 --                         .readdata
			av_writedata      => traffic_controller_ch_0_1_writedata,                                                --                         .writedata
			av_waitrequest    => traffic_controller_ch_0_1_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => mac_clk_clk_clk,                                                                    --                      clk.clk
			reset             => rst_controller_001_reset_out_reset                                                  --                    reset.reset
		);

	traffic_controller_ch_10_11 : component address_decoder_top_traffic_controller_ch_10_11_cmp
		port map (
			av_address        => traffic_controller_ch_10_11_address,                                                  --      avalon_anti_slave_0.address
			av_write          => traffic_controller_ch_10_11_write,                                                    --                         .write
			av_read           => traffic_controller_ch_10_11_read,                                                     --                         .read
			av_readdata       => traffic_controller_ch_10_11_readdata,                                                 --                         .readdata
			av_writedata      => traffic_controller_ch_10_11_writedata,                                                --                         .writedata
			av_waitrequest    => traffic_controller_ch_10_11_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => mac_clk_clk_clk,                                                                      --                      clk.clk
			reset             => rst_controller_001_reset_out_reset                                                    --                    reset.reset
		);

	traffic_controller_ch_2_3 : component address_decoder_top_traffic_controller_ch_2_3_cmp
		port map (
			av_address        => traffic_controller_ch_2_3_address,                                                  --      avalon_anti_slave_0.address
			av_write          => traffic_controller_ch_2_3_write,                                                    --                         .write
			av_read           => traffic_controller_ch_2_3_read,                                                     --                         .read
			av_readdata       => traffic_controller_ch_2_3_readdata,                                                 --                         .readdata
			av_writedata      => traffic_controller_ch_2_3_writedata,                                                --                         .writedata
			av_waitrequest    => traffic_controller_ch_2_3_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => mac_clk_clk_clk,                                                                    --                      clk.clk
			reset             => rst_controller_001_reset_out_reset                                                  --                    reset.reset
		);

	traffic_controller_ch_4_5 : component address_decoder_top_traffic_controller_ch_4_5_cmp
		port map (
			av_address        => traffic_controller_ch_4_5_address,                                                  --      avalon_anti_slave_0.address
			av_write          => traffic_controller_ch_4_5_write,                                                    --                         .write
			av_read           => traffic_controller_ch_4_5_read,                                                     --                         .read
			av_readdata       => traffic_controller_ch_4_5_readdata,                                                 --                         .readdata
			av_writedata      => traffic_controller_ch_4_5_writedata,                                                --                         .writedata
			av_waitrequest    => traffic_controller_ch_4_5_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => mac_clk_clk_clk,                                                                    --                      clk.clk
			reset             => rst_controller_001_reset_out_reset                                                  --                    reset.reset
		);

	traffic_controller_ch_6_7 : component address_decoder_top_traffic_controller_ch_6_7_cmp
		port map (
			av_address        => traffic_controller_ch_6_7_address,                                                  --      avalon_anti_slave_0.address
			av_write          => traffic_controller_ch_6_7_write,                                                    --                         .write
			av_read           => traffic_controller_ch_6_7_read,                                                     --                         .read
			av_readdata       => traffic_controller_ch_6_7_readdata,                                                 --                         .readdata
			av_writedata      => traffic_controller_ch_6_7_writedata,                                                --                         .writedata
			av_waitrequest    => traffic_controller_ch_6_7_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => mac_clk_clk_clk,                                                                    --                      clk.clk
			reset             => rst_controller_001_reset_out_reset                                                  --                    reset.reset
		);

	traffic_controller_ch_8_9 : component address_decoder_top_traffic_controller_ch_8_9_cmp
		port map (
			av_address        => traffic_controller_ch_8_9_address,                                                  --      avalon_anti_slave_0.address
			av_write          => traffic_controller_ch_8_9_write,                                                    --                         .write
			av_read           => traffic_controller_ch_8_9_read,                                                     --                         .read
			av_readdata       => traffic_controller_ch_8_9_readdata,                                                 --                         .readdata
			av_writedata      => traffic_controller_ch_8_9_writedata,                                                --                         .writedata
			av_waitrequest    => traffic_controller_ch_8_9_waitrequest,                                              --                         .waitrequest
			uav_address       => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount    => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read          => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_read,          --                         .read
			uav_write         => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest   => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable    => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata      => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata     => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock          => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess   => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			clk               => mac_clk_clk_clk,                                                                    --                      clk.clk
			reset             => rst_controller_001_reset_out_reset                                                  --                    reset.reset
		);

	mm_interconnect_0 : component address_decoder_top_altera_mm_interconnect_191_3kbf4ri_cmp
		port map (
			master_avalon_universal_master_0_address             => master_avalon_universal_master_0_address,                               --       master_avalon_universal_master_0.address
			master_avalon_universal_master_0_waitrequest         => master_avalon_universal_master_0_waitrequest,                           --                                       .waitrequest
			master_avalon_universal_master_0_burstcount          => master_avalon_universal_master_0_burstcount,                            --                                       .burstcount
			master_avalon_universal_master_0_byteenable          => master_avalon_universal_master_0_byteenable,                            --                                       .byteenable
			master_avalon_universal_master_0_read                => master_avalon_universal_master_0_read,                                  --                                       .read
			master_avalon_universal_master_0_readdata            => master_avalon_universal_master_0_readdata,                              --                                       .readdata
			master_avalon_universal_master_0_readdatavalid       => master_avalon_universal_master_0_readdatavalid,                         --                                       .readdatavalid
			master_avalon_universal_master_0_write               => master_avalon_universal_master_0_write,                                 --                                       .write
			master_avalon_universal_master_0_writedata           => master_avalon_universal_master_0_writedata,                             --                                       .writedata
			master_avalon_universal_master_0_lock                => master_avalon_universal_master_0_lock,                                  --                                       .lock
			master_avalon_universal_master_0_debugaccess         => master_avalon_universal_master_0_debugaccess,                           --                                       .debugaccess
			multi_channel_avalon_universal_slave_0_address       => mm_interconnect_0_multi_channel_avalon_universal_slave_0_address,       -- multi_channel_avalon_universal_slave_0.address
			multi_channel_avalon_universal_slave_0_write         => mm_interconnect_0_multi_channel_avalon_universal_slave_0_write,         --                                       .write
			multi_channel_avalon_universal_slave_0_read          => mm_interconnect_0_multi_channel_avalon_universal_slave_0_read,          --                                       .read
			multi_channel_avalon_universal_slave_0_readdata      => mm_interconnect_0_multi_channel_avalon_universal_slave_0_readdata,      --                                       .readdata
			multi_channel_avalon_universal_slave_0_writedata     => mm_interconnect_0_multi_channel_avalon_universal_slave_0_writedata,     --                                       .writedata
			multi_channel_avalon_universal_slave_0_burstcount    => mm_interconnect_0_multi_channel_avalon_universal_slave_0_burstcount,    --                                       .burstcount
			multi_channel_avalon_universal_slave_0_byteenable    => mm_interconnect_0_multi_channel_avalon_universal_slave_0_byteenable,    --                                       .byteenable
			multi_channel_avalon_universal_slave_0_readdatavalid => mm_interconnect_0_multi_channel_avalon_universal_slave_0_readdatavalid, --                                       .readdatavalid
			multi_channel_avalon_universal_slave_0_waitrequest   => mm_interconnect_0_multi_channel_avalon_universal_slave_0_waitrequest,   --                                       .waitrequest
			multi_channel_avalon_universal_slave_0_lock          => mm_interconnect_0_multi_channel_avalon_universal_slave_0_lock,          --                                       .lock
			multi_channel_avalon_universal_slave_0_debugaccess   => mm_interconnect_0_multi_channel_avalon_universal_slave_0_debugaccess,   --                                       .debugaccess
			mm_clock_crossing_bridge_s0_address                  => mm_interconnect_0_mm_clock_crossing_bridge_s0_address,                  --            mm_clock_crossing_bridge_s0.address
			mm_clock_crossing_bridge_s0_write                    => mm_interconnect_0_mm_clock_crossing_bridge_s0_write,                    --                                       .write
			mm_clock_crossing_bridge_s0_read                     => mm_interconnect_0_mm_clock_crossing_bridge_s0_read,                     --                                       .read
			mm_clock_crossing_bridge_s0_readdata                 => mm_interconnect_0_mm_clock_crossing_bridge_s0_readdata,                 --                                       .readdata
			mm_clock_crossing_bridge_s0_writedata                => mm_interconnect_0_mm_clock_crossing_bridge_s0_writedata,                --                                       .writedata
			mm_clock_crossing_bridge_s0_burstcount               => mm_interconnect_0_mm_clock_crossing_bridge_s0_burstcount,               --                                       .burstcount
			mm_clock_crossing_bridge_s0_byteenable               => mm_interconnect_0_mm_clock_crossing_bridge_s0_byteenable,               --                                       .byteenable
			mm_clock_crossing_bridge_s0_readdatavalid            => mm_interconnect_0_mm_clock_crossing_bridge_s0_readdatavalid,            --                                       .readdatavalid
			mm_clock_crossing_bridge_s0_waitrequest              => mm_interconnect_0_mm_clock_crossing_bridge_s0_waitrequest,              --                                       .waitrequest
			mm_clock_crossing_bridge_s0_debugaccess              => mm_interconnect_0_mm_clock_crossing_bridge_s0_debugaccess,              --                                       .debugaccess
			master_reset_reset_bridge_in_reset_reset             => rst_controller_reset_out_reset,                                         --     master_reset_reset_bridge_in_reset.reset
			csr_clk_clk_clk                                      => csr_clk_clk_clk                                                         --                            csr_clk_clk.clk
		);

	mm_interconnect_1 : component address_decoder_top_altera_mm_interconnect_191_fv6bu5i_cmp
		port map (
			mm_clock_crossing_bridge_m0_address                                => mm_clock_crossing_bridge_m0_address,                                                  --                             mm_clock_crossing_bridge_m0.address
			mm_clock_crossing_bridge_m0_waitrequest                            => mm_clock_crossing_bridge_m0_waitrequest,                                              --                                                        .waitrequest
			mm_clock_crossing_bridge_m0_burstcount                             => mm_clock_crossing_bridge_m0_burstcount,                                               --                                                        .burstcount
			mm_clock_crossing_bridge_m0_byteenable                             => mm_clock_crossing_bridge_m0_byteenable,                                               --                                                        .byteenable
			mm_clock_crossing_bridge_m0_read                                   => mm_clock_crossing_bridge_m0_read,                                                     --                                                        .read
			mm_clock_crossing_bridge_m0_readdata                               => mm_clock_crossing_bridge_m0_readdata,                                                 --                                                        .readdata
			mm_clock_crossing_bridge_m0_readdatavalid                          => mm_clock_crossing_bridge_m0_readdatavalid,                                            --                                                        .readdatavalid
			mm_clock_crossing_bridge_m0_write                                  => mm_clock_crossing_bridge_m0_write,                                                    --                                                        .write
			mm_clock_crossing_bridge_m0_writedata                              => mm_clock_crossing_bridge_m0_writedata,                                                --                                                        .writedata
			mm_clock_crossing_bridge_m0_debugaccess                            => mm_clock_crossing_bridge_m0_debugaccess,                                              --                                                        .debugaccess
			traffic_controller_ch_0_1_avalon_universal_slave_0_address         => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_address,         --      traffic_controller_ch_0_1_avalon_universal_slave_0.address
			traffic_controller_ch_0_1_avalon_universal_slave_0_write           => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_write,           --                                                        .write
			traffic_controller_ch_0_1_avalon_universal_slave_0_read            => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_read,            --                                                        .read
			traffic_controller_ch_0_1_avalon_universal_slave_0_readdata        => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_readdata,        --                                                        .readdata
			traffic_controller_ch_0_1_avalon_universal_slave_0_writedata       => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_writedata,       --                                                        .writedata
			traffic_controller_ch_0_1_avalon_universal_slave_0_burstcount      => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_burstcount,      --                                                        .burstcount
			traffic_controller_ch_0_1_avalon_universal_slave_0_byteenable      => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_byteenable,      --                                                        .byteenable
			traffic_controller_ch_0_1_avalon_universal_slave_0_readdatavalid   => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_readdatavalid,   --                                                        .readdatavalid
			traffic_controller_ch_0_1_avalon_universal_slave_0_waitrequest     => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_waitrequest,     --                                                        .waitrequest
			traffic_controller_ch_0_1_avalon_universal_slave_0_lock            => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_lock,            --                                                        .lock
			traffic_controller_ch_0_1_avalon_universal_slave_0_debugaccess     => mm_interconnect_1_traffic_controller_ch_0_1_avalon_universal_slave_0_debugaccess,     --                                                        .debugaccess
			traffic_controller_ch_2_3_avalon_universal_slave_0_address         => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_address,         --      traffic_controller_ch_2_3_avalon_universal_slave_0.address
			traffic_controller_ch_2_3_avalon_universal_slave_0_write           => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_write,           --                                                        .write
			traffic_controller_ch_2_3_avalon_universal_slave_0_read            => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_read,            --                                                        .read
			traffic_controller_ch_2_3_avalon_universal_slave_0_readdata        => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_readdata,        --                                                        .readdata
			traffic_controller_ch_2_3_avalon_universal_slave_0_writedata       => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_writedata,       --                                                        .writedata
			traffic_controller_ch_2_3_avalon_universal_slave_0_burstcount      => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_burstcount,      --                                                        .burstcount
			traffic_controller_ch_2_3_avalon_universal_slave_0_byteenable      => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_byteenable,      --                                                        .byteenable
			traffic_controller_ch_2_3_avalon_universal_slave_0_readdatavalid   => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_readdatavalid,   --                                                        .readdatavalid
			traffic_controller_ch_2_3_avalon_universal_slave_0_waitrequest     => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_waitrequest,     --                                                        .waitrequest
			traffic_controller_ch_2_3_avalon_universal_slave_0_lock            => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_lock,            --                                                        .lock
			traffic_controller_ch_2_3_avalon_universal_slave_0_debugaccess     => mm_interconnect_1_traffic_controller_ch_2_3_avalon_universal_slave_0_debugaccess,     --                                                        .debugaccess
			traffic_controller_ch_4_5_avalon_universal_slave_0_address         => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_address,         --      traffic_controller_ch_4_5_avalon_universal_slave_0.address
			traffic_controller_ch_4_5_avalon_universal_slave_0_write           => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_write,           --                                                        .write
			traffic_controller_ch_4_5_avalon_universal_slave_0_read            => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_read,            --                                                        .read
			traffic_controller_ch_4_5_avalon_universal_slave_0_readdata        => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_readdata,        --                                                        .readdata
			traffic_controller_ch_4_5_avalon_universal_slave_0_writedata       => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_writedata,       --                                                        .writedata
			traffic_controller_ch_4_5_avalon_universal_slave_0_burstcount      => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_burstcount,      --                                                        .burstcount
			traffic_controller_ch_4_5_avalon_universal_slave_0_byteenable      => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_byteenable,      --                                                        .byteenable
			traffic_controller_ch_4_5_avalon_universal_slave_0_readdatavalid   => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_readdatavalid,   --                                                        .readdatavalid
			traffic_controller_ch_4_5_avalon_universal_slave_0_waitrequest     => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_waitrequest,     --                                                        .waitrequest
			traffic_controller_ch_4_5_avalon_universal_slave_0_lock            => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_lock,            --                                                        .lock
			traffic_controller_ch_4_5_avalon_universal_slave_0_debugaccess     => mm_interconnect_1_traffic_controller_ch_4_5_avalon_universal_slave_0_debugaccess,     --                                                        .debugaccess
			traffic_controller_ch_6_7_avalon_universal_slave_0_address         => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_address,         --      traffic_controller_ch_6_7_avalon_universal_slave_0.address
			traffic_controller_ch_6_7_avalon_universal_slave_0_write           => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_write,           --                                                        .write
			traffic_controller_ch_6_7_avalon_universal_slave_0_read            => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_read,            --                                                        .read
			traffic_controller_ch_6_7_avalon_universal_slave_0_readdata        => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_readdata,        --                                                        .readdata
			traffic_controller_ch_6_7_avalon_universal_slave_0_writedata       => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_writedata,       --                                                        .writedata
			traffic_controller_ch_6_7_avalon_universal_slave_0_burstcount      => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_burstcount,      --                                                        .burstcount
			traffic_controller_ch_6_7_avalon_universal_slave_0_byteenable      => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_byteenable,      --                                                        .byteenable
			traffic_controller_ch_6_7_avalon_universal_slave_0_readdatavalid   => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_readdatavalid,   --                                                        .readdatavalid
			traffic_controller_ch_6_7_avalon_universal_slave_0_waitrequest     => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_waitrequest,     --                                                        .waitrequest
			traffic_controller_ch_6_7_avalon_universal_slave_0_lock            => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_lock,            --                                                        .lock
			traffic_controller_ch_6_7_avalon_universal_slave_0_debugaccess     => mm_interconnect_1_traffic_controller_ch_6_7_avalon_universal_slave_0_debugaccess,     --                                                        .debugaccess
			traffic_controller_ch_8_9_avalon_universal_slave_0_address         => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_address,         --      traffic_controller_ch_8_9_avalon_universal_slave_0.address
			traffic_controller_ch_8_9_avalon_universal_slave_0_write           => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_write,           --                                                        .write
			traffic_controller_ch_8_9_avalon_universal_slave_0_read            => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_read,            --                                                        .read
			traffic_controller_ch_8_9_avalon_universal_slave_0_readdata        => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_readdata,        --                                                        .readdata
			traffic_controller_ch_8_9_avalon_universal_slave_0_writedata       => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_writedata,       --                                                        .writedata
			traffic_controller_ch_8_9_avalon_universal_slave_0_burstcount      => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_burstcount,      --                                                        .burstcount
			traffic_controller_ch_8_9_avalon_universal_slave_0_byteenable      => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_byteenable,      --                                                        .byteenable
			traffic_controller_ch_8_9_avalon_universal_slave_0_readdatavalid   => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_readdatavalid,   --                                                        .readdatavalid
			traffic_controller_ch_8_9_avalon_universal_slave_0_waitrequest     => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_waitrequest,     --                                                        .waitrequest
			traffic_controller_ch_8_9_avalon_universal_slave_0_lock            => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_lock,            --                                                        .lock
			traffic_controller_ch_8_9_avalon_universal_slave_0_debugaccess     => mm_interconnect_1_traffic_controller_ch_8_9_avalon_universal_slave_0_debugaccess,     --                                                        .debugaccess
			traffic_controller_ch_10_11_avalon_universal_slave_0_address       => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_address,       --    traffic_controller_ch_10_11_avalon_universal_slave_0.address
			traffic_controller_ch_10_11_avalon_universal_slave_0_write         => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_write,         --                                                        .write
			traffic_controller_ch_10_11_avalon_universal_slave_0_read          => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_read,          --                                                        .read
			traffic_controller_ch_10_11_avalon_universal_slave_0_readdata      => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_readdata,      --                                                        .readdata
			traffic_controller_ch_10_11_avalon_universal_slave_0_writedata     => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_writedata,     --                                                        .writedata
			traffic_controller_ch_10_11_avalon_universal_slave_0_burstcount    => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_burstcount,    --                                                        .burstcount
			traffic_controller_ch_10_11_avalon_universal_slave_0_byteenable    => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_byteenable,    --                                                        .byteenable
			traffic_controller_ch_10_11_avalon_universal_slave_0_readdatavalid => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_readdatavalid, --                                                        .readdatavalid
			traffic_controller_ch_10_11_avalon_universal_slave_0_waitrequest   => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_waitrequest,   --                                                        .waitrequest
			traffic_controller_ch_10_11_avalon_universal_slave_0_lock          => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_lock,          --                                                        .lock
			traffic_controller_ch_10_11_avalon_universal_slave_0_debugaccess   => mm_interconnect_1_traffic_controller_ch_10_11_avalon_universal_slave_0_debugaccess,   --                                                        .debugaccess
			mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset      => rst_controller_001_reset_out_reset,                                                   -- mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset.reset
			mac_clk_clk_clk                                                    => mac_clk_clk_clk                                                                       --                                             mac_clk_clk.clk
		);

	rst_controller : component altera_reset_controller_cmp
		generic map (
			NUM_RESET_INPUTS          => 1,
			OUTPUT_RESET_SYNC_EDGES   => "deassert",
			SYNC_DEPTH                => 2,
			RESET_REQUEST_PRESENT     => 0,
			RESET_REQ_WAIT_TIME       => 1,
			MIN_RST_ASSERTION_TIME    => 3,
			RESET_REQ_EARLY_DSRT_TIME => 1,
			USE_RESET_REQUEST_IN0     => 0,
			USE_RESET_REQUEST_IN1     => 0,
			USE_RESET_REQUEST_IN2     => 0,
			USE_RESET_REQUEST_IN3     => 0,
			USE_RESET_REQUEST_IN4     => 0,
			USE_RESET_REQUEST_IN5     => 0,
			USE_RESET_REQUEST_IN6     => 0,
			USE_RESET_REQUEST_IN7     => 0,
			USE_RESET_REQUEST_IN8     => 0,
			USE_RESET_REQUEST_IN9     => 0,
			USE_RESET_REQUEST_IN10    => 0,
			USE_RESET_REQUEST_IN11    => 0,
			USE_RESET_REQUEST_IN12    => 0,
			USE_RESET_REQUEST_IN13    => 0,
			USE_RESET_REQUEST_IN14    => 0,
			USE_RESET_REQUEST_IN15    => 0,
			ADAPT_RESET_REQUEST       => 0
		)
		port map (
			reset_in0      => csr_clk_clk_reset_reset_ports_inv, -- reset_in0.reset
			clk            => csr_clk_clk_clk,                   --       clk.clk
			reset_out      => rst_controller_reset_out_reset,    -- reset_out.reset
			reset_req      => open,                              -- (terminated)
			reset_req_in0  => '0',                               -- (terminated)
			reset_in1      => '0',                               -- (terminated)
			reset_req_in1  => '0',                               -- (terminated)
			reset_in2      => '0',                               -- (terminated)
			reset_req_in2  => '0',                               -- (terminated)
			reset_in3      => '0',                               -- (terminated)
			reset_req_in3  => '0',                               -- (terminated)
			reset_in4      => '0',                               -- (terminated)
			reset_req_in4  => '0',                               -- (terminated)
			reset_in5      => '0',                               -- (terminated)
			reset_req_in5  => '0',                               -- (terminated)
			reset_in6      => '0',                               -- (terminated)
			reset_req_in6  => '0',                               -- (terminated)
			reset_in7      => '0',                               -- (terminated)
			reset_req_in7  => '0',                               -- (terminated)
			reset_in8      => '0',                               -- (terminated)
			reset_req_in8  => '0',                               -- (terminated)
			reset_in9      => '0',                               -- (terminated)
			reset_req_in9  => '0',                               -- (terminated)
			reset_in10     => '0',                               -- (terminated)
			reset_req_in10 => '0',                               -- (terminated)
			reset_in11     => '0',                               -- (terminated)
			reset_req_in11 => '0',                               -- (terminated)
			reset_in12     => '0',                               -- (terminated)
			reset_req_in12 => '0',                               -- (terminated)
			reset_in13     => '0',                               -- (terminated)
			reset_req_in13 => '0',                               -- (terminated)
			reset_in14     => '0',                               -- (terminated)
			reset_req_in14 => '0',                               -- (terminated)
			reset_in15     => '0',                               -- (terminated)
			reset_req_in15 => '0'                                -- (terminated)
		);

	rst_controller_001 : component altera_reset_controller_cmp
		generic map (
			NUM_RESET_INPUTS          => 1,
			OUTPUT_RESET_SYNC_EDGES   => "deassert",
			SYNC_DEPTH                => 2,
			RESET_REQUEST_PRESENT     => 0,
			RESET_REQ_WAIT_TIME       => 1,
			MIN_RST_ASSERTION_TIME    => 3,
			RESET_REQ_EARLY_DSRT_TIME => 1,
			USE_RESET_REQUEST_IN0     => 0,
			USE_RESET_REQUEST_IN1     => 0,
			USE_RESET_REQUEST_IN2     => 0,
			USE_RESET_REQUEST_IN3     => 0,
			USE_RESET_REQUEST_IN4     => 0,
			USE_RESET_REQUEST_IN5     => 0,
			USE_RESET_REQUEST_IN6     => 0,
			USE_RESET_REQUEST_IN7     => 0,
			USE_RESET_REQUEST_IN8     => 0,
			USE_RESET_REQUEST_IN9     => 0,
			USE_RESET_REQUEST_IN10    => 0,
			USE_RESET_REQUEST_IN11    => 0,
			USE_RESET_REQUEST_IN12    => 0,
			USE_RESET_REQUEST_IN13    => 0,
			USE_RESET_REQUEST_IN14    => 0,
			USE_RESET_REQUEST_IN15    => 0,
			ADAPT_RESET_REQUEST       => 0
		)
		port map (
			reset_in0      => mac_clk_clk_reset_reset_ports_inv,  -- reset_in0.reset
			clk            => mac_clk_clk_clk,                    --       clk.clk
			reset_out      => rst_controller_001_reset_out_reset, -- reset_out.reset
			reset_req      => open,                               -- (terminated)
			reset_req_in0  => '0',                                -- (terminated)
			reset_in1      => '0',                                -- (terminated)
			reset_req_in1  => '0',                                -- (terminated)
			reset_in2      => '0',                                -- (terminated)
			reset_req_in2  => '0',                                -- (terminated)
			reset_in3      => '0',                                -- (terminated)
			reset_req_in3  => '0',                                -- (terminated)
			reset_in4      => '0',                                -- (terminated)
			reset_req_in4  => '0',                                -- (terminated)
			reset_in5      => '0',                                -- (terminated)
			reset_req_in5  => '0',                                -- (terminated)
			reset_in6      => '0',                                -- (terminated)
			reset_req_in6  => '0',                                -- (terminated)
			reset_in7      => '0',                                -- (terminated)
			reset_req_in7  => '0',                                -- (terminated)
			reset_in8      => '0',                                -- (terminated)
			reset_req_in8  => '0',                                -- (terminated)
			reset_in9      => '0',                                -- (terminated)
			reset_req_in9  => '0',                                -- (terminated)
			reset_in10     => '0',                                -- (terminated)
			reset_req_in10 => '0',                                -- (terminated)
			reset_in11     => '0',                                -- (terminated)
			reset_req_in11 => '0',                                -- (terminated)
			reset_in12     => '0',                                -- (terminated)
			reset_req_in12 => '0',                                -- (terminated)
			reset_in13     => '0',                                -- (terminated)
			reset_req_in13 => '0',                                -- (terminated)
			reset_in14     => '0',                                -- (terminated)
			reset_req_in14 => '0',                                -- (terminated)
			reset_in15     => '0',                                -- (terminated)
			reset_req_in15 => '0'                                 -- (terminated)
		);

	csr_clk_clk_reset_reset_ports_inv <= not csr_clk_clk_reset_reset;

	mac_clk_clk_reset_reset_ports_inv <= not mac_clk_clk_reset_reset;

end architecture rtl; -- of address_decoder_top
