// address_decoder_multi_channel.v

// Generated using ACDS version 19.4 64

`timescale 1 ps / 1 ps
module address_decoder_multi_channel (
		output wire [15:0] channel_0_address,      //     channel_0.address
		output wire        channel_0_write,        //              .write
		output wire        channel_0_read,         //              .read
		input  wire [31:0] channel_0_readdata,     //              .readdata
		output wire [31:0] channel_0_writedata,    //              .writedata
		input  wire        channel_0_waitrequest,  //              .waitrequest
		output wire [15:0] channel_1_address,      //     channel_1.address
		output wire        channel_1_write,        //              .write
		output wire        channel_1_read,         //              .read
		input  wire [31:0] channel_1_readdata,     //              .readdata
		output wire [31:0] channel_1_writedata,    //              .writedata
		input  wire        channel_1_waitrequest,  //              .waitrequest
		output wire [15:0] channel_10_address,     //    channel_10.address
		output wire        channel_10_write,       //              .write
		output wire        channel_10_read,        //              .read
		input  wire [31:0] channel_10_readdata,    //              .readdata
		output wire [31:0] channel_10_writedata,   //              .writedata
		input  wire        channel_10_waitrequest, //              .waitrequest
		output wire [15:0] channel_11_address,     //    channel_11.address
		output wire        channel_11_write,       //              .write
		output wire        channel_11_read,        //              .read
		input  wire [31:0] channel_11_readdata,    //              .readdata
		output wire [31:0] channel_11_writedata,   //              .writedata
		input  wire        channel_11_waitrequest, //              .waitrequest
		output wire [15:0] channel_2_address,      //     channel_2.address
		output wire        channel_2_write,        //              .write
		output wire        channel_2_read,         //              .read
		input  wire [31:0] channel_2_readdata,     //              .readdata
		output wire [31:0] channel_2_writedata,    //              .writedata
		input  wire        channel_2_waitrequest,  //              .waitrequest
		output wire [15:0] channel_3_address,      //     channel_3.address
		output wire        channel_3_write,        //              .write
		output wire        channel_3_read,         //              .read
		input  wire [31:0] channel_3_readdata,     //              .readdata
		output wire [31:0] channel_3_writedata,    //              .writedata
		input  wire        channel_3_waitrequest,  //              .waitrequest
		output wire [15:0] channel_4_address,      //     channel_4.address
		output wire        channel_4_write,        //              .write
		output wire        channel_4_read,         //              .read
		input  wire [31:0] channel_4_readdata,     //              .readdata
		output wire [31:0] channel_4_writedata,    //              .writedata
		input  wire        channel_4_waitrequest,  //              .waitrequest
		output wire [15:0] channel_5_address,      //     channel_5.address
		output wire        channel_5_write,        //              .write
		output wire        channel_5_read,         //              .read
		input  wire [31:0] channel_5_readdata,     //              .readdata
		output wire [31:0] channel_5_writedata,    //              .writedata
		input  wire        channel_5_waitrequest,  //              .waitrequest
		output wire [15:0] channel_6_address,      //     channel_6.address
		output wire        channel_6_write,        //              .write
		output wire        channel_6_read,         //              .read
		input  wire [31:0] channel_6_readdata,     //              .readdata
		output wire [31:0] channel_6_writedata,    //              .writedata
		input  wire        channel_6_waitrequest,  //              .waitrequest
		output wire [15:0] channel_7_address,      //     channel_7.address
		output wire        channel_7_write,        //              .write
		output wire        channel_7_read,         //              .read
		input  wire [31:0] channel_7_readdata,     //              .readdata
		output wire [31:0] channel_7_writedata,    //              .writedata
		input  wire        channel_7_waitrequest,  //              .waitrequest
		output wire [15:0] channel_8_address,      //     channel_8.address
		output wire        channel_8_write,        //              .write
		output wire        channel_8_read,         //              .read
		input  wire [31:0] channel_8_readdata,     //              .readdata
		output wire [31:0] channel_8_writedata,    //              .writedata
		input  wire        channel_8_waitrequest,  //              .waitrequest
		output wire [15:0] channel_9_address,      //     channel_9.address
		output wire        channel_9_write,        //              .write
		output wire        channel_9_read,         //              .read
		input  wire [31:0] channel_9_readdata,     //              .readdata
		output wire [31:0] channel_9_writedata,    //              .writedata
		input  wire        channel_9_waitrequest,  //              .waitrequest
		input  wire        csr_clk_clk,            //       csr_clk.clk
		input  wire        csr_clk_reset_reset_n,  // csr_clk_reset.reset_n
		input  wire [19:0] slave_address,          //         slave.address
		output wire        slave_waitrequest,      //              .waitrequest
		input  wire        slave_read,             //              .read
		output wire [31:0] slave_readdata,         //              .readdata
		input  wire        slave_write,            //              .write
		input  wire [31:0] slave_writedata         //              .writedata
	);

	wire         csr_clk_clk_clk;                                                     // csr_clk:clk_out -> [channel_0:clk, channel_10:clk, channel_11:clk, channel_1:clk, channel_2:clk, channel_3:clk, channel_4:clk, channel_5:clk, channel_6:clk, channel_7:clk, channel_8:clk, channel_9:clk, master:clk, mm_interconnect_0:csr_clk_clk_clk, rst_controller:clk]
	wire         master_avalon_universal_master_0_waitrequest;                        // mm_interconnect_0:master_avalon_universal_master_0_waitrequest -> master:uav_waitrequest
	wire  [31:0] master_avalon_universal_master_0_readdata;                           // mm_interconnect_0:master_avalon_universal_master_0_readdata -> master:uav_readdata
	wire         master_avalon_universal_master_0_debugaccess;                        // master:uav_debugaccess -> mm_interconnect_0:master_avalon_universal_master_0_debugaccess
	wire  [31:0] master_avalon_universal_master_0_address;                            // master:uav_address -> mm_interconnect_0:master_avalon_universal_master_0_address
	wire         master_avalon_universal_master_0_read;                               // master:uav_read -> mm_interconnect_0:master_avalon_universal_master_0_read
	wire   [3:0] master_avalon_universal_master_0_byteenable;                         // master:uav_byteenable -> mm_interconnect_0:master_avalon_universal_master_0_byteenable
	wire         master_avalon_universal_master_0_readdatavalid;                      // mm_interconnect_0:master_avalon_universal_master_0_readdatavalid -> master:uav_readdatavalid
	wire         master_avalon_universal_master_0_lock;                               // master:uav_lock -> mm_interconnect_0:master_avalon_universal_master_0_lock
	wire         master_avalon_universal_master_0_write;                              // master:uav_write -> mm_interconnect_0:master_avalon_universal_master_0_write
	wire  [31:0] master_avalon_universal_master_0_writedata;                          // master:uav_writedata -> mm_interconnect_0:master_avalon_universal_master_0_writedata
	wire   [2:0] master_avalon_universal_master_0_burstcount;                         // master:uav_burstcount -> mm_interconnect_0:master_avalon_universal_master_0_burstcount
	wire  [31:0] mm_interconnect_0_channel_1_avalon_universal_slave_0_readdata;       // channel_1:uav_readdata -> mm_interconnect_0:channel_1_avalon_universal_slave_0_readdata
	wire         mm_interconnect_0_channel_1_avalon_universal_slave_0_waitrequest;    // channel_1:uav_waitrequest -> mm_interconnect_0:channel_1_avalon_universal_slave_0_waitrequest
	wire         mm_interconnect_0_channel_1_avalon_universal_slave_0_debugaccess;    // mm_interconnect_0:channel_1_avalon_universal_slave_0_debugaccess -> channel_1:uav_debugaccess
	wire  [15:0] mm_interconnect_0_channel_1_avalon_universal_slave_0_address;        // mm_interconnect_0:channel_1_avalon_universal_slave_0_address -> channel_1:uav_address
	wire         mm_interconnect_0_channel_1_avalon_universal_slave_0_read;           // mm_interconnect_0:channel_1_avalon_universal_slave_0_read -> channel_1:uav_read
	wire   [3:0] mm_interconnect_0_channel_1_avalon_universal_slave_0_byteenable;     // mm_interconnect_0:channel_1_avalon_universal_slave_0_byteenable -> channel_1:uav_byteenable
	wire         mm_interconnect_0_channel_1_avalon_universal_slave_0_readdatavalid;  // channel_1:uav_readdatavalid -> mm_interconnect_0:channel_1_avalon_universal_slave_0_readdatavalid
	wire         mm_interconnect_0_channel_1_avalon_universal_slave_0_lock;           // mm_interconnect_0:channel_1_avalon_universal_slave_0_lock -> channel_1:uav_lock
	wire         mm_interconnect_0_channel_1_avalon_universal_slave_0_write;          // mm_interconnect_0:channel_1_avalon_universal_slave_0_write -> channel_1:uav_write
	wire  [31:0] mm_interconnect_0_channel_1_avalon_universal_slave_0_writedata;      // mm_interconnect_0:channel_1_avalon_universal_slave_0_writedata -> channel_1:uav_writedata
	wire   [2:0] mm_interconnect_0_channel_1_avalon_universal_slave_0_burstcount;     // mm_interconnect_0:channel_1_avalon_universal_slave_0_burstcount -> channel_1:uav_burstcount
	wire  [31:0] mm_interconnect_0_channel_0_avalon_universal_slave_0_readdata;       // channel_0:uav_readdata -> mm_interconnect_0:channel_0_avalon_universal_slave_0_readdata
	wire         mm_interconnect_0_channel_0_avalon_universal_slave_0_waitrequest;    // channel_0:uav_waitrequest -> mm_interconnect_0:channel_0_avalon_universal_slave_0_waitrequest
	wire         mm_interconnect_0_channel_0_avalon_universal_slave_0_debugaccess;    // mm_interconnect_0:channel_0_avalon_universal_slave_0_debugaccess -> channel_0:uav_debugaccess
	wire  [15:0] mm_interconnect_0_channel_0_avalon_universal_slave_0_address;        // mm_interconnect_0:channel_0_avalon_universal_slave_0_address -> channel_0:uav_address
	wire         mm_interconnect_0_channel_0_avalon_universal_slave_0_read;           // mm_interconnect_0:channel_0_avalon_universal_slave_0_read -> channel_0:uav_read
	wire   [3:0] mm_interconnect_0_channel_0_avalon_universal_slave_0_byteenable;     // mm_interconnect_0:channel_0_avalon_universal_slave_0_byteenable -> channel_0:uav_byteenable
	wire         mm_interconnect_0_channel_0_avalon_universal_slave_0_readdatavalid;  // channel_0:uav_readdatavalid -> mm_interconnect_0:channel_0_avalon_universal_slave_0_readdatavalid
	wire         mm_interconnect_0_channel_0_avalon_universal_slave_0_lock;           // mm_interconnect_0:channel_0_avalon_universal_slave_0_lock -> channel_0:uav_lock
	wire         mm_interconnect_0_channel_0_avalon_universal_slave_0_write;          // mm_interconnect_0:channel_0_avalon_universal_slave_0_write -> channel_0:uav_write
	wire  [31:0] mm_interconnect_0_channel_0_avalon_universal_slave_0_writedata;      // mm_interconnect_0:channel_0_avalon_universal_slave_0_writedata -> channel_0:uav_writedata
	wire   [2:0] mm_interconnect_0_channel_0_avalon_universal_slave_0_burstcount;     // mm_interconnect_0:channel_0_avalon_universal_slave_0_burstcount -> channel_0:uav_burstcount
	wire  [31:0] mm_interconnect_0_channel_2_avalon_universal_slave_0_readdata;       // channel_2:uav_readdata -> mm_interconnect_0:channel_2_avalon_universal_slave_0_readdata
	wire         mm_interconnect_0_channel_2_avalon_universal_slave_0_waitrequest;    // channel_2:uav_waitrequest -> mm_interconnect_0:channel_2_avalon_universal_slave_0_waitrequest
	wire         mm_interconnect_0_channel_2_avalon_universal_slave_0_debugaccess;    // mm_interconnect_0:channel_2_avalon_universal_slave_0_debugaccess -> channel_2:uav_debugaccess
	wire  [15:0] mm_interconnect_0_channel_2_avalon_universal_slave_0_address;        // mm_interconnect_0:channel_2_avalon_universal_slave_0_address -> channel_2:uav_address
	wire         mm_interconnect_0_channel_2_avalon_universal_slave_0_read;           // mm_interconnect_0:channel_2_avalon_universal_slave_0_read -> channel_2:uav_read
	wire   [3:0] mm_interconnect_0_channel_2_avalon_universal_slave_0_byteenable;     // mm_interconnect_0:channel_2_avalon_universal_slave_0_byteenable -> channel_2:uav_byteenable
	wire         mm_interconnect_0_channel_2_avalon_universal_slave_0_readdatavalid;  // channel_2:uav_readdatavalid -> mm_interconnect_0:channel_2_avalon_universal_slave_0_readdatavalid
	wire         mm_interconnect_0_channel_2_avalon_universal_slave_0_lock;           // mm_interconnect_0:channel_2_avalon_universal_slave_0_lock -> channel_2:uav_lock
	wire         mm_interconnect_0_channel_2_avalon_universal_slave_0_write;          // mm_interconnect_0:channel_2_avalon_universal_slave_0_write -> channel_2:uav_write
	wire  [31:0] mm_interconnect_0_channel_2_avalon_universal_slave_0_writedata;      // mm_interconnect_0:channel_2_avalon_universal_slave_0_writedata -> channel_2:uav_writedata
	wire   [2:0] mm_interconnect_0_channel_2_avalon_universal_slave_0_burstcount;     // mm_interconnect_0:channel_2_avalon_universal_slave_0_burstcount -> channel_2:uav_burstcount
	wire  [31:0] mm_interconnect_0_channel_3_avalon_universal_slave_0_readdata;       // channel_3:uav_readdata -> mm_interconnect_0:channel_3_avalon_universal_slave_0_readdata
	wire         mm_interconnect_0_channel_3_avalon_universal_slave_0_waitrequest;    // channel_3:uav_waitrequest -> mm_interconnect_0:channel_3_avalon_universal_slave_0_waitrequest
	wire         mm_interconnect_0_channel_3_avalon_universal_slave_0_debugaccess;    // mm_interconnect_0:channel_3_avalon_universal_slave_0_debugaccess -> channel_3:uav_debugaccess
	wire  [15:0] mm_interconnect_0_channel_3_avalon_universal_slave_0_address;        // mm_interconnect_0:channel_3_avalon_universal_slave_0_address -> channel_3:uav_address
	wire         mm_interconnect_0_channel_3_avalon_universal_slave_0_read;           // mm_interconnect_0:channel_3_avalon_universal_slave_0_read -> channel_3:uav_read
	wire   [3:0] mm_interconnect_0_channel_3_avalon_universal_slave_0_byteenable;     // mm_interconnect_0:channel_3_avalon_universal_slave_0_byteenable -> channel_3:uav_byteenable
	wire         mm_interconnect_0_channel_3_avalon_universal_slave_0_readdatavalid;  // channel_3:uav_readdatavalid -> mm_interconnect_0:channel_3_avalon_universal_slave_0_readdatavalid
	wire         mm_interconnect_0_channel_3_avalon_universal_slave_0_lock;           // mm_interconnect_0:channel_3_avalon_universal_slave_0_lock -> channel_3:uav_lock
	wire         mm_interconnect_0_channel_3_avalon_universal_slave_0_write;          // mm_interconnect_0:channel_3_avalon_universal_slave_0_write -> channel_3:uav_write
	wire  [31:0] mm_interconnect_0_channel_3_avalon_universal_slave_0_writedata;      // mm_interconnect_0:channel_3_avalon_universal_slave_0_writedata -> channel_3:uav_writedata
	wire   [2:0] mm_interconnect_0_channel_3_avalon_universal_slave_0_burstcount;     // mm_interconnect_0:channel_3_avalon_universal_slave_0_burstcount -> channel_3:uav_burstcount
	wire  [31:0] mm_interconnect_0_channel_4_avalon_universal_slave_0_readdata;       // channel_4:uav_readdata -> mm_interconnect_0:channel_4_avalon_universal_slave_0_readdata
	wire         mm_interconnect_0_channel_4_avalon_universal_slave_0_waitrequest;    // channel_4:uav_waitrequest -> mm_interconnect_0:channel_4_avalon_universal_slave_0_waitrequest
	wire         mm_interconnect_0_channel_4_avalon_universal_slave_0_debugaccess;    // mm_interconnect_0:channel_4_avalon_universal_slave_0_debugaccess -> channel_4:uav_debugaccess
	wire  [15:0] mm_interconnect_0_channel_4_avalon_universal_slave_0_address;        // mm_interconnect_0:channel_4_avalon_universal_slave_0_address -> channel_4:uav_address
	wire         mm_interconnect_0_channel_4_avalon_universal_slave_0_read;           // mm_interconnect_0:channel_4_avalon_universal_slave_0_read -> channel_4:uav_read
	wire   [3:0] mm_interconnect_0_channel_4_avalon_universal_slave_0_byteenable;     // mm_interconnect_0:channel_4_avalon_universal_slave_0_byteenable -> channel_4:uav_byteenable
	wire         mm_interconnect_0_channel_4_avalon_universal_slave_0_readdatavalid;  // channel_4:uav_readdatavalid -> mm_interconnect_0:channel_4_avalon_universal_slave_0_readdatavalid
	wire         mm_interconnect_0_channel_4_avalon_universal_slave_0_lock;           // mm_interconnect_0:channel_4_avalon_universal_slave_0_lock -> channel_4:uav_lock
	wire         mm_interconnect_0_channel_4_avalon_universal_slave_0_write;          // mm_interconnect_0:channel_4_avalon_universal_slave_0_write -> channel_4:uav_write
	wire  [31:0] mm_interconnect_0_channel_4_avalon_universal_slave_0_writedata;      // mm_interconnect_0:channel_4_avalon_universal_slave_0_writedata -> channel_4:uav_writedata
	wire   [2:0] mm_interconnect_0_channel_4_avalon_universal_slave_0_burstcount;     // mm_interconnect_0:channel_4_avalon_universal_slave_0_burstcount -> channel_4:uav_burstcount
	wire  [31:0] mm_interconnect_0_channel_5_avalon_universal_slave_0_readdata;       // channel_5:uav_readdata -> mm_interconnect_0:channel_5_avalon_universal_slave_0_readdata
	wire         mm_interconnect_0_channel_5_avalon_universal_slave_0_waitrequest;    // channel_5:uav_waitrequest -> mm_interconnect_0:channel_5_avalon_universal_slave_0_waitrequest
	wire         mm_interconnect_0_channel_5_avalon_universal_slave_0_debugaccess;    // mm_interconnect_0:channel_5_avalon_universal_slave_0_debugaccess -> channel_5:uav_debugaccess
	wire  [15:0] mm_interconnect_0_channel_5_avalon_universal_slave_0_address;        // mm_interconnect_0:channel_5_avalon_universal_slave_0_address -> channel_5:uav_address
	wire         mm_interconnect_0_channel_5_avalon_universal_slave_0_read;           // mm_interconnect_0:channel_5_avalon_universal_slave_0_read -> channel_5:uav_read
	wire   [3:0] mm_interconnect_0_channel_5_avalon_universal_slave_0_byteenable;     // mm_interconnect_0:channel_5_avalon_universal_slave_0_byteenable -> channel_5:uav_byteenable
	wire         mm_interconnect_0_channel_5_avalon_universal_slave_0_readdatavalid;  // channel_5:uav_readdatavalid -> mm_interconnect_0:channel_5_avalon_universal_slave_0_readdatavalid
	wire         mm_interconnect_0_channel_5_avalon_universal_slave_0_lock;           // mm_interconnect_0:channel_5_avalon_universal_slave_0_lock -> channel_5:uav_lock
	wire         mm_interconnect_0_channel_5_avalon_universal_slave_0_write;          // mm_interconnect_0:channel_5_avalon_universal_slave_0_write -> channel_5:uav_write
	wire  [31:0] mm_interconnect_0_channel_5_avalon_universal_slave_0_writedata;      // mm_interconnect_0:channel_5_avalon_universal_slave_0_writedata -> channel_5:uav_writedata
	wire   [2:0] mm_interconnect_0_channel_5_avalon_universal_slave_0_burstcount;     // mm_interconnect_0:channel_5_avalon_universal_slave_0_burstcount -> channel_5:uav_burstcount
	wire  [31:0] mm_interconnect_0_channel_6_avalon_universal_slave_0_readdata;       // channel_6:uav_readdata -> mm_interconnect_0:channel_6_avalon_universal_slave_0_readdata
	wire         mm_interconnect_0_channel_6_avalon_universal_slave_0_waitrequest;    // channel_6:uav_waitrequest -> mm_interconnect_0:channel_6_avalon_universal_slave_0_waitrequest
	wire         mm_interconnect_0_channel_6_avalon_universal_slave_0_debugaccess;    // mm_interconnect_0:channel_6_avalon_universal_slave_0_debugaccess -> channel_6:uav_debugaccess
	wire  [15:0] mm_interconnect_0_channel_6_avalon_universal_slave_0_address;        // mm_interconnect_0:channel_6_avalon_universal_slave_0_address -> channel_6:uav_address
	wire         mm_interconnect_0_channel_6_avalon_universal_slave_0_read;           // mm_interconnect_0:channel_6_avalon_universal_slave_0_read -> channel_6:uav_read
	wire   [3:0] mm_interconnect_0_channel_6_avalon_universal_slave_0_byteenable;     // mm_interconnect_0:channel_6_avalon_universal_slave_0_byteenable -> channel_6:uav_byteenable
	wire         mm_interconnect_0_channel_6_avalon_universal_slave_0_readdatavalid;  // channel_6:uav_readdatavalid -> mm_interconnect_0:channel_6_avalon_universal_slave_0_readdatavalid
	wire         mm_interconnect_0_channel_6_avalon_universal_slave_0_lock;           // mm_interconnect_0:channel_6_avalon_universal_slave_0_lock -> channel_6:uav_lock
	wire         mm_interconnect_0_channel_6_avalon_universal_slave_0_write;          // mm_interconnect_0:channel_6_avalon_universal_slave_0_write -> channel_6:uav_write
	wire  [31:0] mm_interconnect_0_channel_6_avalon_universal_slave_0_writedata;      // mm_interconnect_0:channel_6_avalon_universal_slave_0_writedata -> channel_6:uav_writedata
	wire   [2:0] mm_interconnect_0_channel_6_avalon_universal_slave_0_burstcount;     // mm_interconnect_0:channel_6_avalon_universal_slave_0_burstcount -> channel_6:uav_burstcount
	wire  [31:0] mm_interconnect_0_channel_7_avalon_universal_slave_0_readdata;       // channel_7:uav_readdata -> mm_interconnect_0:channel_7_avalon_universal_slave_0_readdata
	wire         mm_interconnect_0_channel_7_avalon_universal_slave_0_waitrequest;    // channel_7:uav_waitrequest -> mm_interconnect_0:channel_7_avalon_universal_slave_0_waitrequest
	wire         mm_interconnect_0_channel_7_avalon_universal_slave_0_debugaccess;    // mm_interconnect_0:channel_7_avalon_universal_slave_0_debugaccess -> channel_7:uav_debugaccess
	wire  [15:0] mm_interconnect_0_channel_7_avalon_universal_slave_0_address;        // mm_interconnect_0:channel_7_avalon_universal_slave_0_address -> channel_7:uav_address
	wire         mm_interconnect_0_channel_7_avalon_universal_slave_0_read;           // mm_interconnect_0:channel_7_avalon_universal_slave_0_read -> channel_7:uav_read
	wire   [3:0] mm_interconnect_0_channel_7_avalon_universal_slave_0_byteenable;     // mm_interconnect_0:channel_7_avalon_universal_slave_0_byteenable -> channel_7:uav_byteenable
	wire         mm_interconnect_0_channel_7_avalon_universal_slave_0_readdatavalid;  // channel_7:uav_readdatavalid -> mm_interconnect_0:channel_7_avalon_universal_slave_0_readdatavalid
	wire         mm_interconnect_0_channel_7_avalon_universal_slave_0_lock;           // mm_interconnect_0:channel_7_avalon_universal_slave_0_lock -> channel_7:uav_lock
	wire         mm_interconnect_0_channel_7_avalon_universal_slave_0_write;          // mm_interconnect_0:channel_7_avalon_universal_slave_0_write -> channel_7:uav_write
	wire  [31:0] mm_interconnect_0_channel_7_avalon_universal_slave_0_writedata;      // mm_interconnect_0:channel_7_avalon_universal_slave_0_writedata -> channel_7:uav_writedata
	wire   [2:0] mm_interconnect_0_channel_7_avalon_universal_slave_0_burstcount;     // mm_interconnect_0:channel_7_avalon_universal_slave_0_burstcount -> channel_7:uav_burstcount
	wire  [31:0] mm_interconnect_0_channel_8_avalon_universal_slave_0_readdata;       // channel_8:uav_readdata -> mm_interconnect_0:channel_8_avalon_universal_slave_0_readdata
	wire         mm_interconnect_0_channel_8_avalon_universal_slave_0_waitrequest;    // channel_8:uav_waitrequest -> mm_interconnect_0:channel_8_avalon_universal_slave_0_waitrequest
	wire         mm_interconnect_0_channel_8_avalon_universal_slave_0_debugaccess;    // mm_interconnect_0:channel_8_avalon_universal_slave_0_debugaccess -> channel_8:uav_debugaccess
	wire  [15:0] mm_interconnect_0_channel_8_avalon_universal_slave_0_address;        // mm_interconnect_0:channel_8_avalon_universal_slave_0_address -> channel_8:uav_address
	wire         mm_interconnect_0_channel_8_avalon_universal_slave_0_read;           // mm_interconnect_0:channel_8_avalon_universal_slave_0_read -> channel_8:uav_read
	wire   [3:0] mm_interconnect_0_channel_8_avalon_universal_slave_0_byteenable;     // mm_interconnect_0:channel_8_avalon_universal_slave_0_byteenable -> channel_8:uav_byteenable
	wire         mm_interconnect_0_channel_8_avalon_universal_slave_0_readdatavalid;  // channel_8:uav_readdatavalid -> mm_interconnect_0:channel_8_avalon_universal_slave_0_readdatavalid
	wire         mm_interconnect_0_channel_8_avalon_universal_slave_0_lock;           // mm_interconnect_0:channel_8_avalon_universal_slave_0_lock -> channel_8:uav_lock
	wire         mm_interconnect_0_channel_8_avalon_universal_slave_0_write;          // mm_interconnect_0:channel_8_avalon_universal_slave_0_write -> channel_8:uav_write
	wire  [31:0] mm_interconnect_0_channel_8_avalon_universal_slave_0_writedata;      // mm_interconnect_0:channel_8_avalon_universal_slave_0_writedata -> channel_8:uav_writedata
	wire   [2:0] mm_interconnect_0_channel_8_avalon_universal_slave_0_burstcount;     // mm_interconnect_0:channel_8_avalon_universal_slave_0_burstcount -> channel_8:uav_burstcount
	wire  [31:0] mm_interconnect_0_channel_9_avalon_universal_slave_0_readdata;       // channel_9:uav_readdata -> mm_interconnect_0:channel_9_avalon_universal_slave_0_readdata
	wire         mm_interconnect_0_channel_9_avalon_universal_slave_0_waitrequest;    // channel_9:uav_waitrequest -> mm_interconnect_0:channel_9_avalon_universal_slave_0_waitrequest
	wire         mm_interconnect_0_channel_9_avalon_universal_slave_0_debugaccess;    // mm_interconnect_0:channel_9_avalon_universal_slave_0_debugaccess -> channel_9:uav_debugaccess
	wire  [15:0] mm_interconnect_0_channel_9_avalon_universal_slave_0_address;        // mm_interconnect_0:channel_9_avalon_universal_slave_0_address -> channel_9:uav_address
	wire         mm_interconnect_0_channel_9_avalon_universal_slave_0_read;           // mm_interconnect_0:channel_9_avalon_universal_slave_0_read -> channel_9:uav_read
	wire   [3:0] mm_interconnect_0_channel_9_avalon_universal_slave_0_byteenable;     // mm_interconnect_0:channel_9_avalon_universal_slave_0_byteenable -> channel_9:uav_byteenable
	wire         mm_interconnect_0_channel_9_avalon_universal_slave_0_readdatavalid;  // channel_9:uav_readdatavalid -> mm_interconnect_0:channel_9_avalon_universal_slave_0_readdatavalid
	wire         mm_interconnect_0_channel_9_avalon_universal_slave_0_lock;           // mm_interconnect_0:channel_9_avalon_universal_slave_0_lock -> channel_9:uav_lock
	wire         mm_interconnect_0_channel_9_avalon_universal_slave_0_write;          // mm_interconnect_0:channel_9_avalon_universal_slave_0_write -> channel_9:uav_write
	wire  [31:0] mm_interconnect_0_channel_9_avalon_universal_slave_0_writedata;      // mm_interconnect_0:channel_9_avalon_universal_slave_0_writedata -> channel_9:uav_writedata
	wire   [2:0] mm_interconnect_0_channel_9_avalon_universal_slave_0_burstcount;     // mm_interconnect_0:channel_9_avalon_universal_slave_0_burstcount -> channel_9:uav_burstcount
	wire  [31:0] mm_interconnect_0_channel_10_avalon_universal_slave_0_readdata;      // channel_10:uav_readdata -> mm_interconnect_0:channel_10_avalon_universal_slave_0_readdata
	wire         mm_interconnect_0_channel_10_avalon_universal_slave_0_waitrequest;   // channel_10:uav_waitrequest -> mm_interconnect_0:channel_10_avalon_universal_slave_0_waitrequest
	wire         mm_interconnect_0_channel_10_avalon_universal_slave_0_debugaccess;   // mm_interconnect_0:channel_10_avalon_universal_slave_0_debugaccess -> channel_10:uav_debugaccess
	wire  [15:0] mm_interconnect_0_channel_10_avalon_universal_slave_0_address;       // mm_interconnect_0:channel_10_avalon_universal_slave_0_address -> channel_10:uav_address
	wire         mm_interconnect_0_channel_10_avalon_universal_slave_0_read;          // mm_interconnect_0:channel_10_avalon_universal_slave_0_read -> channel_10:uav_read
	wire   [3:0] mm_interconnect_0_channel_10_avalon_universal_slave_0_byteenable;    // mm_interconnect_0:channel_10_avalon_universal_slave_0_byteenable -> channel_10:uav_byteenable
	wire         mm_interconnect_0_channel_10_avalon_universal_slave_0_readdatavalid; // channel_10:uav_readdatavalid -> mm_interconnect_0:channel_10_avalon_universal_slave_0_readdatavalid
	wire         mm_interconnect_0_channel_10_avalon_universal_slave_0_lock;          // mm_interconnect_0:channel_10_avalon_universal_slave_0_lock -> channel_10:uav_lock
	wire         mm_interconnect_0_channel_10_avalon_universal_slave_0_write;         // mm_interconnect_0:channel_10_avalon_universal_slave_0_write -> channel_10:uav_write
	wire  [31:0] mm_interconnect_0_channel_10_avalon_universal_slave_0_writedata;     // mm_interconnect_0:channel_10_avalon_universal_slave_0_writedata -> channel_10:uav_writedata
	wire   [2:0] mm_interconnect_0_channel_10_avalon_universal_slave_0_burstcount;    // mm_interconnect_0:channel_10_avalon_universal_slave_0_burstcount -> channel_10:uav_burstcount
	wire  [31:0] mm_interconnect_0_channel_11_avalon_universal_slave_0_readdata;      // channel_11:uav_readdata -> mm_interconnect_0:channel_11_avalon_universal_slave_0_readdata
	wire         mm_interconnect_0_channel_11_avalon_universal_slave_0_waitrequest;   // channel_11:uav_waitrequest -> mm_interconnect_0:channel_11_avalon_universal_slave_0_waitrequest
	wire         mm_interconnect_0_channel_11_avalon_universal_slave_0_debugaccess;   // mm_interconnect_0:channel_11_avalon_universal_slave_0_debugaccess -> channel_11:uav_debugaccess
	wire  [15:0] mm_interconnect_0_channel_11_avalon_universal_slave_0_address;       // mm_interconnect_0:channel_11_avalon_universal_slave_0_address -> channel_11:uav_address
	wire         mm_interconnect_0_channel_11_avalon_universal_slave_0_read;          // mm_interconnect_0:channel_11_avalon_universal_slave_0_read -> channel_11:uav_read
	wire   [3:0] mm_interconnect_0_channel_11_avalon_universal_slave_0_byteenable;    // mm_interconnect_0:channel_11_avalon_universal_slave_0_byteenable -> channel_11:uav_byteenable
	wire         mm_interconnect_0_channel_11_avalon_universal_slave_0_readdatavalid; // channel_11:uav_readdatavalid -> mm_interconnect_0:channel_11_avalon_universal_slave_0_readdatavalid
	wire         mm_interconnect_0_channel_11_avalon_universal_slave_0_lock;          // mm_interconnect_0:channel_11_avalon_universal_slave_0_lock -> channel_11:uav_lock
	wire         mm_interconnect_0_channel_11_avalon_universal_slave_0_write;         // mm_interconnect_0:channel_11_avalon_universal_slave_0_write -> channel_11:uav_write
	wire  [31:0] mm_interconnect_0_channel_11_avalon_universal_slave_0_writedata;     // mm_interconnect_0:channel_11_avalon_universal_slave_0_writedata -> channel_11:uav_writedata
	wire   [2:0] mm_interconnect_0_channel_11_avalon_universal_slave_0_burstcount;    // mm_interconnect_0:channel_11_avalon_universal_slave_0_burstcount -> channel_11:uav_burstcount
	wire         rst_controller_reset_out_reset;                                      // rst_controller:reset_out -> [channel_0:reset, channel_10:reset, channel_11:reset, channel_1:reset, channel_2:reset, channel_3:reset, channel_4:reset, channel_5:reset, channel_6:reset, channel_7:reset, channel_8:reset, channel_9:reset, master:reset, mm_interconnect_0:master_reset_reset_bridge_in_reset_reset]
	wire         csr_clk_clk_reset_reset;                                             // csr_clk:reset_n_out -> rst_controller:reset_in0

	address_decoder_multi_channel_channel_0 channel_0 (
		.av_address        (channel_0_address),                                                  //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write          (channel_0_write),                                                    //  output,   width = 1,                         .write
		.av_read           (channel_0_read),                                                     //  output,   width = 1,                         .read
		.av_readdata       (channel_0_readdata),                                                 //   input,  width = 32,                         .readdata
		.av_writedata      (channel_0_writedata),                                                //  output,  width = 32,                         .writedata
		.av_waitrequest    (channel_0_waitrequest),                                              //   input,   width = 1,                         .waitrequest
		.uav_address       (mm_interconnect_0_channel_0_avalon_universal_slave_0_address),       //   input,  width = 16, avalon_universal_slave_0.address
		.uav_burstcount    (mm_interconnect_0_channel_0_avalon_universal_slave_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read          (mm_interconnect_0_channel_0_avalon_universal_slave_0_read),          //   input,   width = 1,                         .read
		.uav_write         (mm_interconnect_0_channel_0_avalon_universal_slave_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest   (mm_interconnect_0_channel_0_avalon_universal_slave_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid (mm_interconnect_0_channel_0_avalon_universal_slave_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable    (mm_interconnect_0_channel_0_avalon_universal_slave_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata      (mm_interconnect_0_channel_0_avalon_universal_slave_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata     (mm_interconnect_0_channel_0_avalon_universal_slave_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock          (mm_interconnect_0_channel_0_avalon_universal_slave_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess   (mm_interconnect_0_channel_0_avalon_universal_slave_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.clk               (csr_clk_clk_clk),                                                    //   input,   width = 1,                      clk.clk
		.reset             (rst_controller_reset_out_reset)                                      //   input,   width = 1,                    reset.reset
	);

	address_decoder_multi_channel_channel_1 channel_1 (
		.av_address        (channel_1_address),                                                  //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write          (channel_1_write),                                                    //  output,   width = 1,                         .write
		.av_read           (channel_1_read),                                                     //  output,   width = 1,                         .read
		.av_readdata       (channel_1_readdata),                                                 //   input,  width = 32,                         .readdata
		.av_writedata      (channel_1_writedata),                                                //  output,  width = 32,                         .writedata
		.av_waitrequest    (channel_1_waitrequest),                                              //   input,   width = 1,                         .waitrequest
		.uav_address       (mm_interconnect_0_channel_1_avalon_universal_slave_0_address),       //   input,  width = 16, avalon_universal_slave_0.address
		.uav_burstcount    (mm_interconnect_0_channel_1_avalon_universal_slave_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read          (mm_interconnect_0_channel_1_avalon_universal_slave_0_read),          //   input,   width = 1,                         .read
		.uav_write         (mm_interconnect_0_channel_1_avalon_universal_slave_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest   (mm_interconnect_0_channel_1_avalon_universal_slave_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid (mm_interconnect_0_channel_1_avalon_universal_slave_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable    (mm_interconnect_0_channel_1_avalon_universal_slave_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata      (mm_interconnect_0_channel_1_avalon_universal_slave_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata     (mm_interconnect_0_channel_1_avalon_universal_slave_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock          (mm_interconnect_0_channel_1_avalon_universal_slave_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess   (mm_interconnect_0_channel_1_avalon_universal_slave_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.clk               (csr_clk_clk_clk),                                                    //   input,   width = 1,                      clk.clk
		.reset             (rst_controller_reset_out_reset)                                      //   input,   width = 1,                    reset.reset
	);

	address_decoder_multi_channel_channel_10 channel_10 (
		.av_address        (channel_10_address),                                                  //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write          (channel_10_write),                                                    //  output,   width = 1,                         .write
		.av_read           (channel_10_read),                                                     //  output,   width = 1,                         .read
		.av_readdata       (channel_10_readdata),                                                 //   input,  width = 32,                         .readdata
		.av_writedata      (channel_10_writedata),                                                //  output,  width = 32,                         .writedata
		.av_waitrequest    (channel_10_waitrequest),                                              //   input,   width = 1,                         .waitrequest
		.uav_address       (mm_interconnect_0_channel_10_avalon_universal_slave_0_address),       //   input,  width = 16, avalon_universal_slave_0.address
		.uav_burstcount    (mm_interconnect_0_channel_10_avalon_universal_slave_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read          (mm_interconnect_0_channel_10_avalon_universal_slave_0_read),          //   input,   width = 1,                         .read
		.uav_write         (mm_interconnect_0_channel_10_avalon_universal_slave_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest   (mm_interconnect_0_channel_10_avalon_universal_slave_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid (mm_interconnect_0_channel_10_avalon_universal_slave_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable    (mm_interconnect_0_channel_10_avalon_universal_slave_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata      (mm_interconnect_0_channel_10_avalon_universal_slave_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata     (mm_interconnect_0_channel_10_avalon_universal_slave_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock          (mm_interconnect_0_channel_10_avalon_universal_slave_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess   (mm_interconnect_0_channel_10_avalon_universal_slave_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.clk               (csr_clk_clk_clk),                                                     //   input,   width = 1,                      clk.clk
		.reset             (rst_controller_reset_out_reset)                                       //   input,   width = 1,                    reset.reset
	);

	address_decoder_multi_channel_channel_11 channel_11 (
		.av_address        (channel_11_address),                                                  //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write          (channel_11_write),                                                    //  output,   width = 1,                         .write
		.av_read           (channel_11_read),                                                     //  output,   width = 1,                         .read
		.av_readdata       (channel_11_readdata),                                                 //   input,  width = 32,                         .readdata
		.av_writedata      (channel_11_writedata),                                                //  output,  width = 32,                         .writedata
		.av_waitrequest    (channel_11_waitrequest),                                              //   input,   width = 1,                         .waitrequest
		.uav_address       (mm_interconnect_0_channel_11_avalon_universal_slave_0_address),       //   input,  width = 16, avalon_universal_slave_0.address
		.uav_burstcount    (mm_interconnect_0_channel_11_avalon_universal_slave_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read          (mm_interconnect_0_channel_11_avalon_universal_slave_0_read),          //   input,   width = 1,                         .read
		.uav_write         (mm_interconnect_0_channel_11_avalon_universal_slave_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest   (mm_interconnect_0_channel_11_avalon_universal_slave_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid (mm_interconnect_0_channel_11_avalon_universal_slave_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable    (mm_interconnect_0_channel_11_avalon_universal_slave_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata      (mm_interconnect_0_channel_11_avalon_universal_slave_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata     (mm_interconnect_0_channel_11_avalon_universal_slave_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock          (mm_interconnect_0_channel_11_avalon_universal_slave_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess   (mm_interconnect_0_channel_11_avalon_universal_slave_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.clk               (csr_clk_clk_clk),                                                     //   input,   width = 1,                      clk.clk
		.reset             (rst_controller_reset_out_reset)                                       //   input,   width = 1,                    reset.reset
	);

	address_decoder_multi_channel_channel_2 channel_2 (
		.av_address        (channel_2_address),                                                  //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write          (channel_2_write),                                                    //  output,   width = 1,                         .write
		.av_read           (channel_2_read),                                                     //  output,   width = 1,                         .read
		.av_readdata       (channel_2_readdata),                                                 //   input,  width = 32,                         .readdata
		.av_writedata      (channel_2_writedata),                                                //  output,  width = 32,                         .writedata
		.av_waitrequest    (channel_2_waitrequest),                                              //   input,   width = 1,                         .waitrequest
		.uav_address       (mm_interconnect_0_channel_2_avalon_universal_slave_0_address),       //   input,  width = 16, avalon_universal_slave_0.address
		.uav_burstcount    (mm_interconnect_0_channel_2_avalon_universal_slave_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read          (mm_interconnect_0_channel_2_avalon_universal_slave_0_read),          //   input,   width = 1,                         .read
		.uav_write         (mm_interconnect_0_channel_2_avalon_universal_slave_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest   (mm_interconnect_0_channel_2_avalon_universal_slave_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid (mm_interconnect_0_channel_2_avalon_universal_slave_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable    (mm_interconnect_0_channel_2_avalon_universal_slave_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata      (mm_interconnect_0_channel_2_avalon_universal_slave_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata     (mm_interconnect_0_channel_2_avalon_universal_slave_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock          (mm_interconnect_0_channel_2_avalon_universal_slave_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess   (mm_interconnect_0_channel_2_avalon_universal_slave_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.clk               (csr_clk_clk_clk),                                                    //   input,   width = 1,                      clk.clk
		.reset             (rst_controller_reset_out_reset)                                      //   input,   width = 1,                    reset.reset
	);

	address_decoder_multi_channel_channel_3 channel_3 (
		.av_address        (channel_3_address),                                                  //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write          (channel_3_write),                                                    //  output,   width = 1,                         .write
		.av_read           (channel_3_read),                                                     //  output,   width = 1,                         .read
		.av_readdata       (channel_3_readdata),                                                 //   input,  width = 32,                         .readdata
		.av_writedata      (channel_3_writedata),                                                //  output,  width = 32,                         .writedata
		.av_waitrequest    (channel_3_waitrequest),                                              //   input,   width = 1,                         .waitrequest
		.uav_address       (mm_interconnect_0_channel_3_avalon_universal_slave_0_address),       //   input,  width = 16, avalon_universal_slave_0.address
		.uav_burstcount    (mm_interconnect_0_channel_3_avalon_universal_slave_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read          (mm_interconnect_0_channel_3_avalon_universal_slave_0_read),          //   input,   width = 1,                         .read
		.uav_write         (mm_interconnect_0_channel_3_avalon_universal_slave_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest   (mm_interconnect_0_channel_3_avalon_universal_slave_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid (mm_interconnect_0_channel_3_avalon_universal_slave_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable    (mm_interconnect_0_channel_3_avalon_universal_slave_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata      (mm_interconnect_0_channel_3_avalon_universal_slave_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata     (mm_interconnect_0_channel_3_avalon_universal_slave_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock          (mm_interconnect_0_channel_3_avalon_universal_slave_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess   (mm_interconnect_0_channel_3_avalon_universal_slave_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.clk               (csr_clk_clk_clk),                                                    //   input,   width = 1,                      clk.clk
		.reset             (rst_controller_reset_out_reset)                                      //   input,   width = 1,                    reset.reset
	);

	address_decoder_multi_channel_channel_4 channel_4 (
		.av_address        (channel_4_address),                                                  //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write          (channel_4_write),                                                    //  output,   width = 1,                         .write
		.av_read           (channel_4_read),                                                     //  output,   width = 1,                         .read
		.av_readdata       (channel_4_readdata),                                                 //   input,  width = 32,                         .readdata
		.av_writedata      (channel_4_writedata),                                                //  output,  width = 32,                         .writedata
		.av_waitrequest    (channel_4_waitrequest),                                              //   input,   width = 1,                         .waitrequest
		.uav_address       (mm_interconnect_0_channel_4_avalon_universal_slave_0_address),       //   input,  width = 16, avalon_universal_slave_0.address
		.uav_burstcount    (mm_interconnect_0_channel_4_avalon_universal_slave_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read          (mm_interconnect_0_channel_4_avalon_universal_slave_0_read),          //   input,   width = 1,                         .read
		.uav_write         (mm_interconnect_0_channel_4_avalon_universal_slave_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest   (mm_interconnect_0_channel_4_avalon_universal_slave_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid (mm_interconnect_0_channel_4_avalon_universal_slave_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable    (mm_interconnect_0_channel_4_avalon_universal_slave_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata      (mm_interconnect_0_channel_4_avalon_universal_slave_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata     (mm_interconnect_0_channel_4_avalon_universal_slave_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock          (mm_interconnect_0_channel_4_avalon_universal_slave_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess   (mm_interconnect_0_channel_4_avalon_universal_slave_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.clk               (csr_clk_clk_clk),                                                    //   input,   width = 1,                      clk.clk
		.reset             (rst_controller_reset_out_reset)                                      //   input,   width = 1,                    reset.reset
	);

	address_decoder_multi_channel_channel_5 channel_5 (
		.av_address        (channel_5_address),                                                  //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write          (channel_5_write),                                                    //  output,   width = 1,                         .write
		.av_read           (channel_5_read),                                                     //  output,   width = 1,                         .read
		.av_readdata       (channel_5_readdata),                                                 //   input,  width = 32,                         .readdata
		.av_writedata      (channel_5_writedata),                                                //  output,  width = 32,                         .writedata
		.av_waitrequest    (channel_5_waitrequest),                                              //   input,   width = 1,                         .waitrequest
		.uav_address       (mm_interconnect_0_channel_5_avalon_universal_slave_0_address),       //   input,  width = 16, avalon_universal_slave_0.address
		.uav_burstcount    (mm_interconnect_0_channel_5_avalon_universal_slave_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read          (mm_interconnect_0_channel_5_avalon_universal_slave_0_read),          //   input,   width = 1,                         .read
		.uav_write         (mm_interconnect_0_channel_5_avalon_universal_slave_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest   (mm_interconnect_0_channel_5_avalon_universal_slave_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid (mm_interconnect_0_channel_5_avalon_universal_slave_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable    (mm_interconnect_0_channel_5_avalon_universal_slave_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata      (mm_interconnect_0_channel_5_avalon_universal_slave_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata     (mm_interconnect_0_channel_5_avalon_universal_slave_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock          (mm_interconnect_0_channel_5_avalon_universal_slave_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess   (mm_interconnect_0_channel_5_avalon_universal_slave_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.clk               (csr_clk_clk_clk),                                                    //   input,   width = 1,                      clk.clk
		.reset             (rst_controller_reset_out_reset)                                      //   input,   width = 1,                    reset.reset
	);

	address_decoder_multi_channel_channel_6 channel_6 (
		.av_address        (channel_6_address),                                                  //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write          (channel_6_write),                                                    //  output,   width = 1,                         .write
		.av_read           (channel_6_read),                                                     //  output,   width = 1,                         .read
		.av_readdata       (channel_6_readdata),                                                 //   input,  width = 32,                         .readdata
		.av_writedata      (channel_6_writedata),                                                //  output,  width = 32,                         .writedata
		.av_waitrequest    (channel_6_waitrequest),                                              //   input,   width = 1,                         .waitrequest
		.uav_address       (mm_interconnect_0_channel_6_avalon_universal_slave_0_address),       //   input,  width = 16, avalon_universal_slave_0.address
		.uav_burstcount    (mm_interconnect_0_channel_6_avalon_universal_slave_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read          (mm_interconnect_0_channel_6_avalon_universal_slave_0_read),          //   input,   width = 1,                         .read
		.uav_write         (mm_interconnect_0_channel_6_avalon_universal_slave_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest   (mm_interconnect_0_channel_6_avalon_universal_slave_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid (mm_interconnect_0_channel_6_avalon_universal_slave_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable    (mm_interconnect_0_channel_6_avalon_universal_slave_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata      (mm_interconnect_0_channel_6_avalon_universal_slave_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata     (mm_interconnect_0_channel_6_avalon_universal_slave_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock          (mm_interconnect_0_channel_6_avalon_universal_slave_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess   (mm_interconnect_0_channel_6_avalon_universal_slave_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.clk               (csr_clk_clk_clk),                                                    //   input,   width = 1,                      clk.clk
		.reset             (rst_controller_reset_out_reset)                                      //   input,   width = 1,                    reset.reset
	);

	address_decoder_multi_channel_channel_7 channel_7 (
		.av_address        (channel_7_address),                                                  //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write          (channel_7_write),                                                    //  output,   width = 1,                         .write
		.av_read           (channel_7_read),                                                     //  output,   width = 1,                         .read
		.av_readdata       (channel_7_readdata),                                                 //   input,  width = 32,                         .readdata
		.av_writedata      (channel_7_writedata),                                                //  output,  width = 32,                         .writedata
		.av_waitrequest    (channel_7_waitrequest),                                              //   input,   width = 1,                         .waitrequest
		.uav_address       (mm_interconnect_0_channel_7_avalon_universal_slave_0_address),       //   input,  width = 16, avalon_universal_slave_0.address
		.uav_burstcount    (mm_interconnect_0_channel_7_avalon_universal_slave_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read          (mm_interconnect_0_channel_7_avalon_universal_slave_0_read),          //   input,   width = 1,                         .read
		.uav_write         (mm_interconnect_0_channel_7_avalon_universal_slave_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest   (mm_interconnect_0_channel_7_avalon_universal_slave_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid (mm_interconnect_0_channel_7_avalon_universal_slave_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable    (mm_interconnect_0_channel_7_avalon_universal_slave_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata      (mm_interconnect_0_channel_7_avalon_universal_slave_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata     (mm_interconnect_0_channel_7_avalon_universal_slave_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock          (mm_interconnect_0_channel_7_avalon_universal_slave_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess   (mm_interconnect_0_channel_7_avalon_universal_slave_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.clk               (csr_clk_clk_clk),                                                    //   input,   width = 1,                      clk.clk
		.reset             (rst_controller_reset_out_reset)                                      //   input,   width = 1,                    reset.reset
	);

	address_decoder_multi_channel_channel_8 channel_8 (
		.av_address        (channel_8_address),                                                  //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write          (channel_8_write),                                                    //  output,   width = 1,                         .write
		.av_read           (channel_8_read),                                                     //  output,   width = 1,                         .read
		.av_readdata       (channel_8_readdata),                                                 //   input,  width = 32,                         .readdata
		.av_writedata      (channel_8_writedata),                                                //  output,  width = 32,                         .writedata
		.av_waitrequest    (channel_8_waitrequest),                                              //   input,   width = 1,                         .waitrequest
		.uav_address       (mm_interconnect_0_channel_8_avalon_universal_slave_0_address),       //   input,  width = 16, avalon_universal_slave_0.address
		.uav_burstcount    (mm_interconnect_0_channel_8_avalon_universal_slave_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read          (mm_interconnect_0_channel_8_avalon_universal_slave_0_read),          //   input,   width = 1,                         .read
		.uav_write         (mm_interconnect_0_channel_8_avalon_universal_slave_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest   (mm_interconnect_0_channel_8_avalon_universal_slave_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid (mm_interconnect_0_channel_8_avalon_universal_slave_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable    (mm_interconnect_0_channel_8_avalon_universal_slave_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata      (mm_interconnect_0_channel_8_avalon_universal_slave_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata     (mm_interconnect_0_channel_8_avalon_universal_slave_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock          (mm_interconnect_0_channel_8_avalon_universal_slave_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess   (mm_interconnect_0_channel_8_avalon_universal_slave_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.clk               (csr_clk_clk_clk),                                                    //   input,   width = 1,                      clk.clk
		.reset             (rst_controller_reset_out_reset)                                      //   input,   width = 1,                    reset.reset
	);

	address_decoder_multi_channel_channel_9 channel_9 (
		.av_address        (channel_9_address),                                                  //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write          (channel_9_write),                                                    //  output,   width = 1,                         .write
		.av_read           (channel_9_read),                                                     //  output,   width = 1,                         .read
		.av_readdata       (channel_9_readdata),                                                 //   input,  width = 32,                         .readdata
		.av_writedata      (channel_9_writedata),                                                //  output,  width = 32,                         .writedata
		.av_waitrequest    (channel_9_waitrequest),                                              //   input,   width = 1,                         .waitrequest
		.uav_address       (mm_interconnect_0_channel_9_avalon_universal_slave_0_address),       //   input,  width = 16, avalon_universal_slave_0.address
		.uav_burstcount    (mm_interconnect_0_channel_9_avalon_universal_slave_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read          (mm_interconnect_0_channel_9_avalon_universal_slave_0_read),          //   input,   width = 1,                         .read
		.uav_write         (mm_interconnect_0_channel_9_avalon_universal_slave_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest   (mm_interconnect_0_channel_9_avalon_universal_slave_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid (mm_interconnect_0_channel_9_avalon_universal_slave_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable    (mm_interconnect_0_channel_9_avalon_universal_slave_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata      (mm_interconnect_0_channel_9_avalon_universal_slave_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata     (mm_interconnect_0_channel_9_avalon_universal_slave_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock          (mm_interconnect_0_channel_9_avalon_universal_slave_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess   (mm_interconnect_0_channel_9_avalon_universal_slave_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.clk               (csr_clk_clk_clk),                                                    //   input,   width = 1,                      clk.clk
		.reset             (rst_controller_reset_out_reset)                                      //   input,   width = 1,                    reset.reset
	);

	address_decoder_multi_channel_csr_clk csr_clk (
		.clk_out     (csr_clk_clk_clk),         //  output,  width = 1,          clk.clk
		.in_clk      (csr_clk_clk),             //   input,  width = 1,       clk_in.clk
		.reset_n     (csr_clk_reset_reset_n),   //   input,  width = 1, clk_in_reset.reset_n
		.reset_n_out (csr_clk_clk_reset_reset)  //  output,  width = 1,    clk_reset.reset_n
	);

	address_decoder_multi_channel_master master (
		.av_address        (slave_address),                                  //   input,  width = 20,      avalon_anti_master_0.address
		.av_waitrequest    (slave_waitrequest),                              //  output,   width = 1,                          .waitrequest
		.av_read           (slave_read),                                     //   input,   width = 1,                          .read
		.av_readdata       (slave_readdata),                                 //  output,  width = 32,                          .readdata
		.av_write          (slave_write),                                    //   input,   width = 1,                          .write
		.av_writedata      (slave_writedata),                                //   input,  width = 32,                          .writedata
		.uav_address       (master_avalon_universal_master_0_address),       //  output,  width = 32, avalon_universal_master_0.address
		.uav_burstcount    (master_avalon_universal_master_0_burstcount),    //  output,   width = 3,                          .burstcount
		.uav_read          (master_avalon_universal_master_0_read),          //  output,   width = 1,                          .read
		.uav_write         (master_avalon_universal_master_0_write),         //  output,   width = 1,                          .write
		.uav_waitrequest   (master_avalon_universal_master_0_waitrequest),   //   input,   width = 1,                          .waitrequest
		.uav_readdatavalid (master_avalon_universal_master_0_readdatavalid), //   input,   width = 1,                          .readdatavalid
		.uav_byteenable    (master_avalon_universal_master_0_byteenable),    //  output,   width = 4,                          .byteenable
		.uav_readdata      (master_avalon_universal_master_0_readdata),      //   input,  width = 32,                          .readdata
		.uav_writedata     (master_avalon_universal_master_0_writedata),     //  output,  width = 32,                          .writedata
		.uav_lock          (master_avalon_universal_master_0_lock),          //  output,   width = 1,                          .lock
		.uav_debugaccess   (master_avalon_universal_master_0_debugaccess),   //  output,   width = 1,                          .debugaccess
		.clk               (csr_clk_clk_clk),                                //   input,   width = 1,                       clk.clk
		.reset             (rst_controller_reset_out_reset)                  //   input,   width = 1,                     reset.reset
	);

	address_decoder_multi_channel_altera_mm_interconnect_191_yxycpgi mm_interconnect_0 (
		.master_avalon_universal_master_0_address          (master_avalon_universal_master_0_address),                            //   input,  width = 32,    master_avalon_universal_master_0.address
		.master_avalon_universal_master_0_waitrequest      (master_avalon_universal_master_0_waitrequest),                        //  output,   width = 1,                                    .waitrequest
		.master_avalon_universal_master_0_burstcount       (master_avalon_universal_master_0_burstcount),                         //   input,   width = 3,                                    .burstcount
		.master_avalon_universal_master_0_byteenable       (master_avalon_universal_master_0_byteenable),                         //   input,   width = 4,                                    .byteenable
		.master_avalon_universal_master_0_read             (master_avalon_universal_master_0_read),                               //   input,   width = 1,                                    .read
		.master_avalon_universal_master_0_readdata         (master_avalon_universal_master_0_readdata),                           //  output,  width = 32,                                    .readdata
		.master_avalon_universal_master_0_readdatavalid    (master_avalon_universal_master_0_readdatavalid),                      //  output,   width = 1,                                    .readdatavalid
		.master_avalon_universal_master_0_write            (master_avalon_universal_master_0_write),                              //   input,   width = 1,                                    .write
		.master_avalon_universal_master_0_writedata        (master_avalon_universal_master_0_writedata),                          //   input,  width = 32,                                    .writedata
		.master_avalon_universal_master_0_lock             (master_avalon_universal_master_0_lock),                               //   input,   width = 1,                                    .lock
		.master_avalon_universal_master_0_debugaccess      (master_avalon_universal_master_0_debugaccess),                        //   input,   width = 1,                                    .debugaccess
		.channel_1_avalon_universal_slave_0_address        (mm_interconnect_0_channel_1_avalon_universal_slave_0_address),        //  output,  width = 16,  channel_1_avalon_universal_slave_0.address
		.channel_1_avalon_universal_slave_0_write          (mm_interconnect_0_channel_1_avalon_universal_slave_0_write),          //  output,   width = 1,                                    .write
		.channel_1_avalon_universal_slave_0_read           (mm_interconnect_0_channel_1_avalon_universal_slave_0_read),           //  output,   width = 1,                                    .read
		.channel_1_avalon_universal_slave_0_readdata       (mm_interconnect_0_channel_1_avalon_universal_slave_0_readdata),       //   input,  width = 32,                                    .readdata
		.channel_1_avalon_universal_slave_0_writedata      (mm_interconnect_0_channel_1_avalon_universal_slave_0_writedata),      //  output,  width = 32,                                    .writedata
		.channel_1_avalon_universal_slave_0_burstcount     (mm_interconnect_0_channel_1_avalon_universal_slave_0_burstcount),     //  output,   width = 3,                                    .burstcount
		.channel_1_avalon_universal_slave_0_byteenable     (mm_interconnect_0_channel_1_avalon_universal_slave_0_byteenable),     //  output,   width = 4,                                    .byteenable
		.channel_1_avalon_universal_slave_0_readdatavalid  (mm_interconnect_0_channel_1_avalon_universal_slave_0_readdatavalid),  //   input,   width = 1,                                    .readdatavalid
		.channel_1_avalon_universal_slave_0_waitrequest    (mm_interconnect_0_channel_1_avalon_universal_slave_0_waitrequest),    //   input,   width = 1,                                    .waitrequest
		.channel_1_avalon_universal_slave_0_lock           (mm_interconnect_0_channel_1_avalon_universal_slave_0_lock),           //  output,   width = 1,                                    .lock
		.channel_1_avalon_universal_slave_0_debugaccess    (mm_interconnect_0_channel_1_avalon_universal_slave_0_debugaccess),    //  output,   width = 1,                                    .debugaccess
		.channel_0_avalon_universal_slave_0_address        (mm_interconnect_0_channel_0_avalon_universal_slave_0_address),        //  output,  width = 16,  channel_0_avalon_universal_slave_0.address
		.channel_0_avalon_universal_slave_0_write          (mm_interconnect_0_channel_0_avalon_universal_slave_0_write),          //  output,   width = 1,                                    .write
		.channel_0_avalon_universal_slave_0_read           (mm_interconnect_0_channel_0_avalon_universal_slave_0_read),           //  output,   width = 1,                                    .read
		.channel_0_avalon_universal_slave_0_readdata       (mm_interconnect_0_channel_0_avalon_universal_slave_0_readdata),       //   input,  width = 32,                                    .readdata
		.channel_0_avalon_universal_slave_0_writedata      (mm_interconnect_0_channel_0_avalon_universal_slave_0_writedata),      //  output,  width = 32,                                    .writedata
		.channel_0_avalon_universal_slave_0_burstcount     (mm_interconnect_0_channel_0_avalon_universal_slave_0_burstcount),     //  output,   width = 3,                                    .burstcount
		.channel_0_avalon_universal_slave_0_byteenable     (mm_interconnect_0_channel_0_avalon_universal_slave_0_byteenable),     //  output,   width = 4,                                    .byteenable
		.channel_0_avalon_universal_slave_0_readdatavalid  (mm_interconnect_0_channel_0_avalon_universal_slave_0_readdatavalid),  //   input,   width = 1,                                    .readdatavalid
		.channel_0_avalon_universal_slave_0_waitrequest    (mm_interconnect_0_channel_0_avalon_universal_slave_0_waitrequest),    //   input,   width = 1,                                    .waitrequest
		.channel_0_avalon_universal_slave_0_lock           (mm_interconnect_0_channel_0_avalon_universal_slave_0_lock),           //  output,   width = 1,                                    .lock
		.channel_0_avalon_universal_slave_0_debugaccess    (mm_interconnect_0_channel_0_avalon_universal_slave_0_debugaccess),    //  output,   width = 1,                                    .debugaccess
		.channel_2_avalon_universal_slave_0_address        (mm_interconnect_0_channel_2_avalon_universal_slave_0_address),        //  output,  width = 16,  channel_2_avalon_universal_slave_0.address
		.channel_2_avalon_universal_slave_0_write          (mm_interconnect_0_channel_2_avalon_universal_slave_0_write),          //  output,   width = 1,                                    .write
		.channel_2_avalon_universal_slave_0_read           (mm_interconnect_0_channel_2_avalon_universal_slave_0_read),           //  output,   width = 1,                                    .read
		.channel_2_avalon_universal_slave_0_readdata       (mm_interconnect_0_channel_2_avalon_universal_slave_0_readdata),       //   input,  width = 32,                                    .readdata
		.channel_2_avalon_universal_slave_0_writedata      (mm_interconnect_0_channel_2_avalon_universal_slave_0_writedata),      //  output,  width = 32,                                    .writedata
		.channel_2_avalon_universal_slave_0_burstcount     (mm_interconnect_0_channel_2_avalon_universal_slave_0_burstcount),     //  output,   width = 3,                                    .burstcount
		.channel_2_avalon_universal_slave_0_byteenable     (mm_interconnect_0_channel_2_avalon_universal_slave_0_byteenable),     //  output,   width = 4,                                    .byteenable
		.channel_2_avalon_universal_slave_0_readdatavalid  (mm_interconnect_0_channel_2_avalon_universal_slave_0_readdatavalid),  //   input,   width = 1,                                    .readdatavalid
		.channel_2_avalon_universal_slave_0_waitrequest    (mm_interconnect_0_channel_2_avalon_universal_slave_0_waitrequest),    //   input,   width = 1,                                    .waitrequest
		.channel_2_avalon_universal_slave_0_lock           (mm_interconnect_0_channel_2_avalon_universal_slave_0_lock),           //  output,   width = 1,                                    .lock
		.channel_2_avalon_universal_slave_0_debugaccess    (mm_interconnect_0_channel_2_avalon_universal_slave_0_debugaccess),    //  output,   width = 1,                                    .debugaccess
		.channel_3_avalon_universal_slave_0_address        (mm_interconnect_0_channel_3_avalon_universal_slave_0_address),        //  output,  width = 16,  channel_3_avalon_universal_slave_0.address
		.channel_3_avalon_universal_slave_0_write          (mm_interconnect_0_channel_3_avalon_universal_slave_0_write),          //  output,   width = 1,                                    .write
		.channel_3_avalon_universal_slave_0_read           (mm_interconnect_0_channel_3_avalon_universal_slave_0_read),           //  output,   width = 1,                                    .read
		.channel_3_avalon_universal_slave_0_readdata       (mm_interconnect_0_channel_3_avalon_universal_slave_0_readdata),       //   input,  width = 32,                                    .readdata
		.channel_3_avalon_universal_slave_0_writedata      (mm_interconnect_0_channel_3_avalon_universal_slave_0_writedata),      //  output,  width = 32,                                    .writedata
		.channel_3_avalon_universal_slave_0_burstcount     (mm_interconnect_0_channel_3_avalon_universal_slave_0_burstcount),     //  output,   width = 3,                                    .burstcount
		.channel_3_avalon_universal_slave_0_byteenable     (mm_interconnect_0_channel_3_avalon_universal_slave_0_byteenable),     //  output,   width = 4,                                    .byteenable
		.channel_3_avalon_universal_slave_0_readdatavalid  (mm_interconnect_0_channel_3_avalon_universal_slave_0_readdatavalid),  //   input,   width = 1,                                    .readdatavalid
		.channel_3_avalon_universal_slave_0_waitrequest    (mm_interconnect_0_channel_3_avalon_universal_slave_0_waitrequest),    //   input,   width = 1,                                    .waitrequest
		.channel_3_avalon_universal_slave_0_lock           (mm_interconnect_0_channel_3_avalon_universal_slave_0_lock),           //  output,   width = 1,                                    .lock
		.channel_3_avalon_universal_slave_0_debugaccess    (mm_interconnect_0_channel_3_avalon_universal_slave_0_debugaccess),    //  output,   width = 1,                                    .debugaccess
		.channel_4_avalon_universal_slave_0_address        (mm_interconnect_0_channel_4_avalon_universal_slave_0_address),        //  output,  width = 16,  channel_4_avalon_universal_slave_0.address
		.channel_4_avalon_universal_slave_0_write          (mm_interconnect_0_channel_4_avalon_universal_slave_0_write),          //  output,   width = 1,                                    .write
		.channel_4_avalon_universal_slave_0_read           (mm_interconnect_0_channel_4_avalon_universal_slave_0_read),           //  output,   width = 1,                                    .read
		.channel_4_avalon_universal_slave_0_readdata       (mm_interconnect_0_channel_4_avalon_universal_slave_0_readdata),       //   input,  width = 32,                                    .readdata
		.channel_4_avalon_universal_slave_0_writedata      (mm_interconnect_0_channel_4_avalon_universal_slave_0_writedata),      //  output,  width = 32,                                    .writedata
		.channel_4_avalon_universal_slave_0_burstcount     (mm_interconnect_0_channel_4_avalon_universal_slave_0_burstcount),     //  output,   width = 3,                                    .burstcount
		.channel_4_avalon_universal_slave_0_byteenable     (mm_interconnect_0_channel_4_avalon_universal_slave_0_byteenable),     //  output,   width = 4,                                    .byteenable
		.channel_4_avalon_universal_slave_0_readdatavalid  (mm_interconnect_0_channel_4_avalon_universal_slave_0_readdatavalid),  //   input,   width = 1,                                    .readdatavalid
		.channel_4_avalon_universal_slave_0_waitrequest    (mm_interconnect_0_channel_4_avalon_universal_slave_0_waitrequest),    //   input,   width = 1,                                    .waitrequest
		.channel_4_avalon_universal_slave_0_lock           (mm_interconnect_0_channel_4_avalon_universal_slave_0_lock),           //  output,   width = 1,                                    .lock
		.channel_4_avalon_universal_slave_0_debugaccess    (mm_interconnect_0_channel_4_avalon_universal_slave_0_debugaccess),    //  output,   width = 1,                                    .debugaccess
		.channel_5_avalon_universal_slave_0_address        (mm_interconnect_0_channel_5_avalon_universal_slave_0_address),        //  output,  width = 16,  channel_5_avalon_universal_slave_0.address
		.channel_5_avalon_universal_slave_0_write          (mm_interconnect_0_channel_5_avalon_universal_slave_0_write),          //  output,   width = 1,                                    .write
		.channel_5_avalon_universal_slave_0_read           (mm_interconnect_0_channel_5_avalon_universal_slave_0_read),           //  output,   width = 1,                                    .read
		.channel_5_avalon_universal_slave_0_readdata       (mm_interconnect_0_channel_5_avalon_universal_slave_0_readdata),       //   input,  width = 32,                                    .readdata
		.channel_5_avalon_universal_slave_0_writedata      (mm_interconnect_0_channel_5_avalon_universal_slave_0_writedata),      //  output,  width = 32,                                    .writedata
		.channel_5_avalon_universal_slave_0_burstcount     (mm_interconnect_0_channel_5_avalon_universal_slave_0_burstcount),     //  output,   width = 3,                                    .burstcount
		.channel_5_avalon_universal_slave_0_byteenable     (mm_interconnect_0_channel_5_avalon_universal_slave_0_byteenable),     //  output,   width = 4,                                    .byteenable
		.channel_5_avalon_universal_slave_0_readdatavalid  (mm_interconnect_0_channel_5_avalon_universal_slave_0_readdatavalid),  //   input,   width = 1,                                    .readdatavalid
		.channel_5_avalon_universal_slave_0_waitrequest    (mm_interconnect_0_channel_5_avalon_universal_slave_0_waitrequest),    //   input,   width = 1,                                    .waitrequest
		.channel_5_avalon_universal_slave_0_lock           (mm_interconnect_0_channel_5_avalon_universal_slave_0_lock),           //  output,   width = 1,                                    .lock
		.channel_5_avalon_universal_slave_0_debugaccess    (mm_interconnect_0_channel_5_avalon_universal_slave_0_debugaccess),    //  output,   width = 1,                                    .debugaccess
		.channel_6_avalon_universal_slave_0_address        (mm_interconnect_0_channel_6_avalon_universal_slave_0_address),        //  output,  width = 16,  channel_6_avalon_universal_slave_0.address
		.channel_6_avalon_universal_slave_0_write          (mm_interconnect_0_channel_6_avalon_universal_slave_0_write),          //  output,   width = 1,                                    .write
		.channel_6_avalon_universal_slave_0_read           (mm_interconnect_0_channel_6_avalon_universal_slave_0_read),           //  output,   width = 1,                                    .read
		.channel_6_avalon_universal_slave_0_readdata       (mm_interconnect_0_channel_6_avalon_universal_slave_0_readdata),       //   input,  width = 32,                                    .readdata
		.channel_6_avalon_universal_slave_0_writedata      (mm_interconnect_0_channel_6_avalon_universal_slave_0_writedata),      //  output,  width = 32,                                    .writedata
		.channel_6_avalon_universal_slave_0_burstcount     (mm_interconnect_0_channel_6_avalon_universal_slave_0_burstcount),     //  output,   width = 3,                                    .burstcount
		.channel_6_avalon_universal_slave_0_byteenable     (mm_interconnect_0_channel_6_avalon_universal_slave_0_byteenable),     //  output,   width = 4,                                    .byteenable
		.channel_6_avalon_universal_slave_0_readdatavalid  (mm_interconnect_0_channel_6_avalon_universal_slave_0_readdatavalid),  //   input,   width = 1,                                    .readdatavalid
		.channel_6_avalon_universal_slave_0_waitrequest    (mm_interconnect_0_channel_6_avalon_universal_slave_0_waitrequest),    //   input,   width = 1,                                    .waitrequest
		.channel_6_avalon_universal_slave_0_lock           (mm_interconnect_0_channel_6_avalon_universal_slave_0_lock),           //  output,   width = 1,                                    .lock
		.channel_6_avalon_universal_slave_0_debugaccess    (mm_interconnect_0_channel_6_avalon_universal_slave_0_debugaccess),    //  output,   width = 1,                                    .debugaccess
		.channel_7_avalon_universal_slave_0_address        (mm_interconnect_0_channel_7_avalon_universal_slave_0_address),        //  output,  width = 16,  channel_7_avalon_universal_slave_0.address
		.channel_7_avalon_universal_slave_0_write          (mm_interconnect_0_channel_7_avalon_universal_slave_0_write),          //  output,   width = 1,                                    .write
		.channel_7_avalon_universal_slave_0_read           (mm_interconnect_0_channel_7_avalon_universal_slave_0_read),           //  output,   width = 1,                                    .read
		.channel_7_avalon_universal_slave_0_readdata       (mm_interconnect_0_channel_7_avalon_universal_slave_0_readdata),       //   input,  width = 32,                                    .readdata
		.channel_7_avalon_universal_slave_0_writedata      (mm_interconnect_0_channel_7_avalon_universal_slave_0_writedata),      //  output,  width = 32,                                    .writedata
		.channel_7_avalon_universal_slave_0_burstcount     (mm_interconnect_0_channel_7_avalon_universal_slave_0_burstcount),     //  output,   width = 3,                                    .burstcount
		.channel_7_avalon_universal_slave_0_byteenable     (mm_interconnect_0_channel_7_avalon_universal_slave_0_byteenable),     //  output,   width = 4,                                    .byteenable
		.channel_7_avalon_universal_slave_0_readdatavalid  (mm_interconnect_0_channel_7_avalon_universal_slave_0_readdatavalid),  //   input,   width = 1,                                    .readdatavalid
		.channel_7_avalon_universal_slave_0_waitrequest    (mm_interconnect_0_channel_7_avalon_universal_slave_0_waitrequest),    //   input,   width = 1,                                    .waitrequest
		.channel_7_avalon_universal_slave_0_lock           (mm_interconnect_0_channel_7_avalon_universal_slave_0_lock),           //  output,   width = 1,                                    .lock
		.channel_7_avalon_universal_slave_0_debugaccess    (mm_interconnect_0_channel_7_avalon_universal_slave_0_debugaccess),    //  output,   width = 1,                                    .debugaccess
		.channel_8_avalon_universal_slave_0_address        (mm_interconnect_0_channel_8_avalon_universal_slave_0_address),        //  output,  width = 16,  channel_8_avalon_universal_slave_0.address
		.channel_8_avalon_universal_slave_0_write          (mm_interconnect_0_channel_8_avalon_universal_slave_0_write),          //  output,   width = 1,                                    .write
		.channel_8_avalon_universal_slave_0_read           (mm_interconnect_0_channel_8_avalon_universal_slave_0_read),           //  output,   width = 1,                                    .read
		.channel_8_avalon_universal_slave_0_readdata       (mm_interconnect_0_channel_8_avalon_universal_slave_0_readdata),       //   input,  width = 32,                                    .readdata
		.channel_8_avalon_universal_slave_0_writedata      (mm_interconnect_0_channel_8_avalon_universal_slave_0_writedata),      //  output,  width = 32,                                    .writedata
		.channel_8_avalon_universal_slave_0_burstcount     (mm_interconnect_0_channel_8_avalon_universal_slave_0_burstcount),     //  output,   width = 3,                                    .burstcount
		.channel_8_avalon_universal_slave_0_byteenable     (mm_interconnect_0_channel_8_avalon_universal_slave_0_byteenable),     //  output,   width = 4,                                    .byteenable
		.channel_8_avalon_universal_slave_0_readdatavalid  (mm_interconnect_0_channel_8_avalon_universal_slave_0_readdatavalid),  //   input,   width = 1,                                    .readdatavalid
		.channel_8_avalon_universal_slave_0_waitrequest    (mm_interconnect_0_channel_8_avalon_universal_slave_0_waitrequest),    //   input,   width = 1,                                    .waitrequest
		.channel_8_avalon_universal_slave_0_lock           (mm_interconnect_0_channel_8_avalon_universal_slave_0_lock),           //  output,   width = 1,                                    .lock
		.channel_8_avalon_universal_slave_0_debugaccess    (mm_interconnect_0_channel_8_avalon_universal_slave_0_debugaccess),    //  output,   width = 1,                                    .debugaccess
		.channel_9_avalon_universal_slave_0_address        (mm_interconnect_0_channel_9_avalon_universal_slave_0_address),        //  output,  width = 16,  channel_9_avalon_universal_slave_0.address
		.channel_9_avalon_universal_slave_0_write          (mm_interconnect_0_channel_9_avalon_universal_slave_0_write),          //  output,   width = 1,                                    .write
		.channel_9_avalon_universal_slave_0_read           (mm_interconnect_0_channel_9_avalon_universal_slave_0_read),           //  output,   width = 1,                                    .read
		.channel_9_avalon_universal_slave_0_readdata       (mm_interconnect_0_channel_9_avalon_universal_slave_0_readdata),       //   input,  width = 32,                                    .readdata
		.channel_9_avalon_universal_slave_0_writedata      (mm_interconnect_0_channel_9_avalon_universal_slave_0_writedata),      //  output,  width = 32,                                    .writedata
		.channel_9_avalon_universal_slave_0_burstcount     (mm_interconnect_0_channel_9_avalon_universal_slave_0_burstcount),     //  output,   width = 3,                                    .burstcount
		.channel_9_avalon_universal_slave_0_byteenable     (mm_interconnect_0_channel_9_avalon_universal_slave_0_byteenable),     //  output,   width = 4,                                    .byteenable
		.channel_9_avalon_universal_slave_0_readdatavalid  (mm_interconnect_0_channel_9_avalon_universal_slave_0_readdatavalid),  //   input,   width = 1,                                    .readdatavalid
		.channel_9_avalon_universal_slave_0_waitrequest    (mm_interconnect_0_channel_9_avalon_universal_slave_0_waitrequest),    //   input,   width = 1,                                    .waitrequest
		.channel_9_avalon_universal_slave_0_lock           (mm_interconnect_0_channel_9_avalon_universal_slave_0_lock),           //  output,   width = 1,                                    .lock
		.channel_9_avalon_universal_slave_0_debugaccess    (mm_interconnect_0_channel_9_avalon_universal_slave_0_debugaccess),    //  output,   width = 1,                                    .debugaccess
		.channel_10_avalon_universal_slave_0_address       (mm_interconnect_0_channel_10_avalon_universal_slave_0_address),       //  output,  width = 16, channel_10_avalon_universal_slave_0.address
		.channel_10_avalon_universal_slave_0_write         (mm_interconnect_0_channel_10_avalon_universal_slave_0_write),         //  output,   width = 1,                                    .write
		.channel_10_avalon_universal_slave_0_read          (mm_interconnect_0_channel_10_avalon_universal_slave_0_read),          //  output,   width = 1,                                    .read
		.channel_10_avalon_universal_slave_0_readdata      (mm_interconnect_0_channel_10_avalon_universal_slave_0_readdata),      //   input,  width = 32,                                    .readdata
		.channel_10_avalon_universal_slave_0_writedata     (mm_interconnect_0_channel_10_avalon_universal_slave_0_writedata),     //  output,  width = 32,                                    .writedata
		.channel_10_avalon_universal_slave_0_burstcount    (mm_interconnect_0_channel_10_avalon_universal_slave_0_burstcount),    //  output,   width = 3,                                    .burstcount
		.channel_10_avalon_universal_slave_0_byteenable    (mm_interconnect_0_channel_10_avalon_universal_slave_0_byteenable),    //  output,   width = 4,                                    .byteenable
		.channel_10_avalon_universal_slave_0_readdatavalid (mm_interconnect_0_channel_10_avalon_universal_slave_0_readdatavalid), //   input,   width = 1,                                    .readdatavalid
		.channel_10_avalon_universal_slave_0_waitrequest   (mm_interconnect_0_channel_10_avalon_universal_slave_0_waitrequest),   //   input,   width = 1,                                    .waitrequest
		.channel_10_avalon_universal_slave_0_lock          (mm_interconnect_0_channel_10_avalon_universal_slave_0_lock),          //  output,   width = 1,                                    .lock
		.channel_10_avalon_universal_slave_0_debugaccess   (mm_interconnect_0_channel_10_avalon_universal_slave_0_debugaccess),   //  output,   width = 1,                                    .debugaccess
		.channel_11_avalon_universal_slave_0_address       (mm_interconnect_0_channel_11_avalon_universal_slave_0_address),       //  output,  width = 16, channel_11_avalon_universal_slave_0.address
		.channel_11_avalon_universal_slave_0_write         (mm_interconnect_0_channel_11_avalon_universal_slave_0_write),         //  output,   width = 1,                                    .write
		.channel_11_avalon_universal_slave_0_read          (mm_interconnect_0_channel_11_avalon_universal_slave_0_read),          //  output,   width = 1,                                    .read
		.channel_11_avalon_universal_slave_0_readdata      (mm_interconnect_0_channel_11_avalon_universal_slave_0_readdata),      //   input,  width = 32,                                    .readdata
		.channel_11_avalon_universal_slave_0_writedata     (mm_interconnect_0_channel_11_avalon_universal_slave_0_writedata),     //  output,  width = 32,                                    .writedata
		.channel_11_avalon_universal_slave_0_burstcount    (mm_interconnect_0_channel_11_avalon_universal_slave_0_burstcount),    //  output,   width = 3,                                    .burstcount
		.channel_11_avalon_universal_slave_0_byteenable    (mm_interconnect_0_channel_11_avalon_universal_slave_0_byteenable),    //  output,   width = 4,                                    .byteenable
		.channel_11_avalon_universal_slave_0_readdatavalid (mm_interconnect_0_channel_11_avalon_universal_slave_0_readdatavalid), //   input,   width = 1,                                    .readdatavalid
		.channel_11_avalon_universal_slave_0_waitrequest   (mm_interconnect_0_channel_11_avalon_universal_slave_0_waitrequest),   //   input,   width = 1,                                    .waitrequest
		.channel_11_avalon_universal_slave_0_lock          (mm_interconnect_0_channel_11_avalon_universal_slave_0_lock),          //  output,   width = 1,                                    .lock
		.channel_11_avalon_universal_slave_0_debugaccess   (mm_interconnect_0_channel_11_avalon_universal_slave_0_debugaccess),   //  output,   width = 1,                                    .debugaccess
		.master_reset_reset_bridge_in_reset_reset          (rst_controller_reset_out_reset),                                      //   input,   width = 1,  master_reset_reset_bridge_in_reset.reset
		.csr_clk_clk_clk                                   (csr_clk_clk_clk)                                                      //   input,   width = 1,                         csr_clk_clk.clk
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~csr_clk_clk_reset_reset),       //   input,  width = 1, reset_in0.reset
		.clk            (csr_clk_clk_clk),                //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                               // (terminated),                       
		.reset_req_in0  (1'b0),                           // (terminated),                       
		.reset_in1      (1'b0),                           // (terminated),                       
		.reset_req_in1  (1'b0),                           // (terminated),                       
		.reset_in2      (1'b0),                           // (terminated),                       
		.reset_req_in2  (1'b0),                           // (terminated),                       
		.reset_in3      (1'b0),                           // (terminated),                       
		.reset_req_in3  (1'b0),                           // (terminated),                       
		.reset_in4      (1'b0),                           // (terminated),                       
		.reset_req_in4  (1'b0),                           // (terminated),                       
		.reset_in5      (1'b0),                           // (terminated),                       
		.reset_req_in5  (1'b0),                           // (terminated),                       
		.reset_in6      (1'b0),                           // (terminated),                       
		.reset_req_in6  (1'b0),                           // (terminated),                       
		.reset_in7      (1'b0),                           // (terminated),                       
		.reset_req_in7  (1'b0),                           // (terminated),                       
		.reset_in8      (1'b0),                           // (terminated),                       
		.reset_req_in8  (1'b0),                           // (terminated),                       
		.reset_in9      (1'b0),                           // (terminated),                       
		.reset_req_in9  (1'b0),                           // (terminated),                       
		.reset_in10     (1'b0),                           // (terminated),                       
		.reset_req_in10 (1'b0),                           // (terminated),                       
		.reset_in11     (1'b0),                           // (terminated),                       
		.reset_req_in11 (1'b0),                           // (terminated),                       
		.reset_in12     (1'b0),                           // (terminated),                       
		.reset_req_in12 (1'b0),                           // (terminated),                       
		.reset_in13     (1'b0),                           // (terminated),                       
		.reset_req_in13 (1'b0),                           // (terminated),                       
		.reset_in14     (1'b0),                           // (terminated),                       
		.reset_req_in14 (1'b0),                           // (terminated),                       
		.reset_in15     (1'b0),                           // (terminated),                       
		.reset_req_in15 (1'b0)                            // (terminated),                       
	);

endmodule
