# system info alt_jtag_csr_master on 2020.01.29.11:22:18
system_info:
name,value
DEVICE,1SG165HU2F50E2VG
DEVICE_FAMILY,Stratix 10
GENERATION_ID,0
#
#
# Files generated for alt_jtag_csr_master on 2020.01.29.11:22:18
files:
filepath,kind,attributes,module,is_top
sim/alt_jtag_csr_master.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,alt_jtag_csr_master,true
altera_jtag_avalon_master_191/sim/alt_jtag_csr_master_altera_jtag_avalon_master_191_3zppvky.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,alt_jtag_csr_master_altera_jtag_avalon_master_191_3zppvky,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_jtag_dc_streaming.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_jtag_sld_node.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_jtag_streaming.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_clock_crosser.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_std_synchronizer_nocut.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_base.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_remover.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_inserter.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_stage.sv,SYSTEM_VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.sdc,SDC_ENTITY,NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION,altera_avalon_st_jtag_interface,false
timing_adapter_191/sim/alt_jtag_csr_master_timing_adapter_191_rrgemwi.sv,SYSTEM_VERILOG,,alt_jtag_csr_master_timing_adapter_191_rrgemwi,false
altera_avalon_sc_fifo_191/sim/alt_jtag_csr_master_altera_avalon_sc_fifo_191_e5eqkcq.v,VERILOG,,alt_jtag_csr_master_altera_avalon_sc_fifo_191_e5eqkcq,false
altera_avalon_st_bytes_to_packets_1910/sim/altera_avalon_st_bytes_to_packets.v,VERILOG,,altera_avalon_st_bytes_to_packets,false
altera_avalon_st_packets_to_bytes_1910/sim/altera_avalon_st_packets_to_bytes.v,VERILOG,,altera_avalon_st_packets_to_bytes,false
altera_avalon_packets_to_master_1910/sim/altera_avalon_packets_to_master.v,VERILOG,,altera_avalon_packets_to_master,false
channel_adapter_191/sim/alt_jtag_csr_master_channel_adapter_191_uc27kqq.sv,SYSTEM_VERILOG,,alt_jtag_csr_master_channel_adapter_191_uc27kqq,false
channel_adapter_191/sim/alt_jtag_csr_master_channel_adapter_191_cco4x3a.sv,SYSTEM_VERILOG,,alt_jtag_csr_master_channel_adapter_191_cco4x3a,false
altera_reset_controller_191/sim/mentor/altera_reset_controller.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/mentor/altera_reset_synchronizer.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/aldec/altera_reset_controller.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/aldec/altera_reset_synchronizer.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/cadence/altera_reset_controller.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/cadence/altera_reset_synchronizer.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/synopsys/altera_reset_controller.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_reset_controller,false
altera_reset_controller_191/sim/synopsys/altera_reset_synchronizer.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_reset_controller,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
alt_jtag_csr_master.master_0,alt_jtag_csr_master_altera_jtag_avalon_master_191_3zppvky
alt_jtag_csr_master.master_0.jtag_phy_embedded_in_jtag_master,altera_avalon_st_jtag_interface
alt_jtag_csr_master.master_0.timing_adt,alt_jtag_csr_master_timing_adapter_191_rrgemwi
alt_jtag_csr_master.master_0.fifo,alt_jtag_csr_master_altera_avalon_sc_fifo_191_e5eqkcq
alt_jtag_csr_master.master_0.b2p,altera_avalon_st_bytes_to_packets
alt_jtag_csr_master.master_0.p2b,altera_avalon_st_packets_to_bytes
alt_jtag_csr_master.master_0.transacto,altera_avalon_packets_to_master
alt_jtag_csr_master.master_0.b2p_adapter,alt_jtag_csr_master_channel_adapter_191_uc27kqq
alt_jtag_csr_master.master_0.p2b_adapter,alt_jtag_csr_master_channel_adapter_191_cco4x3a
alt_jtag_csr_master.master_0.rst_controller,altera_reset_controller
