Info: Generated by version: 19.4 build 64
Info: Starting: Create simulation model
Info: qsys-generate C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\reset_release\reset_release.ip --simulation=VHDL --allow-mixed-language-simulation --output-directory=C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\reset_release\reset_release --family="Stratix 10" --part=1SG165HU2F50E2VG
Info: reset_release: "Transforming system: reset_release"
Info: reset_release: "Naming system components in system: reset_release"
Info: reset_release: "Processing generation queue"
Info: reset_release: "Generating: reset_release"
Info: reset_release: "Generating: altera_s10_user_rst_clkgate"
Info: reset_release: Done "reset_release" with 2 modules, 2 files
Info: Generating the following file(s) for MODELSIM simulator in C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/reset_release/reset_release/sim/ directory:
Info: 	common/modelsim_files.tcl
Info: Generating the following file(s) for RIVIERA simulator in C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/reset_release/reset_release/sim/ directory:
Info: 	common/riviera_files.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/reset_release/reset_release/sim/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: qsys-generate succeeded.
Info: Finished: Create simulation model
Info: Starting: Create Modelsim Project.
Info: sim-script-gen --system-file=C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\reset_release\reset_release.ip --output-directory=C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/reset_release/reset_release/sim/ --use-relative-paths=true
Info: Generating the following file(s) for MODELSIM simulator in C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/reset_release/reset_release/sim/ directory:
Info: 	mentor/msim_setup.tcl
Info: Generating the following file(s) for RIVIERA simulator in C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/reset_release/reset_release/sim/ directory:
Info: 	aldec/rivierapro_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/reset_release/reset_release/sim/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create Modelsim Project.
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\reset_release\reset_release.ip --synthesis=VHDL --output-directory=C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\reset_release\reset_release --family="Stratix 10" --part=1SG165HU2F50E2VG
Info: reset_release: "Transforming system: reset_release"
Info: reset_release: "Naming system components in system: reset_release"
Info: reset_release: "Processing generation queue"
Info: reset_release: "Generating: reset_release"
Info: reset_release: "Generating: altera_s10_user_rst_clkgate"
Info: reset_release: Done "reset_release" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Starting: IP-XACT
Info: qsys-generate C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\reset_release\reset_release.ip --synthesis=VERILOG --ipxact --output-directory=C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\reset_release\reset_release --family="Stratix 10" --part=1SG165HU2F50E2VG
Info: Finished: IP-XACT
