Info: Generated by version: 19.4 build 64
Info: Starting: Create simulation model
Info: qsys-generate C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\address_decoder\ip\address_decoder_top\address_decoder_top_traffic_controller_ch_4_5.ip --simulation=VHDL --allow-mixed-language-simulation --output-directory=C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\address_decoder\ip\address_decoder_top\address_decoder_top_traffic_controller_ch_4_5 --family="Stratix 10" --part=1SG165HU2F50E2VG
Warning: traffic_controller_ch_4_5: Invalid device name in input file: 1SG280LN3F43E3VGS1
Warning: traffic_controller_ch_4_5: Used altera_merlin_slave_translator 19.1 (instead of 17.1)
Info: address_decoder_top_traffic_controller_ch_4_5: "Transforming system: address_decoder_top_traffic_controller_ch_4_5"
Info: address_decoder_top_traffic_controller_ch_4_5: "Naming system components in system: address_decoder_top_traffic_controller_ch_4_5"
Info: address_decoder_top_traffic_controller_ch_4_5: "Processing generation queue"
Info: address_decoder_top_traffic_controller_ch_4_5: "Generating: address_decoder_top_traffic_controller_ch_4_5"
Info: address_decoder_top_traffic_controller_ch_4_5: "Generating: address_decoder_top_traffic_controller_ch_4_5_altera_merlin_slave_translator_191_x56fcki"
Info: address_decoder_top_traffic_controller_ch_4_5: Done "address_decoder_top_traffic_controller_ch_4_5" with 2 modules, 2 files
Info: Generating the following file(s) for MODELSIM simulator in C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_4_5/sim/ directory:
Info: 	common/modelsim_files.tcl
Info: Generating the following file(s) for RIVIERA simulator in C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_4_5/sim/ directory:
Info: 	common/riviera_files.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_4_5/sim/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: qsys-generate succeeded.
Info: Finished: Create simulation model
Info: Starting: Create Modelsim Project.
Info: sim-script-gen --system-file=C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\address_decoder\ip\address_decoder_top\address_decoder_top_traffic_controller_ch_4_5.ip --output-directory=C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_4_5/sim/ --use-relative-paths=true
Info: Generating the following file(s) for MODELSIM simulator in C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_4_5/sim/ directory:
Info: 	mentor/msim_setup.tcl
Info: Generating the following file(s) for RIVIERA simulator in C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_4_5/sim/ directory:
Info: 	aldec/rivierapro_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_4_5/sim/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create Modelsim Project.
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\address_decoder\ip\address_decoder_top\address_decoder_top_traffic_controller_ch_4_5.ip --synthesis=VHDL --output-directory=C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\address_decoder\ip\address_decoder_top\address_decoder_top_traffic_controller_ch_4_5 --family="Stratix 10" --part=1SG165HU2F50E2VG
Warning: traffic_controller_ch_4_5: Invalid device name in input file: 1SG280LN3F43E3VGS1
Warning: traffic_controller_ch_4_5: Used altera_merlin_slave_translator 19.1 (instead of 17.1)
Info: address_decoder_top_traffic_controller_ch_4_5: "Transforming system: address_decoder_top_traffic_controller_ch_4_5"
Info: address_decoder_top_traffic_controller_ch_4_5: "Naming system components in system: address_decoder_top_traffic_controller_ch_4_5"
Info: address_decoder_top_traffic_controller_ch_4_5: "Processing generation queue"
Info: address_decoder_top_traffic_controller_ch_4_5: "Generating: address_decoder_top_traffic_controller_ch_4_5"
Info: address_decoder_top_traffic_controller_ch_4_5: "Generating: address_decoder_top_traffic_controller_ch_4_5_altera_merlin_slave_translator_191_x56fcki"
Info: address_decoder_top_traffic_controller_ch_4_5: Done "address_decoder_top_traffic_controller_ch_4_5" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Starting: IP-XACT
Info: qsys-generate C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\address_decoder\ip\address_decoder_top\address_decoder_top_traffic_controller_ch_4_5.ip --synthesis=VERILOG --ipxact --output-directory=C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\address_decoder\ip\address_decoder_top\address_decoder_top_traffic_controller_ch_4_5 --family="Stratix 10" --part=1SG165HU2F50E2VG
Info: Finished: IP-XACT
