
module intel_std_18_1_dummy (
	clk_clk,
	reset_reset_n,
	in_address,
	in_waitrequest,
	in_burstcount,
	in_byteenable,
	in_read,
	in_readdata,
	in_readdatavalid,
	in_write,
	in_writedata,
	slave0_address,
	slave0_write,
	slave0_read,
	slave0_readdata,
	slave0_writedata,
	slave0_begintransfer,
	slave0_beginbursttransfer,
	slave0_burstcount,
	slave0_byteenable,
	slave0_readdatavalid,
	slave0_waitrequest,
	slave1_address,
	slave1_write,
	slave1_read,
	slave1_readdata,
	slave1_writedata,
	slave1_begintransfer,
	slave1_beginbursttransfer,
	slave1_burstcount,
	slave1_byteenable,
	slave1_readdatavalid,
	slave1_waitrequest);	

	input		clk_clk;
	input		reset_reset_n;
	input	[31:0]	in_address;
	output		in_waitrequest;
	input	[3:0]	in_burstcount;
	input	[3:0]	in_byteenable;
	input		in_read;
	output	[31:0]	in_readdata;
	output		in_readdatavalid;
	input		in_write;
	input	[31:0]	in_writedata;
	output	[15:0]	slave0_address;
	output		slave0_write;
	output		slave0_read;
	input	[31:0]	slave0_readdata;
	output	[31:0]	slave0_writedata;
	output		slave0_begintransfer;
	output		slave0_beginbursttransfer;
	output	[3:0]	slave0_burstcount;
	output	[3:0]	slave0_byteenable;
	input		slave0_readdatavalid;
	input		slave0_waitrequest;
	output	[15:0]	slave1_address;
	output		slave1_write;
	output		slave1_read;
	input	[31:0]	slave1_readdata;
	output	[31:0]	slave1_writedata;
	output		slave1_begintransfer;
	output		slave1_beginbursttransfer;
	output	[3:0]	slave1_burstcount;
	output	[3:0]	slave1_byteenable;
	input		slave1_readdatavalid;
	input		slave1_waitrequest;
endmodule
