// address_decoder_top_altera_mm_interconnect_191_fv6bu5i.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 19.4 64

`timescale 1 ps / 1 ps
module address_decoder_top_altera_mm_interconnect_191_fv6bu5i (
		input  wire [16:0] mm_clock_crossing_bridge_m0_address,                                //                             mm_clock_crossing_bridge_m0.address
		output wire        mm_clock_crossing_bridge_m0_waitrequest,                            //                                                        .waitrequest
		input  wire [0:0]  mm_clock_crossing_bridge_m0_burstcount,                             //                                                        .burstcount
		input  wire [3:0]  mm_clock_crossing_bridge_m0_byteenable,                             //                                                        .byteenable
		input  wire        mm_clock_crossing_bridge_m0_read,                                   //                                                        .read
		output wire [31:0] mm_clock_crossing_bridge_m0_readdata,                               //                                                        .readdata
		output wire        mm_clock_crossing_bridge_m0_readdatavalid,                          //                                                        .readdatavalid
		input  wire        mm_clock_crossing_bridge_m0_write,                                  //                                                        .write
		input  wire [31:0] mm_clock_crossing_bridge_m0_writedata,                              //                                                        .writedata
		input  wire        mm_clock_crossing_bridge_m0_debugaccess,                            //                                                        .debugaccess
		output wire [13:0] traffic_controller_ch_0_1_avalon_universal_slave_0_address,         //      traffic_controller_ch_0_1_avalon_universal_slave_0.address
		output wire        traffic_controller_ch_0_1_avalon_universal_slave_0_write,           //                                                        .write
		output wire        traffic_controller_ch_0_1_avalon_universal_slave_0_read,            //                                                        .read
		input  wire [31:0] traffic_controller_ch_0_1_avalon_universal_slave_0_readdata,        //                                                        .readdata
		output wire [31:0] traffic_controller_ch_0_1_avalon_universal_slave_0_writedata,       //                                                        .writedata
		output wire [2:0]  traffic_controller_ch_0_1_avalon_universal_slave_0_burstcount,      //                                                        .burstcount
		output wire [3:0]  traffic_controller_ch_0_1_avalon_universal_slave_0_byteenable,      //                                                        .byteenable
		input  wire        traffic_controller_ch_0_1_avalon_universal_slave_0_readdatavalid,   //                                                        .readdatavalid
		input  wire        traffic_controller_ch_0_1_avalon_universal_slave_0_waitrequest,     //                                                        .waitrequest
		output wire        traffic_controller_ch_0_1_avalon_universal_slave_0_lock,            //                                                        .lock
		output wire        traffic_controller_ch_0_1_avalon_universal_slave_0_debugaccess,     //                                                        .debugaccess
		output wire [13:0] traffic_controller_ch_2_3_avalon_universal_slave_0_address,         //      traffic_controller_ch_2_3_avalon_universal_slave_0.address
		output wire        traffic_controller_ch_2_3_avalon_universal_slave_0_write,           //                                                        .write
		output wire        traffic_controller_ch_2_3_avalon_universal_slave_0_read,            //                                                        .read
		input  wire [31:0] traffic_controller_ch_2_3_avalon_universal_slave_0_readdata,        //                                                        .readdata
		output wire [31:0] traffic_controller_ch_2_3_avalon_universal_slave_0_writedata,       //                                                        .writedata
		output wire [2:0]  traffic_controller_ch_2_3_avalon_universal_slave_0_burstcount,      //                                                        .burstcount
		output wire [3:0]  traffic_controller_ch_2_3_avalon_universal_slave_0_byteenable,      //                                                        .byteenable
		input  wire        traffic_controller_ch_2_3_avalon_universal_slave_0_readdatavalid,   //                                                        .readdatavalid
		input  wire        traffic_controller_ch_2_3_avalon_universal_slave_0_waitrequest,     //                                                        .waitrequest
		output wire        traffic_controller_ch_2_3_avalon_universal_slave_0_lock,            //                                                        .lock
		output wire        traffic_controller_ch_2_3_avalon_universal_slave_0_debugaccess,     //                                                        .debugaccess
		output wire [13:0] traffic_controller_ch_4_5_avalon_universal_slave_0_address,         //      traffic_controller_ch_4_5_avalon_universal_slave_0.address
		output wire        traffic_controller_ch_4_5_avalon_universal_slave_0_write,           //                                                        .write
		output wire        traffic_controller_ch_4_5_avalon_universal_slave_0_read,            //                                                        .read
		input  wire [31:0] traffic_controller_ch_4_5_avalon_universal_slave_0_readdata,        //                                                        .readdata
		output wire [31:0] traffic_controller_ch_4_5_avalon_universal_slave_0_writedata,       //                                                        .writedata
		output wire [2:0]  traffic_controller_ch_4_5_avalon_universal_slave_0_burstcount,      //                                                        .burstcount
		output wire [3:0]  traffic_controller_ch_4_5_avalon_universal_slave_0_byteenable,      //                                                        .byteenable
		input  wire        traffic_controller_ch_4_5_avalon_universal_slave_0_readdatavalid,   //                                                        .readdatavalid
		input  wire        traffic_controller_ch_4_5_avalon_universal_slave_0_waitrequest,     //                                                        .waitrequest
		output wire        traffic_controller_ch_4_5_avalon_universal_slave_0_lock,            //                                                        .lock
		output wire        traffic_controller_ch_4_5_avalon_universal_slave_0_debugaccess,     //                                                        .debugaccess
		output wire [13:0] traffic_controller_ch_6_7_avalon_universal_slave_0_address,         //      traffic_controller_ch_6_7_avalon_universal_slave_0.address
		output wire        traffic_controller_ch_6_7_avalon_universal_slave_0_write,           //                                                        .write
		output wire        traffic_controller_ch_6_7_avalon_universal_slave_0_read,            //                                                        .read
		input  wire [31:0] traffic_controller_ch_6_7_avalon_universal_slave_0_readdata,        //                                                        .readdata
		output wire [31:0] traffic_controller_ch_6_7_avalon_universal_slave_0_writedata,       //                                                        .writedata
		output wire [2:0]  traffic_controller_ch_6_7_avalon_universal_slave_0_burstcount,      //                                                        .burstcount
		output wire [3:0]  traffic_controller_ch_6_7_avalon_universal_slave_0_byteenable,      //                                                        .byteenable
		input  wire        traffic_controller_ch_6_7_avalon_universal_slave_0_readdatavalid,   //                                                        .readdatavalid
		input  wire        traffic_controller_ch_6_7_avalon_universal_slave_0_waitrequest,     //                                                        .waitrequest
		output wire        traffic_controller_ch_6_7_avalon_universal_slave_0_lock,            //                                                        .lock
		output wire        traffic_controller_ch_6_7_avalon_universal_slave_0_debugaccess,     //                                                        .debugaccess
		output wire [13:0] traffic_controller_ch_8_9_avalon_universal_slave_0_address,         //      traffic_controller_ch_8_9_avalon_universal_slave_0.address
		output wire        traffic_controller_ch_8_9_avalon_universal_slave_0_write,           //                                                        .write
		output wire        traffic_controller_ch_8_9_avalon_universal_slave_0_read,            //                                                        .read
		input  wire [31:0] traffic_controller_ch_8_9_avalon_universal_slave_0_readdata,        //                                                        .readdata
		output wire [31:0] traffic_controller_ch_8_9_avalon_universal_slave_0_writedata,       //                                                        .writedata
		output wire [2:0]  traffic_controller_ch_8_9_avalon_universal_slave_0_burstcount,      //                                                        .burstcount
		output wire [3:0]  traffic_controller_ch_8_9_avalon_universal_slave_0_byteenable,      //                                                        .byteenable
		input  wire        traffic_controller_ch_8_9_avalon_universal_slave_0_readdatavalid,   //                                                        .readdatavalid
		input  wire        traffic_controller_ch_8_9_avalon_universal_slave_0_waitrequest,     //                                                        .waitrequest
		output wire        traffic_controller_ch_8_9_avalon_universal_slave_0_lock,            //                                                        .lock
		output wire        traffic_controller_ch_8_9_avalon_universal_slave_0_debugaccess,     //                                                        .debugaccess
		output wire [13:0] traffic_controller_ch_10_11_avalon_universal_slave_0_address,       //    traffic_controller_ch_10_11_avalon_universal_slave_0.address
		output wire        traffic_controller_ch_10_11_avalon_universal_slave_0_write,         //                                                        .write
		output wire        traffic_controller_ch_10_11_avalon_universal_slave_0_read,          //                                                        .read
		input  wire [31:0] traffic_controller_ch_10_11_avalon_universal_slave_0_readdata,      //                                                        .readdata
		output wire [31:0] traffic_controller_ch_10_11_avalon_universal_slave_0_writedata,     //                                                        .writedata
		output wire [2:0]  traffic_controller_ch_10_11_avalon_universal_slave_0_burstcount,    //                                                        .burstcount
		output wire [3:0]  traffic_controller_ch_10_11_avalon_universal_slave_0_byteenable,    //                                                        .byteenable
		input  wire        traffic_controller_ch_10_11_avalon_universal_slave_0_readdatavalid, //                                                        .readdatavalid
		input  wire        traffic_controller_ch_10_11_avalon_universal_slave_0_waitrequest,   //                                                        .waitrequest
		output wire        traffic_controller_ch_10_11_avalon_universal_slave_0_lock,          //                                                        .lock
		output wire        traffic_controller_ch_10_11_avalon_universal_slave_0_debugaccess,   //                                                        .debugaccess
		input  wire        mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset,      // mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset.reset
		input  wire        mac_clk_clk_clk                                                     //                                             mac_clk_clk.clk
	);

	wire          mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_waitrequest;          // mm_clock_crossing_bridge_m0_agent:av_waitrequest -> mm_clock_crossing_bridge_m0_translator:uav_waitrequest
	wire   [31:0] mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_readdata;             // mm_clock_crossing_bridge_m0_agent:av_readdata -> mm_clock_crossing_bridge_m0_translator:uav_readdata
	wire          mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_debugaccess;          // mm_clock_crossing_bridge_m0_translator:uav_debugaccess -> mm_clock_crossing_bridge_m0_agent:av_debugaccess
	wire   [16:0] mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_address;              // mm_clock_crossing_bridge_m0_translator:uav_address -> mm_clock_crossing_bridge_m0_agent:av_address
	wire          mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_read;                 // mm_clock_crossing_bridge_m0_translator:uav_read -> mm_clock_crossing_bridge_m0_agent:av_read
	wire    [3:0] mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_byteenable;           // mm_clock_crossing_bridge_m0_translator:uav_byteenable -> mm_clock_crossing_bridge_m0_agent:av_byteenable
	wire          mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_readdatavalid;        // mm_clock_crossing_bridge_m0_agent:av_readdatavalid -> mm_clock_crossing_bridge_m0_translator:uav_readdatavalid
	wire          mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_lock;                 // mm_clock_crossing_bridge_m0_translator:uav_lock -> mm_clock_crossing_bridge_m0_agent:av_lock
	wire          mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_write;                // mm_clock_crossing_bridge_m0_translator:uav_write -> mm_clock_crossing_bridge_m0_agent:av_write
	wire   [31:0] mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_writedata;            // mm_clock_crossing_bridge_m0_translator:uav_writedata -> mm_clock_crossing_bridge_m0_agent:av_writedata
	wire    [2:0] mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_burstcount;           // mm_clock_crossing_bridge_m0_translator:uav_burstcount -> mm_clock_crossing_bridge_m0_agent:av_burstcount
	wire   [31:0] traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_readdata;                  // traffic_controller_ch_0_1_avalon_universal_slave_0_translator:uav_readdata -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:m0_readdata
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_waitrequest;               // traffic_controller_ch_0_1_avalon_universal_slave_0_translator:uav_waitrequest -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:m0_waitrequest
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_debugaccess;               // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:m0_debugaccess -> traffic_controller_ch_0_1_avalon_universal_slave_0_translator:uav_debugaccess
	wire   [16:0] traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_address;                   // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:m0_address -> traffic_controller_ch_0_1_avalon_universal_slave_0_translator:uav_address
	wire    [3:0] traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_byteenable;                // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:m0_byteenable -> traffic_controller_ch_0_1_avalon_universal_slave_0_translator:uav_byteenable
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_read;                      // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:m0_read -> traffic_controller_ch_0_1_avalon_universal_slave_0_translator:uav_read
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_readdatavalid;             // traffic_controller_ch_0_1_avalon_universal_slave_0_translator:uav_readdatavalid -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_lock;                      // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:m0_lock -> traffic_controller_ch_0_1_avalon_universal_slave_0_translator:uav_lock
	wire   [31:0] traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_writedata;                 // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:m0_writedata -> traffic_controller_ch_0_1_avalon_universal_slave_0_translator:uav_writedata
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_write;                     // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:m0_write -> traffic_controller_ch_0_1_avalon_universal_slave_0_translator:uav_write
	wire    [2:0] traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_burstcount;                // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:m0_burstcount -> traffic_controller_ch_0_1_avalon_universal_slave_0_translator:uav_burstcount
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_valid;              // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rf_source_valid -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire  [100:0] traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_data;               // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rf_source_data -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_ready;              // traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rf_source_ready
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_startofpacket;      // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rf_source_startofpacket -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_endofpacket;        // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rf_source_endofpacket -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_valid;           // traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rf_sink_valid
	wire  [100:0] traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_data;            // traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo:out_data -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rf_sink_data
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_ready;           // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rf_sink_ready -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;   // traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;     // traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rdata_fifo_src_valid;         // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rdata_fifo_src_data;          // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rdata_fifo_src_data -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rdata_fifo_src_ready;         // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          cmd_mux_src_valid;                                                                     // cmd_mux:src_valid -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:cp_valid
	wire   [99:0] cmd_mux_src_data;                                                                      // cmd_mux:src_data -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:cp_data
	wire          cmd_mux_src_ready;                                                                     // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:cp_ready -> cmd_mux:src_ready
	wire    [5:0] cmd_mux_src_channel;                                                                   // cmd_mux:src_channel -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_mux_src_startofpacket;                                                             // cmd_mux:src_startofpacket -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:cp_startofpacket
	wire          cmd_mux_src_endofpacket;                                                               // cmd_mux:src_endofpacket -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:cp_endofpacket
	wire   [31:0] traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_readdata;                  // traffic_controller_ch_2_3_avalon_universal_slave_0_translator:uav_readdata -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:m0_readdata
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_waitrequest;               // traffic_controller_ch_2_3_avalon_universal_slave_0_translator:uav_waitrequest -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:m0_waitrequest
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_debugaccess;               // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:m0_debugaccess -> traffic_controller_ch_2_3_avalon_universal_slave_0_translator:uav_debugaccess
	wire   [16:0] traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_address;                   // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:m0_address -> traffic_controller_ch_2_3_avalon_universal_slave_0_translator:uav_address
	wire    [3:0] traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_byteenable;                // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:m0_byteenable -> traffic_controller_ch_2_3_avalon_universal_slave_0_translator:uav_byteenable
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_read;                      // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:m0_read -> traffic_controller_ch_2_3_avalon_universal_slave_0_translator:uav_read
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_readdatavalid;             // traffic_controller_ch_2_3_avalon_universal_slave_0_translator:uav_readdatavalid -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_lock;                      // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:m0_lock -> traffic_controller_ch_2_3_avalon_universal_slave_0_translator:uav_lock
	wire   [31:0] traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_writedata;                 // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:m0_writedata -> traffic_controller_ch_2_3_avalon_universal_slave_0_translator:uav_writedata
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_write;                     // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:m0_write -> traffic_controller_ch_2_3_avalon_universal_slave_0_translator:uav_write
	wire    [2:0] traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_burstcount;                // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:m0_burstcount -> traffic_controller_ch_2_3_avalon_universal_slave_0_translator:uav_burstcount
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_valid;              // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rf_source_valid -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire  [100:0] traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_data;               // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rf_source_data -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_ready;              // traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rf_source_ready
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_startofpacket;      // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rf_source_startofpacket -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_endofpacket;        // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rf_source_endofpacket -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_valid;           // traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rf_sink_valid
	wire  [100:0] traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_data;            // traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo:out_data -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rf_sink_data
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_ready;           // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rf_sink_ready -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;   // traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;     // traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rdata_fifo_src_valid;         // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rdata_fifo_src_data;          // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rdata_fifo_src_data -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rdata_fifo_src_ready;         // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          cmd_mux_001_src_valid;                                                                 // cmd_mux_001:src_valid -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:cp_valid
	wire   [99:0] cmd_mux_001_src_data;                                                                  // cmd_mux_001:src_data -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:cp_data
	wire          cmd_mux_001_src_ready;                                                                 // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_001:src_ready
	wire    [5:0] cmd_mux_001_src_channel;                                                               // cmd_mux_001:src_channel -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_mux_001_src_startofpacket;                                                         // cmd_mux_001:src_startofpacket -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:cp_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                                           // cmd_mux_001:src_endofpacket -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:cp_endofpacket
	wire   [31:0] traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_readdata;                  // traffic_controller_ch_4_5_avalon_universal_slave_0_translator:uav_readdata -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:m0_readdata
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_waitrequest;               // traffic_controller_ch_4_5_avalon_universal_slave_0_translator:uav_waitrequest -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:m0_waitrequest
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_debugaccess;               // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:m0_debugaccess -> traffic_controller_ch_4_5_avalon_universal_slave_0_translator:uav_debugaccess
	wire   [16:0] traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_address;                   // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:m0_address -> traffic_controller_ch_4_5_avalon_universal_slave_0_translator:uav_address
	wire    [3:0] traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_byteenable;                // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:m0_byteenable -> traffic_controller_ch_4_5_avalon_universal_slave_0_translator:uav_byteenable
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_read;                      // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:m0_read -> traffic_controller_ch_4_5_avalon_universal_slave_0_translator:uav_read
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_readdatavalid;             // traffic_controller_ch_4_5_avalon_universal_slave_0_translator:uav_readdatavalid -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_lock;                      // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:m0_lock -> traffic_controller_ch_4_5_avalon_universal_slave_0_translator:uav_lock
	wire   [31:0] traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_writedata;                 // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:m0_writedata -> traffic_controller_ch_4_5_avalon_universal_slave_0_translator:uav_writedata
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_write;                     // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:m0_write -> traffic_controller_ch_4_5_avalon_universal_slave_0_translator:uav_write
	wire    [2:0] traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_burstcount;                // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:m0_burstcount -> traffic_controller_ch_4_5_avalon_universal_slave_0_translator:uav_burstcount
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_valid;              // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rf_source_valid -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire  [100:0] traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_data;               // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rf_source_data -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_ready;              // traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rf_source_ready
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_startofpacket;      // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rf_source_startofpacket -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_endofpacket;        // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rf_source_endofpacket -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_valid;           // traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rf_sink_valid
	wire  [100:0] traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_data;            // traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo:out_data -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rf_sink_data
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_ready;           // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rf_sink_ready -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;   // traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;     // traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rdata_fifo_src_valid;         // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rdata_fifo_src_data;          // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rdata_fifo_src_data -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rdata_fifo_src_ready;         // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          cmd_mux_002_src_valid;                                                                 // cmd_mux_002:src_valid -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:cp_valid
	wire   [99:0] cmd_mux_002_src_data;                                                                  // cmd_mux_002:src_data -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:cp_data
	wire          cmd_mux_002_src_ready;                                                                 // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_002:src_ready
	wire    [5:0] cmd_mux_002_src_channel;                                                               // cmd_mux_002:src_channel -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_mux_002_src_startofpacket;                                                         // cmd_mux_002:src_startofpacket -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:cp_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                                           // cmd_mux_002:src_endofpacket -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:cp_endofpacket
	wire   [31:0] traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_readdata;                  // traffic_controller_ch_6_7_avalon_universal_slave_0_translator:uav_readdata -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:m0_readdata
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_waitrequest;               // traffic_controller_ch_6_7_avalon_universal_slave_0_translator:uav_waitrequest -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:m0_waitrequest
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_debugaccess;               // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:m0_debugaccess -> traffic_controller_ch_6_7_avalon_universal_slave_0_translator:uav_debugaccess
	wire   [16:0] traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_address;                   // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:m0_address -> traffic_controller_ch_6_7_avalon_universal_slave_0_translator:uav_address
	wire    [3:0] traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_byteenable;                // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:m0_byteenable -> traffic_controller_ch_6_7_avalon_universal_slave_0_translator:uav_byteenable
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_read;                      // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:m0_read -> traffic_controller_ch_6_7_avalon_universal_slave_0_translator:uav_read
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_readdatavalid;             // traffic_controller_ch_6_7_avalon_universal_slave_0_translator:uav_readdatavalid -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_lock;                      // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:m0_lock -> traffic_controller_ch_6_7_avalon_universal_slave_0_translator:uav_lock
	wire   [31:0] traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_writedata;                 // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:m0_writedata -> traffic_controller_ch_6_7_avalon_universal_slave_0_translator:uav_writedata
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_write;                     // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:m0_write -> traffic_controller_ch_6_7_avalon_universal_slave_0_translator:uav_write
	wire    [2:0] traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_burstcount;                // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:m0_burstcount -> traffic_controller_ch_6_7_avalon_universal_slave_0_translator:uav_burstcount
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_valid;              // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rf_source_valid -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire  [100:0] traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_data;               // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rf_source_data -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_ready;              // traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rf_source_ready
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_startofpacket;      // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rf_source_startofpacket -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_endofpacket;        // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rf_source_endofpacket -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_valid;           // traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rf_sink_valid
	wire  [100:0] traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_data;            // traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo:out_data -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rf_sink_data
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_ready;           // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rf_sink_ready -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;   // traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;     // traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rdata_fifo_src_valid;         // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rdata_fifo_src_data;          // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rdata_fifo_src_data -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rdata_fifo_src_ready;         // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          cmd_mux_003_src_valid;                                                                 // cmd_mux_003:src_valid -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:cp_valid
	wire   [99:0] cmd_mux_003_src_data;                                                                  // cmd_mux_003:src_data -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:cp_data
	wire          cmd_mux_003_src_ready;                                                                 // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_003:src_ready
	wire    [5:0] cmd_mux_003_src_channel;                                                               // cmd_mux_003:src_channel -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_mux_003_src_startofpacket;                                                         // cmd_mux_003:src_startofpacket -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:cp_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                                           // cmd_mux_003:src_endofpacket -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:cp_endofpacket
	wire   [31:0] traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_readdata;                  // traffic_controller_ch_8_9_avalon_universal_slave_0_translator:uav_readdata -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:m0_readdata
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_waitrequest;               // traffic_controller_ch_8_9_avalon_universal_slave_0_translator:uav_waitrequest -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:m0_waitrequest
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_debugaccess;               // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:m0_debugaccess -> traffic_controller_ch_8_9_avalon_universal_slave_0_translator:uav_debugaccess
	wire   [16:0] traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_address;                   // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:m0_address -> traffic_controller_ch_8_9_avalon_universal_slave_0_translator:uav_address
	wire    [3:0] traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_byteenable;                // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:m0_byteenable -> traffic_controller_ch_8_9_avalon_universal_slave_0_translator:uav_byteenable
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_read;                      // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:m0_read -> traffic_controller_ch_8_9_avalon_universal_slave_0_translator:uav_read
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_readdatavalid;             // traffic_controller_ch_8_9_avalon_universal_slave_0_translator:uav_readdatavalid -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_lock;                      // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:m0_lock -> traffic_controller_ch_8_9_avalon_universal_slave_0_translator:uav_lock
	wire   [31:0] traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_writedata;                 // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:m0_writedata -> traffic_controller_ch_8_9_avalon_universal_slave_0_translator:uav_writedata
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_write;                     // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:m0_write -> traffic_controller_ch_8_9_avalon_universal_slave_0_translator:uav_write
	wire    [2:0] traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_burstcount;                // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:m0_burstcount -> traffic_controller_ch_8_9_avalon_universal_slave_0_translator:uav_burstcount
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_valid;              // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rf_source_valid -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire  [100:0] traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_data;               // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rf_source_data -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_ready;              // traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rf_source_ready
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_startofpacket;      // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rf_source_startofpacket -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_endofpacket;        // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rf_source_endofpacket -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_valid;           // traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rf_sink_valid
	wire  [100:0] traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_data;            // traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo:out_data -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rf_sink_data
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_ready;           // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rf_sink_ready -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;   // traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;     // traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rdata_fifo_src_valid;         // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rdata_fifo_src_data;          // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rdata_fifo_src_data -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rdata_fifo_src_ready;         // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          cmd_mux_004_src_valid;                                                                 // cmd_mux_004:src_valid -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:cp_valid
	wire   [99:0] cmd_mux_004_src_data;                                                                  // cmd_mux_004:src_data -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:cp_data
	wire          cmd_mux_004_src_ready;                                                                 // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_004:src_ready
	wire    [5:0] cmd_mux_004_src_channel;                                                               // cmd_mux_004:src_channel -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_mux_004_src_startofpacket;                                                         // cmd_mux_004:src_startofpacket -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:cp_startofpacket
	wire          cmd_mux_004_src_endofpacket;                                                           // cmd_mux_004:src_endofpacket -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:cp_endofpacket
	wire   [31:0] traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_readdata;                // traffic_controller_ch_10_11_avalon_universal_slave_0_translator:uav_readdata -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:m0_readdata
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_waitrequest;             // traffic_controller_ch_10_11_avalon_universal_slave_0_translator:uav_waitrequest -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:m0_waitrequest
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_debugaccess;             // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:m0_debugaccess -> traffic_controller_ch_10_11_avalon_universal_slave_0_translator:uav_debugaccess
	wire   [16:0] traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_address;                 // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:m0_address -> traffic_controller_ch_10_11_avalon_universal_slave_0_translator:uav_address
	wire    [3:0] traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_byteenable;              // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:m0_byteenable -> traffic_controller_ch_10_11_avalon_universal_slave_0_translator:uav_byteenable
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_read;                    // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:m0_read -> traffic_controller_ch_10_11_avalon_universal_slave_0_translator:uav_read
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_readdatavalid;           // traffic_controller_ch_10_11_avalon_universal_slave_0_translator:uav_readdatavalid -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_lock;                    // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:m0_lock -> traffic_controller_ch_10_11_avalon_universal_slave_0_translator:uav_lock
	wire   [31:0] traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_writedata;               // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:m0_writedata -> traffic_controller_ch_10_11_avalon_universal_slave_0_translator:uav_writedata
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_write;                   // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:m0_write -> traffic_controller_ch_10_11_avalon_universal_slave_0_translator:uav_write
	wire    [2:0] traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_burstcount;              // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:m0_burstcount -> traffic_controller_ch_10_11_avalon_universal_slave_0_translator:uav_burstcount
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_valid;            // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rf_source_valid -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire  [100:0] traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_data;             // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rf_source_data -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_ready;            // traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rf_source_ready
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_startofpacket;    // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rf_source_startofpacket -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_endofpacket;      // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rf_source_endofpacket -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_valid;         // traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rf_sink_valid
	wire  [100:0] traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_data;          // traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo:out_data -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rf_sink_data
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_ready;         // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rf_sink_ready -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;   // traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rdata_fifo_src_valid;       // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rdata_fifo_src_data;        // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rdata_fifo_src_data -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rdata_fifo_src_ready;       // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          cmd_mux_005_src_valid;                                                                 // cmd_mux_005:src_valid -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:cp_valid
	wire   [99:0] cmd_mux_005_src_data;                                                                  // cmd_mux_005:src_data -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:cp_data
	wire          cmd_mux_005_src_ready;                                                                 // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:cp_ready -> cmd_mux_005:src_ready
	wire    [5:0] cmd_mux_005_src_channel;                                                               // cmd_mux_005:src_channel -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_mux_005_src_startofpacket;                                                         // cmd_mux_005:src_startofpacket -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:cp_startofpacket
	wire          cmd_mux_005_src_endofpacket;                                                           // cmd_mux_005:src_endofpacket -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:cp_endofpacket
	wire          mm_clock_crossing_bridge_m0_agent_cp_valid;                                            // mm_clock_crossing_bridge_m0_agent:cp_valid -> router:sink_valid
	wire   [99:0] mm_clock_crossing_bridge_m0_agent_cp_data;                                             // mm_clock_crossing_bridge_m0_agent:cp_data -> router:sink_data
	wire          mm_clock_crossing_bridge_m0_agent_cp_ready;                                            // router:sink_ready -> mm_clock_crossing_bridge_m0_agent:cp_ready
	wire          mm_clock_crossing_bridge_m0_agent_cp_startofpacket;                                    // mm_clock_crossing_bridge_m0_agent:cp_startofpacket -> router:sink_startofpacket
	wire          mm_clock_crossing_bridge_m0_agent_cp_endofpacket;                                      // mm_clock_crossing_bridge_m0_agent:cp_endofpacket -> router:sink_endofpacket
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_valid;                     // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rp_valid -> router_001:sink_valid
	wire   [99:0] traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_data;                      // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rp_data -> router_001:sink_data
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_ready;                     // router_001:sink_ready -> traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rp_ready
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_startofpacket;             // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rp_startofpacket -> router_001:sink_startofpacket
	wire          traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_endofpacket;               // traffic_controller_ch_0_1_avalon_universal_slave_0_agent:rp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                                  // router_001:src_valid -> rsp_demux:sink_valid
	wire   [99:0] router_001_src_data;                                                                   // router_001:src_data -> rsp_demux:sink_data
	wire          router_001_src_ready;                                                                  // rsp_demux:sink_ready -> router_001:src_ready
	wire    [5:0] router_001_src_channel;                                                                // router_001:src_channel -> rsp_demux:sink_channel
	wire          router_001_src_startofpacket;                                                          // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_001_src_endofpacket;                                                            // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_valid;                     // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rp_valid -> router_002:sink_valid
	wire   [99:0] traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_data;                      // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rp_data -> router_002:sink_data
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_ready;                     // router_002:sink_ready -> traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rp_ready
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_startofpacket;             // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire          traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_endofpacket;               // traffic_controller_ch_2_3_avalon_universal_slave_0_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire          router_002_src_valid;                                                                  // router_002:src_valid -> rsp_demux_001:sink_valid
	wire   [99:0] router_002_src_data;                                                                   // router_002:src_data -> rsp_demux_001:sink_data
	wire          router_002_src_ready;                                                                  // rsp_demux_001:sink_ready -> router_002:src_ready
	wire    [5:0] router_002_src_channel;                                                                // router_002:src_channel -> rsp_demux_001:sink_channel
	wire          router_002_src_startofpacket;                                                          // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_002_src_endofpacket;                                                            // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_valid;                     // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rp_valid -> router_003:sink_valid
	wire   [99:0] traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_data;                      // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rp_data -> router_003:sink_data
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_ready;                     // router_003:sink_ready -> traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rp_ready
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_startofpacket;             // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rp_startofpacket -> router_003:sink_startofpacket
	wire          traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_endofpacket;               // traffic_controller_ch_4_5_avalon_universal_slave_0_agent:rp_endofpacket -> router_003:sink_endofpacket
	wire          router_003_src_valid;                                                                  // router_003:src_valid -> rsp_demux_002:sink_valid
	wire   [99:0] router_003_src_data;                                                                   // router_003:src_data -> rsp_demux_002:sink_data
	wire          router_003_src_ready;                                                                  // rsp_demux_002:sink_ready -> router_003:src_ready
	wire    [5:0] router_003_src_channel;                                                                // router_003:src_channel -> rsp_demux_002:sink_channel
	wire          router_003_src_startofpacket;                                                          // router_003:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_003_src_endofpacket;                                                            // router_003:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_valid;                     // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rp_valid -> router_004:sink_valid
	wire   [99:0] traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_data;                      // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rp_data -> router_004:sink_data
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_ready;                     // router_004:sink_ready -> traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rp_ready
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_startofpacket;             // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rp_startofpacket -> router_004:sink_startofpacket
	wire          traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_endofpacket;               // traffic_controller_ch_6_7_avalon_universal_slave_0_agent:rp_endofpacket -> router_004:sink_endofpacket
	wire          router_004_src_valid;                                                                  // router_004:src_valid -> rsp_demux_003:sink_valid
	wire   [99:0] router_004_src_data;                                                                   // router_004:src_data -> rsp_demux_003:sink_data
	wire          router_004_src_ready;                                                                  // rsp_demux_003:sink_ready -> router_004:src_ready
	wire    [5:0] router_004_src_channel;                                                                // router_004:src_channel -> rsp_demux_003:sink_channel
	wire          router_004_src_startofpacket;                                                          // router_004:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_004_src_endofpacket;                                                            // router_004:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_valid;                     // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rp_valid -> router_005:sink_valid
	wire   [99:0] traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_data;                      // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rp_data -> router_005:sink_data
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_ready;                     // router_005:sink_ready -> traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rp_ready
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_startofpacket;             // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rp_startofpacket -> router_005:sink_startofpacket
	wire          traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_endofpacket;               // traffic_controller_ch_8_9_avalon_universal_slave_0_agent:rp_endofpacket -> router_005:sink_endofpacket
	wire          router_005_src_valid;                                                                  // router_005:src_valid -> rsp_demux_004:sink_valid
	wire   [99:0] router_005_src_data;                                                                   // router_005:src_data -> rsp_demux_004:sink_data
	wire          router_005_src_ready;                                                                  // rsp_demux_004:sink_ready -> router_005:src_ready
	wire    [5:0] router_005_src_channel;                                                                // router_005:src_channel -> rsp_demux_004:sink_channel
	wire          router_005_src_startofpacket;                                                          // router_005:src_startofpacket -> rsp_demux_004:sink_startofpacket
	wire          router_005_src_endofpacket;                                                            // router_005:src_endofpacket -> rsp_demux_004:sink_endofpacket
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_valid;                   // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rp_valid -> router_006:sink_valid
	wire   [99:0] traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_data;                    // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rp_data -> router_006:sink_data
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_ready;                   // router_006:sink_ready -> traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rp_ready
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_startofpacket;           // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rp_startofpacket -> router_006:sink_startofpacket
	wire          traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_endofpacket;             // traffic_controller_ch_10_11_avalon_universal_slave_0_agent:rp_endofpacket -> router_006:sink_endofpacket
	wire          router_006_src_valid;                                                                  // router_006:src_valid -> rsp_demux_005:sink_valid
	wire   [99:0] router_006_src_data;                                                                   // router_006:src_data -> rsp_demux_005:sink_data
	wire          router_006_src_ready;                                                                  // rsp_demux_005:sink_ready -> router_006:src_ready
	wire    [5:0] router_006_src_channel;                                                                // router_006:src_channel -> rsp_demux_005:sink_channel
	wire          router_006_src_startofpacket;                                                          // router_006:src_startofpacket -> rsp_demux_005:sink_startofpacket
	wire          router_006_src_endofpacket;                                                            // router_006:src_endofpacket -> rsp_demux_005:sink_endofpacket
	wire          router_src_valid;                                                                      // router:src_valid -> mm_clock_crossing_bridge_m0_limiter:cmd_sink_valid
	wire   [99:0] router_src_data;                                                                       // router:src_data -> mm_clock_crossing_bridge_m0_limiter:cmd_sink_data
	wire          router_src_ready;                                                                      // mm_clock_crossing_bridge_m0_limiter:cmd_sink_ready -> router:src_ready
	wire    [5:0] router_src_channel;                                                                    // router:src_channel -> mm_clock_crossing_bridge_m0_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                                              // router:src_startofpacket -> mm_clock_crossing_bridge_m0_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                                                // router:src_endofpacket -> mm_clock_crossing_bridge_m0_limiter:cmd_sink_endofpacket
	wire   [99:0] mm_clock_crossing_bridge_m0_limiter_cmd_src_data;                                      // mm_clock_crossing_bridge_m0_limiter:cmd_src_data -> cmd_demux:sink_data
	wire          mm_clock_crossing_bridge_m0_limiter_cmd_src_ready;                                     // cmd_demux:sink_ready -> mm_clock_crossing_bridge_m0_limiter:cmd_src_ready
	wire    [5:0] mm_clock_crossing_bridge_m0_limiter_cmd_src_channel;                                   // mm_clock_crossing_bridge_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
	wire          mm_clock_crossing_bridge_m0_limiter_cmd_src_startofpacket;                             // mm_clock_crossing_bridge_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
	wire          mm_clock_crossing_bridge_m0_limiter_cmd_src_endofpacket;                               // mm_clock_crossing_bridge_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                                                     // rsp_mux:src_valid -> mm_clock_crossing_bridge_m0_limiter:rsp_sink_valid
	wire   [99:0] rsp_mux_src_data;                                                                      // rsp_mux:src_data -> mm_clock_crossing_bridge_m0_limiter:rsp_sink_data
	wire          rsp_mux_src_ready;                                                                     // mm_clock_crossing_bridge_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
	wire    [5:0] rsp_mux_src_channel;                                                                   // rsp_mux:src_channel -> mm_clock_crossing_bridge_m0_limiter:rsp_sink_channel
	wire          rsp_mux_src_startofpacket;                                                             // rsp_mux:src_startofpacket -> mm_clock_crossing_bridge_m0_limiter:rsp_sink_startofpacket
	wire          rsp_mux_src_endofpacket;                                                               // rsp_mux:src_endofpacket -> mm_clock_crossing_bridge_m0_limiter:rsp_sink_endofpacket
	wire          mm_clock_crossing_bridge_m0_limiter_rsp_src_valid;                                     // mm_clock_crossing_bridge_m0_limiter:rsp_src_valid -> mm_clock_crossing_bridge_m0_agent:rp_valid
	wire   [99:0] mm_clock_crossing_bridge_m0_limiter_rsp_src_data;                                      // mm_clock_crossing_bridge_m0_limiter:rsp_src_data -> mm_clock_crossing_bridge_m0_agent:rp_data
	wire          mm_clock_crossing_bridge_m0_limiter_rsp_src_ready;                                     // mm_clock_crossing_bridge_m0_agent:rp_ready -> mm_clock_crossing_bridge_m0_limiter:rsp_src_ready
	wire    [5:0] mm_clock_crossing_bridge_m0_limiter_rsp_src_channel;                                   // mm_clock_crossing_bridge_m0_limiter:rsp_src_channel -> mm_clock_crossing_bridge_m0_agent:rp_channel
	wire          mm_clock_crossing_bridge_m0_limiter_rsp_src_startofpacket;                             // mm_clock_crossing_bridge_m0_limiter:rsp_src_startofpacket -> mm_clock_crossing_bridge_m0_agent:rp_startofpacket
	wire          mm_clock_crossing_bridge_m0_limiter_rsp_src_endofpacket;                               // mm_clock_crossing_bridge_m0_limiter:rsp_src_endofpacket -> mm_clock_crossing_bridge_m0_agent:rp_endofpacket
	wire          cmd_demux_src0_valid;                                                                  // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire   [99:0] cmd_demux_src0_data;                                                                   // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                                  // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [5:0] cmd_demux_src0_channel;                                                                // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                                          // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                            // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                                  // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire   [99:0] cmd_demux_src1_data;                                                                   // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_src1_ready;                                                                  // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire    [5:0] cmd_demux_src1_channel;                                                                // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_src1_startofpacket;                                                          // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_src1_endofpacket;                                                            // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_src2_valid;                                                                  // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
	wire   [99:0] cmd_demux_src2_data;                                                                   // cmd_demux:src2_data -> cmd_mux_002:sink0_data
	wire          cmd_demux_src2_ready;                                                                  // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
	wire    [5:0] cmd_demux_src2_channel;                                                                // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
	wire          cmd_demux_src2_startofpacket;                                                          // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          cmd_demux_src2_endofpacket;                                                            // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_src3_valid;                                                                  // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
	wire   [99:0] cmd_demux_src3_data;                                                                   // cmd_demux:src3_data -> cmd_mux_003:sink0_data
	wire          cmd_demux_src3_ready;                                                                  // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
	wire    [5:0] cmd_demux_src3_channel;                                                                // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
	wire          cmd_demux_src3_startofpacket;                                                          // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          cmd_demux_src3_endofpacket;                                                            // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          cmd_demux_src4_valid;                                                                  // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
	wire   [99:0] cmd_demux_src4_data;                                                                   // cmd_demux:src4_data -> cmd_mux_004:sink0_data
	wire          cmd_demux_src4_ready;                                                                  // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
	wire    [5:0] cmd_demux_src4_channel;                                                                // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
	wire          cmd_demux_src4_startofpacket;                                                          // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
	wire          cmd_demux_src4_endofpacket;                                                            // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
	wire          cmd_demux_src5_valid;                                                                  // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
	wire   [99:0] cmd_demux_src5_data;                                                                   // cmd_demux:src5_data -> cmd_mux_005:sink0_data
	wire          cmd_demux_src5_ready;                                                                  // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
	wire    [5:0] cmd_demux_src5_channel;                                                                // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
	wire          cmd_demux_src5_startofpacket;                                                          // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
	wire          cmd_demux_src5_endofpacket;                                                            // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                                  // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire   [99:0] rsp_demux_src0_data;                                                                   // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                                  // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [5:0] rsp_demux_src0_channel;                                                                // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                                          // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                            // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                              // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire   [99:0] rsp_demux_001_src0_data;                                                               // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire          rsp_demux_001_src0_ready;                                                              // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire    [5:0] rsp_demux_001_src0_channel;                                                            // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                                                      // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                                        // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire          rsp_demux_002_src0_valid;                                                              // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
	wire   [99:0] rsp_demux_002_src0_data;                                                               // rsp_demux_002:src0_data -> rsp_mux:sink2_data
	wire          rsp_demux_002_src0_ready;                                                              // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
	wire    [5:0] rsp_demux_002_src0_channel;                                                            // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
	wire          rsp_demux_002_src0_startofpacket;                                                      // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                                        // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
	wire          rsp_demux_003_src0_valid;                                                              // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
	wire   [99:0] rsp_demux_003_src0_data;                                                               // rsp_demux_003:src0_data -> rsp_mux:sink3_data
	wire          rsp_demux_003_src0_ready;                                                              // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
	wire    [5:0] rsp_demux_003_src0_channel;                                                            // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
	wire          rsp_demux_003_src0_startofpacket;                                                      // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                                        // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
	wire          rsp_demux_004_src0_valid;                                                              // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
	wire   [99:0] rsp_demux_004_src0_data;                                                               // rsp_demux_004:src0_data -> rsp_mux:sink4_data
	wire          rsp_demux_004_src0_ready;                                                              // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
	wire    [5:0] rsp_demux_004_src0_channel;                                                            // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
	wire          rsp_demux_004_src0_startofpacket;                                                      // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
	wire          rsp_demux_004_src0_endofpacket;                                                        // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
	wire          rsp_demux_005_src0_valid;                                                              // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
	wire   [99:0] rsp_demux_005_src0_data;                                                               // rsp_demux_005:src0_data -> rsp_mux:sink5_data
	wire          rsp_demux_005_src0_ready;                                                              // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
	wire    [5:0] rsp_demux_005_src0_channel;                                                            // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
	wire          rsp_demux_005_src0_startofpacket;                                                      // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
	wire          rsp_demux_005_src0_endofpacket;                                                        // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
	wire    [5:0] mm_clock_crossing_bridge_m0_limiter_cmd_valid_data;                                    // mm_clock_crossing_bridge_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid

	address_decoder_top_altera_merlin_master_translator_191_g7h47bq #(
		.AV_ADDRESS_W                (17),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (17),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0),
		.SYNC_RESET                  (0),
		.WAITREQUEST_ALLOWANCE       (0)
	) mm_clock_crossing_bridge_m0_translator (
		.clk                    (mac_clk_clk_clk),                                                                //   input,   width = 1,                       clk.clk
		.reset                  (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                  //   input,   width = 1,                     reset.reset
		.uav_address            (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_address),       //  output,  width = 17, avalon_universal_master_0.address
		.uav_burstcount         (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_burstcount),    //  output,   width = 3,                          .burstcount
		.uav_read               (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_read),          //  output,   width = 1,                          .read
		.uav_write              (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_write),         //  output,   width = 1,                          .write
		.uav_waitrequest        (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_waitrequest),   //   input,   width = 1,                          .waitrequest
		.uav_readdatavalid      (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_readdatavalid), //   input,   width = 1,                          .readdatavalid
		.uav_byteenable         (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_byteenable),    //  output,   width = 4,                          .byteenable
		.uav_readdata           (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_readdata),      //   input,  width = 32,                          .readdata
		.uav_writedata          (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_writedata),     //  output,  width = 32,                          .writedata
		.uav_lock               (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_lock),          //  output,   width = 1,                          .lock
		.uav_debugaccess        (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_debugaccess),   //  output,   width = 1,                          .debugaccess
		.av_address             (mm_clock_crossing_bridge_m0_address),                                            //   input,  width = 17,      avalon_anti_master_0.address
		.av_waitrequest         (mm_clock_crossing_bridge_m0_waitrequest),                                        //  output,   width = 1,                          .waitrequest
		.av_burstcount          (mm_clock_crossing_bridge_m0_burstcount),                                         //   input,   width = 1,                          .burstcount
		.av_byteenable          (mm_clock_crossing_bridge_m0_byteenable),                                         //   input,   width = 4,                          .byteenable
		.av_read                (mm_clock_crossing_bridge_m0_read),                                               //   input,   width = 1,                          .read
		.av_readdata            (mm_clock_crossing_bridge_m0_readdata),                                           //  output,  width = 32,                          .readdata
		.av_readdatavalid       (mm_clock_crossing_bridge_m0_readdatavalid),                                      //  output,   width = 1,                          .readdatavalid
		.av_write               (mm_clock_crossing_bridge_m0_write),                                              //   input,   width = 1,                          .write
		.av_writedata           (mm_clock_crossing_bridge_m0_writedata),                                          //   input,  width = 32,                          .writedata
		.av_debugaccess         (mm_clock_crossing_bridge_m0_debugaccess),                                        //   input,   width = 1,                          .debugaccess
		.av_beginbursttransfer  (1'b0),                                                                           // (terminated),                                        
		.av_begintransfer       (1'b0),                                                                           // (terminated),                                        
		.av_chipselect          (1'b0),                                                                           // (terminated),                                        
		.av_lock                (1'b0),                                                                           // (terminated),                                        
		.uav_clken              (),                                                                               // (terminated),                                        
		.av_clken               (1'b1),                                                                           // (terminated),                                        
		.uav_response           (2'b00),                                                                          // (terminated),                                        
		.av_response            (),                                                                               // (terminated),                                        
		.uav_writeresponsevalid (1'b0),                                                                           // (terminated),                                        
		.av_writeresponsevalid  ()                                                                                // (terminated),                                        
	);

	address_decoder_top_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (14),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (3),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (17),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (1),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) traffic_controller_ch_0_1_avalon_universal_slave_0_translator (
		.clk                    (mac_clk_clk_clk),                                                           //   input,   width = 1,                      clk.clk
		.reset                  (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),             //   input,   width = 1,                    reset.reset
		.uav_address            (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_address),       //   input,  width = 17, avalon_universal_slave_0.address
		.uav_burstcount         (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (traffic_controller_ch_0_1_avalon_universal_slave_0_address),                //  output,  width = 14,      avalon_anti_slave_0.address
		.av_write               (traffic_controller_ch_0_1_avalon_universal_slave_0_write),                  //  output,   width = 1,                         .write
		.av_read                (traffic_controller_ch_0_1_avalon_universal_slave_0_read),                   //  output,   width = 1,                         .read
		.av_readdata            (traffic_controller_ch_0_1_avalon_universal_slave_0_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (traffic_controller_ch_0_1_avalon_universal_slave_0_writedata),              //  output,  width = 32,                         .writedata
		.av_burstcount          (traffic_controller_ch_0_1_avalon_universal_slave_0_burstcount),             //  output,   width = 3,                         .burstcount
		.av_byteenable          (traffic_controller_ch_0_1_avalon_universal_slave_0_byteenable),             //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (traffic_controller_ch_0_1_avalon_universal_slave_0_readdatavalid),          //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (traffic_controller_ch_0_1_avalon_universal_slave_0_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_lock                (traffic_controller_ch_0_1_avalon_universal_slave_0_lock),                   //  output,   width = 1,                         .lock
		.av_debugaccess         (traffic_controller_ch_0_1_avalon_universal_slave_0_debugaccess),            //  output,   width = 1,                         .debugaccess
		.av_begintransfer       (),                                                                          // (terminated),                                       
		.av_beginbursttransfer  (),                                                                          // (terminated),                                       
		.av_writebyteenable     (),                                                                          // (terminated),                                       
		.av_chipselect          (),                                                                          // (terminated),                                       
		.av_clken               (),                                                                          // (terminated),                                       
		.uav_clken              (1'b0),                                                                      // (terminated),                                       
		.av_outputenable        (),                                                                          // (terminated),                                       
		.uav_response           (),                                                                          // (terminated),                                       
		.av_response            (2'b00),                                                                     // (terminated),                                       
		.uav_writeresponsevalid (),                                                                          // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                       // (terminated),                                       
	);

	address_decoder_top_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (14),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (3),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (17),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (1),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) traffic_controller_ch_2_3_avalon_universal_slave_0_translator (
		.clk                    (mac_clk_clk_clk),                                                           //   input,   width = 1,                      clk.clk
		.reset                  (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),             //   input,   width = 1,                    reset.reset
		.uav_address            (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_address),       //   input,  width = 17, avalon_universal_slave_0.address
		.uav_burstcount         (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (traffic_controller_ch_2_3_avalon_universal_slave_0_address),                //  output,  width = 14,      avalon_anti_slave_0.address
		.av_write               (traffic_controller_ch_2_3_avalon_universal_slave_0_write),                  //  output,   width = 1,                         .write
		.av_read                (traffic_controller_ch_2_3_avalon_universal_slave_0_read),                   //  output,   width = 1,                         .read
		.av_readdata            (traffic_controller_ch_2_3_avalon_universal_slave_0_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (traffic_controller_ch_2_3_avalon_universal_slave_0_writedata),              //  output,  width = 32,                         .writedata
		.av_burstcount          (traffic_controller_ch_2_3_avalon_universal_slave_0_burstcount),             //  output,   width = 3,                         .burstcount
		.av_byteenable          (traffic_controller_ch_2_3_avalon_universal_slave_0_byteenable),             //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (traffic_controller_ch_2_3_avalon_universal_slave_0_readdatavalid),          //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (traffic_controller_ch_2_3_avalon_universal_slave_0_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_lock                (traffic_controller_ch_2_3_avalon_universal_slave_0_lock),                   //  output,   width = 1,                         .lock
		.av_debugaccess         (traffic_controller_ch_2_3_avalon_universal_slave_0_debugaccess),            //  output,   width = 1,                         .debugaccess
		.av_begintransfer       (),                                                                          // (terminated),                                       
		.av_beginbursttransfer  (),                                                                          // (terminated),                                       
		.av_writebyteenable     (),                                                                          // (terminated),                                       
		.av_chipselect          (),                                                                          // (terminated),                                       
		.av_clken               (),                                                                          // (terminated),                                       
		.uav_clken              (1'b0),                                                                      // (terminated),                                       
		.av_outputenable        (),                                                                          // (terminated),                                       
		.uav_response           (),                                                                          // (terminated),                                       
		.av_response            (2'b00),                                                                     // (terminated),                                       
		.uav_writeresponsevalid (),                                                                          // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                       // (terminated),                                       
	);

	address_decoder_top_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (14),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (3),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (17),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (1),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) traffic_controller_ch_4_5_avalon_universal_slave_0_translator (
		.clk                    (mac_clk_clk_clk),                                                           //   input,   width = 1,                      clk.clk
		.reset                  (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),             //   input,   width = 1,                    reset.reset
		.uav_address            (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_address),       //   input,  width = 17, avalon_universal_slave_0.address
		.uav_burstcount         (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (traffic_controller_ch_4_5_avalon_universal_slave_0_address),                //  output,  width = 14,      avalon_anti_slave_0.address
		.av_write               (traffic_controller_ch_4_5_avalon_universal_slave_0_write),                  //  output,   width = 1,                         .write
		.av_read                (traffic_controller_ch_4_5_avalon_universal_slave_0_read),                   //  output,   width = 1,                         .read
		.av_readdata            (traffic_controller_ch_4_5_avalon_universal_slave_0_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (traffic_controller_ch_4_5_avalon_universal_slave_0_writedata),              //  output,  width = 32,                         .writedata
		.av_burstcount          (traffic_controller_ch_4_5_avalon_universal_slave_0_burstcount),             //  output,   width = 3,                         .burstcount
		.av_byteenable          (traffic_controller_ch_4_5_avalon_universal_slave_0_byteenable),             //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (traffic_controller_ch_4_5_avalon_universal_slave_0_readdatavalid),          //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (traffic_controller_ch_4_5_avalon_universal_slave_0_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_lock                (traffic_controller_ch_4_5_avalon_universal_slave_0_lock),                   //  output,   width = 1,                         .lock
		.av_debugaccess         (traffic_controller_ch_4_5_avalon_universal_slave_0_debugaccess),            //  output,   width = 1,                         .debugaccess
		.av_begintransfer       (),                                                                          // (terminated),                                       
		.av_beginbursttransfer  (),                                                                          // (terminated),                                       
		.av_writebyteenable     (),                                                                          // (terminated),                                       
		.av_chipselect          (),                                                                          // (terminated),                                       
		.av_clken               (),                                                                          // (terminated),                                       
		.uav_clken              (1'b0),                                                                      // (terminated),                                       
		.av_outputenable        (),                                                                          // (terminated),                                       
		.uav_response           (),                                                                          // (terminated),                                       
		.av_response            (2'b00),                                                                     // (terminated),                                       
		.uav_writeresponsevalid (),                                                                          // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                       // (terminated),                                       
	);

	address_decoder_top_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (14),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (3),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (17),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (1),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) traffic_controller_ch_6_7_avalon_universal_slave_0_translator (
		.clk                    (mac_clk_clk_clk),                                                           //   input,   width = 1,                      clk.clk
		.reset                  (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),             //   input,   width = 1,                    reset.reset
		.uav_address            (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_address),       //   input,  width = 17, avalon_universal_slave_0.address
		.uav_burstcount         (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (traffic_controller_ch_6_7_avalon_universal_slave_0_address),                //  output,  width = 14,      avalon_anti_slave_0.address
		.av_write               (traffic_controller_ch_6_7_avalon_universal_slave_0_write),                  //  output,   width = 1,                         .write
		.av_read                (traffic_controller_ch_6_7_avalon_universal_slave_0_read),                   //  output,   width = 1,                         .read
		.av_readdata            (traffic_controller_ch_6_7_avalon_universal_slave_0_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (traffic_controller_ch_6_7_avalon_universal_slave_0_writedata),              //  output,  width = 32,                         .writedata
		.av_burstcount          (traffic_controller_ch_6_7_avalon_universal_slave_0_burstcount),             //  output,   width = 3,                         .burstcount
		.av_byteenable          (traffic_controller_ch_6_7_avalon_universal_slave_0_byteenable),             //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (traffic_controller_ch_6_7_avalon_universal_slave_0_readdatavalid),          //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (traffic_controller_ch_6_7_avalon_universal_slave_0_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_lock                (traffic_controller_ch_6_7_avalon_universal_slave_0_lock),                   //  output,   width = 1,                         .lock
		.av_debugaccess         (traffic_controller_ch_6_7_avalon_universal_slave_0_debugaccess),            //  output,   width = 1,                         .debugaccess
		.av_begintransfer       (),                                                                          // (terminated),                                       
		.av_beginbursttransfer  (),                                                                          // (terminated),                                       
		.av_writebyteenable     (),                                                                          // (terminated),                                       
		.av_chipselect          (),                                                                          // (terminated),                                       
		.av_clken               (),                                                                          // (terminated),                                       
		.uav_clken              (1'b0),                                                                      // (terminated),                                       
		.av_outputenable        (),                                                                          // (terminated),                                       
		.uav_response           (),                                                                          // (terminated),                                       
		.av_response            (2'b00),                                                                     // (terminated),                                       
		.uav_writeresponsevalid (),                                                                          // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                       // (terminated),                                       
	);

	address_decoder_top_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (14),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (3),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (17),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (1),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) traffic_controller_ch_8_9_avalon_universal_slave_0_translator (
		.clk                    (mac_clk_clk_clk),                                                           //   input,   width = 1,                      clk.clk
		.reset                  (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),             //   input,   width = 1,                    reset.reset
		.uav_address            (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_address),       //   input,  width = 17, avalon_universal_slave_0.address
		.uav_burstcount         (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (traffic_controller_ch_8_9_avalon_universal_slave_0_address),                //  output,  width = 14,      avalon_anti_slave_0.address
		.av_write               (traffic_controller_ch_8_9_avalon_universal_slave_0_write),                  //  output,   width = 1,                         .write
		.av_read                (traffic_controller_ch_8_9_avalon_universal_slave_0_read),                   //  output,   width = 1,                         .read
		.av_readdata            (traffic_controller_ch_8_9_avalon_universal_slave_0_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (traffic_controller_ch_8_9_avalon_universal_slave_0_writedata),              //  output,  width = 32,                         .writedata
		.av_burstcount          (traffic_controller_ch_8_9_avalon_universal_slave_0_burstcount),             //  output,   width = 3,                         .burstcount
		.av_byteenable          (traffic_controller_ch_8_9_avalon_universal_slave_0_byteenable),             //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (traffic_controller_ch_8_9_avalon_universal_slave_0_readdatavalid),          //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (traffic_controller_ch_8_9_avalon_universal_slave_0_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_lock                (traffic_controller_ch_8_9_avalon_universal_slave_0_lock),                   //  output,   width = 1,                         .lock
		.av_debugaccess         (traffic_controller_ch_8_9_avalon_universal_slave_0_debugaccess),            //  output,   width = 1,                         .debugaccess
		.av_begintransfer       (),                                                                          // (terminated),                                       
		.av_beginbursttransfer  (),                                                                          // (terminated),                                       
		.av_writebyteenable     (),                                                                          // (terminated),                                       
		.av_chipselect          (),                                                                          // (terminated),                                       
		.av_clken               (),                                                                          // (terminated),                                       
		.uav_clken              (1'b0),                                                                      // (terminated),                                       
		.av_outputenable        (),                                                                          // (terminated),                                       
		.uav_response           (),                                                                          // (terminated),                                       
		.av_response            (2'b00),                                                                     // (terminated),                                       
		.uav_writeresponsevalid (),                                                                          // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                       // (terminated),                                       
	);

	address_decoder_top_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (14),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (3),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (17),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (1),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) traffic_controller_ch_10_11_avalon_universal_slave_0_translator (
		.clk                    (mac_clk_clk_clk),                                                             //   input,   width = 1,                      clk.clk
		.reset                  (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),               //   input,   width = 1,                    reset.reset
		.uav_address            (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_address),       //   input,  width = 17, avalon_universal_slave_0.address
		.uav_burstcount         (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (traffic_controller_ch_10_11_avalon_universal_slave_0_address),                //  output,  width = 14,      avalon_anti_slave_0.address
		.av_write               (traffic_controller_ch_10_11_avalon_universal_slave_0_write),                  //  output,   width = 1,                         .write
		.av_read                (traffic_controller_ch_10_11_avalon_universal_slave_0_read),                   //  output,   width = 1,                         .read
		.av_readdata            (traffic_controller_ch_10_11_avalon_universal_slave_0_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (traffic_controller_ch_10_11_avalon_universal_slave_0_writedata),              //  output,  width = 32,                         .writedata
		.av_burstcount          (traffic_controller_ch_10_11_avalon_universal_slave_0_burstcount),             //  output,   width = 3,                         .burstcount
		.av_byteenable          (traffic_controller_ch_10_11_avalon_universal_slave_0_byteenable),             //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (traffic_controller_ch_10_11_avalon_universal_slave_0_readdatavalid),          //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (traffic_controller_ch_10_11_avalon_universal_slave_0_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_lock                (traffic_controller_ch_10_11_avalon_universal_slave_0_lock),                   //  output,   width = 1,                         .lock
		.av_debugaccess         (traffic_controller_ch_10_11_avalon_universal_slave_0_debugaccess),            //  output,   width = 1,                         .debugaccess
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	address_decoder_top_altera_merlin_master_agent_191_mpbm6tq #(
		.PKT_WUNIQUE               (99),
		.PKT_DOMAIN_H              (98),
		.PKT_DOMAIN_L              (97),
		.PKT_SNOOP_H               (96),
		.PKT_SNOOP_L               (93),
		.PKT_BARRIER_H             (92),
		.PKT_BARRIER_L             (91),
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_QOS_H                 (71),
		.PKT_QOS_L                 (71),
		.PKT_DATA_SIDEBAND_H       (69),
		.PKT_DATA_SIDEBAND_L       (69),
		.PKT_ADDR_SIDEBAND_H       (68),
		.PKT_ADDR_SIDEBAND_L       (68),
		.PKT_BURST_TYPE_H          (67),
		.PKT_BURST_TYPE_L          (66),
		.PKT_CACHE_H               (85),
		.PKT_CACHE_L               (82),
		.PKT_THREAD_ID_H           (78),
		.PKT_THREAD_ID_L           (78),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_EXCLUSIVE       (58),
		.PKT_TRANS_LOCK            (57),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_ADDR_H                (52),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (53),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.PKT_TRANS_READ            (56),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.ST_DATA_W                 (100),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.DOMAIN_VALUE              (3),
		.BARRIER_VALUE             (0),
		.SNOOP_VALUE               (0),
		.WUNIQUE_VALUE             (0),
		.SYNC_RESET                (0)
	) mm_clock_crossing_bridge_m0_agent (
		.clk                   (mac_clk_clk_clk),                                                                //   input,    width = 1,       clk.clk
		.reset                 (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                  //   input,    width = 1, clk_reset.reset
		.av_address            (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_address),       //   input,   width = 17,        av.address
		.av_write              (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_write),         //   input,    width = 1,          .write
		.av_read               (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_read),          //   input,    width = 1,          .read
		.av_writedata          (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_writedata),     //   input,   width = 32,          .writedata
		.av_readdata           (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_readdata),      //  output,   width = 32,          .readdata
		.av_waitrequest        (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_waitrequest),   //  output,    width = 1,          .waitrequest
		.av_readdatavalid      (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_readdatavalid), //  output,    width = 1,          .readdatavalid
		.av_byteenable         (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_byteenable),    //   input,    width = 4,          .byteenable
		.av_burstcount         (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_burstcount),    //   input,    width = 3,          .burstcount
		.av_debugaccess        (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_debugaccess),   //   input,    width = 1,          .debugaccess
		.av_lock               (mm_clock_crossing_bridge_m0_translator_avalon_universal_master_0_lock),          //   input,    width = 1,          .lock
		.cp_valid              (mm_clock_crossing_bridge_m0_agent_cp_valid),                                     //  output,    width = 1,        cp.valid
		.cp_data               (mm_clock_crossing_bridge_m0_agent_cp_data),                                      //  output,  width = 100,          .data
		.cp_startofpacket      (mm_clock_crossing_bridge_m0_agent_cp_startofpacket),                             //  output,    width = 1,          .startofpacket
		.cp_endofpacket        (mm_clock_crossing_bridge_m0_agent_cp_endofpacket),                               //  output,    width = 1,          .endofpacket
		.cp_ready              (mm_clock_crossing_bridge_m0_agent_cp_ready),                                     //   input,    width = 1,          .ready
		.rp_valid              (mm_clock_crossing_bridge_m0_limiter_rsp_src_valid),                              //   input,    width = 1,        rp.valid
		.rp_data               (mm_clock_crossing_bridge_m0_limiter_rsp_src_data),                               //   input,  width = 100,          .data
		.rp_channel            (mm_clock_crossing_bridge_m0_limiter_rsp_src_channel),                            //   input,    width = 6,          .channel
		.rp_startofpacket      (mm_clock_crossing_bridge_m0_limiter_rsp_src_startofpacket),                      //   input,    width = 1,          .startofpacket
		.rp_endofpacket        (mm_clock_crossing_bridge_m0_limiter_rsp_src_endofpacket),                        //   input,    width = 1,          .endofpacket
		.rp_ready              (mm_clock_crossing_bridge_m0_limiter_rsp_src_ready),                              //  output,    width = 1,          .ready
		.av_response           (),                                                                               // (terminated),                         
		.av_writeresponsevalid ()                                                                                // (terminated),                         
	);

	address_decoder_top_altera_merlin_slave_agent_191_ncfkfri #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (57),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_ADDR_H                (52),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (53),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.PKT_TRANS_READ            (56),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (100),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0)
	) traffic_controller_ch_0_1_avalon_universal_slave_0_agent (
		.clk                     (mac_clk_clk_clk),                                                                     //   input,    width = 1,             clk.clk
		.reset                   (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                       //   input,    width = 1,       clk_reset.reset
		.m0_address              (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_address),                 //  output,   width = 17,              m0.address
		.m0_burstcount           (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_data),                    //  output,  width = 100,                .data
		.rp_startofpacket        (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_src_ready),                                                                   //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_src_valid),                                                                   //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_src_data),                                                                    //   input,  width = 100,                .data
		.cp_startofpacket        (cmd_mux_src_startofpacket),                                                           //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_src_endofpacket),                                                             //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_src_channel),                                                                 //   input,    width = 6,                .channel
		.rf_sink_ready           (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //   input,  width = 101,                .data
		.rf_source_ready         (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_data),             //  output,  width = 101,                .data
		.rdata_fifo_sink_ready   (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                               // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                                // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                                 // (terminated),                               
	);

	address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (101),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.SYNC_RESET          (0)
	) traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (mac_clk_clk_clk),                                                                     //   input,    width = 1,       clk.clk
		.reset             (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                       //   input,    width = 1, clk_reset.reset
		.in_data           (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_data),             //   input,  width = 101,        in.data
		.in_valid          (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //  output,  width = 101,       out.data
		.out_valid         (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                                               // (terminated),                         
		.csr_read          (1'b0),                                                                                // (terminated),                         
		.csr_write         (1'b0),                                                                                // (terminated),                         
		.csr_readdata      (),                                                                                    // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                                                // (terminated),                         
		.almost_full_data  (),                                                                                    // (terminated),                         
		.almost_empty_data (),                                                                                    // (terminated),                         
		.in_empty          (1'b0),                                                                                // (terminated),                         
		.out_empty         (),                                                                                    // (terminated),                         
		.in_error          (1'b0),                                                                                // (terminated),                         
		.out_error         (),                                                                                    // (terminated),                         
		.in_channel        (1'b0),                                                                                // (terminated),                         
		.out_channel       ()                                                                                     // (terminated),                         
	);

	address_decoder_top_altera_merlin_slave_agent_191_ncfkfri #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (57),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_ADDR_H                (52),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (53),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.PKT_TRANS_READ            (56),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (100),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0)
	) traffic_controller_ch_2_3_avalon_universal_slave_0_agent (
		.clk                     (mac_clk_clk_clk),                                                                     //   input,    width = 1,             clk.clk
		.reset                   (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                       //   input,    width = 1,       clk_reset.reset
		.m0_address              (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_address),                 //  output,   width = 17,              m0.address
		.m0_burstcount           (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_data),                    //  output,  width = 100,                .data
		.rp_startofpacket        (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_001_src_ready),                                                               //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_001_src_valid),                                                               //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_001_src_data),                                                                //   input,  width = 100,                .data
		.cp_startofpacket        (cmd_mux_001_src_startofpacket),                                                       //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_001_src_endofpacket),                                                         //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_001_src_channel),                                                             //   input,    width = 6,                .channel
		.rf_sink_ready           (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //   input,  width = 101,                .data
		.rf_source_ready         (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_data),             //  output,  width = 101,                .data
		.rdata_fifo_sink_ready   (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                               // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                                // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                                 // (terminated),                               
	);

	address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (101),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.SYNC_RESET          (0)
	) traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (mac_clk_clk_clk),                                                                     //   input,    width = 1,       clk.clk
		.reset             (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                       //   input,    width = 1, clk_reset.reset
		.in_data           (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_data),             //   input,  width = 101,        in.data
		.in_valid          (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //  output,  width = 101,       out.data
		.out_valid         (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                                               // (terminated),                         
		.csr_read          (1'b0),                                                                                // (terminated),                         
		.csr_write         (1'b0),                                                                                // (terminated),                         
		.csr_readdata      (),                                                                                    // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                                                // (terminated),                         
		.almost_full_data  (),                                                                                    // (terminated),                         
		.almost_empty_data (),                                                                                    // (terminated),                         
		.in_empty          (1'b0),                                                                                // (terminated),                         
		.out_empty         (),                                                                                    // (terminated),                         
		.in_error          (1'b0),                                                                                // (terminated),                         
		.out_error         (),                                                                                    // (terminated),                         
		.in_channel        (1'b0),                                                                                // (terminated),                         
		.out_channel       ()                                                                                     // (terminated),                         
	);

	address_decoder_top_altera_merlin_slave_agent_191_ncfkfri #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (57),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_ADDR_H                (52),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (53),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.PKT_TRANS_READ            (56),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (100),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0)
	) traffic_controller_ch_4_5_avalon_universal_slave_0_agent (
		.clk                     (mac_clk_clk_clk),                                                                     //   input,    width = 1,             clk.clk
		.reset                   (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                       //   input,    width = 1,       clk_reset.reset
		.m0_address              (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_address),                 //  output,   width = 17,              m0.address
		.m0_burstcount           (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_data),                    //  output,  width = 100,                .data
		.rp_startofpacket        (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_002_src_ready),                                                               //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_002_src_valid),                                                               //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_002_src_data),                                                                //   input,  width = 100,                .data
		.cp_startofpacket        (cmd_mux_002_src_startofpacket),                                                       //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_002_src_endofpacket),                                                         //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_002_src_channel),                                                             //   input,    width = 6,                .channel
		.rf_sink_ready           (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //   input,  width = 101,                .data
		.rf_source_ready         (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_data),             //  output,  width = 101,                .data
		.rdata_fifo_sink_ready   (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                               // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                                // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                                 // (terminated),                               
	);

	address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (101),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.SYNC_RESET          (0)
	) traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (mac_clk_clk_clk),                                                                     //   input,    width = 1,       clk.clk
		.reset             (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                       //   input,    width = 1, clk_reset.reset
		.in_data           (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_data),             //   input,  width = 101,        in.data
		.in_valid          (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //  output,  width = 101,       out.data
		.out_valid         (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                                               // (terminated),                         
		.csr_read          (1'b0),                                                                                // (terminated),                         
		.csr_write         (1'b0),                                                                                // (terminated),                         
		.csr_readdata      (),                                                                                    // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                                                // (terminated),                         
		.almost_full_data  (),                                                                                    // (terminated),                         
		.almost_empty_data (),                                                                                    // (terminated),                         
		.in_empty          (1'b0),                                                                                // (terminated),                         
		.out_empty         (),                                                                                    // (terminated),                         
		.in_error          (1'b0),                                                                                // (terminated),                         
		.out_error         (),                                                                                    // (terminated),                         
		.in_channel        (1'b0),                                                                                // (terminated),                         
		.out_channel       ()                                                                                     // (terminated),                         
	);

	address_decoder_top_altera_merlin_slave_agent_191_ncfkfri #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (57),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_ADDR_H                (52),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (53),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.PKT_TRANS_READ            (56),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (100),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0)
	) traffic_controller_ch_6_7_avalon_universal_slave_0_agent (
		.clk                     (mac_clk_clk_clk),                                                                     //   input,    width = 1,             clk.clk
		.reset                   (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                       //   input,    width = 1,       clk_reset.reset
		.m0_address              (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_address),                 //  output,   width = 17,              m0.address
		.m0_burstcount           (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_data),                    //  output,  width = 100,                .data
		.rp_startofpacket        (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_003_src_ready),                                                               //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_003_src_valid),                                                               //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_003_src_data),                                                                //   input,  width = 100,                .data
		.cp_startofpacket        (cmd_mux_003_src_startofpacket),                                                       //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_003_src_endofpacket),                                                         //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_003_src_channel),                                                             //   input,    width = 6,                .channel
		.rf_sink_ready           (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //   input,  width = 101,                .data
		.rf_source_ready         (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_data),             //  output,  width = 101,                .data
		.rdata_fifo_sink_ready   (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                               // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                                // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                                 // (terminated),                               
	);

	address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (101),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.SYNC_RESET          (0)
	) traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (mac_clk_clk_clk),                                                                     //   input,    width = 1,       clk.clk
		.reset             (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                       //   input,    width = 1, clk_reset.reset
		.in_data           (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_data),             //   input,  width = 101,        in.data
		.in_valid          (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //  output,  width = 101,       out.data
		.out_valid         (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                                               // (terminated),                         
		.csr_read          (1'b0),                                                                                // (terminated),                         
		.csr_write         (1'b0),                                                                                // (terminated),                         
		.csr_readdata      (),                                                                                    // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                                                // (terminated),                         
		.almost_full_data  (),                                                                                    // (terminated),                         
		.almost_empty_data (),                                                                                    // (terminated),                         
		.in_empty          (1'b0),                                                                                // (terminated),                         
		.out_empty         (),                                                                                    // (terminated),                         
		.in_error          (1'b0),                                                                                // (terminated),                         
		.out_error         (),                                                                                    // (terminated),                         
		.in_channel        (1'b0),                                                                                // (terminated),                         
		.out_channel       ()                                                                                     // (terminated),                         
	);

	address_decoder_top_altera_merlin_slave_agent_191_ncfkfri #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (57),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_ADDR_H                (52),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (53),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.PKT_TRANS_READ            (56),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (100),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0)
	) traffic_controller_ch_8_9_avalon_universal_slave_0_agent (
		.clk                     (mac_clk_clk_clk),                                                                     //   input,    width = 1,             clk.clk
		.reset                   (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                       //   input,    width = 1,       clk_reset.reset
		.m0_address              (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_address),                 //  output,   width = 17,              m0.address
		.m0_burstcount           (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_data),                    //  output,  width = 100,                .data
		.rp_startofpacket        (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_004_src_ready),                                                               //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_004_src_valid),                                                               //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_004_src_data),                                                                //   input,  width = 100,                .data
		.cp_startofpacket        (cmd_mux_004_src_startofpacket),                                                       //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_004_src_endofpacket),                                                         //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_004_src_channel),                                                             //   input,    width = 6,                .channel
		.rf_sink_ready           (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //   input,  width = 101,                .data
		.rf_source_ready         (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_data),             //  output,  width = 101,                .data
		.rdata_fifo_sink_ready   (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                               // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                                // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                                 // (terminated),                               
	);

	address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (101),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.SYNC_RESET          (0)
	) traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (mac_clk_clk_clk),                                                                     //   input,    width = 1,       clk.clk
		.reset             (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                       //   input,    width = 1, clk_reset.reset
		.in_data           (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_data),             //   input,  width = 101,        in.data
		.in_valid          (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //  output,  width = 101,       out.data
		.out_valid         (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                                               // (terminated),                         
		.csr_read          (1'b0),                                                                                // (terminated),                         
		.csr_write         (1'b0),                                                                                // (terminated),                         
		.csr_readdata      (),                                                                                    // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                                                // (terminated),                         
		.almost_full_data  (),                                                                                    // (terminated),                         
		.almost_empty_data (),                                                                                    // (terminated),                         
		.in_empty          (1'b0),                                                                                // (terminated),                         
		.out_empty         (),                                                                                    // (terminated),                         
		.in_error          (1'b0),                                                                                // (terminated),                         
		.out_error         (),                                                                                    // (terminated),                         
		.in_channel        (1'b0),                                                                                // (terminated),                         
		.out_channel       ()                                                                                     // (terminated),                         
	);

	address_decoder_top_altera_merlin_slave_agent_191_ncfkfri #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (57),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_ADDR_H                (52),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (53),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.PKT_TRANS_READ            (56),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (100),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0)
	) traffic_controller_ch_10_11_avalon_universal_slave_0_agent (
		.clk                     (mac_clk_clk_clk),                                                                       //   input,    width = 1,             clk.clk
		.reset                   (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                         //   input,    width = 1,       clk_reset.reset
		.m0_address              (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_address),                 //  output,   width = 17,              m0.address
		.m0_burstcount           (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_data),                    //  output,  width = 100,                .data
		.rp_startofpacket        (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_005_src_ready),                                                                 //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_005_src_valid),                                                                 //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_005_src_data),                                                                  //   input,  width = 100,                .data
		.cp_startofpacket        (cmd_mux_005_src_startofpacket),                                                         //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_005_src_endofpacket),                                                           //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_005_src_channel),                                                               //   input,    width = 6,                .channel
		.rf_sink_ready           (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //   input,  width = 101,                .data
		.rf_source_ready         (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_data),             //  output,  width = 101,                .data
		.rdata_fifo_sink_ready   (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                                 // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                                  // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                                   // (terminated),                               
	);

	address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (101),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.SYNC_RESET          (0)
	) traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (mac_clk_clk_clk),                                                                       //   input,    width = 1,       clk.clk
		.reset             (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),                         //   input,    width = 1, clk_reset.reset
		.in_data           (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_data),             //   input,  width = 101,        in.data
		.in_valid          (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //  output,  width = 101,       out.data
		.out_valid         (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                                                 // (terminated),                         
		.csr_read          (1'b0),                                                                                  // (terminated),                         
		.csr_write         (1'b0),                                                                                  // (terminated),                         
		.csr_readdata      (),                                                                                      // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                                                  // (terminated),                         
		.almost_full_data  (),                                                                                      // (terminated),                         
		.almost_empty_data (),                                                                                      // (terminated),                         
		.in_empty          (1'b0),                                                                                  // (terminated),                         
		.out_empty         (),                                                                                      // (terminated),                         
		.in_error          (1'b0),                                                                                  // (terminated),                         
		.out_error         (),                                                                                      // (terminated),                         
		.in_channel        (1'b0),                                                                                  // (terminated),                         
		.out_channel       ()                                                                                       // (terminated),                         
	);

	address_decoder_top_altera_merlin_router_191_oyu3via router (
		.sink_ready         (mm_clock_crossing_bridge_m0_agent_cp_ready),                    //  output,    width = 1,      sink.ready
		.sink_valid         (mm_clock_crossing_bridge_m0_agent_cp_valid),                    //   input,    width = 1,          .valid
		.sink_data          (mm_clock_crossing_bridge_m0_agent_cp_data),                     //   input,  width = 100,          .data
		.sink_startofpacket (mm_clock_crossing_bridge_m0_agent_cp_startofpacket),            //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (mm_clock_crossing_bridge_m0_agent_cp_endofpacket),              //   input,    width = 1,          .endofpacket
		.clk                (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_src_ready),                                              //   input,    width = 1,       src.ready
		.src_valid          (router_src_valid),                                              //  output,    width = 1,          .valid
		.src_data           (router_src_data),                                               //  output,  width = 100,          .data
		.src_channel        (router_src_channel),                                            //  output,    width = 6,          .channel
		.src_startofpacket  (router_src_startofpacket),                                      //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                         //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_router_191_eyt5dgy router_001 (
		.sink_ready         (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_valid),         //   input,    width = 1,          .valid
		.sink_data          (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_data),          //   input,  width = 100,          .data
		.sink_startofpacket (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (traffic_controller_ch_0_1_avalon_universal_slave_0_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (mac_clk_clk_clk),                                                           //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),             //   input,    width = 1, clk_reset.reset
		.src_ready          (router_001_src_ready),                                                      //   input,    width = 1,       src.ready
		.src_valid          (router_001_src_valid),                                                      //  output,    width = 1,          .valid
		.src_data           (router_001_src_data),                                                       //  output,  width = 100,          .data
		.src_channel        (router_001_src_channel),                                                    //  output,    width = 6,          .channel
		.src_startofpacket  (router_001_src_startofpacket),                                              //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                                 //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_router_191_eyt5dgy router_002 (
		.sink_ready         (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_valid),         //   input,    width = 1,          .valid
		.sink_data          (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_data),          //   input,  width = 100,          .data
		.sink_startofpacket (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (traffic_controller_ch_2_3_avalon_universal_slave_0_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (mac_clk_clk_clk),                                                           //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),             //   input,    width = 1, clk_reset.reset
		.src_ready          (router_002_src_ready),                                                      //   input,    width = 1,       src.ready
		.src_valid          (router_002_src_valid),                                                      //  output,    width = 1,          .valid
		.src_data           (router_002_src_data),                                                       //  output,  width = 100,          .data
		.src_channel        (router_002_src_channel),                                                    //  output,    width = 6,          .channel
		.src_startofpacket  (router_002_src_startofpacket),                                              //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                                                 //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_router_191_eyt5dgy router_003 (
		.sink_ready         (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_valid),         //   input,    width = 1,          .valid
		.sink_data          (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_data),          //   input,  width = 100,          .data
		.sink_startofpacket (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (traffic_controller_ch_4_5_avalon_universal_slave_0_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (mac_clk_clk_clk),                                                           //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),             //   input,    width = 1, clk_reset.reset
		.src_ready          (router_003_src_ready),                                                      //   input,    width = 1,       src.ready
		.src_valid          (router_003_src_valid),                                                      //  output,    width = 1,          .valid
		.src_data           (router_003_src_data),                                                       //  output,  width = 100,          .data
		.src_channel        (router_003_src_channel),                                                    //  output,    width = 6,          .channel
		.src_startofpacket  (router_003_src_startofpacket),                                              //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                                                 //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_router_191_eyt5dgy router_004 (
		.sink_ready         (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_valid),         //   input,    width = 1,          .valid
		.sink_data          (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_data),          //   input,  width = 100,          .data
		.sink_startofpacket (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (traffic_controller_ch_6_7_avalon_universal_slave_0_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (mac_clk_clk_clk),                                                           //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),             //   input,    width = 1, clk_reset.reset
		.src_ready          (router_004_src_ready),                                                      //   input,    width = 1,       src.ready
		.src_valid          (router_004_src_valid),                                                      //  output,    width = 1,          .valid
		.src_data           (router_004_src_data),                                                       //  output,  width = 100,          .data
		.src_channel        (router_004_src_channel),                                                    //  output,    width = 6,          .channel
		.src_startofpacket  (router_004_src_startofpacket),                                              //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                                                 //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_router_191_eyt5dgy router_005 (
		.sink_ready         (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_valid),         //   input,    width = 1,          .valid
		.sink_data          (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_data),          //   input,  width = 100,          .data
		.sink_startofpacket (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (traffic_controller_ch_8_9_avalon_universal_slave_0_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (mac_clk_clk_clk),                                                           //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),             //   input,    width = 1, clk_reset.reset
		.src_ready          (router_005_src_ready),                                                      //   input,    width = 1,       src.ready
		.src_valid          (router_005_src_valid),                                                      //  output,    width = 1,          .valid
		.src_data           (router_005_src_data),                                                       //  output,  width = 100,          .data
		.src_channel        (router_005_src_channel),                                                    //  output,    width = 6,          .channel
		.src_startofpacket  (router_005_src_startofpacket),                                              //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_005_src_endofpacket)                                                 //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_router_191_eyt5dgy router_006 (
		.sink_ready         (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_valid),         //   input,    width = 1,          .valid
		.sink_data          (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_data),          //   input,  width = 100,          .data
		.sink_startofpacket (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (traffic_controller_ch_10_11_avalon_universal_slave_0_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (mac_clk_clk_clk),                                                             //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset),               //   input,    width = 1, clk_reset.reset
		.src_ready          (router_006_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_006_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_006_src_data),                                                         //  output,  width = 100,          .data
		.src_channel        (router_006_src_channel),                                                      //  output,    width = 6,          .channel
		.src_startofpacket  (router_006_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_006_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_traffic_limiter_191_kcba44q #(
		.SYNC_RESET                (0),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.MAX_OUTSTANDING_RESPONSES (2),
		.PIPELINED                 (0),
		.ST_DATA_W                 (100),
		.ST_CHANNEL_W              (6),
		.VALID_WIDTH               (6),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.SUPPORTS_POSTED_WRITES    (1),
		.SUPPORTS_NONPOSTED_WRITES (0),
		.REORDER                   (0)
	) mm_clock_crossing_bridge_m0_limiter (
		.clk                    (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset                  (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                              //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                              //   input,    width = 1,          .valid
		.cmd_sink_data          (router_src_data),                                               //   input,  width = 100,          .data
		.cmd_sink_channel       (router_src_channel),                                            //   input,    width = 6,          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                                      //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                        //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (mm_clock_crossing_bridge_m0_limiter_cmd_src_ready),             //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (mm_clock_crossing_bridge_m0_limiter_cmd_src_data),              //  output,  width = 100,          .data
		.cmd_src_channel        (mm_clock_crossing_bridge_m0_limiter_cmd_src_channel),           //  output,    width = 6,          .channel
		.cmd_src_startofpacket  (mm_clock_crossing_bridge_m0_limiter_cmd_src_startofpacket),     //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (mm_clock_crossing_bridge_m0_limiter_cmd_src_endofpacket),       //  output,    width = 1,          .endofpacket
		.rsp_sink_ready         (rsp_mux_src_ready),                                             //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_src_valid),                                             //   input,    width = 1,          .valid
		.rsp_sink_channel       (rsp_mux_src_channel),                                           //   input,    width = 6,          .channel
		.rsp_sink_data          (rsp_mux_src_data),                                              //   input,  width = 100,          .data
		.rsp_sink_startofpacket (rsp_mux_src_startofpacket),                                     //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_src_endofpacket),                                       //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (mm_clock_crossing_bridge_m0_limiter_rsp_src_ready),             //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (mm_clock_crossing_bridge_m0_limiter_rsp_src_valid),             //  output,    width = 1,          .valid
		.rsp_src_data           (mm_clock_crossing_bridge_m0_limiter_rsp_src_data),              //  output,  width = 100,          .data
		.rsp_src_channel        (mm_clock_crossing_bridge_m0_limiter_rsp_src_channel),           //  output,    width = 6,          .channel
		.rsp_src_startofpacket  (mm_clock_crossing_bridge_m0_limiter_rsp_src_startofpacket),     //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (mm_clock_crossing_bridge_m0_limiter_rsp_src_endofpacket),       //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (mm_clock_crossing_bridge_m0_limiter_cmd_valid_data)             //  output,    width = 6, cmd_valid.data
	);

	address_decoder_top_altera_merlin_demultiplexer_191_mkj5isy cmd_demux (
		.clk                (mac_clk_clk_clk),                                               //   input,    width = 1,        clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1,  clk_reset.reset
		.sink_ready         (mm_clock_crossing_bridge_m0_limiter_cmd_src_ready),             //  output,    width = 1,       sink.ready
		.sink_channel       (mm_clock_crossing_bridge_m0_limiter_cmd_src_channel),           //   input,    width = 6,           .channel
		.sink_data          (mm_clock_crossing_bridge_m0_limiter_cmd_src_data),              //   input,  width = 100,           .data
		.sink_startofpacket (mm_clock_crossing_bridge_m0_limiter_cmd_src_startofpacket),     //   input,    width = 1,           .startofpacket
		.sink_endofpacket   (mm_clock_crossing_bridge_m0_limiter_cmd_src_endofpacket),       //   input,    width = 1,           .endofpacket
		.sink_valid         (mm_clock_crossing_bridge_m0_limiter_cmd_valid_data),            //   input,    width = 6, sink_valid.data
		.src0_ready         (cmd_demux_src0_ready),                                          //   input,    width = 1,       src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                          //  output,    width = 1,           .valid
		.src0_data          (cmd_demux_src0_data),                                           //  output,  width = 100,           .data
		.src0_channel       (cmd_demux_src0_channel),                                        //  output,    width = 6,           .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                  //  output,    width = 1,           .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                                    //  output,    width = 1,           .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                                          //   input,    width = 1,       src1.ready
		.src1_valid         (cmd_demux_src1_valid),                                          //  output,    width = 1,           .valid
		.src1_data          (cmd_demux_src1_data),                                           //  output,  width = 100,           .data
		.src1_channel       (cmd_demux_src1_channel),                                        //  output,    width = 6,           .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                                  //  output,    width = 1,           .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket),                                    //  output,    width = 1,           .endofpacket
		.src2_ready         (cmd_demux_src2_ready),                                          //   input,    width = 1,       src2.ready
		.src2_valid         (cmd_demux_src2_valid),                                          //  output,    width = 1,           .valid
		.src2_data          (cmd_demux_src2_data),                                           //  output,  width = 100,           .data
		.src2_channel       (cmd_demux_src2_channel),                                        //  output,    width = 6,           .channel
		.src2_startofpacket (cmd_demux_src2_startofpacket),                                  //  output,    width = 1,           .startofpacket
		.src2_endofpacket   (cmd_demux_src2_endofpacket),                                    //  output,    width = 1,           .endofpacket
		.src3_ready         (cmd_demux_src3_ready),                                          //   input,    width = 1,       src3.ready
		.src3_valid         (cmd_demux_src3_valid),                                          //  output,    width = 1,           .valid
		.src3_data          (cmd_demux_src3_data),                                           //  output,  width = 100,           .data
		.src3_channel       (cmd_demux_src3_channel),                                        //  output,    width = 6,           .channel
		.src3_startofpacket (cmd_demux_src3_startofpacket),                                  //  output,    width = 1,           .startofpacket
		.src3_endofpacket   (cmd_demux_src3_endofpacket),                                    //  output,    width = 1,           .endofpacket
		.src4_ready         (cmd_demux_src4_ready),                                          //   input,    width = 1,       src4.ready
		.src4_valid         (cmd_demux_src4_valid),                                          //  output,    width = 1,           .valid
		.src4_data          (cmd_demux_src4_data),                                           //  output,  width = 100,           .data
		.src4_channel       (cmd_demux_src4_channel),                                        //  output,    width = 6,           .channel
		.src4_startofpacket (cmd_demux_src4_startofpacket),                                  //  output,    width = 1,           .startofpacket
		.src4_endofpacket   (cmd_demux_src4_endofpacket),                                    //  output,    width = 1,           .endofpacket
		.src5_ready         (cmd_demux_src5_ready),                                          //   input,    width = 1,       src5.ready
		.src5_valid         (cmd_demux_src5_valid),                                          //  output,    width = 1,           .valid
		.src5_data          (cmd_demux_src5_data),                                           //  output,  width = 100,           .data
		.src5_channel       (cmd_demux_src5_channel),                                        //  output,    width = 6,           .channel
		.src5_startofpacket (cmd_demux_src5_startofpacket),                                  //  output,    width = 1,           .startofpacket
		.src5_endofpacket   (cmd_demux_src5_endofpacket)                                     //  output,    width = 1,           .endofpacket
	);

	address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy cmd_mux (
		.clk                 (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset               (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                             //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_src_valid),                                             //  output,    width = 1,          .valid
		.src_data            (cmd_mux_src_data),                                              //  output,  width = 100,          .data
		.src_channel         (cmd_mux_src_channel),                                           //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                     //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                       //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                                          //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                                          //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src0_channel),                                        //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_src0_data),                                           //   input,  width = 100,          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                                     //   input,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy cmd_mux_001 (
		.clk                 (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset               (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                                         //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_001_src_valid),                                         //  output,    width = 1,          .valid
		.src_data            (cmd_mux_001_src_data),                                          //  output,  width = 100,          .data
		.src_channel         (cmd_mux_001_src_channel),                                       //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                                 //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                                   //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src1_ready),                                          //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src1_valid),                                          //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src1_channel),                                        //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_src1_data),                                           //   input,  width = 100,          .data
		.sink0_startofpacket (cmd_demux_src1_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src1_endofpacket)                                     //   input,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy cmd_mux_002 (
		.clk                 (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset               (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                                         //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_002_src_valid),                                         //  output,    width = 1,          .valid
		.src_data            (cmd_mux_002_src_data),                                          //  output,  width = 100,          .data
		.src_channel         (cmd_mux_002_src_channel),                                       //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),                                 //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),                                   //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src2_ready),                                          //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src2_valid),                                          //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src2_channel),                                        //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_src2_data),                                           //   input,  width = 100,          .data
		.sink0_startofpacket (cmd_demux_src2_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src2_endofpacket)                                     //   input,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy cmd_mux_003 (
		.clk                 (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset               (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                                         //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_003_src_valid),                                         //  output,    width = 1,          .valid
		.src_data            (cmd_mux_003_src_data),                                          //  output,  width = 100,          .data
		.src_channel         (cmd_mux_003_src_channel),                                       //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),                                 //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),                                   //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src3_ready),                                          //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src3_valid),                                          //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src3_channel),                                        //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_src3_data),                                           //   input,  width = 100,          .data
		.sink0_startofpacket (cmd_demux_src3_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src3_endofpacket)                                     //   input,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy cmd_mux_004 (
		.clk                 (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset               (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_004_src_ready),                                         //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_004_src_valid),                                         //  output,    width = 1,          .valid
		.src_data            (cmd_mux_004_src_data),                                          //  output,  width = 100,          .data
		.src_channel         (cmd_mux_004_src_channel),                                       //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_004_src_startofpacket),                                 //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_004_src_endofpacket),                                   //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src4_ready),                                          //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src4_valid),                                          //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src4_channel),                                        //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_src4_data),                                           //   input,  width = 100,          .data
		.sink0_startofpacket (cmd_demux_src4_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src4_endofpacket)                                     //   input,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy cmd_mux_005 (
		.clk                 (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset               (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_005_src_ready),                                         //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_005_src_valid),                                         //  output,    width = 1,          .valid
		.src_data            (cmd_mux_005_src_data),                                          //  output,  width = 100,          .data
		.src_channel         (cmd_mux_005_src_channel),                                       //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_005_src_startofpacket),                                 //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_005_src_endofpacket),                                   //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src5_ready),                                          //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src5_valid),                                          //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src5_channel),                                        //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_src5_data),                                           //   input,  width = 100,          .data
		.sink0_startofpacket (cmd_demux_src5_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src5_endofpacket)                                     //   input,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa rsp_demux (
		.clk                (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_001_src_ready),                                          //  output,    width = 1,      sink.ready
		.sink_channel       (router_001_src_channel),                                        //   input,    width = 6,          .channel
		.sink_data          (router_001_src_data),                                           //   input,  width = 100,          .data
		.sink_startofpacket (router_001_src_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                                    //   input,    width = 1,          .endofpacket
		.sink_valid         (router_001_src_valid),                                          //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_src0_ready),                                          //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                          //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_src0_data),                                           //  output,  width = 100,          .data
		.src0_channel       (rsp_demux_src0_channel),                                        //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                  //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                                     //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa rsp_demux_001 (
		.clk                (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_002_src_ready),                                          //  output,    width = 1,      sink.ready
		.sink_channel       (router_002_src_channel),                                        //   input,    width = 6,          .channel
		.sink_data          (router_002_src_data),                                           //   input,  width = 100,          .data
		.sink_startofpacket (router_002_src_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                                    //   input,    width = 1,          .endofpacket
		.sink_valid         (router_002_src_valid),                                          //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                                      //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                                      //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_001_src0_data),                                       //  output,  width = 100,          .data
		.src0_channel       (rsp_demux_001_src0_channel),                                    //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                              //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)                                 //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa rsp_demux_002 (
		.clk                (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_003_src_ready),                                          //  output,    width = 1,      sink.ready
		.sink_channel       (router_003_src_channel),                                        //   input,    width = 6,          .channel
		.sink_data          (router_003_src_data),                                           //   input,  width = 100,          .data
		.sink_startofpacket (router_003_src_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_003_src_endofpacket),                                    //   input,    width = 1,          .endofpacket
		.sink_valid         (router_003_src_valid),                                          //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                                      //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                                      //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_002_src0_data),                                       //  output,  width = 100,          .data
		.src0_channel       (rsp_demux_002_src0_channel),                                    //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),                              //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket)                                 //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa rsp_demux_003 (
		.clk                (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_004_src_ready),                                          //  output,    width = 1,      sink.ready
		.sink_channel       (router_004_src_channel),                                        //   input,    width = 6,          .channel
		.sink_data          (router_004_src_data),                                           //   input,  width = 100,          .data
		.sink_startofpacket (router_004_src_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_004_src_endofpacket),                                    //   input,    width = 1,          .endofpacket
		.sink_valid         (router_004_src_valid),                                          //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                                      //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                                      //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_003_src0_data),                                       //  output,  width = 100,          .data
		.src0_channel       (rsp_demux_003_src0_channel),                                    //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),                              //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket)                                 //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa rsp_demux_004 (
		.clk                (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_005_src_ready),                                          //  output,    width = 1,      sink.ready
		.sink_channel       (router_005_src_channel),                                        //   input,    width = 6,          .channel
		.sink_data          (router_005_src_data),                                           //   input,  width = 100,          .data
		.sink_startofpacket (router_005_src_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_005_src_endofpacket),                                    //   input,    width = 1,          .endofpacket
		.sink_valid         (router_005_src_valid),                                          //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_004_src0_ready),                                      //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_004_src0_valid),                                      //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_004_src0_data),                                       //  output,  width = 100,          .data
		.src0_channel       (rsp_demux_004_src0_channel),                                    //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_004_src0_startofpacket),                              //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_004_src0_endofpacket)                                 //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa rsp_demux_005 (
		.clk                (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset              (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_006_src_ready),                                          //  output,    width = 1,      sink.ready
		.sink_channel       (router_006_src_channel),                                        //   input,    width = 6,          .channel
		.sink_data          (router_006_src_data),                                           //   input,  width = 100,          .data
		.sink_startofpacket (router_006_src_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_006_src_endofpacket),                                    //   input,    width = 1,          .endofpacket
		.sink_valid         (router_006_src_valid),                                          //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_005_src0_ready),                                      //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_005_src0_valid),                                      //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_005_src0_data),                                       //  output,  width = 100,          .data
		.src0_channel       (rsp_demux_005_src0_channel),                                    //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_005_src0_startofpacket),                              //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_005_src0_endofpacket)                                 //  output,    width = 1,          .endofpacket
	);

	address_decoder_top_altera_merlin_multiplexer_191_hkbv22i rsp_mux (
		.clk                 (mac_clk_clk_clk),                                               //   input,    width = 1,       clk.clk
		.reset               (mm_clock_crossing_bridge_m0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                             //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_src_valid),                                             //  output,    width = 1,          .valid
		.src_data            (rsp_mux_src_data),                                              //  output,  width = 100,          .data
		.src_channel         (rsp_mux_src_channel),                                           //  output,    width = 6,          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                     //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                       //  output,    width = 1,          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                                          //  output,    width = 1,     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                                          //   input,    width = 1,          .valid
		.sink0_channel       (rsp_demux_src0_channel),                                        //   input,    width = 6,          .channel
		.sink0_data          (rsp_demux_src0_data),                                           //   input,  width = 100,          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                                  //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket),                                    //   input,    width = 1,          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),                                      //  output,    width = 1,     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),                                      //   input,    width = 1,          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),                                    //   input,    width = 6,          .channel
		.sink1_data          (rsp_demux_001_src0_data),                                       //   input,  width = 100,          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),                              //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket),                                //   input,    width = 1,          .endofpacket
		.sink2_ready         (rsp_demux_002_src0_ready),                                      //  output,    width = 1,     sink2.ready
		.sink2_valid         (rsp_demux_002_src0_valid),                                      //   input,    width = 1,          .valid
		.sink2_channel       (rsp_demux_002_src0_channel),                                    //   input,    width = 6,          .channel
		.sink2_data          (rsp_demux_002_src0_data),                                       //   input,  width = 100,          .data
		.sink2_startofpacket (rsp_demux_002_src0_startofpacket),                              //   input,    width = 1,          .startofpacket
		.sink2_endofpacket   (rsp_demux_002_src0_endofpacket),                                //   input,    width = 1,          .endofpacket
		.sink3_ready         (rsp_demux_003_src0_ready),                                      //  output,    width = 1,     sink3.ready
		.sink3_valid         (rsp_demux_003_src0_valid),                                      //   input,    width = 1,          .valid
		.sink3_channel       (rsp_demux_003_src0_channel),                                    //   input,    width = 6,          .channel
		.sink3_data          (rsp_demux_003_src0_data),                                       //   input,  width = 100,          .data
		.sink3_startofpacket (rsp_demux_003_src0_startofpacket),                              //   input,    width = 1,          .startofpacket
		.sink3_endofpacket   (rsp_demux_003_src0_endofpacket),                                //   input,    width = 1,          .endofpacket
		.sink4_ready         (rsp_demux_004_src0_ready),                                      //  output,    width = 1,     sink4.ready
		.sink4_valid         (rsp_demux_004_src0_valid),                                      //   input,    width = 1,          .valid
		.sink4_channel       (rsp_demux_004_src0_channel),                                    //   input,    width = 6,          .channel
		.sink4_data          (rsp_demux_004_src0_data),                                       //   input,  width = 100,          .data
		.sink4_startofpacket (rsp_demux_004_src0_startofpacket),                              //   input,    width = 1,          .startofpacket
		.sink4_endofpacket   (rsp_demux_004_src0_endofpacket),                                //   input,    width = 1,          .endofpacket
		.sink5_ready         (rsp_demux_005_src0_ready),                                      //  output,    width = 1,     sink5.ready
		.sink5_valid         (rsp_demux_005_src0_valid),                                      //   input,    width = 1,          .valid
		.sink5_channel       (rsp_demux_005_src0_channel),                                    //   input,    width = 6,          .channel
		.sink5_data          (rsp_demux_005_src0_data),                                       //   input,  width = 100,          .data
		.sink5_startofpacket (rsp_demux_005_src0_startofpacket),                              //   input,    width = 1,          .startofpacket
		.sink5_endofpacket   (rsp_demux_005_src0_endofpacket)                                 //   input,    width = 1,          .endofpacket
	);

endmodule
