-- address_decoder_top_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi.vhd

-- Generated using ACDS version 19.4 64

library IEEE;
library alt_hiconnect_sc_fifo_191;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity address_decoder_top_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi is
	generic (
		IMPL                  : string  := "reg";
		SYMBOLS_PER_BEAT      : integer := 1;
		BITS_PER_SYMBOL       : integer := 3;
		FIFO_DEPTH            : integer := 2;
		CHANNEL_WIDTH         : integer := 0;
		ERROR_WIDTH           : integer := 0;
		USE_PACKETS           : integer := 0;
		EMPTY_LATENCY         : integer := 1;
		ALMOST_FULL_THRESHOLD : integer := 2;
		SHOWAHEAD             : integer := 1
	);
	port (
		clk       : in  std_logic                    := '0';             --       clk.clk
		reset     : in  std_logic                    := '0';             -- clk_reset.reset
		in_data   : in  std_logic_vector(2 downto 0) := (others => '0'); --        in.data
		in_valid  : in  std_logic                    := '0';             --          .valid
		in_ready  : out std_logic;                                       --          .ready
		out_data  : out std_logic_vector(2 downto 0);                    --       out.data
		out_valid : out std_logic;                                       --          .valid
		out_ready : in  std_logic                    := '0'              --          .ready
	);
end entity address_decoder_top_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi;

architecture rtl of address_decoder_top_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi is
	component address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq_cmp is
		generic (
			IMPL                  : string  := "infer";
			SYMBOLS_PER_BEAT      : integer := 1;
			BITS_PER_SYMBOL       : integer := 8;
			FIFO_DEPTH            : integer := 16;
			CHANNEL_WIDTH         : integer := 0;
			ERROR_WIDTH           : integer := 0;
			USE_PACKETS           : integer := 0;
			EMPTY_LATENCY         : integer := 3;
			ALMOST_FULL_THRESHOLD : integer := 12;
			SHOWAHEAD             : integer := 1
		);
		port (
			clk               : in  std_logic                    := 'X';             -- clk
			reset             : in  std_logic                    := 'X';             -- reset
			in_data           : in  std_logic_vector(2 downto 0) := (others => 'X'); -- data
			in_valid          : in  std_logic                    := 'X';             -- valid
			in_ready          : out std_logic;                                       -- ready
			out_data          : out std_logic_vector(2 downto 0);                    -- data
			out_valid         : out std_logic;                                       -- valid
			out_ready         : in  std_logic                    := 'X';             -- ready
			in_startofpacket  : in  std_logic                    := 'X';             -- startofpacket
			in_endofpacket    : in  std_logic                    := 'X';             -- endofpacket
			out_startofpacket : out std_logic;                                       -- startofpacket
			out_endofpacket   : out std_logic;                                       -- endofpacket
			in_empty          : in  std_logic_vector(0 downto 0) := (others => 'X'); -- empty
			out_empty         : out std_logic_vector(0 downto 0);                    -- empty
			in_error          : in  std_logic_vector(0 downto 0) := (others => 'X'); -- error
			out_error         : out std_logic_vector(0 downto 0);                    -- error
			in_channel        : in  std_logic_vector(0 downto 0) := (others => 'X'); -- channel
			out_channel       : out std_logic_vector(0 downto 0)                     -- channel
		);
	end component address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq_cmp;

	for my_alt_hiconnect_sc_fifo_dest_id_fifo : address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq_cmp
		use entity alt_hiconnect_sc_fifo_191.address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq;
begin

	my_alt_hiconnect_sc_fifo_dest_id_fifo : component address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq_cmp
		generic map (
			IMPL                  => IMPL,
			SYMBOLS_PER_BEAT      => SYMBOLS_PER_BEAT,
			BITS_PER_SYMBOL       => BITS_PER_SYMBOL,
			FIFO_DEPTH            => FIFO_DEPTH,
			CHANNEL_WIDTH         => CHANNEL_WIDTH,
			ERROR_WIDTH           => ERROR_WIDTH,
			USE_PACKETS           => USE_PACKETS,
			EMPTY_LATENCY         => EMPTY_LATENCY,
			ALMOST_FULL_THRESHOLD => ALMOST_FULL_THRESHOLD,
			SHOWAHEAD             => SHOWAHEAD
		)
		port map (
			clk               => clk,       --       clk.clk
			reset             => reset,     -- clk_reset.reset
			in_data           => in_data,   --        in.data
			in_valid          => in_valid,  --          .valid
			in_ready          => in_ready,  --          .ready
			out_data          => out_data,  --       out.data
			out_valid         => out_valid, --          .valid
			out_ready         => out_ready, --          .ready
			in_startofpacket  => '0',       -- (terminated)
			in_endofpacket    => '0',       -- (terminated)
			out_startofpacket => open,      -- (terminated)
			out_endofpacket   => open,      -- (terminated)
			in_empty          => "0",       -- (terminated)
			out_empty         => open,      -- (terminated)
			in_error          => "0",       -- (terminated)
			out_error         => open,      -- (terminated)
			in_channel        => "0",       -- (terminated)
			out_channel       => open       -- (terminated)
		);

end architecture rtl; -- of address_decoder_top_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi
