{ 
  "configurations" : [
    { 
      "name" : "0",
      "parameters" :{
        "aib_clk1_sel" : "aib_clk1_pld_pcs_rx_clk_out",
        "aib_clk2_sel" : "aib_clk2_pld_pma_clkdiv_rx_user",
        "hdpldadapt_aib_fabric_pld_pma_hclk_hz" : "31'd0",
        "hdpldadapt_aib_fabric_rx_transfer_clk_hz" : "31'd644531250",
        "asn_bypass_pma_pcie_sw_done" : "disable",
        "asn_wait_for_dll_reset_cnt" : "8'd64",
        "asn_wait_for_fifo_flush_cnt" : "8'd64",
        "asn_wait_for_pma_pcie_sw_done_cnt" : "8'd64",
        "bonding_dft_en" : "dft_dis",
        "bonding_dft_val" : "dft_0",
        "chnl_bonding" : "disable",
        "clock_del_measure_enable" : "disable",
        "hdpldadapt_csr_clk_hz" : "31'd0",
        "ctrl_plane_bonding" : "individual",
        "ds_bypass_pipeln" : "ds_bypass_pipeln_dis",
        "duplex_mode" : "enable",
        "dv_mode" : "dv_mode_dis",
        "fifo_double_read" : "fifo_double_read_en",
        "fifo_mode" : "phase_comp",
        "fifo_rd_clk_ins_sm_scg_en" : "enable",
        "fifo_rd_clk_scg_en" : "disable",
        "fifo_rd_clk_sel" : "fifo_rd_clk_pld_rx_clk1",
        "fifo_stop_rd" : "rd_empty",
        "fifo_stop_wr" : "n_wr_full",
        "fifo_width" : "fifo_double_width",
        "fifo_wr_clk_del_sm_scg_en" : "enable",
        "fifo_wr_clk_scg_en" : "disable",
        "fifo_wr_clk_sel" : "fifo_wr_clk_rx_transfer_clk",
        "free_run_div_clk" : "out_of_reset_sync",
        "fsr_pld_10g_rx_crc32_err_rst_val" : "reset_to_zero_crc32",
        "fsr_pld_8g_sigdet_out_rst_val" : "reset_to_zero_sigdet",
        "fsr_pld_ltd_b_rst_val" : "reset_to_one_ltdb",
        "fsr_pld_ltr_rst_val" : "reset_to_zero_ltr",
        "fsr_pld_rx_fifo_align_clr_rst_val" : "reset_to_zero_alignclr",
        "gb_rx_idwidth" : "idwidth_32",
        "gb_rx_odwidth" : "odwidth_66",
        "hip_mode" : "disable_hip",
        "hrdrst_align_bypass" : "enable",
        "hrdrst_dll_lock_bypass" : "disable",
        "hrdrst_rx_osc_clk_scg_en" : "disable",
        "hrdrst_user_ctl_en" : "disable",
        "indv" : "indv_en",
        "internal_clk1_sel1" : "pma_clks_or_txfiford_post_ct_mux_clk1_mux1",
        "internal_clk1_sel2" : "pma_clks_clk1_mux2",
        "internal_clk2_sel1" : "pma_clks_or_rxfifowr_post_ct_mux_clk2_mux1",
        "internal_clk2_sel2" : "pma_clks_clk2_mux2",
        "loopback_mode" : "disable",
        "low_latency_en" : "disable",
        "lpbk_mode" : "disable",
        "osc_clk_scg_en" : "disable",
        "phcomp_rd_del" : "phcomp_rd_del2",
        "pipe_enable" : "disable",
        "pipe_mode" : "disable_pipe",
        "hdpldadapt_pld_avmm1_clk_rowclk_hz" : "31'd0",
        "hdpldadapt_pld_avmm2_clk_rowclk_hz" : "31'd0",
        "pld_clk1_delay_en" : "enable",
        "pld_clk1_delay_sel" : "delay_path13",
        "pld_clk1_inv_en" : "disable",
        "hdpldadapt_pld_rx_clk1_dcm_hz" : "31'd156250000",
        "hdpldadapt_pld_rx_clk1_rowclk_hz" : "31'd156250000",
        "hdpldadapt_pld_sclk1_rowclk_hz" : "31'd0",
        "hdpldadapt_pld_sclk2_rowclk_hz" : "31'd0",
        "pma_hclk_scg_en" : "enable",
        "powerdown_mode" : "powerup",
        "rx_datapath_tb_sel" : "cp_bond",
        "rx_fastbond_rden" : "rden_ds_fast_us_fast",
        "rx_fastbond_wren" : "wren_ds_del_us_del",
        "rx_fifo_power_mode" : "full_width_ps_dw",
        "rx_fifo_read_latency_adjust" : "disable",
        "rx_fifo_write_ctrl" : "blklock_ignore",
        "rx_fifo_write_latency_adjust" : "disable",
        "rx_osc_clock_setting" : "osc_clk_div_by1",
        "rx_pld_8g_eidleinfersel_polling_bypass" : "disable",
        "rx_pld_pma_eye_monitor_polling_bypass" : "disable",
        "rx_pld_pma_pcie_switch_polling_bypass" : "disable",
        "rx_pld_pma_reser_out_polling_bypass" : "disable",
        "rx_prbs_flags_sr_enable" : "disable",
        "rx_true_b2b" : "b2b",
        "rx_usertest_sel" : "enable",
        "rxfifo_empty" : "empty_dw",
        "rxfifo_full" : "full_pc_dw",
        "rxfifo_mode" : "rxphase_comp",
        "rxfifo_pempty" : "6'd2",
        "rxfifo_pfull" : "6'd10",
        "rxfiford_post_ct_sel" : "rxfiford_sclk_post_ct",
        "rxfifowr_post_ct_sel" : "rxfifowr_sclk_post_ct",
        "sclk_sel" : "sclk1_rowclk",
        "hdpldadapt_speed_grade" : "dash_2",
        "stretch_num_stages" : "four_stage",
        "sup_mode" : "user_mode",
        "txfiford_post_ct_sel" : "txfiford_sclk_post_ct",
        "txfifowr_post_ct_sel" : "txfifowr_sclk_post_ct",
        "us_bypass_pipeln" : "us_bypass_pipeln_dis",
        "word_align" : "wa_en",
        "word_align_enable" : "enable",
        "silicon_rev" : "14nm5bcr2eb"
      }
    }
  ]
}

