<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
  <spirit:vendor>Intel Corporation</spirit:vendor>
  <spirit:library>address_decoder_channel_csr_clk</spirit:library>
  <spirit:name>csr_clk</spirit:name>
  <spirit:version>17.1</spirit:version>
  <spirit:busInterfaces>
    <spirit:busInterface>
      <spirit:name>clk</spirit:name>
      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="17.1"></spirit:busType>
      <spirit:master></spirit:master>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>clk</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>clk_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>associatedDirectClock</spirit:name>
          <spirit:displayName>Associated direct clock</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="associatedDirectClock">clk_in</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>clockRate</spirit:name>
          <spirit:displayName>Clock rate</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="clockRate">125000000</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>clockRateKnown</spirit:name>
          <spirit:displayName>Clock rate known</spirit:displayName>
          <spirit:value spirit:format="bool" spirit:id="clockRateKnown">true</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>externallyDriven</spirit:name>
          <spirit:displayName>Externally driven</spirit:displayName>
          <spirit:value spirit:format="bool" spirit:id="externallyDriven">true</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ptfSchematicName</spirit:name>
          <spirit:displayName>PTF schematic name</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>clk_in</spirit:name>
      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="17.1"></spirit:busType>
      <spirit:slave></spirit:slave>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>clk</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>in_clk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>clockRate</spirit:name>
          <spirit:displayName>Clock rate</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="clockRate">125000000</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>externallyDriven</spirit:name>
          <spirit:displayName>Externally driven</spirit:displayName>
          <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ptfSchematicName</spirit:name>
          <spirit:displayName>PTF schematic name</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <altera:altera_assignments>
          <spirit:parameters>
            <spirit:parameter>
              <spirit:name>qsys.ui.export_name</spirit:name>
              <spirit:value spirit:format="string" spirit:id="qsys.ui.export_name">clk</spirit:value>
            </spirit:parameter>
          </spirit:parameters>
        </altera:altera_assignments>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>clk_in_reset</spirit:name>
      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="17.1"></spirit:busType>
      <spirit:slave></spirit:slave>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>reset_n</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>reset_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>associatedClock</spirit:name>
          <spirit:displayName>Associated clock</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>synchronousEdges</spirit:name>
          <spirit:displayName>Synchronous edges</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="synchronousEdges">NONE</spirit:value>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <altera:altera_assignments>
          <spirit:parameters>
            <spirit:parameter>
              <spirit:name>qsys.ui.export_name</spirit:name>
              <spirit:value spirit:format="string" spirit:id="qsys.ui.export_name">reset</spirit:value>
            </spirit:parameter>
          </spirit:parameters>
        </altera:altera_assignments>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>clk_reset</spirit:name>
      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="17.1"></spirit:busType>
      <spirit:master></spirit:master>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>reset_n</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>reset_n_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>associatedClock</spirit:name>
          <spirit:displayName>Associated clock</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>associatedDirectReset</spirit:name>
          <spirit:displayName>Associated direct reset</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="associatedDirectReset">clk_in_reset</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>associatedResetSinks</spirit:name>
          <spirit:displayName>Associated reset sinks</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="associatedResetSinks">clk_in_reset</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>synchronousEdges</spirit:name>
          <spirit:displayName>Synchronous edges</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="synchronousEdges">NONE</spirit:value>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
  </spirit:busInterfaces>
  <spirit:model>
    <spirit:views>
      <spirit:view>
        <spirit:name>QUARTUS_SYNTH</spirit:name>
        <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
        <spirit:modelName>clock_source</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>QUARTUS_SYNTH</spirit:localName>
        </spirit:fileSetRef>
      </spirit:view>
    </spirit:views>
    <spirit:ports>
      <spirit:port>
        <spirit:name>in_clk</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>reset_n</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>reset_n_out</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
    </spirit:ports>
  </spirit:model>
  <spirit:vendorExtensions>
    <altera:entity_info>
      <spirit:vendor>Intel Corporation</spirit:vendor>
      <spirit:library>address_decoder_channel_csr_clk</spirit:library>
      <spirit:name>clock_source</spirit:name>
      <spirit:version>17.1</spirit:version>
    </altera:entity_info>
    <altera:altera_module_parameters>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>clockFrequency</spirit:name>
          <spirit:displayName>Clock frequency</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="clockFrequency">125000000</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>clockFrequencyKnown</spirit:name>
          <spirit:displayName>Clock frequency is known</spirit:displayName>
          <spirit:value spirit:format="bool" spirit:id="clockFrequencyKnown">true</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>inputClockFrequency</spirit:name>
          <spirit:displayName>inputClockFrequency</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="inputClockFrequency">0</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>resetSynchronousEdges</spirit:name>
          <spirit:displayName>Reset synchronous edges</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="resetSynchronousEdges">NONE</spirit:value>
        </spirit:parameter>
      </spirit:parameters>
    </altera:altera_module_parameters>
    <altera:altera_system_parameters>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>device</spirit:name>
          <spirit:displayName>Device</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="device">1SG280LN3F43E3VGS1</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>deviceFamily</spirit:name>
          <spirit:displayName>Device family</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="deviceFamily">Stratix 10</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>deviceSpeedGrade</spirit:name>
          <spirit:displayName>Device Speed Grade</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">3</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>bonusData</spirit:name>
          <spirit:displayName>bonusData</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="bonusData">bonusData 
{
}
</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>hideFromIPCatalog</spirit:name>
          <spirit:displayName>Hide from IP Catalog</spirit:displayName>
          <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>lockedInterfaceDefinition</spirit:name>
          <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
    <interfaces>
        <interface>
            <name>clk</name>
            <type>clock</type>
            <isStart>true</isStart>
            <ports>
                <port>
                    <name>clk_out</name>
                    <role>clk</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedDirectClock</key>
                        <value>clk_in</value>
                    </entry>
                    <entry>
                        <key>clockRate</key>
                        <value>125000000</value>
                    </entry>
                    <entry>
                        <key>clockRateKnown</key>
                        <value>true</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>true</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>clk_in</name>
            <type>clock</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>in_clk</name>
                    <role>clk</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>qsys.ui.export_name</key>
                        <value>clk</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>clockRate</key>
                        <value>125000000</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>clk_in_reset</name>
            <type>reset</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>reset_n</name>
                    <role>reset_n</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>qsys.ui.export_name</key>
                        <value>reset</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                    </entry>
                    <entry>
                        <key>synchronousEdges</key>
                        <value>NONE</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>clk_reset</name>
            <type>reset</type>
            <isStart>true</isStart>
            <ports>
                <port>
                    <name>reset_n_out</name>
                    <role>reset_n</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                    </entry>
                    <entry>
                        <key>associatedDirectReset</key>
                        <value>clk_in_reset</value>
                    </entry>
                    <entry>
                        <key>associatedResetSinks</key>
                        <value>clk_in_reset</value>
                    </entry>
                    <entry>
                        <key>synchronousEdges</key>
                        <value>NONE</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
    </interfaces>
</boundaryDefinition>]]></spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>systemInfos</spirit:name>
          <spirit:displayName>systemInfos</spirit:displayName>
          <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
    <connPtSystemInfos>
        <entry>
            <key>clk</key>
            <value>
                <connectionPointName>clk</connectionPointName>
                <suppliedSystemInfos/>
                <consumedSystemInfos>
                    <entry>
                        <key>CLOCK_RATE</key>
                        <value>125000000</value>
                    </entry>
                </consumedSystemInfos>
            </value>
        </entry>
        <entry>
            <key>clk_in</key>
            <value>
                <connectionPointName>clk_in</connectionPointName>
                <suppliedSystemInfos>
                    <entry>
                        <key>CLOCK_RATE</key>
                        <value>0</value>
                    </entry>
                </suppliedSystemInfos>
                <consumedSystemInfos/>
            </value>
        </entry>
    </connPtSystemInfos>
</systemInfosDefinition>]]></spirit:value>
        </spirit:parameter>
      </spirit:parameters>
    </altera:altera_system_parameters>
    <altera:altera_interface_boundary>
      <altera:interface_mapping altera:name="clk" altera:internal="csr_clk.clk" altera:type="clock" altera:dir="start">
        <altera:port_mapping altera:name="clk_out" altera:internal="clk_out"></altera:port_mapping>
      </altera:interface_mapping>
      <altera:interface_mapping altera:name="clk_in" altera:internal="csr_clk.clk_in" altera:type="clock" altera:dir="end">
        <altera:port_mapping altera:name="in_clk" altera:internal="in_clk"></altera:port_mapping>
      </altera:interface_mapping>
      <altera:interface_mapping altera:name="clk_in_reset" altera:internal="csr_clk.clk_in_reset" altera:type="reset" altera:dir="end">
        <altera:port_mapping altera:name="reset_n" altera:internal="reset_n"></altera:port_mapping>
      </altera:interface_mapping>
      <altera:interface_mapping altera:name="clk_reset" altera:internal="csr_clk.clk_reset" altera:type="reset" altera:dir="start">
        <altera:port_mapping altera:name="reset_n_out" altera:internal="reset_n_out"></altera:port_mapping>
      </altera:interface_mapping>
    </altera:altera_interface_boundary>
    <altera:altera_has_warnings>false</altera:altera_has_warnings>
    <altera:altera_has_errors>false</altera:altera_has_errors>
  </spirit:vendorExtensions>
</spirit:component>
