// address_decoder_channel_csr_clk.v

// Generated using ACDS version 19.4 64

`timescale 1 ps / 1 ps
module address_decoder_channel_csr_clk (
		input  wire  in_clk,      //       clk_in.clk
		input  wire  reset_n,     // clk_in_reset.reset_n
		output wire  clk_out,     //          clk.clk
		output wire  reset_n_out  //    clk_reset.reset_n
	);

	assign clk_out = in_clk;

	assign reset_n_out = reset_n;

endmodule
