-- alt_usxgmii_phy.vhd

-- Generated using ACDS version 19.4 64

library IEEE;
library alt_mge_phy_1930;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity alt_usxgmii_phy is
	port (
		csr_clk              : in  std_logic                     := '0';             --              csr_clk.clk
		xgmii_rx_coreclkin   : in  std_logic                     := '0';             --   xgmii_rx_coreclkin.clk
		xgmii_tx_coreclkin   : in  std_logic                     := '0';             --   xgmii_tx_coreclkin.clk
		reset                : in  std_logic                     := '0';             --                reset.reset
		rx_digitalreset      : in  std_logic                     := '0';             --      rx_digitalreset.rx_digitalreset
		tx_digitalreset      : in  std_logic                     := '0';             --      tx_digitalreset.tx_digitalreset
		csr_readdata         : out std_logic_vector(31 downto 0);                    --        avalon_mm_csr.readdata
		csr_writedata        : in  std_logic_vector(31 downto 0) := (others => '0'); --                     .writedata
		csr_address          : in  std_logic_vector(10 downto 0) := (others => '0'); --                     .address
		csr_waitrequest      : out std_logic;                                        --                     .waitrequest
		csr_read             : in  std_logic                     := '0';             --                     .read
		csr_write            : in  std_logic                     := '0';             --                     .write
		xgmii_tx_valid       : in  std_logic                     := '0';             --       xgmii_tx_valid.export
		xgmii_tx_control     : in  std_logic_vector(3 downto 0)  := (others => '0'); --     xgmii_tx_control.export
		xgmii_tx_data        : in  std_logic_vector(31 downto 0) := (others => '0'); --        xgmii_tx_data.export
		xgmii_rx_valid       : out std_logic;                                        --       xgmii_rx_valid.export
		xgmii_rx_control     : out std_logic_vector(3 downto 0);                     --     xgmii_rx_control.export
		xgmii_rx_data        : out std_logic_vector(31 downto 0);                    --        xgmii_rx_data.export
		led_an               : out std_logic;                                        --               led_an.export
		rx_block_lock        : out std_logic;                                        --        rx_block_lock.rx_enh_blk_lock
		operating_speed      : out std_logic_vector(2 downto 0);                     --      operating_speed.export
		tx_serial_clk        : in  std_logic_vector(0 downto 0)  := (others => '0'); --        tx_serial_clk.clk
		rx_cdr_refclk_1      : in  std_logic                     := '0';             --      rx_cdr_refclk_1.clk
		rx_pma_clkout        : out std_logic;                                        --        rx_pma_clkout.clk
		tx_analogreset       : in  std_logic_vector(0 downto 0)  := (others => '0'); --       tx_analogreset.tx_analogreset
		rx_analogreset       : in  std_logic_vector(0 downto 0)  := (others => '0'); --       rx_analogreset.rx_analogreset
		tx_analogreset_stat  : out std_logic_vector(0 downto 0);                     --  tx_analogreset_stat.tx_analogreset_stat
		rx_analogreset_stat  : out std_logic_vector(0 downto 0);                     --  rx_analogreset_stat.rx_analogreset_stat
		tx_digitalreset_stat : out std_logic_vector(0 downto 0);                     -- tx_digitalreset_stat.tx_digitalreset_stat
		rx_digitalreset_stat : out std_logic_vector(0 downto 0);                     -- rx_digitalreset_stat.rx_digitalreset_stat
		tx_cal_busy          : out std_logic_vector(0 downto 0);                     --          tx_cal_busy.tx_cal_busy
		rx_cal_busy          : out std_logic_vector(0 downto 0);                     --          rx_cal_busy.rx_cal_busy
		tx_serial_data       : out std_logic_vector(0 downto 0);                     --       tx_serial_data.tx_serial_data
		rx_serial_data       : in  std_logic_vector(0 downto 0)  := (others => '0'); --       rx_serial_data.rx_serial_data
		rx_is_lockedtodata   : out std_logic_vector(0 downto 0);                     --   rx_is_lockedtodata.rx_is_lockedtodata
		reconfig_clk         : in  std_logic_vector(0 downto 0)  := (others => '0'); --         reconfig_clk.clk
		reconfig_reset       : in  std_logic_vector(0 downto 0)  := (others => '0'); --       reconfig_reset.reset
		reconfig_write       : in  std_logic_vector(0 downto 0)  := (others => '0'); --        reconfig_avmm.write
		reconfig_read        : in  std_logic_vector(0 downto 0)  := (others => '0'); --                     .read
		reconfig_address     : in  std_logic_vector(10 downto 0) := (others => '0'); --                     .address
		reconfig_writedata   : in  std_logic_vector(31 downto 0) := (others => '0'); --                     .writedata
		reconfig_readdata    : out std_logic_vector(31 downto 0);                    --                     .readdata
		reconfig_waitrequest : out std_logic_vector(0 downto 0)                      --                     .waitrequest
	);
end entity alt_usxgmii_phy;

architecture rtl of alt_usxgmii_phy is
	component alt_usxgmii_phy_alt_mge_phy_1930_yuuknna_cmp is
		port (
			csr_clk              : in  std_logic                     := 'X';             -- clk
			xgmii_rx_coreclkin   : in  std_logic                     := 'X';             -- clk
			xgmii_tx_coreclkin   : in  std_logic                     := 'X';             -- clk
			reset                : in  std_logic                     := 'X';             -- reset
			rx_digitalreset      : in  std_logic                     := 'X';             -- rx_digitalreset
			tx_digitalreset      : in  std_logic                     := 'X';             -- tx_digitalreset
			csr_readdata         : out std_logic_vector(31 downto 0);                    -- readdata
			csr_writedata        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			csr_address          : in  std_logic_vector(10 downto 0) := (others => 'X'); -- address
			csr_waitrequest      : out std_logic;                                        -- waitrequest
			csr_read             : in  std_logic                     := 'X';             -- read
			csr_write            : in  std_logic                     := 'X';             -- write
			xgmii_tx_valid       : in  std_logic                     := 'X';             -- export
			xgmii_tx_control     : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- export
			xgmii_tx_data        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
			xgmii_rx_valid       : out std_logic;                                        -- export
			xgmii_rx_control     : out std_logic_vector(3 downto 0);                     -- export
			xgmii_rx_data        : out std_logic_vector(31 downto 0);                    -- export
			led_an               : out std_logic;                                        -- export
			rx_block_lock        : out std_logic;                                        -- rx_enh_blk_lock
			operating_speed      : out std_logic_vector(2 downto 0);                     -- export
			tx_serial_clk        : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- clk
			rx_cdr_refclk_1      : in  std_logic                     := 'X';             -- clk
			rx_pma_clkout        : out std_logic;                                        -- clk
			tx_analogreset       : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- tx_analogreset
			rx_analogreset       : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_analogreset
			tx_analogreset_stat  : out std_logic_vector(0 downto 0);                     -- tx_analogreset_stat
			rx_analogreset_stat  : out std_logic_vector(0 downto 0);                     -- rx_analogreset_stat
			tx_digitalreset_stat : out std_logic_vector(0 downto 0);                     -- tx_digitalreset_stat
			rx_digitalreset_stat : out std_logic_vector(0 downto 0);                     -- rx_digitalreset_stat
			tx_cal_busy          : out std_logic_vector(0 downto 0);                     -- tx_cal_busy
			rx_cal_busy          : out std_logic_vector(0 downto 0);                     -- rx_cal_busy
			tx_serial_data       : out std_logic_vector(0 downto 0);                     -- tx_serial_data
			rx_serial_data       : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_serial_data
			rx_is_lockedtodata   : out std_logic_vector(0 downto 0);                     -- rx_is_lockedtodata
			reconfig_clk         : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- clk
			reconfig_reset       : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- reset
			reconfig_write       : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- write
			reconfig_read        : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- read
			reconfig_address     : in  std_logic_vector(10 downto 0) := (others => 'X'); -- address
			reconfig_writedata   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			reconfig_readdata    : out std_logic_vector(31 downto 0);                    -- readdata
			reconfig_waitrequest : out std_logic_vector(0 downto 0)                      -- waitrequest
		);
	end component alt_usxgmii_phy_alt_mge_phy_1930_yuuknna_cmp;

	for alt_mge_phy_0 : alt_usxgmii_phy_alt_mge_phy_1930_yuuknna_cmp
		use entity alt_mge_phy_1930.alt_usxgmii_phy_alt_mge_phy_1930_yuuknna;
begin

	alt_mge_phy_0 : component alt_usxgmii_phy_alt_mge_phy_1930_yuuknna_cmp
		port map (
			csr_clk              => csr_clk,              --              csr_clk.clk
			xgmii_rx_coreclkin   => xgmii_rx_coreclkin,   --   xgmii_rx_coreclkin.clk
			xgmii_tx_coreclkin   => xgmii_tx_coreclkin,   --   xgmii_tx_coreclkin.clk
			reset                => reset,                --                reset.reset
			rx_digitalreset      => rx_digitalreset,      --      rx_digitalreset.rx_digitalreset
			tx_digitalreset      => tx_digitalreset,      --      tx_digitalreset.tx_digitalreset
			csr_readdata         => csr_readdata,         --        avalon_mm_csr.readdata
			csr_writedata        => csr_writedata,        --                     .writedata
			csr_address          => csr_address,          --                     .address
			csr_waitrequest      => csr_waitrequest,      --                     .waitrequest
			csr_read             => csr_read,             --                     .read
			csr_write            => csr_write,            --                     .write
			xgmii_tx_valid       => xgmii_tx_valid,       --       xgmii_tx_valid.export
			xgmii_tx_control     => xgmii_tx_control,     --     xgmii_tx_control.export
			xgmii_tx_data        => xgmii_tx_data,        --        xgmii_tx_data.export
			xgmii_rx_valid       => xgmii_rx_valid,       --       xgmii_rx_valid.export
			xgmii_rx_control     => xgmii_rx_control,     --     xgmii_rx_control.export
			xgmii_rx_data        => xgmii_rx_data,        --        xgmii_rx_data.export
			led_an               => led_an,               --               led_an.export
			rx_block_lock        => rx_block_lock,        --        rx_block_lock.rx_enh_blk_lock
			operating_speed      => operating_speed,      --      operating_speed.export
			tx_serial_clk        => tx_serial_clk,        --        tx_serial_clk.clk
			rx_cdr_refclk_1      => rx_cdr_refclk_1,      --      rx_cdr_refclk_1.clk
			rx_pma_clkout        => rx_pma_clkout,        --        rx_pma_clkout.clk
			tx_analogreset       => tx_analogreset,       --       tx_analogreset.tx_analogreset
			rx_analogreset       => rx_analogreset,       --       rx_analogreset.rx_analogreset
			tx_analogreset_stat  => tx_analogreset_stat,  --  tx_analogreset_stat.tx_analogreset_stat
			rx_analogreset_stat  => rx_analogreset_stat,  --  rx_analogreset_stat.rx_analogreset_stat
			tx_digitalreset_stat => tx_digitalreset_stat, -- tx_digitalreset_stat.tx_digitalreset_stat
			rx_digitalreset_stat => rx_digitalreset_stat, -- rx_digitalreset_stat.rx_digitalreset_stat
			tx_cal_busy          => tx_cal_busy,          --          tx_cal_busy.tx_cal_busy
			rx_cal_busy          => rx_cal_busy,          --          rx_cal_busy.rx_cal_busy
			tx_serial_data       => tx_serial_data,       --       tx_serial_data.tx_serial_data
			rx_serial_data       => rx_serial_data,       --       rx_serial_data.rx_serial_data
			rx_is_lockedtodata   => rx_is_lockedtodata,   --   rx_is_lockedtodata.rx_is_lockedtodata
			reconfig_clk         => reconfig_clk,         --         reconfig_clk.clk
			reconfig_reset       => reconfig_reset,       --       reconfig_reset.reset
			reconfig_write       => reconfig_write,       --        reconfig_avmm.write
			reconfig_read        => reconfig_read,        --                     .read
			reconfig_address     => reconfig_address,     --                     .address
			reconfig_writedata   => reconfig_writedata,   --                     .writedata
			reconfig_readdata    => reconfig_readdata,    --                     .readdata
			reconfig_waitrequest => reconfig_waitrequest  --                     .waitrequest
		);

end architecture rtl; -- of alt_usxgmii_phy
