-- intel_std_18_1_dummy.vhd

-- Generated using ACDS version 18.1 646

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity intel_std_18_1_dummy is
	port (
		clk_clk                   : in  std_logic                     := '0';             --    clk.clk
		in_address                : in  std_logic_vector(31 downto 0) := (others => '0'); --     in.address
		in_waitrequest            : out std_logic;                                        --       .waitrequest
		in_burstcount             : in  std_logic_vector(3 downto 0)  := (others => '0'); --       .burstcount
		in_byteenable             : in  std_logic_vector(3 downto 0)  := (others => '0'); --       .byteenable
		in_read                   : in  std_logic                     := '0';             --       .read
		in_readdata               : out std_logic_vector(31 downto 0);                    --       .readdata
		in_readdatavalid          : out std_logic;                                        --       .readdatavalid
		in_write                  : in  std_logic                     := '0';             --       .write
		in_writedata              : in  std_logic_vector(31 downto 0) := (others => '0'); --       .writedata
		reset_reset_n             : in  std_logic                     := '0';             --  reset.reset_n
		slave0_address            : out std_logic_vector(15 downto 0);                    -- slave0.address
		slave0_write              : out std_logic;                                        --       .write
		slave0_read               : out std_logic;                                        --       .read
		slave0_readdata           : in  std_logic_vector(31 downto 0) := (others => '0'); --       .readdata
		slave0_writedata          : out std_logic_vector(31 downto 0);                    --       .writedata
		slave0_begintransfer      : out std_logic;                                        --       .begintransfer
		slave0_beginbursttransfer : out std_logic;                                        --       .beginbursttransfer
		slave0_burstcount         : out std_logic_vector(3 downto 0);                     --       .burstcount
		slave0_byteenable         : out std_logic_vector(3 downto 0);                     --       .byteenable
		slave0_readdatavalid      : in  std_logic                     := '0';             --       .readdatavalid
		slave0_waitrequest        : in  std_logic                     := '0';             --       .waitrequest
		slave1_address            : out std_logic_vector(15 downto 0);                    -- slave1.address
		slave1_write              : out std_logic;                                        --       .write
		slave1_read               : out std_logic;                                        --       .read
		slave1_readdata           : in  std_logic_vector(31 downto 0) := (others => '0'); --       .readdata
		slave1_writedata          : out std_logic_vector(31 downto 0);                    --       .writedata
		slave1_begintransfer      : out std_logic;                                        --       .begintransfer
		slave1_beginbursttransfer : out std_logic;                                        --       .beginbursttransfer
		slave1_burstcount         : out std_logic_vector(3 downto 0);                     --       .burstcount
		slave1_byteenable         : out std_logic_vector(3 downto 0);                     --       .byteenable
		slave1_readdatavalid      : in  std_logic                     := '0';             --       .readdatavalid
		slave1_waitrequest        : in  std_logic                     := '0'              --       .waitrequest
	);
end entity intel_std_18_1_dummy;

architecture rtl of intel_std_18_1_dummy is
	component altera_merlin_master_translator is
		generic (
			AV_ADDRESS_W                : integer := 32;
			AV_DATA_W                   : integer := 32;
			AV_BURSTCOUNT_W             : integer := 4;
			AV_BYTEENABLE_W             : integer := 4;
			UAV_ADDRESS_W               : integer := 38;
			UAV_BURSTCOUNT_W            : integer := 10;
			USE_READ                    : integer := 1;
			USE_WRITE                   : integer := 1;
			USE_BEGINBURSTTRANSFER      : integer := 0;
			USE_BEGINTRANSFER           : integer := 0;
			USE_CHIPSELECT              : integer := 0;
			USE_BURSTCOUNT              : integer := 1;
			USE_READDATAVALID           : integer := 1;
			USE_WAITREQUEST             : integer := 1;
			USE_READRESPONSE            : integer := 0;
			USE_WRITERESPONSE           : integer := 0;
			AV_SYMBOLS_PER_WORD         : integer := 4;
			AV_ADDRESS_SYMBOLS          : integer := 0;
			AV_BURSTCOUNT_SYMBOLS       : integer := 0;
			AV_CONSTANT_BURST_BEHAVIOR  : integer := 0;
			UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
			AV_LINEWRAPBURSTS           : integer := 0;
			AV_REGISTERINCOMINGSIGNALS  : integer := 0
		);
		port (
			clk                    : in  std_logic                     := 'X';             -- clk
			reset                  : in  std_logic                     := 'X';             -- reset
			uav_address            : out std_logic_vector(37 downto 0);                    -- address
			uav_burstcount         : out std_logic_vector(9 downto 0);                     -- burstcount
			uav_read               : out std_logic;                                        -- read
			uav_write              : out std_logic;                                        -- write
			uav_waitrequest        : in  std_logic                     := 'X';             -- waitrequest
			uav_readdatavalid      : in  std_logic                     := 'X';             -- readdatavalid
			uav_byteenable         : out std_logic_vector(3 downto 0);                     -- byteenable
			uav_readdata           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			uav_writedata          : out std_logic_vector(31 downto 0);                    -- writedata
			uav_lock               : out std_logic;                                        -- lock
			uav_debugaccess        : out std_logic;                                        -- debugaccess
			av_address             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- address
			av_waitrequest         : out std_logic;                                        -- waitrequest
			av_burstcount          : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- burstcount
			av_byteenable          : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			av_read                : in  std_logic                     := 'X';             -- read
			av_readdata            : out std_logic_vector(31 downto 0);                    -- readdata
			av_readdatavalid       : out std_logic;                                        -- readdatavalid
			av_write               : in  std_logic                     := 'X';             -- write
			av_writedata           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			av_beginbursttransfer  : in  std_logic                     := 'X';             -- beginbursttransfer
			av_begintransfer       : in  std_logic                     := 'X';             -- begintransfer
			av_chipselect          : in  std_logic                     := 'X';             -- chipselect
			av_lock                : in  std_logic                     := 'X';             -- lock
			av_debugaccess         : in  std_logic                     := 'X';             -- debugaccess
			uav_clken              : out std_logic;                                        -- clken
			av_clken               : in  std_logic                     := 'X';             -- clken
			uav_response           : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- response
			av_response            : out std_logic_vector(1 downto 0);                     -- response
			uav_writeresponsevalid : in  std_logic                     := 'X';             -- writeresponsevalid
			av_writeresponsevalid  : out std_logic                                         -- writeresponsevalid
		);
	end component altera_merlin_master_translator;

	component altera_merlin_slave_translator is
		generic (
			AV_ADDRESS_W                   : integer := 30;
			AV_DATA_W                      : integer := 32;
			UAV_DATA_W                     : integer := 32;
			AV_BURSTCOUNT_W                : integer := 4;
			AV_BYTEENABLE_W                : integer := 4;
			UAV_BYTEENABLE_W               : integer := 4;
			UAV_ADDRESS_W                  : integer := 32;
			UAV_BURSTCOUNT_W               : integer := 4;
			AV_READLATENCY                 : integer := 0;
			USE_READDATAVALID              : integer := 1;
			USE_WAITREQUEST                : integer := 1;
			USE_UAV_CLKEN                  : integer := 0;
			USE_READRESPONSE               : integer := 0;
			USE_WRITERESPONSE              : integer := 0;
			AV_SYMBOLS_PER_WORD            : integer := 4;
			AV_ADDRESS_SYMBOLS             : integer := 0;
			AV_BURSTCOUNT_SYMBOLS          : integer := 0;
			AV_CONSTANT_BURST_BEHAVIOR     : integer := 0;
			UAV_CONSTANT_BURST_BEHAVIOR    : integer := 0;
			AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
			CHIPSELECT_THROUGH_READLATENCY : integer := 0;
			AV_READ_WAIT_CYCLES            : integer := 0;
			AV_WRITE_WAIT_CYCLES           : integer := 0;
			AV_SETUP_WAIT_CYCLES           : integer := 0;
			AV_DATA_HOLD_CYCLES            : integer := 0
		);
		port (
			clk                    : in  std_logic                     := 'X';             -- clk
			reset                  : in  std_logic                     := 'X';             -- reset
			uav_address            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- address
			uav_burstcount         : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- burstcount
			uav_read               : in  std_logic                     := 'X';             -- read
			uav_write              : in  std_logic                     := 'X';             -- write
			uav_waitrequest        : out std_logic;                                        -- waitrequest
			uav_readdatavalid      : out std_logic;                                        -- readdatavalid
			uav_byteenable         : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata           : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock               : in  std_logic                     := 'X';             -- lock
			uav_debugaccess        : in  std_logic                     := 'X';             -- debugaccess
			av_address             : out std_logic_vector(15 downto 0);                    -- address
			av_write               : out std_logic;                                        -- write
			av_read                : out std_logic;                                        -- read
			av_readdata            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata           : out std_logic_vector(31 downto 0);                    -- writedata
			av_begintransfer       : out std_logic;                                        -- begintransfer
			av_beginbursttransfer  : out std_logic;                                        -- beginbursttransfer
			av_burstcount          : out std_logic_vector(3 downto 0);                     -- burstcount
			av_byteenable          : out std_logic_vector(3 downto 0);                     -- byteenable
			av_readdatavalid       : in  std_logic                     := 'X';             -- readdatavalid
			av_waitrequest         : in  std_logic                     := 'X';             -- waitrequest
			av_writebyteenable     : out std_logic_vector(3 downto 0);                     -- writebyteenable
			av_lock                : out std_logic;                                        -- lock
			av_chipselect          : out std_logic;                                        -- chipselect
			av_clken               : out std_logic;                                        -- clken
			uav_clken              : in  std_logic                     := 'X';             -- clken
			av_debugaccess         : out std_logic;                                        -- debugaccess
			av_outputenable        : out std_logic;                                        -- outputenable
			uav_response           : out std_logic_vector(1 downto 0);                     -- response
			av_response            : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- response
			uav_writeresponsevalid : out std_logic;                                        -- writeresponsevalid
			av_writeresponsevalid  : in  std_logic                     := 'X'              -- writeresponsevalid
		);
	end component altera_merlin_slave_translator;

	component intel_std_18_1_dummy_mm_interconnect_0 is
		port (
			clk_0_clk_clk                                  : in  std_logic                     := 'X';             -- clk
			master_reset_reset_bridge_in_reset_reset       : in  std_logic                     := 'X';             -- reset
			master_avalon_universal_master_0_address       : in  std_logic_vector(37 downto 0) := (others => 'X'); -- address
			master_avalon_universal_master_0_waitrequest   : out std_logic;                                        -- waitrequest
			master_avalon_universal_master_0_burstcount    : in  std_logic_vector(9 downto 0)  := (others => 'X'); -- burstcount
			master_avalon_universal_master_0_byteenable    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			master_avalon_universal_master_0_read          : in  std_logic                     := 'X';             -- read
			master_avalon_universal_master_0_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			master_avalon_universal_master_0_readdatavalid : out std_logic;                                        -- readdatavalid
			master_avalon_universal_master_0_write         : in  std_logic                     := 'X';             -- write
			master_avalon_universal_master_0_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			master_avalon_universal_master_0_lock          : in  std_logic                     := 'X';             -- lock
			master_avalon_universal_master_0_debugaccess   : in  std_logic                     := 'X';             -- debugaccess
			slave0_avalon_universal_slave_0_address        : out std_logic_vector(31 downto 0);                    -- address
			slave0_avalon_universal_slave_0_write          : out std_logic;                                        -- write
			slave0_avalon_universal_slave_0_read           : out std_logic;                                        -- read
			slave0_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			slave0_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			slave0_avalon_universal_slave_0_burstcount     : out std_logic_vector(3 downto 0);                     -- burstcount
			slave0_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     -- byteenable
			slave0_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := 'X';             -- readdatavalid
			slave0_avalon_universal_slave_0_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			slave0_avalon_universal_slave_0_lock           : out std_logic;                                        -- lock
			slave0_avalon_universal_slave_0_debugaccess    : out std_logic;                                        -- debugaccess
			slave1_avalon_universal_slave_0_address        : out std_logic_vector(31 downto 0);                    -- address
			slave1_avalon_universal_slave_0_write          : out std_logic;                                        -- write
			slave1_avalon_universal_slave_0_read           : out std_logic;                                        -- read
			slave1_avalon_universal_slave_0_readdata       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			slave1_avalon_universal_slave_0_writedata      : out std_logic_vector(31 downto 0);                    -- writedata
			slave1_avalon_universal_slave_0_burstcount     : out std_logic_vector(3 downto 0);                     -- burstcount
			slave1_avalon_universal_slave_0_byteenable     : out std_logic_vector(3 downto 0);                     -- byteenable
			slave1_avalon_universal_slave_0_readdatavalid  : in  std_logic                     := 'X';             -- readdatavalid
			slave1_avalon_universal_slave_0_waitrequest    : in  std_logic                     := 'X';             -- waitrequest
			slave1_avalon_universal_slave_0_lock           : out std_logic;                                        -- lock
			slave1_avalon_universal_slave_0_debugaccess    : out std_logic                                         -- debugaccess
		);
	end component intel_std_18_1_dummy_mm_interconnect_0;

	component altera_reset_controller is
		generic (
			NUM_RESET_INPUTS          : integer := 6;
			OUTPUT_RESET_SYNC_EDGES   : string  := "deassert";
			SYNC_DEPTH                : integer := 2;
			RESET_REQUEST_PRESENT     : integer := 0;
			RESET_REQ_WAIT_TIME       : integer := 1;
			MIN_RST_ASSERTION_TIME    : integer := 3;
			RESET_REQ_EARLY_DSRT_TIME : integer := 1;
			USE_RESET_REQUEST_IN0     : integer := 0;
			USE_RESET_REQUEST_IN1     : integer := 0;
			USE_RESET_REQUEST_IN2     : integer := 0;
			USE_RESET_REQUEST_IN3     : integer := 0;
			USE_RESET_REQUEST_IN4     : integer := 0;
			USE_RESET_REQUEST_IN5     : integer := 0;
			USE_RESET_REQUEST_IN6     : integer := 0;
			USE_RESET_REQUEST_IN7     : integer := 0;
			USE_RESET_REQUEST_IN8     : integer := 0;
			USE_RESET_REQUEST_IN9     : integer := 0;
			USE_RESET_REQUEST_IN10    : integer := 0;
			USE_RESET_REQUEST_IN11    : integer := 0;
			USE_RESET_REQUEST_IN12    : integer := 0;
			USE_RESET_REQUEST_IN13    : integer := 0;
			USE_RESET_REQUEST_IN14    : integer := 0;
			USE_RESET_REQUEST_IN15    : integer := 0;
			ADAPT_RESET_REQUEST       : integer := 0
		);
		port (
			reset_in0      : in  std_logic := 'X'; -- reset
			clk            : in  std_logic := 'X'; -- clk
			reset_out      : out std_logic;        -- reset
			reset_req      : out std_logic;        -- reset_req
			reset_req_in0  : in  std_logic := 'X'; -- reset_req
			reset_in1      : in  std_logic := 'X'; -- reset
			reset_req_in1  : in  std_logic := 'X'; -- reset_req
			reset_in2      : in  std_logic := 'X'; -- reset
			reset_req_in2  : in  std_logic := 'X'; -- reset_req
			reset_in3      : in  std_logic := 'X'; -- reset
			reset_req_in3  : in  std_logic := 'X'; -- reset_req
			reset_in4      : in  std_logic := 'X'; -- reset
			reset_req_in4  : in  std_logic := 'X'; -- reset_req
			reset_in5      : in  std_logic := 'X'; -- reset
			reset_req_in5  : in  std_logic := 'X'; -- reset_req
			reset_in6      : in  std_logic := 'X'; -- reset
			reset_req_in6  : in  std_logic := 'X'; -- reset_req
			reset_in7      : in  std_logic := 'X'; -- reset
			reset_req_in7  : in  std_logic := 'X'; -- reset_req
			reset_in8      : in  std_logic := 'X'; -- reset
			reset_req_in8  : in  std_logic := 'X'; -- reset_req
			reset_in9      : in  std_logic := 'X'; -- reset
			reset_req_in9  : in  std_logic := 'X'; -- reset_req
			reset_in10     : in  std_logic := 'X'; -- reset
			reset_req_in10 : in  std_logic := 'X'; -- reset_req
			reset_in11     : in  std_logic := 'X'; -- reset
			reset_req_in11 : in  std_logic := 'X'; -- reset_req
			reset_in12     : in  std_logic := 'X'; -- reset
			reset_req_in12 : in  std_logic := 'X'; -- reset_req
			reset_in13     : in  std_logic := 'X'; -- reset
			reset_req_in13 : in  std_logic := 'X'; -- reset_req
			reset_in14     : in  std_logic := 'X'; -- reset
			reset_req_in14 : in  std_logic := 'X'; -- reset_req
			reset_in15     : in  std_logic := 'X'; -- reset
			reset_req_in15 : in  std_logic := 'X'  -- reset_req
		);
	end component altera_reset_controller;

	signal master_avalon_universal_master_0_waitrequest                    : std_logic;                     -- mm_interconnect_0:master_avalon_universal_master_0_waitrequest -> master:uav_waitrequest
	signal master_avalon_universal_master_0_readdata                       : std_logic_vector(31 downto 0); -- mm_interconnect_0:master_avalon_universal_master_0_readdata -> master:uav_readdata
	signal master_avalon_universal_master_0_debugaccess                    : std_logic;                     -- master:uav_debugaccess -> mm_interconnect_0:master_avalon_universal_master_0_debugaccess
	signal master_avalon_universal_master_0_address                        : std_logic_vector(37 downto 0); -- master:uav_address -> mm_interconnect_0:master_avalon_universal_master_0_address
	signal master_avalon_universal_master_0_read                           : std_logic;                     -- master:uav_read -> mm_interconnect_0:master_avalon_universal_master_0_read
	signal master_avalon_universal_master_0_byteenable                     : std_logic_vector(3 downto 0);  -- master:uav_byteenable -> mm_interconnect_0:master_avalon_universal_master_0_byteenable
	signal master_avalon_universal_master_0_readdatavalid                  : std_logic;                     -- mm_interconnect_0:master_avalon_universal_master_0_readdatavalid -> master:uav_readdatavalid
	signal master_avalon_universal_master_0_lock                           : std_logic;                     -- master:uav_lock -> mm_interconnect_0:master_avalon_universal_master_0_lock
	signal master_avalon_universal_master_0_write                          : std_logic;                     -- master:uav_write -> mm_interconnect_0:master_avalon_universal_master_0_write
	signal master_avalon_universal_master_0_writedata                      : std_logic_vector(31 downto 0); -- master:uav_writedata -> mm_interconnect_0:master_avalon_universal_master_0_writedata
	signal master_avalon_universal_master_0_burstcount                     : std_logic_vector(9 downto 0);  -- master:uav_burstcount -> mm_interconnect_0:master_avalon_universal_master_0_burstcount
	signal mm_interconnect_0_slave0_avalon_universal_slave_0_readdata      : std_logic_vector(31 downto 0); -- slave0:uav_readdata -> mm_interconnect_0:slave0_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_slave0_avalon_universal_slave_0_waitrequest   : std_logic;                     -- slave0:uav_waitrequest -> mm_interconnect_0:slave0_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_slave0_avalon_universal_slave_0_debugaccess   : std_logic;                     -- mm_interconnect_0:slave0_avalon_universal_slave_0_debugaccess -> slave0:uav_debugaccess
	signal mm_interconnect_0_slave0_avalon_universal_slave_0_address       : std_logic_vector(31 downto 0); -- mm_interconnect_0:slave0_avalon_universal_slave_0_address -> slave0:uav_address
	signal mm_interconnect_0_slave0_avalon_universal_slave_0_read          : std_logic;                     -- mm_interconnect_0:slave0_avalon_universal_slave_0_read -> slave0:uav_read
	signal mm_interconnect_0_slave0_avalon_universal_slave_0_byteenable    : std_logic_vector(3 downto 0);  -- mm_interconnect_0:slave0_avalon_universal_slave_0_byteenable -> slave0:uav_byteenable
	signal mm_interconnect_0_slave0_avalon_universal_slave_0_readdatavalid : std_logic;                     -- slave0:uav_readdatavalid -> mm_interconnect_0:slave0_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_slave0_avalon_universal_slave_0_lock          : std_logic;                     -- mm_interconnect_0:slave0_avalon_universal_slave_0_lock -> slave0:uav_lock
	signal mm_interconnect_0_slave0_avalon_universal_slave_0_write         : std_logic;                     -- mm_interconnect_0:slave0_avalon_universal_slave_0_write -> slave0:uav_write
	signal mm_interconnect_0_slave0_avalon_universal_slave_0_writedata     : std_logic_vector(31 downto 0); -- mm_interconnect_0:slave0_avalon_universal_slave_0_writedata -> slave0:uav_writedata
	signal mm_interconnect_0_slave0_avalon_universal_slave_0_burstcount    : std_logic_vector(3 downto 0);  -- mm_interconnect_0:slave0_avalon_universal_slave_0_burstcount -> slave0:uav_burstcount
	signal mm_interconnect_0_slave1_avalon_universal_slave_0_readdata      : std_logic_vector(31 downto 0); -- slave1:uav_readdata -> mm_interconnect_0:slave1_avalon_universal_slave_0_readdata
	signal mm_interconnect_0_slave1_avalon_universal_slave_0_waitrequest   : std_logic;                     -- slave1:uav_waitrequest -> mm_interconnect_0:slave1_avalon_universal_slave_0_waitrequest
	signal mm_interconnect_0_slave1_avalon_universal_slave_0_debugaccess   : std_logic;                     -- mm_interconnect_0:slave1_avalon_universal_slave_0_debugaccess -> slave1:uav_debugaccess
	signal mm_interconnect_0_slave1_avalon_universal_slave_0_address       : std_logic_vector(31 downto 0); -- mm_interconnect_0:slave1_avalon_universal_slave_0_address -> slave1:uav_address
	signal mm_interconnect_0_slave1_avalon_universal_slave_0_read          : std_logic;                     -- mm_interconnect_0:slave1_avalon_universal_slave_0_read -> slave1:uav_read
	signal mm_interconnect_0_slave1_avalon_universal_slave_0_byteenable    : std_logic_vector(3 downto 0);  -- mm_interconnect_0:slave1_avalon_universal_slave_0_byteenable -> slave1:uav_byteenable
	signal mm_interconnect_0_slave1_avalon_universal_slave_0_readdatavalid : std_logic;                     -- slave1:uav_readdatavalid -> mm_interconnect_0:slave1_avalon_universal_slave_0_readdatavalid
	signal mm_interconnect_0_slave1_avalon_universal_slave_0_lock          : std_logic;                     -- mm_interconnect_0:slave1_avalon_universal_slave_0_lock -> slave1:uav_lock
	signal mm_interconnect_0_slave1_avalon_universal_slave_0_write         : std_logic;                     -- mm_interconnect_0:slave1_avalon_universal_slave_0_write -> slave1:uav_write
	signal mm_interconnect_0_slave1_avalon_universal_slave_0_writedata     : std_logic_vector(31 downto 0); -- mm_interconnect_0:slave1_avalon_universal_slave_0_writedata -> slave1:uav_writedata
	signal mm_interconnect_0_slave1_avalon_universal_slave_0_burstcount    : std_logic_vector(3 downto 0);  -- mm_interconnect_0:slave1_avalon_universal_slave_0_burstcount -> slave1:uav_burstcount
	signal rst_controller_reset_out_reset                                  : std_logic;                     -- rst_controller:reset_out -> [master:reset, mm_interconnect_0:master_reset_reset_bridge_in_reset_reset, slave0:reset, slave1:reset]
	signal reset_reset_n_ports_inv                                         : std_logic;                     -- reset_reset_n:inv -> rst_controller:reset_in0

begin

	master : component altera_merlin_master_translator
		generic map (
			AV_ADDRESS_W                => 32,
			AV_DATA_W                   => 32,
			AV_BURSTCOUNT_W             => 4,
			AV_BYTEENABLE_W             => 4,
			UAV_ADDRESS_W               => 38,
			UAV_BURSTCOUNT_W            => 10,
			USE_READ                    => 1,
			USE_WRITE                   => 1,
			USE_BEGINBURSTTRANSFER      => 0,
			USE_BEGINTRANSFER           => 0,
			USE_CHIPSELECT              => 0,
			USE_BURSTCOUNT              => 1,
			USE_READDATAVALID           => 1,
			USE_WAITREQUEST             => 1,
			USE_READRESPONSE            => 0,
			USE_WRITERESPONSE           => 0,
			AV_SYMBOLS_PER_WORD         => 4,
			AV_ADDRESS_SYMBOLS          => 0,
			AV_BURSTCOUNT_SYMBOLS       => 0,
			AV_CONSTANT_BURST_BEHAVIOR  => 0,
			UAV_CONSTANT_BURST_BEHAVIOR => 0,
			AV_LINEWRAPBURSTS           => 0,
			AV_REGISTERINCOMINGSIGNALS  => 0
		)
		port map (
			clk                    => clk_clk,                                        --                       clk.clk
			reset                  => rst_controller_reset_out_reset,                 --                     reset.reset
			uav_address            => master_avalon_universal_master_0_address,       -- avalon_universal_master_0.address
			uav_burstcount         => master_avalon_universal_master_0_burstcount,    --                          .burstcount
			uav_read               => master_avalon_universal_master_0_read,          --                          .read
			uav_write              => master_avalon_universal_master_0_write,         --                          .write
			uav_waitrequest        => master_avalon_universal_master_0_waitrequest,   --                          .waitrequest
			uav_readdatavalid      => master_avalon_universal_master_0_readdatavalid, --                          .readdatavalid
			uav_byteenable         => master_avalon_universal_master_0_byteenable,    --                          .byteenable
			uav_readdata           => master_avalon_universal_master_0_readdata,      --                          .readdata
			uav_writedata          => master_avalon_universal_master_0_writedata,     --                          .writedata
			uav_lock               => master_avalon_universal_master_0_lock,          --                          .lock
			uav_debugaccess        => master_avalon_universal_master_0_debugaccess,   --                          .debugaccess
			av_address             => in_address,                                     --      avalon_anti_master_0.address
			av_waitrequest         => in_waitrequest,                                 --                          .waitrequest
			av_burstcount          => in_burstcount,                                  --                          .burstcount
			av_byteenable          => in_byteenable,                                  --                          .byteenable
			av_read                => in_read,                                        --                          .read
			av_readdata            => in_readdata,                                    --                          .readdata
			av_readdatavalid       => in_readdatavalid,                               --                          .readdatavalid
			av_write               => in_write,                                       --                          .write
			av_writedata           => in_writedata,                                   --                          .writedata
			av_beginbursttransfer  => '0',                                            --               (terminated)
			av_begintransfer       => '0',                                            --               (terminated)
			av_chipselect          => '0',                                            --               (terminated)
			av_lock                => '0',                                            --               (terminated)
			av_debugaccess         => '0',                                            --               (terminated)
			uav_clken              => open,                                           --               (terminated)
			av_clken               => '1',                                            --               (terminated)
			uav_response           => "00",                                           --               (terminated)
			av_response            => open,                                           --               (terminated)
			uav_writeresponsevalid => '0',                                            --               (terminated)
			av_writeresponsevalid  => open                                            --               (terminated)
		);

	slave0 : component altera_merlin_slave_translator
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 4,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 4,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 0,
			AV_BURSTCOUNT_SYMBOLS          => 0,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 1,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0
		)
		port map (
			clk                    => clk_clk,                                                         --                      clk.clk
			reset                  => rst_controller_reset_out_reset,                                  --                    reset.reset
			uav_address            => mm_interconnect_0_slave0_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => mm_interconnect_0_slave0_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read               => mm_interconnect_0_slave0_avalon_universal_slave_0_read,          --                         .read
			uav_write              => mm_interconnect_0_slave0_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest        => mm_interconnect_0_slave0_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => mm_interconnect_0_slave0_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => mm_interconnect_0_slave0_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata           => mm_interconnect_0_slave0_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata          => mm_interconnect_0_slave0_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock               => mm_interconnect_0_slave0_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess        => mm_interconnect_0_slave0_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			av_address             => slave0_address,                                                  --      avalon_anti_slave_0.address
			av_write               => slave0_write,                                                    --                         .write
			av_read                => slave0_read,                                                     --                         .read
			av_readdata            => slave0_readdata,                                                 --                         .readdata
			av_writedata           => slave0_writedata,                                                --                         .writedata
			av_begintransfer       => slave0_begintransfer,                                            --                         .begintransfer
			av_beginbursttransfer  => slave0_beginbursttransfer,                                       --                         .beginbursttransfer
			av_burstcount          => slave0_burstcount,                                               --                         .burstcount
			av_byteenable          => slave0_byteenable,                                               --                         .byteenable
			av_readdatavalid       => slave0_readdatavalid,                                            --                         .readdatavalid
			av_waitrequest         => slave0_waitrequest,                                              --                         .waitrequest
			av_writebyteenable     => open,                                                            --              (terminated)
			av_lock                => open,                                                            --              (terminated)
			av_chipselect          => open,                                                            --              (terminated)
			av_clken               => open,                                                            --              (terminated)
			uav_clken              => '0',                                                             --              (terminated)
			av_debugaccess         => open,                                                            --              (terminated)
			av_outputenable        => open,                                                            --              (terminated)
			uav_response           => open,                                                            --              (terminated)
			av_response            => "00",                                                            --              (terminated)
			uav_writeresponsevalid => open,                                                            --              (terminated)
			av_writeresponsevalid  => '0'                                                              --              (terminated)
		);

	slave1 : component altera_merlin_slave_translator
		generic map (
			AV_ADDRESS_W                   => 16,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 4,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 32,
			UAV_BURSTCOUNT_W               => 4,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 1,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 0,
			AV_BURSTCOUNT_SYMBOLS          => 0,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 1,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0
		)
		port map (
			clk                    => clk_clk,                                                         --                      clk.clk
			reset                  => rst_controller_reset_out_reset,                                  --                    reset.reset
			uav_address            => mm_interconnect_0_slave1_avalon_universal_slave_0_address,       -- avalon_universal_slave_0.address
			uav_burstcount         => mm_interconnect_0_slave1_avalon_universal_slave_0_burstcount,    --                         .burstcount
			uav_read               => mm_interconnect_0_slave1_avalon_universal_slave_0_read,          --                         .read
			uav_write              => mm_interconnect_0_slave1_avalon_universal_slave_0_write,         --                         .write
			uav_waitrequest        => mm_interconnect_0_slave1_avalon_universal_slave_0_waitrequest,   --                         .waitrequest
			uav_readdatavalid      => mm_interconnect_0_slave1_avalon_universal_slave_0_readdatavalid, --                         .readdatavalid
			uav_byteenable         => mm_interconnect_0_slave1_avalon_universal_slave_0_byteenable,    --                         .byteenable
			uav_readdata           => mm_interconnect_0_slave1_avalon_universal_slave_0_readdata,      --                         .readdata
			uav_writedata          => mm_interconnect_0_slave1_avalon_universal_slave_0_writedata,     --                         .writedata
			uav_lock               => mm_interconnect_0_slave1_avalon_universal_slave_0_lock,          --                         .lock
			uav_debugaccess        => mm_interconnect_0_slave1_avalon_universal_slave_0_debugaccess,   --                         .debugaccess
			av_address             => slave1_address,                                                  --      avalon_anti_slave_0.address
			av_write               => slave1_write,                                                    --                         .write
			av_read                => slave1_read,                                                     --                         .read
			av_readdata            => slave1_readdata,                                                 --                         .readdata
			av_writedata           => slave1_writedata,                                                --                         .writedata
			av_begintransfer       => slave1_begintransfer,                                            --                         .begintransfer
			av_beginbursttransfer  => slave1_beginbursttransfer,                                       --                         .beginbursttransfer
			av_burstcount          => slave1_burstcount,                                               --                         .burstcount
			av_byteenable          => slave1_byteenable,                                               --                         .byteenable
			av_readdatavalid       => slave1_readdatavalid,                                            --                         .readdatavalid
			av_waitrequest         => slave1_waitrequest,                                              --                         .waitrequest
			av_writebyteenable     => open,                                                            --              (terminated)
			av_lock                => open,                                                            --              (terminated)
			av_chipselect          => open,                                                            --              (terminated)
			av_clken               => open,                                                            --              (terminated)
			uav_clken              => '0',                                                             --              (terminated)
			av_debugaccess         => open,                                                            --              (terminated)
			av_outputenable        => open,                                                            --              (terminated)
			uav_response           => open,                                                            --              (terminated)
			av_response            => "00",                                                            --              (terminated)
			uav_writeresponsevalid => open,                                                            --              (terminated)
			av_writeresponsevalid  => '0'                                                              --              (terminated)
		);

	mm_interconnect_0 : component intel_std_18_1_dummy_mm_interconnect_0
		port map (
			clk_0_clk_clk                                  => clk_clk,                                                         --                          clk_0_clk.clk
			master_reset_reset_bridge_in_reset_reset       => rst_controller_reset_out_reset,                                  -- master_reset_reset_bridge_in_reset.reset
			master_avalon_universal_master_0_address       => master_avalon_universal_master_0_address,                        --   master_avalon_universal_master_0.address
			master_avalon_universal_master_0_waitrequest   => master_avalon_universal_master_0_waitrequest,                    --                                   .waitrequest
			master_avalon_universal_master_0_burstcount    => master_avalon_universal_master_0_burstcount,                     --                                   .burstcount
			master_avalon_universal_master_0_byteenable    => master_avalon_universal_master_0_byteenable,                     --                                   .byteenable
			master_avalon_universal_master_0_read          => master_avalon_universal_master_0_read,                           --                                   .read
			master_avalon_universal_master_0_readdata      => master_avalon_universal_master_0_readdata,                       --                                   .readdata
			master_avalon_universal_master_0_readdatavalid => master_avalon_universal_master_0_readdatavalid,                  --                                   .readdatavalid
			master_avalon_universal_master_0_write         => master_avalon_universal_master_0_write,                          --                                   .write
			master_avalon_universal_master_0_writedata     => master_avalon_universal_master_0_writedata,                      --                                   .writedata
			master_avalon_universal_master_0_lock          => master_avalon_universal_master_0_lock,                           --                                   .lock
			master_avalon_universal_master_0_debugaccess   => master_avalon_universal_master_0_debugaccess,                    --                                   .debugaccess
			slave0_avalon_universal_slave_0_address        => mm_interconnect_0_slave0_avalon_universal_slave_0_address,       --    slave0_avalon_universal_slave_0.address
			slave0_avalon_universal_slave_0_write          => mm_interconnect_0_slave0_avalon_universal_slave_0_write,         --                                   .write
			slave0_avalon_universal_slave_0_read           => mm_interconnect_0_slave0_avalon_universal_slave_0_read,          --                                   .read
			slave0_avalon_universal_slave_0_readdata       => mm_interconnect_0_slave0_avalon_universal_slave_0_readdata,      --                                   .readdata
			slave0_avalon_universal_slave_0_writedata      => mm_interconnect_0_slave0_avalon_universal_slave_0_writedata,     --                                   .writedata
			slave0_avalon_universal_slave_0_burstcount     => mm_interconnect_0_slave0_avalon_universal_slave_0_burstcount,    --                                   .burstcount
			slave0_avalon_universal_slave_0_byteenable     => mm_interconnect_0_slave0_avalon_universal_slave_0_byteenable,    --                                   .byteenable
			slave0_avalon_universal_slave_0_readdatavalid  => mm_interconnect_0_slave0_avalon_universal_slave_0_readdatavalid, --                                   .readdatavalid
			slave0_avalon_universal_slave_0_waitrequest    => mm_interconnect_0_slave0_avalon_universal_slave_0_waitrequest,   --                                   .waitrequest
			slave0_avalon_universal_slave_0_lock           => mm_interconnect_0_slave0_avalon_universal_slave_0_lock,          --                                   .lock
			slave0_avalon_universal_slave_0_debugaccess    => mm_interconnect_0_slave0_avalon_universal_slave_0_debugaccess,   --                                   .debugaccess
			slave1_avalon_universal_slave_0_address        => mm_interconnect_0_slave1_avalon_universal_slave_0_address,       --    slave1_avalon_universal_slave_0.address
			slave1_avalon_universal_slave_0_write          => mm_interconnect_0_slave1_avalon_universal_slave_0_write,         --                                   .write
			slave1_avalon_universal_slave_0_read           => mm_interconnect_0_slave1_avalon_universal_slave_0_read,          --                                   .read
			slave1_avalon_universal_slave_0_readdata       => mm_interconnect_0_slave1_avalon_universal_slave_0_readdata,      --                                   .readdata
			slave1_avalon_universal_slave_0_writedata      => mm_interconnect_0_slave1_avalon_universal_slave_0_writedata,     --                                   .writedata
			slave1_avalon_universal_slave_0_burstcount     => mm_interconnect_0_slave1_avalon_universal_slave_0_burstcount,    --                                   .burstcount
			slave1_avalon_universal_slave_0_byteenable     => mm_interconnect_0_slave1_avalon_universal_slave_0_byteenable,    --                                   .byteenable
			slave1_avalon_universal_slave_0_readdatavalid  => mm_interconnect_0_slave1_avalon_universal_slave_0_readdatavalid, --                                   .readdatavalid
			slave1_avalon_universal_slave_0_waitrequest    => mm_interconnect_0_slave1_avalon_universal_slave_0_waitrequest,   --                                   .waitrequest
			slave1_avalon_universal_slave_0_lock           => mm_interconnect_0_slave1_avalon_universal_slave_0_lock,          --                                   .lock
			slave1_avalon_universal_slave_0_debugaccess    => mm_interconnect_0_slave1_avalon_universal_slave_0_debugaccess    --                                   .debugaccess
		);

	rst_controller : component altera_reset_controller
		generic map (
			NUM_RESET_INPUTS          => 1,
			OUTPUT_RESET_SYNC_EDGES   => "deassert",
			SYNC_DEPTH                => 2,
			RESET_REQUEST_PRESENT     => 0,
			RESET_REQ_WAIT_TIME       => 1,
			MIN_RST_ASSERTION_TIME    => 3,
			RESET_REQ_EARLY_DSRT_TIME => 1,
			USE_RESET_REQUEST_IN0     => 0,
			USE_RESET_REQUEST_IN1     => 0,
			USE_RESET_REQUEST_IN2     => 0,
			USE_RESET_REQUEST_IN3     => 0,
			USE_RESET_REQUEST_IN4     => 0,
			USE_RESET_REQUEST_IN5     => 0,
			USE_RESET_REQUEST_IN6     => 0,
			USE_RESET_REQUEST_IN7     => 0,
			USE_RESET_REQUEST_IN8     => 0,
			USE_RESET_REQUEST_IN9     => 0,
			USE_RESET_REQUEST_IN10    => 0,
			USE_RESET_REQUEST_IN11    => 0,
			USE_RESET_REQUEST_IN12    => 0,
			USE_RESET_REQUEST_IN13    => 0,
			USE_RESET_REQUEST_IN14    => 0,
			USE_RESET_REQUEST_IN15    => 0,
			ADAPT_RESET_REQUEST       => 0
		)
		port map (
			reset_in0      => reset_reset_n_ports_inv,        -- reset_in0.reset
			clk            => clk_clk,                        --       clk.clk
			reset_out      => rst_controller_reset_out_reset, -- reset_out.reset
			reset_req      => open,                           -- (terminated)
			reset_req_in0  => '0',                            -- (terminated)
			reset_in1      => '0',                            -- (terminated)
			reset_req_in1  => '0',                            -- (terminated)
			reset_in2      => '0',                            -- (terminated)
			reset_req_in2  => '0',                            -- (terminated)
			reset_in3      => '0',                            -- (terminated)
			reset_req_in3  => '0',                            -- (terminated)
			reset_in4      => '0',                            -- (terminated)
			reset_req_in4  => '0',                            -- (terminated)
			reset_in5      => '0',                            -- (terminated)
			reset_req_in5  => '0',                            -- (terminated)
			reset_in6      => '0',                            -- (terminated)
			reset_req_in6  => '0',                            -- (terminated)
			reset_in7      => '0',                            -- (terminated)
			reset_req_in7  => '0',                            -- (terminated)
			reset_in8      => '0',                            -- (terminated)
			reset_req_in8  => '0',                            -- (terminated)
			reset_in9      => '0',                            -- (terminated)
			reset_req_in9  => '0',                            -- (terminated)
			reset_in10     => '0',                            -- (terminated)
			reset_req_in10 => '0',                            -- (terminated)
			reset_in11     => '0',                            -- (terminated)
			reset_req_in11 => '0',                            -- (terminated)
			reset_in12     => '0',                            -- (terminated)
			reset_req_in12 => '0',                            -- (terminated)
			reset_in13     => '0',                            -- (terminated)
			reset_req_in13 => '0',                            -- (terminated)
			reset_in14     => '0',                            -- (terminated)
			reset_req_in14 => '0',                            -- (terminated)
			reset_in15     => '0',                            -- (terminated)
			reset_req_in15 => '0'                             -- (terminated)
		);

	reset_reset_n_ports_inv <= not reset_reset_n;

end architecture rtl; -- of intel_std_18_1_dummy
