
proc get_design_libraries {} {
  set libraries [dict create]
  dict set libraries alt_em10g32_1930                                1
  dict set libraries alt_usxgmii_mac                                 1
  dict set libraries altera_common_sv_packages                       1
  dict set libraries alt_mge_phy_pcs_1930                            1
  dict set libraries alt_mge_phy_xcvr_term_1930                      1
  dict set libraries altera_xcvr_native_s10_htile_1921               1
  dict set libraries alt_mge_phy_1930                                1
  dict set libraries alt_usxgmii_phy                                 1
  dict set libraries address_decoder_channel_csr_clk                 1
  dict set libraries altera_merlin_slave_translator_191              1
  dict set libraries address_decoder_channel_mac                     1
  dict set libraries altera_merlin_master_translator_191             1
  dict set libraries address_decoder_channel_master                  1
  dict set libraries address_decoder_channel_phy                     1
  dict set libraries address_decoder_channel_xcvr_rcfg               1
  dict set libraries altera_merlin_master_agent_191                  1
  dict set libraries altera_merlin_slave_agent_191                   1
  dict set libraries altera_avalon_sc_fifo_191                       1
  dict set libraries altera_merlin_router_191                        1
  dict set libraries altera_merlin_traffic_limiter_191               1
  dict set libraries alt_hiconnect_sc_fifo_191                       1
  dict set libraries altera_merlin_demultiplexer_191                 1
  dict set libraries altera_merlin_multiplexer_191                   1
  dict set libraries altera_mm_interconnect_191                      1
  dict set libraries altera_reset_controller_191                     1
  dict set libraries address_decoder_channel                         1
  dict set libraries address_decoder_multi_channel_channel_0         1
  dict set libraries address_decoder_multi_channel_channel_1         1
  dict set libraries address_decoder_multi_channel_channel_10        1
  dict set libraries address_decoder_multi_channel_channel_11        1
  dict set libraries address_decoder_multi_channel_channel_2         1
  dict set libraries address_decoder_multi_channel_channel_3         1
  dict set libraries address_decoder_multi_channel_channel_4         1
  dict set libraries address_decoder_multi_channel_channel_5         1
  dict set libraries address_decoder_multi_channel_channel_6         1
  dict set libraries address_decoder_multi_channel_channel_7         1
  dict set libraries address_decoder_multi_channel_channel_8         1
  dict set libraries address_decoder_multi_channel_channel_9         1
  dict set libraries address_decoder_multi_channel_csr_clk           1
  dict set libraries address_decoder_multi_channel_master            1
  dict set libraries address_decoder_multi_channel                   1
  dict set libraries address_decoder_top_csr_clk                     1
  dict set libraries address_decoder_top_mac_clk                     1
  dict set libraries address_decoder_top_master                      1
  dict set libraries altera_avalon_dc_fifo_191                       1
  dict set libraries altera_avalon_mm_clock_crossing_bridge_191      1
  dict set libraries address_decoder_top_mm_clock_crossing_bridge    1
  dict set libraries address_decoder_top_multi_channel               1
  dict set libraries address_decoder_top_traffic_controller_ch_0_1   1
  dict set libraries address_decoder_top_traffic_controller_ch_10_11 1
  dict set libraries address_decoder_top_traffic_controller_ch_2_3   1
  dict set libraries address_decoder_top_traffic_controller_ch_4_5   1
  dict set libraries address_decoder_top_traffic_controller_ch_6_7   1
  dict set libraries address_decoder_top_traffic_controller_ch_8_9   1
  dict set libraries address_decoder_top                             1
  dict set libraries altera_jtag_dc_streaming_191                    1
  dict set libraries timing_adapter_191                              1
  dict set libraries altera_avalon_st_bytes_to_packets_1910          1
  dict set libraries altera_avalon_st_packets_to_bytes_1910          1
  dict set libraries altera_avalon_packets_to_master_1910            1
  dict set libraries channel_adapter_191                             1
  dict set libraries altera_jtag_avalon_master_191                   1
  dict set libraries alt_jtag_csr_master                             1
  dict set libraries altera_xcvr_atx_pll_s10_htile_191               1
  dict set libraries alt_mge_xcvr_atx_pll_10g                        1
  dict set libraries altera_xcvr_fpll_s10_htile_1911                 1
  dict set libraries alt_mge_core_pll                                1
  dict set libraries altera_xcvr_reset_control_s10_1911              1
  dict set libraries alt_mge_xcvr_reset_ctrl_channel                 1
  dict set libraries altera_s10_user_rst_clkgate_1910                1
  dict set libraries reset_release                                   1
  return $libraries
}

proc get_memory_files {QSYS_SIMDIR} {
  set memory_files [list]
  return $memory_files
}

proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
  set design_files [dict create]
  dict set design_files "altera_common_sv_packages::altera_xcvr_native_s10_functions_h" "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/altera_xcvr_native_s10_functions_h.sv"]\"  -work altera_common_sv_packages"
  return $design_files
}

proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
  set design_files [list]
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS {\"+incdir+[normalize_path "$QSYS_SIMDIR/../models/"]\"} \"[normalize_path "$QSYS_SIMDIR/../models/tb_top.sv"]\"  "                                                                                                                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/alt_mge_channel.v"]\"  "                                                                                                                                                                                                                                                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/alt_mge_multi_channel.sv"]\"  "                                                                                                                                                                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/alt_mge_reset_synchronizer.v"]\"  "                                                                                                                                                                                                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/alt_em10g32.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/alt_em10g32unit.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_clk_rst.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_clock_crosser.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_crc32.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_crc32_gf_mult32_kc.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_creg_map.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_creg_top.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_frm_decoder.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_pipeline_base.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_reset_synchronizer.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rr_clock_crosser.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rst_cnt.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_fctl_overflow.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_fctl_preamble.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_frm_control.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_pfc_flow_control.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_pfc_pause_conversion.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_pkt_backpressure_control.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_rs_gmii16b.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_rs_gmii16b_top.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_rs_gmii_mii.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_rs_layer.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_rs_xgmii.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_status_aligner.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_top.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_stat_mem.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_stat_reg.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_data_frm_gen.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_srcaddr_inserter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_err_aligner.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_flow_control.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_frm_arbiter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_frm_muxer.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_pause_beat_conversion.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_pause_frm_gen.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_pause_req.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_pfc_frm_gen.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rr_buffer.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_rs_gmii16b.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_rs_gmii16b_top.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_rs_layer.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_rs_xgmii_layer.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_sc_fifo.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_top.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_gmii_decoder.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_gmii_decoder_dfa.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_gmii_encoder.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_gmii_encoder_dfa.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v"]\"  -work alt_em10g32_1930"                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v"]\"  -work alt_em10g32_1930"                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_avalon_st_adapter/alt_em10g32_vldpkt_rddly.v"]\"  -work alt_em10g32_1930"                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser.v"]\"  -work alt_em10g32_1930"                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser_sync.v"]\"  -work alt_em10g32_1930"                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v"]\"  -work alt_em10g32_1930"                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v"]\"  -work alt_em10g32_1930"                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v"]\"  -work alt_em10g32_1930"                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_32_to_64_xgmii_conversion.v"]\"  -work alt_em10g32_1930"                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_64_to_32_xgmii_conversion.v"]\"  -work alt_em10g32_1930"                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_32_to_64_adapter.v"]\"  -work alt_em10g32_1930"                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_64_to_32_adapter.v"]\"  -work alt_em10g32_1930"                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_data_format_adapter.v"]\"  -work alt_em10g32_1930"                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_altsyncram_bundle.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_altsyncram.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_avalon_dc_fifo_lat_calc.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_avalon_dc_fifo_hecc.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_avalon_dc_fifo_secc.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_avalon_sc_fifo.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_avalon_sc_fifo_hecc.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_avalon_sc_fifo_secc.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_ecc_dec_18_12.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_ecc_dec_39_32.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_ecc_enc_12_18.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_ecc_enc_32_39.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_rs_xgmii_layer_ultra.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_rs_xgmii_ultra.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_avst_to_gmii_if.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_gmii_to_avst_if.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_gmii_tsu.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_gmii16b_tsu.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_lpm_mult.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_ptp_aligner.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_ptp_detector.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_rx_ptp_top.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_gmii_crc_inserter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_gmii16b_crc_inserter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_gmii_ptp_inserter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_gmii16b_ptp_inserter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_gmii16b_ptp_inserter_1g2p5g10g.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_ptp_processor.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_ptp_top.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_xgmii_crc_inserter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_xgmii_tsu.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_crc328generator.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_crc32ctl8.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_crc32galois8.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_gmii_crc_inserter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_gmii16b_crc_inserter.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/aldec/rtl/alt_em10g32_gmii16b_crc32.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/alt_em10g32_avalon_dc_fifo.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/alt_em10g32_dcfifo_synchronizer_bundle.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/alt_em10g32_std_synchronizer.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/alt_em10g32_1930/sim/altera_std_synchronizer_nocut.v"]\"  -work alt_em10g32_1930"                                                                                                                                                                                                     
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/mac/alt_usxgmii_mac/sim/alt_usxgmii_mac.vhd"]\"  -work alt_usxgmii_mac"                                                                                                                                                                                                                                            
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_async_fifo_fpga.sv"]\" -l altera_common_sv_packages -work alt_mge_phy_pcs_1930"                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_bitsync.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_mbow_clock_crosser.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_pcs.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_pcs_csr_top.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_pcs_rst_sync.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_pipeline_base.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_std_synchronizer_bundle.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_an_top.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_creg_map.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_creg_top.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_incr_cnt.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_pcs.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_rx_64_to_32_wadpt.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_rx_data_derep.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_rx_rm_fifo.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_rx_rm_fifo_top.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_rx_top.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_tx_32_to_64_wadpt.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_tx_clockcomp_fifo.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_tx_data_mux.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_tx_data_rep.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_tx_top.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxg32_umii_fault.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_xgmii_1588_latency.sv"]\" -l altera_common_sv_packages -work alt_mge_phy_pcs_1930"                                                                                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_xgmii_1588_ppm_counter.sv"]\" -l altera_common_sv_packages -work alt_mge_phy_pcs_1930"                                                                                                                                                          
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_xgmii_clockcomp.sv"]\" -l altera_common_sv_packages -work alt_mge_phy_pcs_1930"                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_xgmii_pcs.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_xgmii_rx_fifo.sv"]\" -l altera_common_sv_packages -work alt_mge_phy_pcs_1930"                                                                                                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_xgmii_soft_fifo.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_1588_ppm_counter.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_a_fifo_24.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_carrier_sense.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_clock_crosser.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_colision_detect.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_control.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_gray_cnt.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_gxb_aligned_rxsync.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_host_control.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_mdio_reg.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_mii_rx_if_pcs.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_mii_tx_if_pcs.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_ph_calculator.sv"]\" -l altera_common_sv_packages -work alt_mge_phy_pcs_1930"                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_pma_gige.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_pma.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_reset_synchronizer.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_rx_converter.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_rx_encapsulation_strx_gx.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_rx_fifo_rd.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_sdpm_altsyncram.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_sgmii_clk_enable.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_std_synchronizer.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_top_1000_base_x_strx_gx.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_top_autoneg.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_top_pcs_strx_gx.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_top_rx_converter.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_top_sgmii_strx_gx.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_top_tx_converter.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_tx_converter.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_tx_encapsulation.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_xcvr_resync.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_xcvr_latency_pulse_measurement.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/latency_pulse_measurement.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_sgmii_8_to_16_converter.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge16_pcs_sgmii_16_to_8_converter.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/aldec/alt_mge_phy_usxgmii_1588_latency.sv"]\" -l altera_common_sv_packages -work alt_mge_phy_pcs_1930"                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_pcs_1930/sim/altera_std_synchronizer_nocut.v"]\"  -work alt_mge_phy_pcs_1930"                                                                                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_xcvr_term_1930/sim/aldec/alt_mge_phy_gf_clock_mux.v"]\"  -work alt_mge_phy_xcvr_term_1930"                                                                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_xcvr_term_1930/sim/aldec/alt_mge16_phy_xcvr_term.v"]\"  -work alt_mge_phy_xcvr_term_1930"                                                                                                                                                                                 
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_arbiter.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/altera_std_synchronizer_nocut.v"]\"  -work altera_xcvr_native_s10_htile_1921"                                                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_resync_std.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_reset_counter_s10.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/s10_avmm_h.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_avmm_csr.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_prbs_accum.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_odi_accel.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_rcfg_arb.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_early_spd_chng_s10_htile.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_anlg_reset_seq.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                          
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_dig_reset_seq.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_reset_seq.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_anlg_reset_seq_wrapper.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_re_cal_chnl.v"]\"  -work altera_xcvr_native_s10_htile_1921"                                                                                                                                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_pcie_rx_eios_prot.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_rx_maib_wa.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/reconfig/alt_mge_phy_reconfig_parameters_CFG0.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_rcfg_opt_logic_x6s27ia.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_s10_htile_1921"                                                                                                                                  
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/alt_mge_phy_1930/sim/alt_usxgmii_phy_alt_mge_phy_1930_yuuknna.vhd"]\"  -work alt_mge_phy_1930"                                                                                                                                                                                                 
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/phy/alt_usxgmii_phy/sim/alt_usxgmii_phy.vhd"]\"  -work alt_usxgmii_phy"                                                                                                                                                                                                                                            
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_csr_clk/sim/address_decoder_channel_csr_clk.vhd"]\"  -work address_decoder_channel_csr_clk"                                                                                                                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_mac/altera_merlin_slave_translator_191/sim/address_decoder_channel_mac_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                                                         
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_mac/sim/address_decoder_channel_mac.vhd"]\"  -work address_decoder_channel_mac"                                                                                                                                                                 
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_master/altera_merlin_master_translator_191/sim/address_decoder_channel_master_altera_merlin_master_translator_191_g7h47bq.sv"]\"  -work altera_merlin_master_translator_191"                                                                
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_master/sim/address_decoder_channel_master.vhd"]\"  -work address_decoder_channel_master"                                                                                                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_phy/altera_merlin_slave_translator_191/sim/address_decoder_channel_phy_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                                                         
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_phy/sim/address_decoder_channel_phy.vhd"]\"  -work address_decoder_channel_phy"                                                                                                                                                                 
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_xcvr_rcfg/altera_merlin_slave_translator_191/sim/address_decoder_channel_xcvr_rcfg_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                                             
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_xcvr_rcfg/sim/address_decoder_channel_xcvr_rcfg.vhd"]\"  -work address_decoder_channel_xcvr_rcfg"                                                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_master_translator_191/sim/address_decoder_channel_altera_merlin_master_translator_191_g7h47bq.sv"]\"  -work altera_merlin_master_translator_191"                                                                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_slave_translator_191/sim/address_decoder_channel_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                                                                                            
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_master_agent_191/sim/address_decoder_channel_altera_merlin_master_agent_191_mpbm6tq.sv"]\"  -work altera_merlin_master_agent_191"                                                                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_slave_agent_191/sim/address_decoder_channel_altera_merlin_slave_agent_191_ncfkfri.sv"]\"  -work altera_merlin_slave_agent_191"                                                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_slave_agent_191/sim/altera_merlin_burst_uncompressor.sv"]\"  -work altera_merlin_slave_agent_191"                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_avalon_sc_fifo_191/sim/address_decoder_channel_altera_avalon_sc_fifo_191_e5eqkcq.v"]\"  -work altera_avalon_sc_fifo_191"                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_router_191/sim/address_decoder_channel_altera_merlin_router_191_6k4dpta.sv"]\"  -work altera_merlin_router_191"                                                                                                                                          
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_router_191/sim/address_decoder_channel_altera_merlin_router_191_bli6daa.sv"]\"  -work altera_merlin_router_191"                                                                                                                                          
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_traffic_limiter_191/sim/address_decoder_channel_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_191_zonrf6q.vhd"]\"  -work altera_merlin_traffic_limiter_191"                                                                                            
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/alt_hiconnect_sc_fifo_191/sim/address_decoder_channel_alt_hiconnect_sc_fifo_191_7qtmpqq.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/alt_hiconnect_sc_fifo_191/sim/alt_st_infer_scfifo.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/alt_hiconnect_sc_fifo_191/sim/alt_st_fifo_empty.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo_a6.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo_a7.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/alt_hiconnect_sc_fifo_191/sim/alt_st_reg_scfifo.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                               
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_traffic_limiter_191/sim/address_decoder_channel_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi.vhd"]\"  -work altera_merlin_traffic_limiter_191"                                                                                            
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_traffic_limiter_191/sim/altera_merlin_reorder_memory.sv"]\"  -work altera_merlin_traffic_limiter_191"                                                                                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_traffic_limiter_191/sim/altera_avalon_st_pipeline_base.v"]\"  -work altera_merlin_traffic_limiter_191"                                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_traffic_limiter_191/sim/address_decoder_channel_altera_merlin_traffic_limiter_191_kcba44q.sv"]\"  -work altera_merlin_traffic_limiter_191"                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_demultiplexer_191/sim/address_decoder_channel_altera_merlin_demultiplexer_191_exog3dy.sv"]\"  -work altera_merlin_demultiplexer_191"                                                                                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_multiplexer_191/sim/address_decoder_channel_altera_merlin_multiplexer_191_bhqatui.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_demultiplexer_191/sim/address_decoder_channel_altera_merlin_demultiplexer_191_z5qvpii.sv"]\"  -work altera_merlin_demultiplexer_191"                                                                                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_multiplexer_191/sim/address_decoder_channel_altera_merlin_multiplexer_191_om25mwy.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                                                                
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_mm_interconnect_191/sim/address_decoder_channel_altera_mm_interconnect_191_wasz7ki_mac_avalon_universal_slave_0_translator.vhd"]\"  -work altera_mm_interconnect_191"                                                                                               
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_mm_interconnect_191/sim/address_decoder_channel_altera_mm_interconnect_191_wasz7ki_phy_avalon_universal_slave_0_translator.vhd"]\"  -work altera_mm_interconnect_191"                                                                                               
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_mm_interconnect_191/sim/address_decoder_channel_altera_mm_interconnect_191_wasz7ki.vhd"]\"  -work altera_mm_interconnect_191"                                                                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_reset_controller_191/sim/aldec/altera_reset_controller.v"]\"  -work altera_reset_controller_191"                                                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/altera_reset_controller_191/sim/aldec/altera_reset_synchronizer.v"]\"  -work altera_reset_controller_191"                                                                                                                                                         
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_channel/sim/address_decoder_channel.vhd"]\"  -work address_decoder_channel"                                                                                                                                                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_0/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_channel_0_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                           
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_0/sim/address_decoder_multi_channel_channel_0.vhd"]\"  -work address_decoder_multi_channel_channel_0"                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_1/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_channel_1_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                           
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_1/sim/address_decoder_multi_channel_channel_1.vhd"]\"  -work address_decoder_multi_channel_channel_1"                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_10/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_channel_10_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                         
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_10/sim/address_decoder_multi_channel_channel_10.vhd"]\"  -work address_decoder_multi_channel_channel_10"                                                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_11/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_channel_11_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                         
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_11/sim/address_decoder_multi_channel_channel_11.vhd"]\"  -work address_decoder_multi_channel_channel_11"                                                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_2/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_channel_2_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                           
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_2/sim/address_decoder_multi_channel_channel_2.vhd"]\"  -work address_decoder_multi_channel_channel_2"                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_3/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_channel_3_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                           
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_3/sim/address_decoder_multi_channel_channel_3.vhd"]\"  -work address_decoder_multi_channel_channel_3"                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_4/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_channel_4_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                           
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_4/sim/address_decoder_multi_channel_channel_4.vhd"]\"  -work address_decoder_multi_channel_channel_4"                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_5/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_channel_5_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                           
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_5/sim/address_decoder_multi_channel_channel_5.vhd"]\"  -work address_decoder_multi_channel_channel_5"                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_6/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_channel_6_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                           
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_6/sim/address_decoder_multi_channel_channel_6.vhd"]\"  -work address_decoder_multi_channel_channel_6"                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_7/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_channel_7_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                           
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_7/sim/address_decoder_multi_channel_channel_7.vhd"]\"  -work address_decoder_multi_channel_channel_7"                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_8/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_channel_8_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                           
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_8/sim/address_decoder_multi_channel_channel_8.vhd"]\"  -work address_decoder_multi_channel_channel_8"                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_9/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_channel_9_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                           
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_channel_9/sim/address_decoder_multi_channel_channel_9.vhd"]\"  -work address_decoder_multi_channel_channel_9"                                                                                                                       
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_csr_clk/sim/address_decoder_multi_channel_csr_clk.vhd"]\"  -work address_decoder_multi_channel_csr_clk"                                                                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_master/altera_merlin_master_translator_191/sim/address_decoder_multi_channel_master_altera_merlin_master_translator_191_g7h47bq.sv"]\"  -work altera_merlin_master_translator_191"                                              
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_multi_channel/address_decoder_multi_channel_master/sim/address_decoder_multi_channel_master.vhd"]\"  -work address_decoder_multi_channel_master"                                                                                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_master_translator_191/sim/address_decoder_multi_channel_altera_merlin_master_translator_191_g7h47bq.sv"]\"  -work altera_merlin_master_translator_191"                                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_slave_translator_191/sim/address_decoder_multi_channel_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_master_agent_191/sim/address_decoder_multi_channel_altera_merlin_master_agent_191_mpbm6tq.sv"]\"  -work altera_merlin_master_agent_191"                                                                                                            
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_slave_agent_191/sim/address_decoder_multi_channel_altera_merlin_slave_agent_191_ncfkfri.sv"]\"  -work altera_merlin_slave_agent_191"                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_slave_agent_191/sim/altera_merlin_burst_uncompressor.sv"]\"  -work altera_merlin_slave_agent_191"                                                                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_avalon_sc_fifo_191/sim/address_decoder_multi_channel_altera_avalon_sc_fifo_191_e5eqkcq.v"]\"  -work altera_avalon_sc_fifo_191"                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_router_191/sim/address_decoder_multi_channel_altera_merlin_router_191_32egg6a.sv"]\"  -work altera_merlin_router_191"                                                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_router_191/sim/address_decoder_multi_channel_altera_merlin_router_191_4vwofdq.sv"]\"  -work altera_merlin_router_191"                                                                                                                              
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_traffic_limiter_191/sim/address_decoder_multi_channel_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_191_zonrf6q.vhd"]\"  -work altera_merlin_traffic_limiter_191"                                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/alt_hiconnect_sc_fifo_191/sim/address_decoder_multi_channel_alt_hiconnect_sc_fifo_191_7qtmpqq.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/alt_hiconnect_sc_fifo_191/sim/alt_st_infer_scfifo.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/alt_hiconnect_sc_fifo_191/sim/alt_st_fifo_empty.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo_a6.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo_a7.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/alt_hiconnect_sc_fifo_191/sim/alt_st_reg_scfifo.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                         
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_traffic_limiter_191/sim/address_decoder_multi_channel_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi.vhd"]\"  -work altera_merlin_traffic_limiter_191"                                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_traffic_limiter_191/sim/altera_merlin_reorder_memory.sv"]\"  -work altera_merlin_traffic_limiter_191"                                                                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_traffic_limiter_191/sim/altera_avalon_st_pipeline_base.v"]\"  -work altera_merlin_traffic_limiter_191"                                                                                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_traffic_limiter_191/sim/address_decoder_multi_channel_altera_merlin_traffic_limiter_191_kcba44q.sv"]\"  -work altera_merlin_traffic_limiter_191"                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_demultiplexer_191/sim/address_decoder_multi_channel_altera_merlin_demultiplexer_191_vs5t6hy.sv"]\"  -work altera_merlin_demultiplexer_191"                                                                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_multiplexer_191/sim/address_decoder_multi_channel_altera_merlin_multiplexer_191_fc2mo2q.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                                                          
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_demultiplexer_191/sim/address_decoder_multi_channel_altera_merlin_demultiplexer_191_dhpl4fi.sv"]\"  -work altera_merlin_demultiplexer_191"                                                                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_multiplexer_191/sim/address_decoder_multi_channel_altera_merlin_multiplexer_191_qznn4dq.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                                                          
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_mm_interconnect_191/sim/address_decoder_multi_channel_altera_mm_interconnect_191_yxycpgi.vhd"]\"  -work altera_mm_interconnect_191"                                                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_reset_controller_191/sim/aldec/altera_reset_controller.v"]\"  -work altera_reset_controller_191"                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/altera_reset_controller_191/sim/aldec/altera_reset_synchronizer.v"]\"  -work altera_reset_controller_191"                                                                                                                                                   
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_multi_channel/sim/address_decoder_multi_channel.vhd"]\"  -work address_decoder_multi_channel"                                                                                                                                                                                      
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_csr_clk/sim/address_decoder_top_csr_clk.vhd"]\"  -work address_decoder_top_csr_clk"                                                                                                                                                                     
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_mac_clk/sim/address_decoder_top_mac_clk.vhd"]\"  -work address_decoder_top_mac_clk"                                                                                                                                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_master/altera_merlin_master_translator_191/sim/address_decoder_top_master_altera_merlin_master_translator_191_g7h47bq.sv"]\"  -work altera_merlin_master_translator_191"                                                                            
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_master/sim/address_decoder_top_master.vhd"]\"  -work address_decoder_top_master"                                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_mm_clock_crossing_bridge/altera_avalon_dc_fifo_191/sim/address_decoder_top_mm_clock_crossing_bridge_altera_avalon_dc_fifo_191_27jzy3q.v"]\"  -work altera_avalon_dc_fifo_191"                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_mm_clock_crossing_bridge/altera_avalon_dc_fifo_191/sim/altera_dcfifo_synchronizer_bundle.v"]\"  -work altera_avalon_dc_fifo_191"                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_mm_clock_crossing_bridge/altera_avalon_dc_fifo_191/sim/altera_std_synchronizer_nocut.v"]\"  -work altera_avalon_dc_fifo_191"                                                                                                                   
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_mm_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge_191/sim/address_decoder_top_mm_clock_crossing_bridge_altera_avalon_mm_clock_crossing_bridge_altera_avalon_dc_fifo_191_dlm75pi.vhd"]\"  -work altera_avalon_mm_clock_crossing_bridge_191"
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_mm_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge_191/sim/address_decoder_top_mm_clock_crossing_bridge_altera_avalon_mm_clock_crossing_bridge_altera_avalon_dc_fifo_191_7stozva.vhd"]\"  -work altera_avalon_mm_clock_crossing_bridge_191"
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_mm_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge_191/sim/address_decoder_top_mm_clock_crossing_bridge_altera_avalon_mm_clock_crossing_bridge_191_pbdlwri.v"]\"  -work altera_avalon_mm_clock_crossing_bridge_191"               
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_mm_clock_crossing_bridge/sim/address_decoder_top_mm_clock_crossing_bridge.vhd"]\"  -work address_decoder_top_mm_clock_crossing_bridge"                                                                                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_multi_channel/altera_merlin_slave_translator_191/sim/address_decoder_top_multi_channel_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                                                 
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_multi_channel/sim/address_decoder_top_multi_channel.vhd"]\"  -work address_decoder_top_multi_channel"                                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_0_1/altera_merlin_slave_translator_191/sim/address_decoder_top_traffic_controller_ch_0_1_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                         
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_0_1/sim/address_decoder_top_traffic_controller_ch_0_1.vhd"]\"  -work address_decoder_top_traffic_controller_ch_0_1"                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_10_11/altera_merlin_slave_translator_191/sim/address_decoder_top_traffic_controller_ch_10_11_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                     
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_10_11/sim/address_decoder_top_traffic_controller_ch_10_11.vhd"]\"  -work address_decoder_top_traffic_controller_ch_10_11"                                                                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_2_3/altera_merlin_slave_translator_191/sim/address_decoder_top_traffic_controller_ch_2_3_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                         
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_2_3/sim/address_decoder_top_traffic_controller_ch_2_3.vhd"]\"  -work address_decoder_top_traffic_controller_ch_2_3"                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_4_5/altera_merlin_slave_translator_191/sim/address_decoder_top_traffic_controller_ch_4_5_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                         
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_4_5/sim/address_decoder_top_traffic_controller_ch_4_5.vhd"]\"  -work address_decoder_top_traffic_controller_ch_4_5"                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_6_7/altera_merlin_slave_translator_191/sim/address_decoder_top_traffic_controller_ch_6_7_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                         
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_6_7/sim/address_decoder_top_traffic_controller_ch_6_7.vhd"]\"  -work address_decoder_top_traffic_controller_ch_6_7"                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_8_9/altera_merlin_slave_translator_191/sim/address_decoder_top_traffic_controller_ch_8_9_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                         
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/ip/address_decoder_top/address_decoder_top_traffic_controller_ch_8_9/sim/address_decoder_top_traffic_controller_ch_8_9.vhd"]\"  -work address_decoder_top_traffic_controller_ch_8_9"                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_master_translator_191/sim/address_decoder_top_altera_merlin_master_translator_191_g7h47bq.sv"]\"  -work altera_merlin_master_translator_191"                                                                                                                 
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_slave_translator_191/sim/address_decoder_top_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_master_agent_191/sim/address_decoder_top_altera_merlin_master_agent_191_mpbm6tq.sv"]\"  -work altera_merlin_master_agent_191"                                                                                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_slave_agent_191/sim/address_decoder_top_altera_merlin_slave_agent_191_ncfkfri.sv"]\"  -work altera_merlin_slave_agent_191"                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_slave_agent_191/sim/altera_merlin_burst_uncompressor.sv"]\"  -work altera_merlin_slave_agent_191"                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_avalon_sc_fifo_191/sim/address_decoder_top_altera_avalon_sc_fifo_191_e5eqkcq.v"]\"  -work altera_avalon_sc_fifo_191"                                                                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_router_191/sim/address_decoder_top_altera_merlin_router_191_fwgsesi.sv"]\"  -work altera_merlin_router_191"                                                                                                                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_router_191/sim/address_decoder_top_altera_merlin_router_191_eo734fy.sv"]\"  -work altera_merlin_router_191"                                                                                                                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_demultiplexer_191/sim/address_decoder_top_altera_merlin_demultiplexer_191_cvl73xa.sv"]\"  -work altera_merlin_demultiplexer_191"                                                                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_multiplexer_191/sim/address_decoder_top_altera_merlin_multiplexer_191_mbb35ky.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_demultiplexer_191/sim/address_decoder_top_altera_merlin_demultiplexer_191_6ywz4pa.sv"]\"  -work altera_merlin_demultiplexer_191"                                                                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_multiplexer_191/sim/address_decoder_top_altera_merlin_multiplexer_191_drzivnq.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                                                                    
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_mm_interconnect_191/sim/address_decoder_top_altera_mm_interconnect_191_3kbf4ri_multi_channel_avalon_universal_slave_0_translator.vhd"]\"  -work altera_mm_interconnect_191"                                                                                             
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_mm_interconnect_191/sim/address_decoder_top_altera_mm_interconnect_191_3kbf4ri_mm_clock_crossing_bridge_s0_translator.vhd"]\"  -work altera_mm_interconnect_191"                                                                                                        
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_mm_interconnect_191/sim/address_decoder_top_altera_mm_interconnect_191_3kbf4ri.vhd"]\"  -work altera_mm_interconnect_191"                                                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_router_191/sim/address_decoder_top_altera_merlin_router_191_oyu3via.sv"]\"  -work altera_merlin_router_191"                                                                                                                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_router_191/sim/address_decoder_top_altera_merlin_router_191_eyt5dgy.sv"]\"  -work altera_merlin_router_191"                                                                                                                                                  
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_traffic_limiter_191/sim/address_decoder_top_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_191_zonrf6q.vhd"]\"  -work altera_merlin_traffic_limiter_191"                                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/alt_hiconnect_sc_fifo_191/sim/address_decoder_top_alt_hiconnect_sc_fifo_191_7qtmpqq.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/alt_hiconnect_sc_fifo_191/sim/alt_st_infer_scfifo.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                                 
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/alt_hiconnect_sc_fifo_191/sim/alt_st_fifo_empty.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo_a6.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/alt_hiconnect_sc_fifo_191/sim/alt_st_mlab_scfifo_a7.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/alt_hiconnect_sc_fifo_191/sim/alt_st_reg_scfifo.sv"]\"  -work alt_hiconnect_sc_fifo_191"                                                                                                                                                                                   
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_traffic_limiter_191/sim/address_decoder_top_altera_merlin_traffic_limiter_alt_hiconnect_sc_fifo_191_5pm2ohi.vhd"]\"  -work altera_merlin_traffic_limiter_191"                                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_traffic_limiter_191/sim/altera_merlin_reorder_memory.sv"]\"  -work altera_merlin_traffic_limiter_191"                                                                                                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_traffic_limiter_191/sim/altera_avalon_st_pipeline_base.v"]\"  -work altera_merlin_traffic_limiter_191"                                                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_traffic_limiter_191/sim/address_decoder_top_altera_merlin_traffic_limiter_191_kcba44q.sv"]\"  -work altera_merlin_traffic_limiter_191"                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_demultiplexer_191/sim/address_decoder_top_altera_merlin_demultiplexer_191_mkj5isy.sv"]\"  -work altera_merlin_demultiplexer_191"                                                                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_multiplexer_191/sim/address_decoder_top_altera_merlin_multiplexer_191_hdlfwfy.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_demultiplexer_191/sim/address_decoder_top_altera_merlin_demultiplexer_191_s3vmtaa.sv"]\"  -work altera_merlin_demultiplexer_191"                                                                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_multiplexer_191/sim/address_decoder_top_altera_merlin_multiplexer_191_hkbv22i.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_merlin_multiplexer_191/sim/altera_merlin_arbitrator.sv"]\"  -work altera_merlin_multiplexer_191"                                                                                                                                                                    
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_mm_interconnect_191/sim/address_decoder_top_altera_mm_interconnect_191_fv6bu5i.vhd"]\"  -work altera_mm_interconnect_191"                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_reset_controller_191/sim/aldec/altera_reset_controller.v"]\"  -work altera_reset_controller_191"                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/altera_reset_controller_191/sim/aldec/altera_reset_synchronizer.v"]\"  -work altera_reset_controller_191"                                                                                                                                                             
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/address_decoder/address_decoder_top/sim/address_decoder_top.vhd"]\"  -work address_decoder_top"                                                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.v"]\"  -work altera_jtag_dc_streaming_191"                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_jtag_dc_streaming_191/sim/altera_jtag_dc_streaming.v"]\"  -work altera_jtag_dc_streaming_191"                                                                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_jtag_dc_streaming_191/sim/altera_jtag_sld_node.v"]\"  -work altera_jtag_dc_streaming_191"                                                                                                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_jtag_dc_streaming_191/sim/altera_jtag_streaming.v"]\"  -work altera_jtag_dc_streaming_191"                                                                                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_jtag_dc_streaming_191/sim/altera_avalon_st_clock_crosser.v"]\"  -work altera_jtag_dc_streaming_191"                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_jtag_dc_streaming_191/sim/altera_std_synchronizer_nocut.v"]\"  -work altera_jtag_dc_streaming_191"                                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_base.v"]\"  -work altera_jtag_dc_streaming_191"                                                                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_remover.v"]\"  -work altera_jtag_dc_streaming_191"                                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_inserter.v"]\"  -work altera_jtag_dc_streaming_191"                                                                                                                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_stage.sv"]\"  -work altera_jtag_dc_streaming_191"                                                                                                                                                            
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/timing_adapter_191/sim/alt_jtag_csr_master_timing_adapter_191_rrgemwi.sv"]\"  -work timing_adapter_191"                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_avalon_sc_fifo_191/sim/alt_jtag_csr_master_altera_avalon_sc_fifo_191_e5eqkcq.v"]\"  -work altera_avalon_sc_fifo_191"                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_avalon_st_bytes_to_packets_1910/sim/altera_avalon_st_bytes_to_packets.v"]\"  -work altera_avalon_st_bytes_to_packets_1910"                                                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_avalon_st_packets_to_bytes_1910/sim/altera_avalon_st_packets_to_bytes.v"]\"  -work altera_avalon_st_packets_to_bytes_1910"                                                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_avalon_packets_to_master_1910/sim/altera_avalon_packets_to_master.v"]\"  -work altera_avalon_packets_to_master_1910"                                                                                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/channel_adapter_191/sim/alt_jtag_csr_master_channel_adapter_191_uc27kqq.sv"]\"  -work channel_adapter_191"                                                                                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/channel_adapter_191/sim/alt_jtag_csr_master_channel_adapter_191_cco4x3a.sv"]\"  -work channel_adapter_191"                                                                                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_reset_controller_191/sim/aldec/altera_reset_controller.v"]\"  -work altera_reset_controller_191"                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_reset_controller_191/sim/aldec/altera_reset_synchronizer.v"]\"  -work altera_reset_controller_191"                                                                                                                                                          
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/altera_jtag_avalon_master_191/sim/alt_jtag_csr_master_altera_jtag_avalon_master_191_3zppvky.vhd"]\"  -work altera_jtag_avalon_master_191"                                                                                                                                   
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/jtag_avalon_master/alt_jtag_csr_master/sim/alt_jtag_csr_master.vhd"]\"  -work alt_jtag_csr_master"                                                                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g/altera_xcvr_atx_pll_s10_htile_191/sim/altera_std_synchronizer_nocut.v"]\"  -work altera_xcvr_atx_pll_s10_htile_191"                                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g/altera_xcvr_atx_pll_s10_htile_191/sim/alt_xcvr_resync.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_s10_htile_191"                                                                                                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g/altera_xcvr_atx_pll_s10_htile_191/sim/alt_xcvr_arbiter.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_s10_htile_191"                                                                                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g/altera_xcvr_atx_pll_s10_htile_191/sim/s10_avmm_h.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_s10_htile_191"                                                                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g/altera_xcvr_atx_pll_s10_htile_191/sim/alt_xcvr_native_anlg_reset_seq.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_s10_htile_191"                                                                                                                          
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g/altera_xcvr_atx_pll_s10_htile_191/sim/alt_xcvr_pll_rcfg_arb.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_s10_htile_191"                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g/altera_xcvr_atx_pll_s10_htile_191/sim/alt_xcvr_pll_embedded_debug.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_s10_htile_191"                                                                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g/altera_xcvr_atx_pll_s10_htile_191/sim/alt_xcvr_pll_avmm_csr.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_s10_htile_191"                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g/altera_xcvr_atx_pll_s10_htile_191/sim/alt_mge_xcvr_atx_pll_10g_altera_xcvr_atx_pll_s10_htile_191_z7zd7fa.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_s10_htile_191"                                                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g/altera_xcvr_atx_pll_s10_htile_191/sim/alt_xcvr_pll_rcfg_opt_logic_z7zd7fa.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_s10_htile_191"                                                                                                                     
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g/sim/alt_mge_xcvr_atx_pll_10g.vhd"]\"  -work alt_mge_xcvr_atx_pll_10g"                                                                                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_fpll/alt_mge_core_pll/altera_xcvr_fpll_s10_htile_1911/sim/altera_std_synchronizer_nocut.v"]\"  -work altera_xcvr_fpll_s10_htile_1911"                                                                                                                                                                 
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_fpll/alt_mge_core_pll/altera_xcvr_fpll_s10_htile_1911/sim/s10_avmm_h.sv"]\" -l altera_common_sv_packages -work altera_xcvr_fpll_s10_htile_1911"                                                                                                                                                            
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_fpll/alt_mge_core_pll/altera_xcvr_fpll_s10_htile_1911/sim/alt_xcvr_native_anlg_reset_seq.sv"]\" -l altera_common_sv_packages -work altera_xcvr_fpll_s10_htile_1911"                                                                                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_fpll/alt_mge_core_pll/altera_xcvr_fpll_s10_htile_1911/sim/alt_xcvr_pll_rcfg_arb.sv"]\" -l altera_common_sv_packages -work altera_xcvr_fpll_s10_htile_1911"                                                                                                                                                 
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_fpll/alt_mge_core_pll/altera_xcvr_fpll_s10_htile_1911/sim/alt_xcvr_pll_embedded_debug.sv"]\" -l altera_common_sv_packages -work altera_xcvr_fpll_s10_htile_1911"                                                                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_fpll/alt_mge_core_pll/altera_xcvr_fpll_s10_htile_1911/sim/alt_xcvr_pll_avmm_csr.sv"]\" -l altera_common_sv_packages -work altera_xcvr_fpll_s10_htile_1911"                                                                                                                                                 
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_fpll/alt_mge_core_pll/altera_xcvr_fpll_s10_htile_1911/sim/alt_xcvr_resync.sv"]\" -l altera_common_sv_packages -work altera_xcvr_fpll_s10_htile_1911"                                                                                                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_fpll/alt_mge_core_pll/altera_xcvr_fpll_s10_htile_1911/sim/alt_xcvr_arbiter.sv"]\" -l altera_common_sv_packages -work altera_xcvr_fpll_s10_htile_1911"                                                                                                                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_fpll/alt_mge_core_pll/altera_xcvr_fpll_s10_htile_1911/sim/alt_mge_core_pll_altera_xcvr_fpll_s10_htile_1911_zbplmea.sv"]\" -l altera_common_sv_packages -work altera_xcvr_fpll_s10_htile_1911"                                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_fpll/alt_mge_core_pll/altera_xcvr_fpll_s10_htile_1911/sim/alt_xcvr_pll_rcfg_opt_logic_zbplmea.sv"]\" -l altera_common_sv_packages -work altera_xcvr_fpll_s10_htile_1911"                                                                                                                                   
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/pll_fpll/alt_mge_core_pll/sim/alt_mge_core_pll.vhd"]\"  -work alt_mge_core_pll"                                                                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_channel/altera_xcvr_reset_control_s10_1911/sim/altera_std_synchronizer_nocut.v"]\"  -work altera_xcvr_reset_control_s10_1911"                                                                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_channel/altera_xcvr_reset_control_s10_1911/sim/alt_xcvr_resync_std.sv"]\"  -work altera_xcvr_reset_control_s10_1911"                                                                                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_channel/altera_xcvr_reset_control_s10_1911/sim/altera_xcvr_reset_control_s10.sv"]\"  -work altera_xcvr_reset_control_s10_1911"                                                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_channel/altera_xcvr_reset_control_s10_1911/sim/alt_xcvr_reset_counter_s10.sv"]\"  -work altera_xcvr_reset_control_s10_1911"                                                                                                                                      
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_channel/sim/alt_mge_xcvr_reset_ctrl_channel.vhd"]\"  -work alt_mge_xcvr_reset_ctrl_channel"                                                                                                                                                                          
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/reset_release/reset_release/altera_s10_user_rst_clkgate_1910/sim/altera_s10_user_rst_clkgate.sv"]\"  -work altera_s10_user_rst_clkgate_1910"                                                                                                                                                                   
  lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../../../rtl/reset_release/reset_release/sim/reset_release.vhd"]\"  -work reset_release"                                                                                                                                                                                                                                        
  return $design_files
}

proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
  set ELAB_OPTIONS ""
  if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
  } else {
  }
  return $ELAB_OPTIONS
}


proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
  set SIM_OPTIONS ""
  if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
  } else {
  }
  return $SIM_OPTIONS
}


proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
  set ENV_VARIABLES [dict create]
  set LD_LIBRARY_PATH [dict create]
  dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
  if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
  } else {
  }
  return $ENV_VARIABLES
}


proc normalize_path {FILEPATH} {
    if {[catch { package require fileutil } err]} { 
        return $FILEPATH 
    } 
    set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]  
    if {[file pathtype $FILEPATH] eq "relative"} { 
        set path [fileutil::relative [pwd] $path] 
    } 
    return $path 
} 
