-- alt_mge_xcvr_atx_pll_10g.vhd

-- Generated using ACDS version 19.4 64

library IEEE;
library altera_xcvr_atx_pll_s10_htile_191;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity alt_mge_xcvr_atx_pll_10g is
	port (
		pll_refclk0     : in  std_logic := '0'; --     pll_refclk0.clk
		tx_serial_clk   : out std_logic;        --   tx_serial_clk.clk
		pll_locked      : out std_logic;        --      pll_locked.pll_locked
		pll_cal_busy    : out std_logic;        --    pll_cal_busy.pll_cal_busy
		mcgb_serial_clk : out std_logic         -- mcgb_serial_clk.clk
	);
end entity alt_mge_xcvr_atx_pll_10g;

architecture rtl of alt_mge_xcvr_atx_pll_10g is
	component alt_mge_xcvr_atx_pll_10g_altera_xcvr_atx_pll_s10_htile_191_z7zd7fa_cmp is
		generic (
			rcfg_enable                                                      : integer := 0;
			rcfg_jtag_enable                                                 : integer := 0;
			rcfg_separate_avmm_busy                                          : integer := 0;
			dbg_embedded_debug_enable                                        : integer := 0;
			dbg_capability_reg_enable                                        : integer := 0;
			dbg_user_identifier                                              : integer := 0;
			dbg_stat_soft_logic_enable                                       : integer := 0;
			dbg_ctrl_soft_logic_enable                                       : integer := 0;
			rcfg_emb_strm_enable                                             : integer := 0;
			rcfg_profile_cnt                                                 : integer := 2;
			hssi_avmm2_if_pcs_arbiter_ctrl                                   : string  := "avmm2_arbiter_uc_sel";
			hssi_avmm2_if_pcs_cal_done                                       : string  := "avmm2_cal_done_assert";
			hssi_avmm2_if_pcs_cal_reserved                                   : integer := 0;
			hssi_avmm2_if_pcs_calibration_feature_en                         : string  := "avmm2_pcs_calibration_dis";
			hssi_avmm2_if_pldadapt_gate_dis                                  : string  := "disable";
			hssi_avmm2_if_pcs_hip_cal_en                                     : string  := "disable";
			hssi_avmm2_if_hssiadapt_avmm_osc_clock_setting                   : string  := "osc_clk_div_by1";
			hssi_avmm2_if_pldadapt_avmm_osc_clock_setting                    : string  := "osc_clk_div_by1";
			hssi_avmm2_if_hssiadapt_avmm_testbus_sel                         : string  := "avmm1_transfer_testbus";
			hssi_avmm2_if_pldadapt_avmm_testbus_sel                          : string  := "avmm1_transfer_testbus";
			hssi_avmm2_if_hssiadapt_hip_mode                                 : string  := "disable_hip";
			hssi_avmm2_if_pldadapt_hip_mode                                  : string  := "disable_hip";
			hssi_avmm2_if_silicon_rev                                        : string  := "14nm5";
			hssi_avmm2_if_calibration_type                                   : string  := "one_time";
			atx_pll_analog_mode                                              : string  := "user_custom";
			atx_pll_bonding                                                  : string  := "bond_off";
			atx_pll_bw_mode                                                  : string  := "bw_mode_off";
			atx_pll_cascadeclk_test                                          : string  := "cascadetest_off";
			atx_pll_cgb_div                                                  : integer := 1;
			atx_pll_chgpmp_testmode                                          : string  := "cp_normal";
			atx_pll_clk_high_perf_voltage                                    : integer := 0;
			atx_pll_clk_low_power_voltage                                    : integer := 0;
			atx_pll_clk_mid_power_voltage                                    : integer := 0;
			atx_pll_datarate_bps                                             : string  := "1";
			atx_pll_device_variant                                           : string  := "device_off";
			atx_pll_clk_vreg_boost_expected_voltage                          : integer := 0;
			atx_pll_clk_vreg_boost_scratch                                   : integer := 0;
			atx_pll_clk_vreg_boost_step_size                                 : integer := 0;
			atx_pll_lc_vreg1_boost_expected_voltage                          : integer := 0;
			atx_pll_lc_vreg1_boost_scratch                                   : integer := 0;
			atx_pll_lc_vreg_boost_expected_voltage                           : integer := 0;
			atx_pll_lc_vreg_boost_scratch                                    : integer := 0;
			atx_pll_mcgb_vreg_boost_expected_voltage                         : integer := 0;
			atx_pll_mcgb_vreg_boost_scratch                                  : integer := 0;
			atx_pll_mcgb_vreg_boost_step_size                                : integer := 0;
			atx_pll_pm_dprio_lc_dprio_status_select                          : string  := "dprio_normal_status";
			atx_pll_vreg1_boost_step_size                                    : integer := 0;
			atx_pll_vreg_boost_step_size                                     : integer := 0;
			atx_pll_enable_hclk                                              : string  := "false";
			atx_pll_expected_lc_boost_voltage                                : integer := 0;
			atx_pll_f_max_lcnt_fpll_cascading                                : string  := "1";
			atx_pll_f_max_pfd                                                : string  := "1";
			atx_pll_f_max_pfd_fractional                                     : string  := "1";
			atx_pll_f_max_ref                                                : string  := "1";
			atx_pll_f_max_tank_0                                             : string  := "1";
			atx_pll_f_max_tank_1                                             : string  := "1";
			atx_pll_f_max_tank_2                                             : string  := "1";
			atx_pll_f_max_vco                                                : string  := "1";
			atx_pll_f_max_vco_fractional                                     : string  := "1";
			atx_pll_f_max_x1                                                 : string  := "1";
			atx_pll_f_min_pfd                                                : string  := "1";
			atx_pll_f_min_ref                                                : string  := "1";
			atx_pll_f_min_tank_0                                             : string  := "1";
			atx_pll_f_min_tank_1                                             : string  := "1";
			atx_pll_f_min_tank_2                                             : string  := "1";
			atx_pll_f_min_vco                                                : string  := "1";
			atx_pll_fpll_refclk_selection                                    : string  := "select_div_by_2";
			atx_pll_hclk_en                                                  : string  := "hclk_disabled";
			atx_pll_initial_settings                                         : string  := "true";
			atx_pll_is_otn                                                   : string  := "false";
			atx_pll_is_sdi                                                   : string  := "true";
			atx_pll_l_counter                                                : integer := 1;
			atx_pll_lc_cal_reserved                                          : string  := "lc_cal_reserved_off";
			atx_pll_lc_dyn_reconfig                                          : string  := "lc_dyn_reconfig_off";
			atx_pll_lc_to_fpll_l_counter                                     : string  := "lcounter_setting0";
			atx_pll_lc_to_fpll_l_counter_scratch                             : integer := 1;
			atx_pll_lccmu_mode                                               : string  := "lccmu_pd";
			atx_pll_lcpll_gt_in_sel                                          : string  := "lc_gt_in_sel0";
			atx_pll_lcpll_gt_out_left_enb                                    : string  := "lcpll_gt_out_left_dis";
			atx_pll_lcpll_gt_out_mid_enb                                     : string  := "lcpll_gt_out_mid_dis";
			atx_pll_lcpll_gt_out_right_enb                                   : string  := "lcpll_gt_out_right_dis";
			atx_pll_lcpll_lckdet_sel                                         : string  := "lc_lckdet_sel0";
			atx_pll_max_fractional_percentage                                : integer := 0;
			atx_pll_mcnt_divide                                              : integer := 8;
			atx_pll_min_fractional_percentage                                : integer := 0;
			atx_pll_n_counter                                                : integer := 1;
			atx_pll_out_freq                                                 : string  := "1";
			atx_pll_pfd_delay_compensation                                   : string  := "normal_delay";
			atx_pll_pfd_pulse_width                                          : string  := "pulse_width_setting0";
			atx_pll_pma_width                                                : integer := 8;
			atx_pll_power_mode                                               : string  := "power_off";
			atx_pll_power_rail_et                                            : integer := 0;
			atx_pll_powerdown_mode                                           : string  := "powerup_off";
			atx_pll_primary_use                                              : string  := "hssi_x1";
			atx_pll_prot_mode                                                : string  := "prot_off";
			atx_pll_reference_clock_frequency                                : string  := "1";
			atx_pll_regulator_bypass                                         : string  := "reg_enable";
			atx_pll_bcm_silicon_rev                                          : string  := "rev_off";
			atx_pll_sup_mode                                                 : string  := "sup_off";
			atx_pll_vccdreg_clk                                              : string  := "vreg_clk0";
			atx_pll_vccdreg_fb                                               : string  := "vreg_fb0";
			atx_pll_vccdreg_fw                                               : string  := "vreg_fw0";
			atx_pll_vco_freq                                                 : string  := "1";
			atx_pll_xatb_lccmu_atb                                           : string  := "atb_selectdisable";
			atx_pll_chgpmp_compensation                                      : string  := "cp_mode_enable";
			atx_pll_chgpmp_current_setting                                   : string  := "cp_current_setting0";
			atx_pll_cp_current_boost                                         : string  := "normal_setting";
			atx_pll_lf_3rd_pole_freq                                         : string  := "lf_3rd_pole_setting0";
			atx_pll_lf_cbig_size                                             : string  := "lf_cbig_setting0";
			atx_pll_lf_order                                                 : string  := "lf_2nd_order";
			atx_pll_lf_resistance                                            : string  := "lf_setting0";
			atx_pll_lf_ripplecap                                             : string  := "lf_ripple_cap_0";
			atx_pll_lc_sel_tank                                              : string  := "lctank0";
			atx_pll_lc_tank_band                                             : string  := "lc_band0";
			atx_pll_lc_tank_voltage_coarse                                   : string  := "vreg_setting_coarse0";
			atx_pll_lc_tank_voltage_fine                                     : string  := "vreg_setting5";
			atx_pll_output_regulator_supply                                  : string  := "vreg1v_setting3";
			atx_pll_overrange_voltage                                        : string  := "over_setting5";
			atx_pll_underrange_voltage                                       : string  := "under_setting4";
			atx_pll_xd2a_lc_d2a_voltage                                      : string  := "d2a_disable";
			atx_pll_dsm_mode                                                 : string  := "dsm_mode_integer";
			atx_pll_pll_dsm_out_sel                                          : string  := "pll_dsm_disable";
			atx_pll_pll_ecn_bypass                                           : string  := "pll_ecn_bypass_disable";
			atx_pll_pll_ecn_test_en                                          : string  := "pll_ecn_test_disable";
			atx_pll_dsm_fractional_division                                  : string  := "0";
			atx_pll_pll_fractional_value_ready                               : string  := "pll_k_ready";
			atx_pll_direct_fb                                                : string  := "direct_fb";
			atx_pll_iqclk_sel                                                : string  := "power_down";
			atx_pll_lcnt_bypass                                              : string  := "lcnt_no_bypass";
			atx_pll_lcnt_divide                                              : integer := 1;
			atx_pll_lcnt_off                                                 : string  := "lcnt_off";
			atx_pll_ref_clk_div                                              : integer := 1;
			atx_pll_silicon_rev                                              : string  := "14nm5cr2";
			atx_pll_is_cascaded_pll                                          : string  := "false";
			hssi_pma_lc_refclk_select_mux_powerdown_mode                     : string  := "powerup";
			hssi_pma_lc_refclk_select_mux_silicon_rev                        : string  := "14nm5cr2";
			hssi_pma_lc_refclk_select_mux_refclk_select                      : string  := "ref_iqclk0";
			hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping : string  := "ref_iqclk0";
			hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping : string  := "ref_iqclk0";
			hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping : string  := "ref_iqclk0";
			hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping : string  := "ref_iqclk0";
			hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping : string  := "ref_iqclk0";
			hssi_refclk_divider_silicon_rev                                  : string  := "14nm5cr2";
			hip_cal_en                                                       : string  := "disable";
			calibration_en                                                   : string  := "enable";
			enable_analog_resets                                             : integer := 0;
			enable_pcie_hip_connectivity                                     : integer := 0;
			enable_mcgb                                                      : integer := 0;
			enable_mcgb_reset                                                : integer := 0;
			enable_mcgb_debug_ports_parameters                               : integer := 0;
			hssi_pma_cgb_master_prot_mode                                    : string  := "";
			hssi_pma_cgb_master_silicon_rev                                  : string  := "";
			hssi_pma_cgb_master_x1_div_m_sel                                 : string  := "";
			hssi_pma_cgb_master_cgb_enable_iqtxrxclk                         : string  := "";
			hssi_pma_cgb_master_ser_mode                                     : string  := "";
			hssi_pma_cgb_master_datarate_bps                                 : string  := "";
			hssi_pma_cgb_master_cgb_power_down                               : string  := "normal_cgb";
			hssi_pma_cgb_master_observe_cgb_clocks                           : string  := "observe_nothing";
			hssi_pma_cgb_master_tx_ucontrol_reset_pcie                       : string  := "pcscorehip_controls_mcgb";
			hssi_pma_cgb_master_vccdreg_output                               : string  := "vccdreg_nominal";
			hssi_pma_cgb_master_input_select                                 : string  := "fpll_top";
			hssi_pma_cgb_master_input_select_gen3                            : string  := "not_used"
		);
		port (
			pll_refclk0             : in  std_logic                     := 'X';             -- clk
			tx_serial_clk           : out std_logic;                                        -- clk
			pll_locked              : out std_logic;                                        -- pll_locked
			pll_cal_busy            : out std_logic;                                        -- pll_cal_busy
			mcgb_serial_clk         : out std_logic;                                        -- clk
			pll_powerdown           : in  std_logic                     := 'X';             -- pll_powerdown
			pll_refclk1             : in  std_logic                     := 'X';             -- clk
			pll_refclk2             : in  std_logic                     := 'X';             -- clk
			pll_refclk3             : in  std_logic                     := 'X';             -- clk
			pll_refclk4             : in  std_logic                     := 'X';             -- clk
			tx_serial_clk_gxt       : out std_logic;                                        -- clk
			gxt_input_from_abv_atx  : in  std_logic                     := 'X';             -- clk
			gxt_input_from_blw_atx  : in  std_logic                     := 'X';             -- clk
			gxt_output_to_abv_atx   : out std_logic;                                        -- clk
			gxt_output_to_blw_atx   : out std_logic;                                        -- clk
			pll_locked_hip          : out std_logic;                                        -- pll_locked_hip
			pll_pcie_clk            : out std_logic;                                        -- pll_pcie_clk
			pll_cascade_clk         : out std_logic;                                        -- clk
			atx_to_fpll_cascade_clk : out std_logic;                                        -- clk
			reconfig_clk0           : in  std_logic                     := 'X';             -- clk
			reconfig_reset0         : in  std_logic                     := 'X';             -- reset
			reconfig_write0         : in  std_logic                     := 'X';             -- write
			reconfig_read0          : in  std_logic                     := 'X';             -- read
			reconfig_address0       : in  std_logic_vector(10 downto 0) := (others => 'X'); -- address
			reconfig_writedata0     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			reconfig_readdata0      : out std_logic_vector(31 downto 0);                    -- readdata
			reconfig_waitrequest0   : out std_logic;                                        -- waitrequest
			avmm_busy0              : out std_logic;                                        -- avmm_busy0
			hip_cal_done            : out std_logic;                                        -- hip_cal_done
			clklow                  : out std_logic;                                        -- clk
			fref                    : out std_logic;                                        -- clk
			overrange               : out std_logic;                                        -- debug
			underrange              : out std_logic;                                        -- debug
			mcgb_rst                : in  std_logic                     := 'X';             -- mcgb_rst
			mcgb_rst_stat           : out std_logic;                                        -- mcgb_rst_stat
			mcgb_aux_clk0           : in  std_logic                     := 'X';             -- tx_serial_clk
			mcgb_aux_clk1           : in  std_logic                     := 'X';             -- tx_serial_clk
			mcgb_aux_clk2           : in  std_logic                     := 'X';             -- tx_serial_clk
			tx_bonding_clocks       : out std_logic_vector(5 downto 0);                     -- clk
			pcie_sw                 : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- pcie_sw
			pcie_sw_done            : out std_logic_vector(1 downto 0);                     -- pcie_sw_done
			reconfig_clk1           : in  std_logic                     := 'X';             -- clk
			reconfig_reset1         : in  std_logic                     := 'X';             -- reset
			reconfig_write1         : in  std_logic                     := 'X';             -- write
			reconfig_read1          : in  std_logic                     := 'X';             -- read
			reconfig_address1       : in  std_logic_vector(10 downto 0) := (others => 'X'); -- address
			reconfig_writedata1     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			reconfig_readdata1      : out std_logic_vector(31 downto 0);                    -- readdata
			reconfig_waitrequest1   : out std_logic;                                        -- waitrequest
			mcgb_cal_busy           : out std_logic;                                        -- mcgb_cal_busy
			mcgb_hip_cal_done       : out std_logic                                         -- hip_cal_done
		);
	end component alt_mge_xcvr_atx_pll_10g_altera_xcvr_atx_pll_s10_htile_191_z7zd7fa_cmp;

	for xcvr_atx_pll_s10_htile_0 : alt_mge_xcvr_atx_pll_10g_altera_xcvr_atx_pll_s10_htile_191_z7zd7fa_cmp
		use entity altera_xcvr_atx_pll_s10_htile_191.alt_mge_xcvr_atx_pll_10g_altera_xcvr_atx_pll_s10_htile_191_z7zd7fa;
begin

	xcvr_atx_pll_s10_htile_0 : component alt_mge_xcvr_atx_pll_10g_altera_xcvr_atx_pll_s10_htile_191_z7zd7fa_cmp
		generic map (
			rcfg_enable                                                      => 0,
			rcfg_jtag_enable                                                 => 0,
			rcfg_separate_avmm_busy                                          => 0,
			dbg_embedded_debug_enable                                        => 0,
			dbg_capability_reg_enable                                        => 0,
			dbg_user_identifier                                              => 0,
			dbg_stat_soft_logic_enable                                       => 0,
			dbg_ctrl_soft_logic_enable                                       => 0,
			rcfg_emb_strm_enable                                             => 0,
			rcfg_profile_cnt                                                 => 2,
			hssi_avmm2_if_pcs_arbiter_ctrl                                   => "avmm2_arbiter_uc_sel",
			hssi_avmm2_if_pcs_cal_done                                       => "avmm2_cal_done_deassert",
			hssi_avmm2_if_pcs_cal_reserved                                   => 0,
			hssi_avmm2_if_pcs_calibration_feature_en                         => "avmm2_pcs_calibration_en",
			hssi_avmm2_if_pldadapt_gate_dis                                  => "disable",
			hssi_avmm2_if_pcs_hip_cal_en                                     => "disable",
			hssi_avmm2_if_hssiadapt_avmm_osc_clock_setting                   => "osc_clk_div_by1",
			hssi_avmm2_if_pldadapt_avmm_osc_clock_setting                    => "osc_clk_div_by1",
			hssi_avmm2_if_hssiadapt_avmm_testbus_sel                         => "avmm1_transfer_testbus",
			hssi_avmm2_if_pldadapt_avmm_testbus_sel                          => "avmm1_transfer_testbus",
			hssi_avmm2_if_hssiadapt_hip_mode                                 => "disable_hip",
			hssi_avmm2_if_pldadapt_hip_mode                                  => "disable_hip",
			hssi_avmm2_if_silicon_rev                                        => "14nm5bcr2eb",
			hssi_avmm2_if_calibration_type                                   => "one_time",
			atx_pll_analog_mode                                              => "user_custom",
			atx_pll_bonding                                                  => "cpri_bonding",
			atx_pll_bw_mode                                                  => "mid_bw",
			atx_pll_cascadeclk_test                                          => "cascadetest_off",
			atx_pll_cgb_div                                                  => 1,
			atx_pll_chgpmp_testmode                                          => "cp_normal",
			atx_pll_clk_high_perf_voltage                                    => 0,
			atx_pll_clk_low_power_voltage                                    => 0,
			atx_pll_clk_mid_power_voltage                                    => 0,
			atx_pll_datarate_bps                                             => "10312500000",
			atx_pll_device_variant                                           => "device_off",
			atx_pll_clk_vreg_boost_expected_voltage                          => 0,
			atx_pll_clk_vreg_boost_scratch                                   => 0,
			atx_pll_clk_vreg_boost_step_size                                 => 0,
			atx_pll_lc_vreg1_boost_expected_voltage                          => 0,
			atx_pll_lc_vreg1_boost_scratch                                   => 0,
			atx_pll_lc_vreg_boost_expected_voltage                           => 0,
			atx_pll_lc_vreg_boost_scratch                                    => 0,
			atx_pll_mcgb_vreg_boost_expected_voltage                         => 0,
			atx_pll_mcgb_vreg_boost_scratch                                  => 0,
			atx_pll_mcgb_vreg_boost_step_size                                => 0,
			atx_pll_pm_dprio_lc_dprio_status_select                          => "dprio_normal_status",
			atx_pll_vreg1_boost_step_size                                    => 0,
			atx_pll_vreg_boost_step_size                                     => 0,
			atx_pll_enable_hclk                                              => "false",
			atx_pll_expected_lc_boost_voltage                                => 0,
			atx_pll_f_max_lcnt_fpll_cascading                                => "1200000000",
			atx_pll_f_max_pfd                                                => "350000000",
			atx_pll_f_max_pfd_fractional                                     => "1",
			atx_pll_f_max_ref                                                => "800000000",
			atx_pll_f_max_tank_0                                             => "8800000000",
			atx_pll_f_max_tank_1                                             => "11400000000",
			atx_pll_f_max_tank_2                                             => "14400000000",
			atx_pll_f_max_vco                                                => "14400000000",
			atx_pll_f_max_vco_fractional                                     => "1",
			atx_pll_f_max_x1                                                 => "8700000000",
			atx_pll_f_min_pfd                                                => "61440000",
			atx_pll_f_min_ref                                                => "61440000",
			atx_pll_f_min_tank_0                                             => "6500000000",
			atx_pll_f_min_tank_1                                             => "8800000000",
			atx_pll_f_min_tank_2                                             => "11400000000",
			atx_pll_f_min_vco                                                => "7200000000",
			atx_pll_fpll_refclk_selection                                    => "select_vco_output",
			atx_pll_hclk_en                                                  => "hclk_disabled",
			atx_pll_initial_settings                                         => "true",
			atx_pll_is_otn                                                   => "false",
			atx_pll_is_sdi                                                   => "false",
			atx_pll_l_counter                                                => 2,
			atx_pll_lc_cal_reserved                                          => "lc_cal_reserved_off",
			atx_pll_lc_dyn_reconfig                                          => "lc_dyn_reconfig_off",
			atx_pll_lc_to_fpll_l_counter                                     => "lcounter_setting0",
			atx_pll_lc_to_fpll_l_counter_scratch                             => 0,
			atx_pll_lccmu_mode                                               => "lccmu_normal",
			atx_pll_lcpll_gt_in_sel                                          => "lc_gt_in_sel0",
			atx_pll_lcpll_gt_out_left_enb                                    => "lcpll_gt_out_left_dis",
			atx_pll_lcpll_gt_out_mid_enb                                     => "lcpll_gt_out_mid_dis",
			atx_pll_lcpll_gt_out_right_enb                                   => "lcpll_gt_out_right_dis",
			atx_pll_lcpll_lckdet_sel                                         => "lc_lckdet_sel0",
			atx_pll_max_fractional_percentage                                => 100,
			atx_pll_mcnt_divide                                              => 16,
			atx_pll_min_fractional_percentage                                => 0,
			atx_pll_n_counter                                                => 2,
			atx_pll_out_freq                                                 => "5156250000",
			atx_pll_pfd_delay_compensation                                   => "normal_delay",
			atx_pll_pfd_pulse_width                                          => "pulse_width_setting0",
			atx_pll_pma_width                                                => 64,
			atx_pll_power_mode                                               => "mid_power",
			atx_pll_power_rail_et                                            => 1030,
			atx_pll_powerdown_mode                                           => "powerup_off",
			atx_pll_primary_use                                              => "hssi_x1",
			atx_pll_prot_mode                                                => "basic_tx",
			atx_pll_reference_clock_frequency                                => "644531250",
			atx_pll_regulator_bypass                                         => "reg_enable",
			atx_pll_bcm_silicon_rev                                          => "rev_off",
			atx_pll_sup_mode                                                 => "user_mode",
			atx_pll_vccdreg_clk                                              => "vreg_clk5",
			atx_pll_vccdreg_fb                                               => "vreg_fb0",
			atx_pll_vccdreg_fw                                               => "vreg_fw5",
			atx_pll_vco_freq                                                 => "10312500000",
			atx_pll_xatb_lccmu_atb                                           => "atb_selectdisable",
			atx_pll_chgpmp_compensation                                      => "cp_mode_enable",
			atx_pll_chgpmp_current_setting                                   => "cp_current_setting23",
			atx_pll_cp_current_boost                                         => "normal_setting",
			atx_pll_lf_3rd_pole_freq                                         => "lf_3rd_pole_setting1",
			atx_pll_lf_cbig_size                                             => "lf_cbig_setting4",
			atx_pll_lf_order                                                 => "lf_3rd_order",
			atx_pll_lf_resistance                                            => "lf_setting1",
			atx_pll_lf_ripplecap                                             => "lf_ripple_cap_0",
			atx_pll_lc_sel_tank                                              => "lctank1",
			atx_pll_lc_tank_band                                             => "lc_band4",
			atx_pll_lc_tank_voltage_coarse                                   => "vreg_setting_coarse0",
			atx_pll_lc_tank_voltage_fine                                     => "vreg_setting5",
			atx_pll_output_regulator_supply                                  => "vreg1v_setting0",
			atx_pll_overrange_voltage                                        => "over_setting0",
			atx_pll_underrange_voltage                                       => "under_setting4",
			atx_pll_xd2a_lc_d2a_voltage                                      => "d2a_setting_4",
			atx_pll_dsm_mode                                                 => "dsm_mode_integer",
			atx_pll_pll_dsm_out_sel                                          => "pll_dsm_disable",
			atx_pll_pll_ecn_bypass                                           => "pll_ecn_bypass_disable",
			atx_pll_pll_ecn_test_en                                          => "pll_ecn_test_disable",
			atx_pll_dsm_fractional_division                                  => "1",
			atx_pll_pll_fractional_value_ready                               => "pll_k_ready",
			atx_pll_direct_fb                                                => "direct_fb",
			atx_pll_iqclk_sel                                                => "iqtxrxclk0",
			atx_pll_lcnt_bypass                                              => "lcnt_no_bypass",
			atx_pll_lcnt_divide                                              => 2,
			atx_pll_lcnt_off                                                 => "lcnt_on",
			atx_pll_ref_clk_div                                              => 2,
			atx_pll_silicon_rev                                              => "14nm5bcr2eb",
			atx_pll_is_cascaded_pll                                          => "false",
			hssi_pma_lc_refclk_select_mux_powerdown_mode                     => "powerup",
			hssi_pma_lc_refclk_select_mux_silicon_rev                        => "14nm5bcr2eb",
			hssi_pma_lc_refclk_select_mux_refclk_select                      => "ref_iqclk0",
			hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping => "ref_iqclk0",
			hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping => "power_down",
			hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping => "power_down",
			hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping => "power_down",
			hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping => "power_down",
			hssi_refclk_divider_silicon_rev                                  => "14nm5bcr2eb",
			hip_cal_en                                                       => "disable",
			calibration_en                                                   => "enable",
			enable_analog_resets                                             => 0,
			enable_pcie_hip_connectivity                                     => 0,
			enable_mcgb                                                      => 1,
			enable_mcgb_reset                                                => 0,
			enable_mcgb_debug_ports_parameters                               => 0,
			hssi_pma_cgb_master_prot_mode                                    => "basic_tx",
			hssi_pma_cgb_master_silicon_rev                                  => "14nm5bcr2eb",
			hssi_pma_cgb_master_x1_div_m_sel                                 => "divbypass",
			hssi_pma_cgb_master_cgb_enable_iqtxrxclk                         => "disable_iqtxrxclk",
			hssi_pma_cgb_master_ser_mode                                     => "sixty_four_bit",
			hssi_pma_cgb_master_datarate_bps                                 => "10312500000",
			hssi_pma_cgb_master_cgb_power_down                               => "normal_cgb",
			hssi_pma_cgb_master_observe_cgb_clocks                           => "observe_nothing",
			hssi_pma_cgb_master_tx_ucontrol_reset_pcie                       => "pcscorehip_controls_mcgb",
			hssi_pma_cgb_master_vccdreg_output                               => "vccdreg_nominal",
			hssi_pma_cgb_master_input_select                                 => "lcpll_top",
			hssi_pma_cgb_master_input_select_gen3                            => "not_used"
		)
		port map (
			pll_refclk0             => pll_refclk0,                        --     pll_refclk0.clk
			tx_serial_clk           => tx_serial_clk,                      --   tx_serial_clk.clk
			pll_locked              => pll_locked,                         --      pll_locked.pll_locked
			pll_cal_busy            => pll_cal_busy,                       --    pll_cal_busy.pll_cal_busy
			mcgb_serial_clk         => mcgb_serial_clk,                    -- mcgb_serial_clk.clk
			pll_powerdown           => '0',                                --     (terminated)
			pll_refclk1             => '0',                                --     (terminated)
			pll_refclk2             => '0',                                --     (terminated)
			pll_refclk3             => '0',                                --     (terminated)
			pll_refclk4             => '0',                                --     (terminated)
			tx_serial_clk_gxt       => open,                               --     (terminated)
			gxt_input_from_abv_atx  => '0',                                --     (terminated)
			gxt_input_from_blw_atx  => '0',                                --     (terminated)
			gxt_output_to_abv_atx   => open,                               --     (terminated)
			gxt_output_to_blw_atx   => open,                               --     (terminated)
			pll_locked_hip          => open,                               --     (terminated)
			pll_pcie_clk            => open,                               --     (terminated)
			pll_cascade_clk         => open,                               --     (terminated)
			atx_to_fpll_cascade_clk => open,                               --     (terminated)
			reconfig_clk0           => '0',                                --     (terminated)
			reconfig_reset0         => '0',                                --     (terminated)
			reconfig_write0         => '0',                                --     (terminated)
			reconfig_read0          => '0',                                --     (terminated)
			reconfig_address0       => "00000000000",                      --     (terminated)
			reconfig_writedata0     => "00000000000000000000000000000000", --     (terminated)
			reconfig_readdata0      => open,                               --     (terminated)
			reconfig_waitrequest0   => open,                               --     (terminated)
			avmm_busy0              => open,                               --     (terminated)
			hip_cal_done            => open,                               --     (terminated)
			clklow                  => open,                               --     (terminated)
			fref                    => open,                               --     (terminated)
			overrange               => open,                               --     (terminated)
			underrange              => open,                               --     (terminated)
			mcgb_rst                => '0',                                --     (terminated)
			mcgb_rst_stat           => open,                               --     (terminated)
			mcgb_aux_clk0           => '0',                                --     (terminated)
			mcgb_aux_clk1           => '0',                                --     (terminated)
			mcgb_aux_clk2           => '0',                                --     (terminated)
			tx_bonding_clocks       => open,                               --     (terminated)
			pcie_sw                 => "00",                               --     (terminated)
			pcie_sw_done            => open,                               --     (terminated)
			reconfig_clk1           => '0',                                --     (terminated)
			reconfig_reset1         => '0',                                --     (terminated)
			reconfig_write1         => '0',                                --     (terminated)
			reconfig_read1          => '0',                                --     (terminated)
			reconfig_address1       => "00000000000",                      --     (terminated)
			reconfig_writedata1     => "00000000000000000000000000000000", --     (terminated)
			reconfig_readdata1      => open,                               --     (terminated)
			reconfig_waitrequest1   => open,                               --     (terminated)
			mcgb_cal_busy           => open,                               --     (terminated)
			mcgb_hip_cal_done       => open                                --     (terminated)
		);

end architecture rtl; -- of alt_mge_xcvr_atx_pll_10g
