<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2020.01.29.11:16:40"
 outputDirectory="C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/phy/alt_usxgmii_phy/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Stratix 10"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="1SG165HU2F50E2VG"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="2"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CSR_CLK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CSR_CLK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CSR_CLK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_XGMII_RX_CORECLKIN_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_XGMII_RX_CORECLKIN_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_XGMII_RX_CORECLKIN_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_XGMII_TX_CORECLKIN_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_XGMII_TX_CORECLKIN_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_XGMII_TX_CORECLKIN_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_RX_CDR_REFCLK_1_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_RX_CDR_REFCLK_1_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_RX_CDR_REFCLK_1_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_RECONFIG_CLK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_RECONFIG_CLK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_RECONFIG_CLK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <interface name="csr_clk" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="csr_clk" direction="input" role="clk" width="1" />
  </interface>
  <interface name="xgmii_rx_coreclkin" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="xgmii_rx_coreclkin" direction="input" role="clk" width="1" />
  </interface>
  <interface name="xgmii_tx_coreclkin" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="xgmii_tx_coreclkin" direction="input" role="clk" width="1" />
  </interface>
  <interface name="reset" kind="reset" start="0">
   <property name="associatedClock" value="" />
   <property name="synchronousEdges" value="NONE" />
   <port name="reset" direction="input" role="reset" width="1" />
  </interface>
  <interface name="rx_digitalreset" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="rx_digitalreset"
       direction="input"
       role="rx_digitalreset"
       width="1" />
  </interface>
  <interface name="tx_digitalreset" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="tx_digitalreset"
       direction="input"
       role="tx_digitalreset"
       width="1" />
  </interface>
  <interface name="avalon_mm_csr" kind="avalon" start="0">
   <property name="addressAlignment" value="DYNAMIC" />
   <property name="addressGroup" value="0" />
   <property name="addressSpan" value="8192" />
   <property name="addressUnits" value="WORDS" />
   <property name="alwaysBurstMaxBurst" value="false" />
   <property name="associatedClock" value="csr_clk" />
   <property name="associatedReset" value="reset" />
   <property name="bitsPerSymbol" value="8" />
   <property name="bridgedAddressOffset" value="0" />
   <property name="bridgesToMaster" value="" />
   <property name="burstOnBurstBoundariesOnly" value="false" />
   <property name="burstcountUnits" value="WORDS" />
   <property name="constantBurstBehavior" value="false" />
   <property name="explicitAddressSpan" value="0" />
   <property name="holdTime" value="0" />
   <property name="interleaveBursts" value="false" />
   <property name="isBigEndian" value="false" />
   <property name="isFlash" value="false" />
   <property name="isMemoryDevice" value="false" />
   <property name="isNonVolatileStorage" value="false" />
   <property name="linewrapBursts" value="false" />
   <property name="maximumPendingReadTransactions" value="0" />
   <property name="maximumPendingWriteTransactions" value="0" />
   <property name="minimumReadLatency" value="1" />
   <property name="minimumResponseLatency" value="1" />
   <property name="minimumUninterruptedRunLength" value="1" />
   <property name="prSafe" value="false" />
   <property name="printableDevice" value="false" />
   <property name="readLatency" value="0" />
   <property name="readWaitStates" value="0" />
   <property name="readWaitTime" value="0" />
   <property name="registerIncomingSignals" value="false" />
   <property name="registerOutgoingSignals" value="false" />
   <property name="setupTime" value="0" />
   <property name="timingUnits" value="Cycles" />
   <property name="transparentBridge" value="false" />
   <property name="waitrequestAllowance" value="0" />
   <property name="wellBehavedWaitrequest" value="false" />
   <property name="writeLatency" value="0" />
   <property name="writeWaitStates" value="0" />
   <property name="writeWaitTime" value="0" />
   <port name="csr_readdata" direction="output" role="readdata" width="32" />
   <port name="csr_writedata" direction="input" role="writedata" width="32" />
   <port name="csr_address" direction="input" role="address" width="11" />
   <port
       name="csr_waitrequest"
       direction="output"
       role="waitrequest"
       width="1" />
   <port name="csr_read" direction="input" role="read" width="1" />
   <port name="csr_write" direction="input" role="write" width="1" />
  </interface>
  <interface name="xgmii_tx_valid" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="xgmii_tx_valid" direction="input" role="export" width="1" />
  </interface>
  <interface name="xgmii_tx_control" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="xgmii_tx_control" direction="input" role="export" width="4" />
  </interface>
  <interface name="xgmii_tx_data" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="xgmii_tx_data" direction="input" role="export" width="32" />
  </interface>
  <interface name="xgmii_rx_valid" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="xgmii_rx_valid" direction="output" role="export" width="1" />
  </interface>
  <interface name="xgmii_rx_control" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="xgmii_rx_control" direction="output" role="export" width="4" />
  </interface>
  <interface name="xgmii_rx_data" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="xgmii_rx_data" direction="output" role="export" width="32" />
  </interface>
  <interface name="led_an" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="led_an" direction="output" role="export" width="1" />
  </interface>
  <interface name="rx_block_lock" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="rx_block_lock"
       direction="output"
       role="rx_enh_blk_lock"
       width="1" />
  </interface>
  <interface name="operating_speed" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="operating_speed" direction="output" role="export" width="3" />
  </interface>
  <interface name="tx_serial_clk" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="tx_serial_clk" direction="input" role="clk" width="1" />
  </interface>
  <interface name="rx_cdr_refclk_1" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="rx_cdr_refclk_1" direction="input" role="clk" width="1" />
  </interface>
  <interface name="rx_pma_clkout" kind="clock" start="1">
   <property name="associatedDirectClock" value="" />
   <property name="clockRate" value="0" />
   <property name="clockRateKnown" value="false" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="rx_pma_clkout" direction="output" role="clk" width="1" />
  </interface>
  <interface name="tx_analogreset" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="tx_analogreset"
       direction="input"
       role="tx_analogreset"
       width="1" />
  </interface>
  <interface name="rx_analogreset" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="rx_analogreset"
       direction="input"
       role="rx_analogreset"
       width="1" />
  </interface>
  <interface name="tx_analogreset_stat" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="tx_analogreset_stat"
       direction="output"
       role="tx_analogreset_stat"
       width="1" />
  </interface>
  <interface name="rx_analogreset_stat" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="rx_analogreset_stat"
       direction="output"
       role="rx_analogreset_stat"
       width="1" />
  </interface>
  <interface name="tx_digitalreset_stat" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="tx_digitalreset_stat"
       direction="output"
       role="tx_digitalreset_stat"
       width="1" />
  </interface>
  <interface name="rx_digitalreset_stat" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="rx_digitalreset_stat"
       direction="output"
       role="rx_digitalreset_stat"
       width="1" />
  </interface>
  <interface name="tx_cal_busy" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="tx_cal_busy" direction="output" role="tx_cal_busy" width="1" />
  </interface>
  <interface name="rx_cal_busy" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="rx_cal_busy" direction="output" role="rx_cal_busy" width="1" />
  </interface>
  <interface name="tx_serial_data" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="tx_serial_data"
       direction="output"
       role="tx_serial_data"
       width="1" />
  </interface>
  <interface name="rx_serial_data" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="rx_serial_data"
       direction="input"
       role="rx_serial_data"
       width="1" />
  </interface>
  <interface name="rx_is_lockedtodata" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="rx_is_lockedtodata"
       direction="output"
       role="rx_is_lockedtodata"
       width="1" />
  </interface>
  <interface name="reconfig_clk" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="reconfig_clk" direction="input" role="clk" width="1" />
  </interface>
  <interface name="reconfig_reset" kind="reset" start="0">
   <property name="associatedClock" value="reconfig_clk" />
   <property name="synchronousEdges" value="DEASSERT" />
   <port name="reconfig_reset" direction="input" role="reset" width="1" />
  </interface>
  <interface name="reconfig_avmm" kind="avalon" start="0">
   <property name="addressAlignment" value="DYNAMIC" />
   <property name="addressGroup" value="0" />
   <property name="addressSpan" value="8192" />
   <property name="addressUnits" value="WORDS" />
   <property name="alwaysBurstMaxBurst" value="false" />
   <property name="associatedClock" value="reconfig_clk" />
   <property name="associatedReset" value="reconfig_reset" />
   <property name="bitsPerSymbol" value="8" />
   <property name="bridgedAddressOffset" value="0" />
   <property name="bridgesToMaster" value="" />
   <property name="burstOnBurstBoundariesOnly" value="false" />
   <property name="burstcountUnits" value="WORDS" />
   <property name="constantBurstBehavior" value="false" />
   <property name="explicitAddressSpan" value="0" />
   <property name="holdTime" value="0" />
   <property name="interleaveBursts" value="false" />
   <property name="isBigEndian" value="false" />
   <property name="isFlash" value="false" />
   <property name="isMemoryDevice" value="false" />
   <property name="isNonVolatileStorage" value="false" />
   <property name="linewrapBursts" value="false" />
   <property name="maximumPendingReadTransactions" value="0" />
   <property name="maximumPendingWriteTransactions" value="0" />
   <property name="minimumReadLatency" value="1" />
   <property name="minimumResponseLatency" value="1" />
   <property name="minimumUninterruptedRunLength" value="1" />
   <property name="prSafe" value="false" />
   <property name="printableDevice" value="false" />
   <property name="readLatency" value="0" />
   <property name="readWaitStates" value="1" />
   <property name="readWaitTime" value="1" />
   <property name="registerIncomingSignals" value="false" />
   <property name="registerOutgoingSignals" value="false" />
   <property name="setupTime" value="0" />
   <property name="timingUnits" value="Cycles" />
   <property name="transparentBridge" value="false" />
   <property name="waitrequestAllowance" value="0" />
   <property name="wellBehavedWaitrequest" value="false" />
   <property name="writeLatency" value="0" />
   <property name="writeWaitStates" value="0" />
   <property name="writeWaitTime" value="0" />
   <port name="reconfig_write" direction="input" role="write" width="1" />
   <port name="reconfig_read" direction="input" role="read" width="1" />
   <port name="reconfig_address" direction="input" role="address" width="11" />
   <port
       name="reconfig_writedata"
       direction="input"
       role="writedata"
       width="32" />
   <port
       name="reconfig_readdata"
       direction="output"
       role="readdata"
       width="32" />
   <port
       name="reconfig_waitrequest"
       direction="output"
       role="waitrequest"
       width="1" />
  </interface>
 </perimeter>
 <entity kind="alt_usxgmii_phy" version="1.0" name="alt_usxgmii_phy">
  <parameter name="AUTO_XGMII_RX_CORECLKIN_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_XGMII_TX_CORECLKIN_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_RX_CDR_REFCLK_1_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_GENERATION_ID" value="0" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Stratix 10" />
  <parameter name="AUTO_RECONFIG_CLK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_XGMII_RX_CORECLKIN_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_RECONFIG_CLK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_RX_CDR_REFCLK_1_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_XGMII_TX_CORECLKIN_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_XGMII_TX_CORECLKIN_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_RX_CDR_REFCLK_1_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
  <parameter name="AUTO_XGMII_RX_CORECLKIN_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_RECONFIG_CLK_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_DEVICE" value="1SG165HU2F50E2VG" />
  <parameter name="AUTO_CSR_CLK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_CSR_CLK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_CSR_CLK_CLOCK_DOMAIN" value="-1" />
  <generatedFiles>
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\synth\alt_usxgmii_phy.vhd"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\synth\alt_usxgmii_phy.vhd"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="C:/Users/mklee/AppData/Local/Temp/alt8290_6148029088922141087.dir/0002_alt_em10g32_0_gen/rtl/phy/alt_usxgmii_phy.ip" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="J:/programme/quartus/ip/altera/ethernet/alt_mge_phy/alt_mge_phy_hw.tcl" />
   <file
       path="J:/programme/quartus/ip/altera/ethernet/alt_mge_phy/alt_mge_phy_pcs_hw.tcl" />
   <file
       path="J:/programme/quartus/ip/altera/ethernet/alt_mge_phy/alt_mge_phy_xcvr_term_hw.tcl" />
   <file
       path="J:/programme/quartus/ip/altera/alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10_htile/tcl/altera_xcvr_native_s10_htile_hw.tcl" />
  </childSourceFiles>
  <messages>
   <message level="Info" culprit="alt_usxgmii_phy">"Generating: alt_usxgmii_phy"</message>
   <message level="Info" culprit="alt_usxgmii_phy">"Generating: alt_usxgmii_phy_alt_mge_phy_1930_yuuknna"</message>
   <message level="Info" culprit="alt_usxgmii_phy">"Generating: alt_mge_phy_pcs"</message>
   <message level="Info" culprit="alt_usxgmii_phy">"Generating: alt_mge16_phy_xcvr_term"</message>
   <message level="Info" culprit="alt_usxgmii_phy">"Generating: alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia"</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./altera_std_synchronizer_nocut.v VERILOG PATH ../../../../primitives/altera_std_synchronizer/altera_std_synchronizer_nocut.v</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_resync_std.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_generic/alt_xcvr_resync_std.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_reset_counter_s10.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_reset_control_s10/alt_xcvr_reset_counter_s10.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./altera_xcvr_native_s10_functions_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/altera_xcvr_native_s10_functions_h.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./s10_avmm_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/s10_avmm_h.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_avmm_csr.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_prbs_accum.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_prbs_accum.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_odi_accel.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_odi_accel.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_rcfg_arb.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_rcfg_arb.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_early_spd_chng_s10_htile.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_early_spd_chng_s10_htile.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_anlg_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_dig_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_dig_reset_seq.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_reset_seq.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_anlg_reset_seq_wrapper.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq_wrapper.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_re_cal_chnl.v VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_re_cal_chnl.v</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_pcie_rx_eios_prot.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_pcie_rx_eios_prot.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_rx_maib_wa.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_rx_maib_wa.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Building configuration data for reconfiguration profile 0</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Validating reconfiguration profile 0</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Current IP configuration matches reconfiguration profile 0</message>
   <message level="Info" culprit="alt_mge_xcvr_native">The TX PCS-Core Interface FIFO is operating in full-rate transfer mode.</message>
   <message level="Info" culprit="alt_mge_xcvr_native">The RX PCS-Core Interface FIFO is operating in full-rate transfer mode.</message>
   <message level="Info" culprit="alt_mge_xcvr_native">For the selected device(1SG165HU2F50E2VG), transceiver speed grade is 2 and core speed grade is 2.</message>
   <message level="Info" culprit="alt_mge_xcvr_native">For current configuration, TX PCS FIFO depth is "16" and TX Core FIFO depth is "16".</message>
   <message level="Info" culprit="alt_mge_xcvr_native">For current configuration, RX PCS FIFO depth is "16" and RX Core FIFO depth is "32".</message>
   <message level="Info" culprit="alt_mge_xcvr_native"><![CDATA[<b>"PCS clkout"</b> (pcs_clkout) is selected to drive tx_clkout port and the clock frequency is 322.265625 MHz.]]></message>
   <message level="Info" culprit="alt_mge_xcvr_native"><![CDATA[<b>"PCS clkout"</b> (pcs_clkout) is selected to drive rx_clkout port and the clock frequency is 322.265625 MHz.]]></message>
   <message level="Info" culprit="alt_mge_xcvr_native">"pma_div_clkout" is selected to drive rx_clkout2 port and it should not be used for register mode data transfers (Relevant parameter: "Selected rx_clkout2 clock source" (rx_clkout2_sel)).</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Design example cannot be generated for the current configuration. Please check under Design Example tab and system message below for more detailed information.</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Generating configuration files for reconfiguration profile 0</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Generating SystemVerilog configuration file</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Generating C header configuration file</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Generating MIF configuration file</message>
  </messages>
 </entity>
 <entity
   kind="alt_mge_phy"
   version="19.3.0"
   name="alt_usxgmii_phy_alt_mge_phy_1930_yuuknna">
  <parameter name="ANALOG_VOLTAGE" value="1_0V" />
  <parameter name="TX_PLL_CLOCK_NETWORK_1G" value="xN" />
  <parameter name="EXT_PHY_MGBASET" value="0" />
  <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
  <parameter name="DEVICE_FAMILY" value="Stratix 10" />
  <parameter name="CRETE_TILE" value="htile" />
  <parameter name="SHOW_HIDDEN_OPTIONS" value="0" />
  <parameter name="ENABLE_SGMII" value="0" />
  <parameter name="TX_PMA_CLK_DIV_1G" value="1" />
  <parameter name="REFCLK_FREQ_BASER" value="0" />
  <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
  <parameter name="SPEED_VARIANT" value="4" />
  <parameter name="DEFAULT_MODE" value="3" />
  <parameter name="ENABLE_IEEE1588" value="0" />
  <parameter name="EXCLUDE_NATIVE_PHY" value="0" />
  <parameter name="TX_PMA_CLK_DIV_2P5G" value="1" />
  <parameter name="XCVR_RCFG_JTAG_ENABLE" value="0" />
  <parameter name="DEVICE" value="1SG165HU2F50E2VG" />
  <parameter name="DEVICE_DIE_TYPES" value="HSSI_CRETE2E,MAIN_ND5" />
  <parameter name="XCVR_SET_ODI_SOFT_LOGIC_ENABLE" value="0" />
  <parameter name="BASE_DEVICE" value="ND5U" />
  <parameter name="TX_PLL_CLOCK_NETWORK_2P5G" value="xN" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
  <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE" value="0" />
  <parameter name="EXT_PHY_NBASET" value="1" />
  <parameter name="AUTO_DEVICE" value="1SG165HU2F50E2VG" />
  <parameter name="PHY_IDENTIFIER" value="0" />
  <parameter name="XCVR_SET_USER_IDENTIFIER" value="0" />
  <generatedFiles>
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_1930\synth\alt_usxgmii_phy_alt_mge_phy_1930_yuuknna.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_1930\synth\alt_usxgmii_phy_alt_mge_phy_1930_yuuknna.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="J:/programme/quartus/ip/altera/ethernet/alt_mge_phy/alt_mge_phy_hw.tcl" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="J:/programme/quartus/ip/altera/ethernet/alt_mge_phy/alt_mge_phy_pcs_hw.tcl" />
   <file
       path="J:/programme/quartus/ip/altera/ethernet/alt_mge_phy/alt_mge_phy_xcvr_term_hw.tcl" />
   <file
       path="J:/programme/quartus/ip/altera/alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10_htile/tcl/altera_xcvr_native_s10_htile_hw.tcl" />
  </childSourceFiles>
  <instantiator instantiator="alt_usxgmii_phy" as="alt_mge_phy_0" />
  <messages>
   <message level="Info" culprit="alt_usxgmii_phy">"Generating: alt_usxgmii_phy_alt_mge_phy_1930_yuuknna"</message>
   <message level="Info" culprit="alt_usxgmii_phy">"Generating: alt_mge_phy_pcs"</message>
   <message level="Info" culprit="alt_usxgmii_phy">"Generating: alt_mge16_phy_xcvr_term"</message>
   <message level="Info" culprit="alt_usxgmii_phy">"Generating: alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia"</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./altera_std_synchronizer_nocut.v VERILOG PATH ../../../../primitives/altera_std_synchronizer/altera_std_synchronizer_nocut.v</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_resync_std.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_generic/alt_xcvr_resync_std.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_reset_counter_s10.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_reset_control_s10/alt_xcvr_reset_counter_s10.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./altera_xcvr_native_s10_functions_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/altera_xcvr_native_s10_functions_h.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./s10_avmm_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/s10_avmm_h.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_avmm_csr.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_prbs_accum.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_prbs_accum.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_odi_accel.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_odi_accel.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_rcfg_arb.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_rcfg_arb.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_early_spd_chng_s10_htile.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_early_spd_chng_s10_htile.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_anlg_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_dig_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_dig_reset_seq.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_reset_seq.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_anlg_reset_seq_wrapper.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq_wrapper.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_re_cal_chnl.v VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_re_cal_chnl.v</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_pcie_rx_eios_prot.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_pcie_rx_eios_prot.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_rx_maib_wa.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_rx_maib_wa.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Building configuration data for reconfiguration profile 0</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Validating reconfiguration profile 0</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Current IP configuration matches reconfiguration profile 0</message>
   <message level="Info" culprit="alt_mge_xcvr_native">The TX PCS-Core Interface FIFO is operating in full-rate transfer mode.</message>
   <message level="Info" culprit="alt_mge_xcvr_native">The RX PCS-Core Interface FIFO is operating in full-rate transfer mode.</message>
   <message level="Info" culprit="alt_mge_xcvr_native">For the selected device(1SG165HU2F50E2VG), transceiver speed grade is 2 and core speed grade is 2.</message>
   <message level="Info" culprit="alt_mge_xcvr_native">For current configuration, TX PCS FIFO depth is "16" and TX Core FIFO depth is "16".</message>
   <message level="Info" culprit="alt_mge_xcvr_native">For current configuration, RX PCS FIFO depth is "16" and RX Core FIFO depth is "32".</message>
   <message level="Info" culprit="alt_mge_xcvr_native"><![CDATA[<b>"PCS clkout"</b> (pcs_clkout) is selected to drive tx_clkout port and the clock frequency is 322.265625 MHz.]]></message>
   <message level="Info" culprit="alt_mge_xcvr_native"><![CDATA[<b>"PCS clkout"</b> (pcs_clkout) is selected to drive rx_clkout port and the clock frequency is 322.265625 MHz.]]></message>
   <message level="Info" culprit="alt_mge_xcvr_native">"pma_div_clkout" is selected to drive rx_clkout2 port and it should not be used for register mode data transfers (Relevant parameter: "Selected rx_clkout2 clock source" (rx_clkout2_sel)).</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Design example cannot be generated for the current configuration. Please check under Design Example tab and system message below for more detailed information.</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Generating configuration files for reconfiguration profile 0</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Generating SystemVerilog configuration file</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Generating C header configuration file</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Generating MIF configuration file</message>
  </messages>
 </entity>
 <entity kind="alt_mge_phy_pcs" version="19.3.0" name="alt_mge_phy_pcs">
  <parameter name="EXT_PHY_MGBASET" value="0" />
  <parameter name="DEVICE_FAMILY" value="Stratix 10" />
  <parameter name="ENABLE_SGMII" value="0" />
  <parameter name="IS_MGBASE_T" value="0" />
  <parameter name="EXT_PHY_NBASET" value="1" />
  <parameter name="IS_1G_10G" value="0" />
  <parameter name="DEV_VERSION" value="4867" />
  <parameter name="IS_1G_2P5G" value="0" />
  <parameter name="SPEED_VARIANT" value="4" />
  <parameter name="PMA_MODE" value="32" />
  <parameter name="PHY_IDENTIFIER" value="0" />
  <parameter name="IS_10G_USXGMII" value="1" />
  <parameter name="IS_2P5G" value="0" />
  <parameter name="ENABLE_IEEE1588" value="0" />
  <generatedFiles>
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_async_fifo_fpga.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_bitsync.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_mbow_clock_crosser.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_pcs.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_pcs_csr_top.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_pcs_rst_sync.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_pipeline_base.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_std_synchronizer_bundle.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_an_top.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_creg_map.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_creg_top.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_incr_cnt.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_pcs.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_rx_64_to_32_wadpt.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_rx_data_derep.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_rx_rm_fifo.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_rx_rm_fifo_top.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_rx_top.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_tx_32_to_64_wadpt.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_tx_clockcomp_fifo.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_tx_data_mux.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_tx_data_rep.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_tx_top.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_umii_fault.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_xgmii_1588_latency.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_xgmii_1588_ppm_counter.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_xgmii_clockcomp.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_xgmii_pcs.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_xgmii_rx_fifo.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_xgmii_soft_fifo.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_1588_ppm_counter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_a_fifo_24.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_carrier_sense.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_clock_crosser.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_colision_detect.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_control.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_gray_cnt.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_gxb_aligned_rxsync.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_host_control.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_mdio_reg.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_mii_rx_if_pcs.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_mii_tx_if_pcs.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_ph_calculator.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_pma_gige.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_pma.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_reset_synchronizer.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_rx_converter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_rx_encapsulation_strx_gx.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_rx_fifo_rd.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_sdpm_altsyncram.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_sgmii_clk_enable.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_std_synchronizer.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_top_1000_base_x_strx_gx.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_top_autoneg.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_top_pcs_strx_gx.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_top_rx_converter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_top_sgmii_strx_gx.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_top_tx_converter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_tx_converter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_tx_encapsulation.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_xcvr_resync.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_xcvr_latency_pulse_measurement.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\latency_pulse_measurement.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_sgmii_8_to_16_converter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_sgmii_16_to_8_converter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxgmii_1588_latency.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\altera_std_synchronizer_nocut.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_pcs.ocp"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_pcs.sdc"
       attributes="NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\debug\stp\build_stp.tcl"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\debug\stp\base_stp_1G2p5G10GPHY.xml"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_async_fifo_fpga.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_bitsync.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_mbow_clock_crosser.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_pcs.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_pcs_csr_top.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_pcs_rst_sync.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_pipeline_base.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_std_synchronizer_bundle.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_an_top.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_creg_map.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_creg_top.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_incr_cnt.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_pcs.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_rx_64_to_32_wadpt.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_rx_data_derep.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_rx_rm_fifo.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_rx_rm_fifo_top.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_rx_top.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_tx_32_to_64_wadpt.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_tx_clockcomp_fifo.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_tx_data_mux.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_tx_data_rep.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_tx_top.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_umii_fault.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_xgmii_1588_latency.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_xgmii_1588_ppm_counter.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_xgmii_clockcomp.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_xgmii_pcs.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_xgmii_rx_fifo.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_xgmii_soft_fifo.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_1588_ppm_counter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_a_fifo_24.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_carrier_sense.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_clock_crosser.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_colision_detect.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_control.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_gray_cnt.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_gxb_aligned_rxsync.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_host_control.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_mdio_reg.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_mii_rx_if_pcs.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_mii_tx_if_pcs.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_ph_calculator.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_pma_gige.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_pma.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_reset_synchronizer.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_rx_converter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_rx_encapsulation_strx_gx.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_rx_fifo_rd.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_sdpm_altsyncram.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_sgmii_clk_enable.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_std_synchronizer.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_top_1000_base_x_strx_gx.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_top_autoneg.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_top_pcs_strx_gx.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_top_rx_converter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_top_sgmii_strx_gx.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_top_tx_converter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_tx_converter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_tx_encapsulation.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_xcvr_resync.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_xcvr_latency_pulse_measurement.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\latency_pulse_measurement.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_sgmii_8_to_16_converter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge16_pcs_sgmii_16_to_8_converter.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxgmii_1588_latency.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\altera_std_synchronizer_nocut.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_pcs.ocp"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\alt_mge_phy_usxg32_pcs.sdc"
       attributes="NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\debug\stp\build_stp.tcl"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_pcs_1930\synth\debug\stp\base_stp_1G2p5G10GPHY.xml"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="J:/programme/quartus/ip/altera/ethernet/alt_mge_phy/alt_mge_phy_pcs_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="alt_usxgmii_phy_alt_mge_phy_1930_yuuknna" as="mge_pcs" />
  <messages>
   <message level="Info" culprit="alt_usxgmii_phy">"Generating: alt_mge_phy_pcs"</message>
  </messages>
 </entity>
 <entity
   kind="alt_mge_phy_xcvr_term"
   version="19.3.0"
   name="alt_mge16_phy_xcvr_term">
  <parameter name="EXCLUDE_NATIVE_PHY" value="0" />
  <parameter name="EXT_PHY_MGBASET" value="0" />
  <parameter name="DEVICE_FAMILY" value="Stratix 10" />
  <parameter name="IS_MGBASE_T" value="0" />
  <parameter name="EXT_PHY_NBASET" value="1" />
  <parameter name="IS_1G_10G" value="0" />
  <parameter name="IS_1G_2P5G" value="0" />
  <parameter name="SPEED_VARIANT" value="4" />
  <parameter name="BASER_REG_MODE" value="1" />
  <parameter name="IS_10G_USXGMII" value="1" />
  <parameter name="IS_2P5G" value="0" />
  <parameter name="ENABLE_RX_PIPELINE" value="1" />
  <parameter name="ENABLE_IEEE1588" value="0" />
  <generatedFiles>
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_xcvr_term_1930\synth\alt_mge_phy_gf_clock_mux.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_xcvr_term_1930\synth\alt_mge16_phy_xcvr_term.v"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_xcvr_term_1930\synth\alt_mge_phy_gf_clock_mux.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\alt_mge_phy_xcvr_term_1930\synth\alt_mge16_phy_xcvr_term.v"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="J:/programme/quartus/ip/altera/ethernet/alt_mge_phy/alt_mge_phy_xcvr_term_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="alt_usxgmii_phy_alt_mge_phy_1930_yuuknna"
     as="xcvr_term" />
  <messages>
   <message level="Info" culprit="alt_usxgmii_phy">"Generating: alt_mge16_phy_xcvr_term"</message>
  </messages>
 </entity>
 <entity
   kind="altera_xcvr_native_s10_htile"
   version="19.2.1"
   name="alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia">
  <parameter name="l_pcs_channel_enable_hard_reset" value="0" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_st_rst"
     value="aib_rx_dcc_st_rst_setting0" />
  <parameter name="pma_rx_buf_ctle_eq_gain" value="0" />
  <parameter name="enable_port_tx_enh_frame" value="0" />
  <parameter name="enh_tx_64b66b_enable" value="1" />
  <parameter name="pma_rx_buf_reserve_rx_channel" value="false" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_st_rst"
     value="aib_dllstr_align_st_rst_setting0" />
  <parameter name="pma_adapt_adp_rstn" value="radp_rstn_1" />
  <parameter name="enable_port_tx_fifo_pempty" value="0" />
  <parameter name="hssi_10g_tx_pcs_frmgen_wordslip" value="frmgen_wordslip_dis" />
  <parameter name="l_rx_hssi_aib_indv" value="indv_en" />
  <parameter name="cdr_pll_side" value="side_off" />
  <parameter name="hssi_adapt_tx_tx_fifo_power_mode" value="full_width_full_depth" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_hip_en"
     value="disable" />
  <parameter name="hssi_aibcr_tx_aib_inctrl_gr3" value="aib_inctrl3_setting2" />
  <parameter
     name="pma_tx_buf_powermode_ac_tx_vod_no_jitcomp"
     value="tx_vod_no_jitcomp_ac_l0" />
  <parameter name="hssi_aibcr_tx_aib_inctrl_gr2" value="aib_inctrl2_setting2" />
  <parameter name="pma_rx_dfe_oc_sa_cdrno" value="0" />
  <parameter name="hssi_aibcr_rx_aib_outndrv_r56" value="aib_ndrv56_setting1" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs10g_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter name="hssi_aibcr_tx_aib_inctrl_gr1" value="aib_inctrl1_setting3" />
  <parameter name="hssi_aibcr_tx_aib_inctrl_gr0" value="aib_inctrl0_setting1" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_st_lockreq_muxsel"
     value="aib_rx_dcc_st_lockreq_muxsel_setting0" />
  <parameter name="pma_rx_buf_powermode_dc_aoc" value="powerdown_aoc" />
  <parameter name="pma_cgb_ser_powerdown" value="normal_poweron_ser" />
  <parameter name="hssi_fifo_rx_pcs_prot_mode" value="teng_mode" />
  <parameter name="cdr_pll_bw_mode" value="mid_bw" />
  <parameter
     name="design_example_tx_pll_kind"
     value="altera_xcvr_atx_pll_s10_htile" />
  <parameter name="hssi_10g_tx_pcs_distdwn_master" value="distdwn_master_en" />
  <parameter name="pma_rx_buf_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="enable_port_rx_enh_frame_lock" value="0" />
  <parameter
     name="cdr_pll_chgpmp_up_pd_trim_double"
     value="normal_up_trim_current" />
  <parameter name="hssi_pldadapt_rx_asn_wait_for_dll_reset_cnt" value="64" />
  <parameter name="hssi_pldadapt_tx_frmgen_mfrm_length" value="2048" />
  <parameter name="l_rx_core_aib_indv" value="indv_en" />
  <parameter
     name="pma_adapt_adp_ac_ctle_mode_sel"
     value="radp_ac_ctle_mode_sel_concurrent" />
  <parameter name="pma_rx_dfe_oc_sa_cdrne" value="0" />
  <parameter name="l_std_rx_pld_pcs_width" value="10" />
  <parameter name="pma_rx_dfe_tap3_coeff" value="0" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_prot_mode_rx"
     value="teng_krfec_mode_rx" />
  <parameter
     name="hssi_tx_pcs_pma_interface_pldif_datawidth_mode"
     value="pldif_data_10bit" />
  <parameter name="enable_port_rx_polinv" value="0" />
  <parameter name="hssi_adapt_rx_hd_hssiadapt_csr_clk_hz" value="0" />
  <parameter name="pma_tx_buf_enable_idle_tx_channel_support" value="false" />
  <parameter name="hssi_krfec_tx_pcs_pipeln_scrambler" value="enable" />
  <parameter name="enable_rx_fast_pipeln_reg" value="0" />
  <parameter name="hssi_pldadapt_rx_free_run_div_clk" value="out_of_reset_sync" />
  <parameter name="hssi_8g_rx_pcs_hip_mode" value="dis_hip" />
  <parameter name="hssi_10g_tx_pcs_compin_sel" value="compin_master" />
  <parameter
     name="pma_adapt_adp_dc_ctle_hold_en"
     value="radp_dc_ctle_hold_en_not_hold" />
  <parameter name="pma_rx_buf_term_sel" value="r_r4" />
  <parameter
     name="pma_rx_deser_pm_cr2_tx_rx_pcie_gen_bitwidth"
     value="pcie_gen3_32b" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs10g_advanced_user_mode_tx"
     value="disable" />
  <parameter
     name="hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en"
     value="hip_rx_disable" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_rx_clk_hz"
     value="0" />
  <parameter name="base_device" value="Unknown" />
  <parameter
     name="hssi_10g_tx_pcs_enc64b66b_txsm_clken"
     value="enc64b66b_txsm_clk_en" />
  <parameter name="hssi_rx_pld_pcs_interface_pcs_rx_block_sel" value="teng" />
  <parameter name="pma_cgb_x1_clock_source_sel" value="lcpll_top" />
  <parameter name="hssi_adapt_rx_rx_txeq_en" value="disable" />
  <parameter name="pma_cgb_uc_vcc_setting" value="vcc_setting1" />
  <parameter name="hssi_10g_rx_pcs_rxfifo_pfull" value="23" />
  <parameter name="hssi_adapt_rx_rx_pre_cursor_en" value="disable" />
  <parameter name="pma_tx_buf_term_p_tune" value="rterm_p7" />
  <parameter name="enh_rx_dispchk_enable" value="0" />
  <parameter name="pma_rx_deser_pcie_g3_hclk_en" value="disable_hclk_div2" />
  <parameter name="pma_rx_deser_powermode_ac_deser_bs" value="deser_ac_bs_off" />
  <parameter name="set_embedded_debug_enable" value="0" />
  <parameter
     name="hssi_adapt_rx_fsr_pld_10g_rx_crc32_err_rst_val"
     value="reset_to_zero_crc32" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period"
     value="uhsif_dcn_test_period_4" />
  <parameter name="hssi_10g_rx_pcs_frmsync_bypass" value="frmsync_bypass_en" />
  <parameter name="pma_rx_dfe_oc_sa_cdrpo" value="0" />
  <parameter name="hssi_pldadapt_tx_txfifo_pfull" value="10" />
  <parameter name="hssi_adapt_tx_fifo_ready_bypass" value="disable" />
  <parameter name="hssi_10g_rx_pcs_rx_sm_pipeln" value="rx_sm_pipeln_en" />
  <parameter name="pma_rx_dfe_oc_sa_odie_sgn" value="oc_sa_odie_sgn_0" />
  <parameter name="cdr_pll_clk90_dfe_tfall_adj" value="clk90_dfe_tf0" />
  <parameter
     name="hssi_pldadapt_rx_hdpldadapt_aib_fabric_pld_pma_hclk_hz"
     value="0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_low_latency_en_tx"
     value="disable" />
  <parameter name="l_rcfg_ifaces" value="1" />
  <parameter name="anlg_link" value="sr" />
  <parameter name="pma_rx_buf_vcm_sel" value="vcm_l1" />
  <parameter name="pma_tx_ser_bonding_mode" value="bond_off" />
  <parameter name="hssi_pipe_gen1_2_rpre_emph_a_val" value="0" />
  <parameter name="can_gen_exdesign_basic_enh" value="1" />
  <parameter name="pma_rx_buf_rx_pin_as_refclk_mode" value="false" />
  <parameter name="hssi_krfec_rx_pcs_parity_invalid_enum" value="8" />
  <parameter name="tx_output_swing_message" value="" />
  <parameter name="pma_rx_dfe_oc_sa_cdrpe" value="0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_pcs_tx_data_source"
     value="hip_disable" />
  <parameter name="tx_pma_div_clkout_divider" value="33" />
  <parameter name="cdr_pll_vreg_output" value="vccdreg_nominal" />
  <parameter name="usr_rx_dv_mode" value="enable" />
  <parameter name="pma_adapt_adp_po_sleep_win" value="radp_po_sleep_win_2_sec" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs10g_fifo_mode_tx"
     value="reg_tx" />
  <parameter name="enable_direct_reset_control" value="0" />
  <parameter name="enable_ehip" value="0" />
  <parameter name="hssi_adapt_rx_fifo_mode" value="phase_comp" />
  <parameter name="hssi_8g_rx_pcs_clock_gate_pc_rdclk" value="en_pc_rdclk_gating" />
  <parameter name="hssi_8g_rx_pcs_phase_comp_rdptr" value="disable_rdptr" />
  <parameter name="hssi_pldadapt_rx_pipe_enable" value="disable" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_pcs_refclk_dig_nonatpg_mode_clk_hz"
     value="0" />
  <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_st_rst_prgmnvrt"
     value="aib_dllstr_align_st_rst_prgmnvrt_setting0" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_manual_dn"
     value="aib_tx_dcc_manual_dn0" />
  <parameter name="cdr_pll_cal_vco_count_length" value="sel_8b_count" />
  <parameter name="cdr_pll_set_cdr_vco_reset" value="vco_normal" />
  <parameter name="hssi_aibcr_rx_aib_rx_selflock" value="aib_rx_selflock_enable" />
  <parameter name="enable_port_rx_fifo_pempty" value="0" />
  <parameter name="display_std_tx_pld_adapt_width" value="8" />
  <parameter name="hssi_avmm1_if_hssiadapt_sr_sup_mode" value="user_mode" />
  <parameter name="hssi_pldadapt_tx_osc_clk_scg_en" value="disable" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_entest"
     value="aib_dllstr_align_test_disable" />
  <parameter name="cdr_pll_f_max_ref" value="800000000" />
  <parameter name="hssi_8g_rx_pcs_wa_clk_slip_spacing" value="16" />
  <parameter
     name="hssi_common_pcs_pma_interface_dft_observation_clock_selection"
     value="dft_clk_obsrv_tx0" />
  <parameter name="hssi_10g_rx_pcs_low_latency_en" value="disable" />
  <parameter name="hssi_aibcr_rx_aib_outndrv_r12" value="aib_ndrv12_setting1" />
  <parameter name="l_adapt_mode_manual" value="1" />
  <parameter name="hssi_adapt_rx_rx_osc_clock_setting" value="osc_clk_div_by1" />
  <parameter name="hssi_adapt_rx_rxfifo_pempty" value="2" />
  <parameter name="hssi_adapt_tx_txfifo_pfull" value="5" />
  <parameter name="hssi_pldadapt_tx_word_align_enable" value="enable" />
  <parameter name="dbg_embedded_debug_enable" value="0" />
  <parameter name="std_rx_word_aligner_pattern" value="0" />
  <parameter name="pma_tx_buf_dcd_clk_div_ctrl" value="dcd_ck_div128" />
  <parameter name="pma_rx_deser_bti_protected" value="false" />
  <parameter name="hssi_krfec_rx_pcs_pipeln_errtrap_ind" value="enable" />
  <parameter
     name="hssi_pldadapt_rx_rxfiford_post_ct_sel"
     value="rxfiford_sclk_post_ct" />
  <parameter name="hssi_pldadapt_tx_sup_mode" value="user_mode" />
  <parameter
     name="hssi_avmm1_if_hssiadapt_avmm_osc_clock_setting"
     value="osc_clk_div_by1" />
  <parameter name="pma_adapt_powermode_dc_adaptation" value="powerdown_adapt" />
  <parameter name="pma_tx_buf_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
  <parameter name="pma_tx_buf_uc_gen4" value="gen4_off" />
  <parameter name="hssi_pldadapt_rx_rx_fifo_write_latency_adjust" value="disable" />
  <parameter name="pma_tx_buf_uc_gen3" value="gen3_off" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable"
     value="uhsif_dcn_test_mode_disable" />
  <parameter name="hssi_adapt_rx_rx_adp_go_b4txeq_en" value="enable" />
  <parameter
     name="hssi_pipe_gen3_phystatus_rst_toggle_g3"
     value="dis_phystatus_rst_toggle_g3" />
  <parameter name="hssi_tx_pcs_pma_interface_sq_wave_num" value="sq_wave_default" />
  <parameter name="hssi_8g_rx_pcs_rx_refclk" value="dis_refclk_sel" />
  <parameter name="hssi_krfec_rx_pcs_receive_order" value="receive_lsb" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs8g_prot_mode_tx"
     value="disabled_prot_mode_tx" />
  <parameter name="pma_rx_dfe_tap4_sgn" value="tap4_sign_0" />
  <parameter name="hssi_pipe_gen1_2_phystatus_delay_val" value="0" />
  <parameter name="hssi_8g_rx_pcs_rx_rcvd_clk" value="rcvd_clk_rcvd_clk" />
  <parameter name="hssi_common_pcs_pma_interface_ignore_sigdet_g23" value="false" />
  <parameter name="silicon_revision" value="14nm5bcr2eb" />
  <parameter name="hssi_pldadapt_rx_fifo_wr_clk_scg_en" value="disable" />
  <parameter name="pma_rx_dfe_pdb_tap_4t9" value="tap4t9_dfe_powerdown" />
  <parameter name="hssi_pldadapt_tx_ds_master" value="ds_master_en" />
  <parameter name="pma_adapt_adp_po_startpos" value="radp_po_startpos_6ov7" />
  <parameter
     name="hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en"
     value="false" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_test_clk_pll_en_n"
     value="aib_dllstr_align_test_clk_pll_en_n_disable" />
  <parameter name="hssi_krfec_rx_pcs_pipeln_errtrap_lfsr" value="disable" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter name="hssi_rx_pcs_pma_interface_clkslip_sel" value="pld" />
  <parameter name="hssi_pldadapt_rx_comp_cnt" value="0" />
  <parameter
     name="hssi_pldadapt_tx_hdpldadapt_pld_tx_clk1_dcm_hz"
     value="156250000" />
  <parameter name="set_odi_soft_logic_enable" value="0" />
  <parameter name="hssi_adapt_rx_pma_coreclkin_sel" value="pma_coreclkin_pld_sel" />
  <parameter name="pma_rx_dfe_tap8_coeff" value="0" />
  <parameter
     name="pma_cdr_refclk_inclk3_logical_to_physical_mapping"
     value="ref_iqclk0" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_power_mode" value="mid_power" />
  <parameter name="hssi_common_pcs_pma_interface_pc_en_counter" value="0" />
  <parameter name="cdr_pll_powermode_dc_rvcotop" value="rvcotop_dc_div2" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin"
     value="uhsif_dcn_margin_2" />
  <parameter name="hssi_pldadapt_rx_rx_osc_clock_setting" value="osc_clk_div_by1" />
  <parameter name="pma_cgb_sup_mode" value="user_mode" />
  <parameter name="hssi_8g_tx_pcs_tx_bitslip" value="dis_tx_bitslip" />
  <parameter name="pma_rx_buf_diag_lp_en" value="dlp_off" />
  <parameter name="pma_rx_buf_vga_dc_gain" value="0" />
  <parameter name="can_gen_exdesign_pcie_pipe" value="1" />
  <parameter name="hssi_krfec_rx_pcs_reconfig_settings" value="{}" />
  <parameter
     name="hssi_aibcr_tx_aib_red_dtx_shiften"
     value="aib_red_dtx_shift_disable" />
  <parameter name="hssi_10g_rx_pcs_rxfifo_mode" value="register_mode" />
  <parameter name="hssi_8g_tx_pcs_hip_mode" value="dis_hip" />
  <parameter name="hssi_10g_tx_pcs_gb_tx_odwidth" value="odwidth_32" />
  <parameter name="hssi_8g_rx_pcs_auto_speed_nego" value="dis_asn" />
  <parameter name="pma_rx_dfe_pdb_edge_pre_h1" value="cdr_pre_h1_enable" />
  <parameter name="pma_tx_ser_duty_cycle_correction_mode_ctrl" value="dcc_disable" />
  <parameter name="pma_tx_buf_term_sel" value="r_r1" />
  <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
  <parameter name="pma_rx_sd_optimal" value="true" />
  <parameter name="hssi_adapt_rx_rxfiford_to_aib_sel" value="rxfiford_sclk_to_aib" />
  <parameter
     name="hssi_pldadapt_tx_hdpldadapt_aib_fabric_pma_aib_tx_clk_hz"
     value="644531250" />
  <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
  <parameter name="hssi_krfec_rx_pcs_ctrl_bit_reverse" value="ctrl_bit_reverse_en" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter name="std_rx_word_aligner_mode" value="synchronous state machine" />
  <parameter name="hssi_10g_rx_pcs_fec_enable" value="fec_dis" />
  <parameter name="generate_docs" value="1" />
  <parameter
     name="hssi_pldadapt_tx_fsr_hip_fsr_out_bit0_rst_val"
     value="reset_to_one_hfsrout0" />
  <parameter name="hssi_10g_tx_pcs_sup_mode" value="user_mode" />
  <parameter name="cdr_pll_auto_reset_on" value="auto_reset_off" />
  <parameter name="hssi_pldadapt_rx_powerdown_mode" value="powerup" />
  <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
  <parameter name="pma_adapt_adp_force_freqlock" value="radp_force_freqlock_use" />
  <parameter
     name="cdr_pll_bbpd_data_pattern_filter_select"
     value="bbpd_data_pat_off" />
  <parameter name="pma_rx_dfe_dfe_mode" value="cdr_mode" />
  <parameter name="enable_port_tx_pcs_fifo_empty" value="0" />
  <parameter name="hssi_10g_tx_pcs_fifo_stop_wr" value="n_wr_full" />
  <parameter
     name="hssi_adapt_rx_rx_pld_8g_wa_boundary_polling_bypass"
     value="disable" />
  <parameter
     name="pma_adapt_powermode_dc_deser_adapt"
     value="powerdown_adapt_deser" />
  <parameter name="hip_cal_en" value="disable" />
  <parameter name="hssi_10g_tx_pcs_random_disp" value="disable" />
  <parameter name="hssi_adapt_rx_internal_clk2_sel3" value="pma_clks_clk2_mux3" />
  <parameter name="pma_rx_dfe_tap15_coeff" value="0" />
  <parameter name="l_crete_nf" value="0" />
  <parameter
     name="hssi_adapt_rx_internal_clk2_sel0"
     value="pma_clks_or_rxfiford_post_ct_or_rxfifowr_pre_or_post_ct_mux_clk2_mux0" />
  <parameter name="hssi_10g_tx_pcs_scrm_pipeln" value="enable" />
  <parameter
     name="hssi_adapt_rx_internal_clk2_sel2"
     value="pma_clks_or_rxfifowr_pre_ct_mux_clk2_mux2" />
  <parameter
     name="hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt"
     value="enum_invalid_sh_cnt_10g" />
  <parameter
     name="hssi_adapt_rx_internal_clk2_sel1"
     value="pma_clks_or_rxfifowr_pre_or_post_ct_mux_clk2_mux1" />
  <parameter
     name="hssi_pldadapt_tx_hdpldadapt_pld_tx_clk1_rowclk_hz"
     value="156250000" />
  <parameter name="hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn" value="disable" />
  <parameter name="pma_rx_buf_dfe_h1_cal_en" value="dfe_h1_cal_disable" />
  <parameter name="adme_enable_bg_cal" value="0" />
  <parameter name="hssi_common_pcs_pma_interface_sim_mode" value="disable" />
  <parameter name="hssi_aibcr_tx_redundancy_en" value="disable" />
  <parameter name="pma_tx_buf_powermode_ac_pre_tap" value="tx_pre_tap_ac_off" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_selflock"
     value="aib_dllstr_align_selflock_enable" />
  <parameter name="pma_tx_buf_dcd_detection_en" value="disable" />
  <parameter name="pma_adapt_adp_vga_bypass" value="radp_vga_bypass_bypass" />
  <parameter name="hssi_pldadapt_tx_fifo_rd_clk_frm_gen_scg_en" value="enable" />
  <parameter name="l_tx_adapt_pcs_width" value="66" />
  <parameter name="hssi_pipe_gen1_2_txswing" value="dis_txswing" />
  <parameter name="hssi_adapt_tx_us_master" value="us_master_en" />
  <parameter name="hssi_adapt_tx_presethint_bypass" value="enable" />
  <parameter name="data_rate_bps" value="10312500000" />
  <parameter name="tx_pma_pre_emp_switching_ctrl_1st_post_tap" value="0" />
  <parameter
     name="pma_cdr_refclk_inclk0_logical_to_physical_mapping"
     value="ref_iqclk0" />
  <parameter name="cdr_pll_set_cdr_v2i_enable" value="enable_v2i_bias" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs8g_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter name="pma_rx_dfe_odi_dlev_sign" value="odi_dlev_pos" />
  <parameter name="pma_cgb_input_select_gen3" value="not_used" />
  <parameter name="pma_mode" value="basic" />
  <parameter name="hssi_pldadapt_tx_dv_gen" value="dv_gen_dis" />
  <parameter name="hssi_8g_rx_pcs_wa_rknumber_data" value="3" />
  <parameter name="pma_rx_dfe_tap10_coeff" value="0" />
  <parameter name="adme_pma_mode" value="basic" />
  <parameter name="hssi_tx_pld_pcs_interface_hd_pcs8g_fifo_mode_tx" value="reg_tx" />
  <parameter
     name="pma_adapt_adp_dc_ctle_initial_load"
     value="radp_dc_ctle_initial_load_0" />
  <parameter name="hssi_8g_rx_pcs_tx_rx_parallel_loopback" value="dis_plpbk" />
  <parameter name="enable_port_tx_clkout_hioint" value="0" />
  <parameter name="pma_rx_dfe_initial_settings" value="true" />
  <parameter name="pma_tx_buf_calibration_en" value="false" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_shared_fifo_width_rx"
     value="single_rx" />
  <parameter name="hssi_10g_tx_pcs_fifo_stop_rd" value="n_rd_empty" />
  <parameter
     name="hssi_avmm1_if_hssiadapt_nfhssi_calibratio_feature_en"
     value="disable" />
  <parameter name="pma_rx_buf_pdb_rx" value="normal_rx_on" />
  <parameter name="pma_rx_dfe_oc_sa_cdrno_sgn" value="oc_sa_cdrno_sgn_0" />
  <parameter name="hssi_pipe_gen1_2_rpre_emph_c_val" value="0" />
  <parameter name="hssi_adapt_rx_rx_fifo_write_latency_adjust" value="disable" />
  <parameter
     name="pma_adapt_adp_odi_dfe_spec_en"
     value="radp_odi_dfe_spec_en_enable" />
  <parameter name="pma_rx_odi_vreg_voltage_sel" value="vreg0" />
  <parameter name="l_enable_rx_pcs_dir" value="0" />
  <parameter name="pma_rx_dfe_tap2_sgn" value="tap2_sign_0" />
  <parameter name="hssi_rx_pld_pcs_interface_hd_krfec_sup_mode" value="user_mode" />
  <parameter name="pma_cgb_input_select_xn" value="not_used" />
  <parameter name="hssi_10g_rx_pcs_crcchk_inv" value="crcchk_inv_en" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_sup_mode"
     value="user_mode" />
  <parameter name="hssi_adapt_rx_hrdrst_dcd_cal_done_bypass" value="disable" />
  <parameter name="hssi_adapt_tx_pipe_mode" value="disable_pipe" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs10g_pma_dw_rx"
     value="pma_32b_rx" />
  <parameter name="pma_tx_buf_link" value="link_off" />
  <parameter
     name="hssi_8g_rx_pcs_clock_gate_bds_dec_asn"
     value="en_bds_dec_asn_clk_gating" />
  <parameter name="hssi_pldadapt_rx_rxfifo_empty" value="empty_dw" />
  <parameter
     name="hssi_8g_tx_pcs_clock_gate_sw_fifowr"
     value="en_sw_fifowr_clk_gating" />
  <parameter name="cdr_pll_ltd_ltr_micro_controller_select" value="ltd_ltr_pcs" />
  <parameter name="std_tx_bitslip_enable" value="0" />
  <parameter name="hssi_tx_pcs_pma_interface_pma_dw_tx" value="pma_32b_tx" />
  <parameter name="pma_adapt_adp_dlev_sel" value="radp_dlev_sel_mux" />
  <parameter name="dbg_stat_soft_logic_enable" value="0" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_st_new_dll"
     value="aib_dllstr_align_new_dll_setting0" />
  <parameter
     name="hssi_pldadapt_rx_fsr_pld_10g_rx_crc32_err_rst_val"
     value="reset_to_zero_crc32" />
  <parameter name="cdr_pll_f_max_vco" value="14150000000" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_uc_rx_rstb" value="rx_reset_on" />
  <parameter name="pma_tx_buf_duty_cycle_correction_reference2" value="dcc_ref2_2" />
  <parameter
     name="hssi_10g_tx_pcs_enc_64b66b_txsm_bypass"
     value="enc_64b66b_txsm_bypass_dis" />
  <parameter name="pma_rx_dfe_oc_sa_dne" value="0" />
  <parameter name="pma_tx_buf_duty_cycle_correction_reference1" value="dcc_ref1_4" />
  <parameter name="hssi_krfec_rx_pcs_dv_start" value="with_blklock" />
  <parameter name="pma_adapt_offset_mode" value="offset_disable" />
  <parameter name="cdr_pll_f_min_gt_channel" value="8700000000" />
  <parameter name="hssi_avmm1_if_hssiadapt_sr_powerdown_mode" value="powerup" />
  <parameter
     name="hssi_8g_tx_pcs_ctrl_plane_bonding_distribution"
     value="not_master_chnl_distr" />
  <parameter name="pma_rx_dfe_oc_sa_dpe_sgn" value="oc_sa_dpe_sgn_0" />
  <parameter
     name="pma_adapt_adp_clkout_div_sel"
     value="radp_clkout_div_sel_div2_4cycle" />
  <parameter
     name="hssi_pldadapt_rx_hdpldadapt_pld_rx_clk1_dcm_hz"
     value="156250000" />
  <parameter name="anlg_voltage" value="1_0V" />
  <parameter name="std_rx_byterev_enable" value="0" />
  <parameter name="hssi_8g_tx_pcs_bonding_dft_val" value="dft_0" />
  <parameter name="pma_cgb_input_select_x1" value="fpll_bot" />
  <parameter name="hssi_adapt_rx_rx_pcs_testbus_sel" value="direct_tr_tb_bit0_sel" />
  <parameter name="pma_rx_buf_rx_oc_or_lfeq_coeff" value="0" />
  <parameter name="hssi_adapt_tx_hrdrst_dll_lock_bypass" value="disable" />
  <parameter name="manual_tx_core_aib_bonding_comp_cnt" value="0" />
  <parameter name="hssi_10g_rx_pcs_sup_mode" value="user_mode" />
  <parameter name="pma_rx_buf_pm_cr2_tx_rx_testmux_select" value="setting0" />
  <parameter name="hssi_pldadapt_rx_bonding_dft_val" value="dft_0" />
  <parameter name="hssi_pldadapt_rx_hrdrst_rst_sm_dis" value="enable_rx_rst_sm" />
  <parameter name="hssi_common_pcs_pma_interface_bypass_pma_sw_done" value="false" />
  <parameter name="pma_tx_buf_res_cal_local" value="non_local" />
  <parameter name="hssi_avmm1_if_hssiadapt_sr_sr_reserved_in_en" value="enable" />
  <parameter name="enable_port_rx_is_lockedtoref" value="0" />
  <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_pma_rx_divclk_hz" value="322265625" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_uc_cal_clk_bypass" value="cal_clk_0" />
  <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
  <parameter name="hssi_8g_rx_pcs_pipe_if_enable" value="dis_pipe_rx" />
  <parameter name="pma_rx_deser_deser_aib_dftppm_en" value="disable" />
  <parameter name="pma_rx_dfe_oc_sa_dpe" value="0" />
  <parameter name="hssi_10g_rx_pcs_dispchk_bypass" value="dispchk_bypass_en" />
  <parameter name="pma_rx_dfe_oc_sa_vrefe_sgn" value="oc_sa_vrefe_sgn_0" />
  <parameter name="device_revision" value="14nm5bcr2eb" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_lpbk_en"
     value="disable" />
  <parameter name="hssi_adapt_rx_hd_hssiadapt_pld_pma_hclk_hz" value="0" />
  <parameter name="duplex_mode" value="duplex" />
  <parameter name="hssi_aibcr_rx_aib_rx_dcc_byp" value="aib_rx_dcc_byp_disable" />
  <parameter name="cdr_pll_rx_pin_as_refclk_mode" value="false" />
  <parameter name="pma_rx_sd_powermode_dc_sd" value="powerdown_sd" />
  <parameter name="hssi_adapt_rx_ctrl_plane_bonding" value="individual" />
  <parameter name="hssi_adapt_rx_hrdrst_user_ctl_en" value="disable" />
  <parameter name="hssi_pldadapt_rx_rxfifo_pempty" value="2" />
  <parameter name="pma_adapt_adp_dc_ctle_mode0_win_start" value="0" />
  <parameter name="pma_rx_dfe_oc_sa_dno" value="0" />
  <parameter name="pma_cgb_scratch3_x1_clock_src" value="not_used" />
  <parameter
     name="hssi_aibnd_tx_aib_red_drx_shiften"
     value="aib_red_drx_shift_disable" />
  <parameter name="hssi_aibcr_rx_op_mode" value="rx_dcc_enable" />
  <parameter name="hssi_pldadapt_rx_internal_clk1_sel2" value="pma_clks_clk1_mux2" />
  <parameter name="pma_tx_buf_bti_protected" value="false" />
  <parameter name="l_pipe_early_spd_chng" value="0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_ctrl_plane_bonding_tx"
     value="individual_tx" />
  <parameter name="pma_rx_dfe_tap13_sgn" value="tap13_sign_0" />
  <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
  <parameter
     name="hssi_pldadapt_rx_internal_clk1_sel1"
     value="pma_clks_or_txfiford_post_ct_mux_clk1_mux1" />
  <parameter name="hssi_8g_tx_pcs_reconfig_settings" value="{}" />
  <parameter name="hssi_krfec_tx_pcs_transcode_err" value="trans_err_dis" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_gt_enabled" value="disable" />
  <parameter name="hssi_10g_tx_pcs_txfifo_empty" value="empty_default" />
  <parameter name="hssi_pipe_gen3_bypass_rx_preset_enable" value="false" />
  <parameter name="hssi_pldadapt_tx_phcomp_rd_del" value="phcomp_rd_del3" />
  <parameter name="hssi_10g_rx_pcs_crcchk_pipeln" value="crcchk_pipeln_en" />
  <parameter name="hssi_aibnd_rx_aib_outpdrv_r78" value="aib_pdrv78_setting1" />
  <parameter
     name="hssi_adapt_rx_datapath_mapping_mode"
     value="map_10g_2x2x_2x1x_fifo" />
  <parameter name="device_family" value="Stratix 10" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_tx_clk_hz"
     value="322265625" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_pcs_refclk_dig_nonatpg_mode_clk_hz"
     value="0" />
  <parameter name="hssi_pldadapt_rx_compin_sel" value="compin_master" />
  <parameter
     name="pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch2_src"
     value="cdr_clkin_scratch2_src_refclk_iqclk" />
  <parameter name="pma_adapt_adp_vga_dlev_offset" value="4" />
  <parameter
     name="hssi_pipe_gen3_rate_match_pad_insertion"
     value="dis_rm_fifo_pad_ins" />
  <parameter name="datapath_select" value="Enhanced" />
  <parameter name="cdr_pll_requires_gt_capable_channel" value="false" />
  <parameter
     name="pma_adapt_adp_odi_control_sel"
     value="radp_odi_control_sel_from_cram" />
  <parameter name="pma_rx_dfe_bti_protected" value="false" />
  <parameter
     name="hssi_avmm1_if_hssiadapt_avmm_testbus_sel"
     value="avmm1_transfer_testbus" />
  <parameter name="enh_rx_frmsync_enable" value="0" />
  <parameter name="hssi_krfec_tx_pcs_burst_err" value="burst_err_dis" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_if_prot_mode_tx"
     value="teng_reg_mode_tx" />
  <parameter name="pma_rx_dfe_oc_sa_dpo" value="0" />
  <parameter
     name="pma_tx_ser_xtx_path_xchnseq_txpath_chnseq_idle_direct_on"
     value="cgb_idle_direct_off" />
  <parameter name="hssi_adapt_rx_txfiford_pre_ct_sel" value="txfiford_sclk_pre_ct" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_dly_pst"
     value="aib_dllstr_align_dly_pst_setting0" />
  <parameter name="cdr_pll_set_cdr_vco_speed" value="2" />
  <parameter name="pma_adapt_adp_dc_ctle_accum_depth" value="8" />
  <parameter
     name="hssi_pldadapt_tx_fsr_hip_fsr_in_bit3_rst_val"
     value="reset_to_zero_hfsrin3" />
  <parameter name="hssi_8g_tx_pcs_bypass_pipeline_reg" value="dis_bypass_pipeline" />
  <parameter name="pma_rx_odi_power_mode" value="mid_power" />
  <parameter name="hssi_pldadapt_tx_fifo_width" value="fifo_double_width" />
  <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
  <parameter name="hssi_pldadapt_rx_fifo_width" value="fifo_double_width" />
  <parameter name="hssi_adapt_tx_hd_hssiadapt_aib_hssi_pld_sclk_hz" value="0" />
  <parameter name="hssi_aibcr_rx_aib_rx_clkdiv" value="aib_rx_clkdiv_setting1" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_st_core_updnen"
     value="aib_rx_dcc_st_core_updnen_setting0" />
  <parameter name="hssi_common_pcs_pma_interface_phfifo_flush_wait" value="0" />
  <parameter name="pma_rx_buf_bodybias_enable" value="bodybias_en" />
  <parameter name="rx_ctle_ac_gain" value="0" />
  <parameter
     name="hssi_adapt_tx_fsr_hip_fsr_in_bit1_rst_val"
     value="reset_to_one_hfsrin1" />
  <parameter name="pma_adapt_adp_tx_up_dn_flip" value="radp_tx_up_dn_flip_0" />
  <parameter name="hssi_pldadapt_rx_pld_clk1_sel" value="pld_clk1_dcm" />
  <parameter name="hssi_aibnd_rx_aib_datasel_gr2" value="aib_datasel2_setting1" />
  <parameter name="hssi_aibnd_rx_aib_datasel_gr1" value="aib_datasel1_setting1" />
  <parameter name="hssi_aibnd_rx_aib_datasel_gr0" value="aib_datasel0_setting0" />
  <parameter
     name="pma_rx_buf_pm_cr2_tx_rx_uc_odi_eye_right"
     value="uc_odi_eye_right_off" />
  <parameter name="pma_rx_buf_eq_sel" value="eq_sel_1" />
  <parameter
     name="hssi_avmm1_if_pcs_calibration_feature_en"
     value="avmm1_pcs_calibration_en" />
  <parameter name="hssi_10g_rx_pcs_ber_clken" value="ber_clk_en" />
  <parameter name="enable_port_rx_is_lockedtodata" value="1" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_dy_ctl_static"
     value="aib_rx_dcc_dy_ctl_static_setting1" />
  <parameter name="pma_adapt_adp_dc_ctle_mode1_h1_ratio" value="8" />
  <parameter name="pma_cgb_bitslip_enable" value="disable_bitslip" />
  <parameter name="enable_channel_powerdown" value="0" />
  <parameter name="hssi_common_pcs_pma_interface_bypass_pcie_switch" value="true" />
  <parameter name="pma_adapt_odi_mode" value="odi_disable" />
  <parameter name="pma_rx_odi_prot_mode" value="basic_rx" />
  <parameter
     name="pma_pcie_gen_switch_rx_path_pcie_gen_switch_en"
     value="bypass_pcie_switch" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_st_core_dn_prgmnvrt"
     value="aib_dllstr_align_st_core_dn_prgmnvrt_setting0" />
  <parameter name="hssi_10g_rx_pcs_descrm_clken" value="descrm_clk_en" />
  <parameter name="hssi_tx_pcs_pma_interface_prbs_clken" value="prbs_clk_dis" />
  <parameter
     name="hssi_aibnd_tx_aib_red_txferclkout_shiften"
     value="aib_red_txferclkout_shift_disable" />
  <parameter name="avmm_ehip_mode" value="disable_hip" />
  <parameter name="hssi_adapt_tx_hd_hssiadapt_csr_clk_hz" value="0" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value"
     value="0" />
  <parameter name="hssi_adapt_rx_word_mark" value="wm_en" />
  <parameter
     name="pma_adapt_adp_oc_onetime_threshold"
     value="radp_oc_onetime_threshold_1024" />
  <parameter
     name="hssi_tx_pcs_pma_interface_tx_static_polarity_inversion"
     value="tx_stat_polinv_dis" />
  <parameter name="rx_pma_optimal_settings" value="1" />
  <parameter name="l_enable_frequency_rules" value="1" />
  <parameter name="hssi_10g_rx_pcs_pld_if_type" value="reg" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_prot_mode" value="basic_tx" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_st_core_updnen"
     value="aib_dllstr_align_st_core_updnen_setting0" />
  <parameter
     name="rcfg_sdc_derived_params"
     value="enable_multi_profile,dbg_embedded_debug_enable,dbg_capability_reg_enable,dbg_user_identifier,dbg_stat_soft_logic_enable,dbg_ctrl_soft_logic_enable,l_tx_transfer_clk_hz,l_rx_transfer_clk_hz,enable_background_cal,l_tx_fifo_transfer_mode,l_rx_fifo_transfer_mode,l_num_tx_digitalreset,l_num_rx_digitalreset,l_enable_channel_bonding,l_enable_pma_bonding,l_enable_pcs_bonding,l_tx_hssi_aib_indv,l_tx_core_aib_indv,l_rx_hssi_aib_indv,l_rx_core_aib_indv,display_std_tx_pld_adapt_width,display_std_rx_pld_adapt_width,datapath_select" />
  <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
  <parameter name="hssi_avmm1_if_pcs_cal_reserved" value="0" />
  <parameter name="enh_tx_frmgen_enable" value="0" />
  <parameter
     name="pma_adapt_adp_ac_ctle_hold_en"
     value="radp_ac_ctle_hold_en_not_hold" />
  <parameter name="rx_fifo_mode" value="Phase compensation" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_dy_ctlsel"
     value="aib_dllstr_align_dy_ctlsel_setting0" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_dy_ctl_static"
     value="aib_dllstr_align_dy_ctl_static_setting1" />
  <parameter name="cdr_pll_chgpmp_replicate" value="disable_replica_bias_ctrl" />
  <parameter name="hssi_gen3_rx_pcs_rx_test_out_sel" value="rx_test_out0" />
  <parameter name="hssi_adapt_tx_tx_fifo_write_latency_adjust" value="disable" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs10g_fifo_mode_rx"
     value="reg_rx" />
  <parameter name="pma_rx_sd_power_mode" value="mid_power" />
  <parameter name="hssi_adapt_rx_pma_aib_rx_clk_expected_setting" value="x2" />
  <parameter name="pma_rx_buf_ctle_tia_isel" value="ib_tia_bw1" />
  <parameter name="enh_rx_bitslip_enable" value="0" />
  <parameter name="pma_rx_deser_sup_mode" value="user_mode" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_func_mode"
     value="enable" />
  <parameter name="hssi_10g_tx_pcs_fec_clken" value="fec_clk_dis" />
  <parameter
     name="hssi_adapt_tx_fsr_pld_txelecidle_rst_val"
     value="reset_to_zero_txelec" />
  <parameter
     name="pma_adapt_adp_ac_ctle_ph1_win"
     value="radp_ac_ctle_ph1_win_2p19" />
  <parameter name="hssi_10g_rx_pcs_control_del" value="control_del_none" />
  <parameter name="hssi_pldadapt_tx_pld_clk1_sel" value="pld_clk1_dcm" />
  <parameter name="hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode" value="tx" />
  <parameter name="l_enable_pcs_bonding" value="0" />
  <parameter name="hssi_adapt_tx_hrdrst_align_bypass" value="enable" />
  <parameter name="hssi_aibcr_tx_silicon_rev" value="14nm5bcr2eb" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_ctrl_plane_bonding"
     value="individual" />
  <parameter
     name="pma_txpath_chnsequencer_txpath_chnseq_idle_direct_on"
     value="cgb_idle_direct_off" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_rst_prgmnvrt"
     value="aib_tx_dcc_st_rst_prgmnvrt_setting0" />
  <parameter name="cdr_pll_cdr_phaselock_mode" value="no_ignore_lock" />
  <parameter name="hssi_8g_rx_pcs_pad_or_edb_error_replace" value="replace_edb" />
  <parameter name="hssi_8g_tx_pcs_tx_fast_pld_reg" value="dis_tx_fast_pld_reg" />
  <parameter name="pma_rx_dfe_tap8_sgn" value="tap8_sign_0" />
  <parameter name="hssi_10g_tx_pcs_low_latency_en" value="disable" />
  <parameter name="hssi_aibnd_rx_aib_inctrl_gr0" value="aib_inctrl0_setting1" />
  <parameter name="dbg_prbs_soft_logic_enable" value="0" />
  <parameter name="hssi_10g_tx_pcs_prot_mode" value="teng_1588_mode" />
  <parameter name="hssi_aibnd_rx_aib_inctrl_gr1" value="aib_inctrl1_setting3" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pcs_tx_ac_pwr_uw_per_mhz"
     value="0" />
  <parameter
     name="hssi_8g_tx_pcs_clock_gate_dw_fifowr"
     value="en_dw_fifowr_clk_gating" />
  <parameter name="hssi_aibnd_rx_aib_inctrl_gr2" value="aib_inctrl2_setting2" />
  <parameter name="hssi_aibnd_rx_aib_inctrl_gr3" value="aib_inctrl3_setting3" />
  <parameter name="cdr_pll_clk0_dfe_trise_adj" value="clk0_dfe_tr0" />
  <parameter name="rcfg_profile_data4" value="" />
  <parameter name="rcfg_profile_data3" value="" />
  <parameter name="rcfg_profile_data2" value="" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_uc_cal_enable" value="rx_cal_off" />
  <parameter name="rcfg_profile_data1" value="" />
  <parameter
     name="rcfg_profile_data0"
     value="rcfg_debug 0 rcfg_enable 1 rcfg_jtag_enable 0 rcfg_separate_avmm_busy 0 rcfg_enable_avmm_busy_port 0 set_capability_reg_enable 0 set_user_identifier 0 set_csr_soft_logic_enable 0 support_mode user_mode channel_type GX protocol_mode teng_1588_mode pma_mode basic duplex_mode duplex channels 1 set_data_rate 10312.5 rcfg_iface_enable 0 enable_simple_interface 0 enable_split_interface 0 set_enable_calibration 1 enable_double_rate_transfer 0 enable_direct_reset_control 0 disable_reset_sequencer 0 disable_digital_reset_sequencer 0 enable_ehip 0 avmm_ehip_mode disable_hip adapter_ehip_mode disable_hip bonded_mode not_bonded set_pcs_bonding_master Auto pcs_reset_sequencing_mode not_bonded manual_pcs_bonding_mode individual manual_pcs_bonding_comp_cnt 0 manual_tx_hssi_aib_bonding_mode individual manual_tx_hssi_aib_bonding_comp_cnt 0 manual_tx_core_aib_bonding_mode individual manual_tx_core_aib_bonding_comp_cnt 0 manual_rx_hssi_aib_bonding_mode individual manual_rx_hssi_aib_bonding_comp_cnt 0 manual_rx_core_aib_bonding_mode individual manual_rx_core_aib_bonding_comp_cnt 0 manual_tx_hssi_aib_indv indv_en manual_tx_core_aib_indv indv_en manual_rx_hssi_aib_indv indv_en manual_rx_core_aib_indv indv_en tx_pma_clk_div 1 plls 1 pll_select 0 enable_port_tx_pma_iqtxrx_clkout 0 enable_port_tx_pma_elecidle 0 number_physical_bonding_clocks 1 enable_qpi_mode 0 enable_qpi_async_transfer 1 enable_port_tx_pma_qpipullup 0 enable_port_tx_pma_qpipulldn 0 enable_port_tx_pma_rxfound 0 enable_port_rx_pma_qpipulldn 0 enable_port_tx_pma_txdetectrx 0 cdr_refclk_cnt 1 cdr_refclk_select 0 set_cdr_refclk_freq 644.53125 rx_ppm_detect_threshold 100 enable_port_rx_pma_iqtxrx_clkout 0 enable_port_rx_pma_clkslip 0 enable_port_rx_is_lockedtodata 1 enable_port_rx_is_lockedtoref 0 enable_ports_rx_manual_cdr_mode 0 enable_ports_rx_prbs 0 enable_port_rx_seriallpbken 1 std_pcs_pma_width 10 std_low_latency_bypass_enable 0 enable_hip 0 enable_hard_reset 0 set_hip_cal_en 0 hip_mode disable_hip hip_prot_mode gen1 hip_channels x1 std_tx_byte_ser_mode Disabled std_rx_byte_deser_mode Disabled std_tx_8b10b_enable 1 std_tx_8b10b_disp_ctrl_enable 0 std_rx_8b10b_enable 1 std_rx_rmfifo_mode disabled std_rx_rmfifo_pattern_n 0 std_rx_rmfifo_pattern_p 0 enable_port_rx_std_rmfifo_full 0 enable_port_rx_std_rmfifo_empty 0 pcie_rate_match Bypass std_tx_bitslip_enable 0 enable_port_tx_std_bitslipboundarysel 0 std_rx_word_aligner_mode {synchronous state machine} std_rx_word_aligner_pattern_len 10 std_rx_word_aligner_pattern 0 std_rx_word_aligner_rknumber 3 std_rx_word_aligner_renumber 3 std_rx_word_aligner_rgnumber 3 std_rx_word_aligner_fast_sync_status_enable 0 enable_port_rx_std_wa_patternalign 0 enable_port_rx_std_wa_a1a2size 0 enable_port_rx_std_bitslipboundarysel 1 enable_port_rx_std_bitslip 0 std_tx_bitrev_enable 0 std_tx_byterev_enable 0 std_tx_polinv_enable 0 enable_port_tx_polinv 0 std_rx_bitrev_enable 0 enable_port_rx_std_bitrev_ena 0 std_rx_byterev_enable 0 enable_port_rx_std_byterev_ena 0 std_rx_polinv_enable 0 enable_port_rx_polinv 0 enable_port_rx_std_signaldetect 0 enable_ports_pipe_sw 0 enable_ports_pipe_rx_elecidle 0 enable_ports_pipe_hclk 0 enh_pcs_pma_width 32 enh_pld_pcs_width 66 enh_low_latency_enable 0 enh_advanced_user_mode 0 enh_tx_frmgen_enable 0 enh_tx_frmgen_mfrm_length 2048 enh_tx_frmgen_burst_enable 0 enable_port_tx_enh_frame 0 enable_port_tx_enh_frame_diag_status 0 enable_port_tx_enh_frame_burst_en 0 enh_rx_frmsync_enable 0 enh_rx_frmsync_mfrm_length 2048 enable_port_rx_enh_frame 0 enable_port_rx_enh_frame_lock 0 enable_port_rx_enh_frame_diag_status 0 enh_tx_crcgen_enable 0 enh_tx_crcerr_enable 0 enh_rx_crcchk_enable 0 enable_port_rx_enh_crc32_err 0 enable_port_rx_enh_highber 1 enable_port_rx_enh_highber_clr_cnt 1 enable_port_rx_enh_clr_errblk_count 1 enh_tx_64b66b_enable 1 enh_rx_64b66b_enable 1 enh_tx_sh_err 0 enh_tx_scram_enable 1 enh_tx_scram_seed 288230376151711743 enh_rx_descram_enable 1 enh_tx_dispgen_enable 0 enh_rx_dispchk_enable 0 enh_tx_randomdispbit_enable 0 enh_rx_blksync_enable 1 enable_port_rx_enh_blk_lock 1 enh_tx_bitslip_enable 0 enh_tx_polinv_enable 0 enh_rx_bitslip_enable 0 enh_rx_polinv_enable 0 enable_port_tx_enh_bitslip 0 enable_port_rx_enh_bitslip 0 enh_rx_krfec_err_mark_enable 0 enh_rx_krfec_err_mark_type 10G enh_tx_krfec_burst_err_enable 0 enh_tx_krfec_burst_err_len 1 enable_port_krfec_tx_enh_frame 0 enable_port_krfec_rx_enh_frame 0 enable_port_krfec_rx_enh_frame_diag_status 0 pcs_direct_width 8 enable_tx_fast_pipeln_reg 0 enable_rx_fast_pipeln_reg 0 parallel_loopback_mode disable loopback_tx_clk_sel internal_clk enable_debug_ports 0 tx_fifo_mode {Phase compensation} tx_fifo_pfull 10 tx_fifo_pempty 2 enable_port_tx_fifo_full 0 enable_port_tx_fifo_empty 0 enable_port_tx_fifo_pfull 0 enable_port_tx_fifo_pempty 0 enable_port_tx_pcs_fifo_full 0 enable_port_tx_pcs_fifo_empty 0 enable_port_tx_dll_lock 0 rx_fifo_mode {Phase compensation} rx_fifo_pfull 10 rx_fifo_pempty 2 rx_fifo_align_del 0 rx_fifo_control_del 0 enable_port_rx_data_valid 1 enable_port_rx_fifo_full 0 enable_port_rx_fifo_empty 0 enable_port_rx_fifo_pfull 0 enable_port_rx_fifo_pempty 0 enable_port_rx_fifo_del 0 enable_port_rx_fifo_insert 0 enable_port_rx_fifo_rd_en 0 enable_port_rx_fifo_align_clr 0 enable_port_rx_pcs_fifo_full 0 enable_port_rx_pcs_fifo_empty 0 tx_clkout_sel pcs_clkout enable_port_tx_clkout2 0 tx_clkout2_sel pcs_clkout enable_port_tx_clkout_hioint 0 enable_port_tx_clkout2_hioint 0 tx_pma_div_clkout_divider 33 tx_coreclkin_clock_network dedicated tx_pcs_bonding_clock_network dedicated rx_clkout_sel pcs_clkout enable_port_rx_clkout2 1 rx_clkout2_sel pma_div_clkout enable_port_rx_clkout_hioint 0 enable_port_rx_clkout2_hioint 0 rx_pma_div_clkout_divider 33 rx_coreclkin_clock_network dedicated osc_clk_divider 1 enable_port_tx_fifo_latency_adj_ena 0 enable_port_rx_fifo_latency_adj_ena 0 enable_port_latency_measurement 1 enable_port_clock_delay_measurement 0 delay_measurement_clkout_sel clock_delay_measurement_clkout delay_measurement_clkout2_sel clock_delay_measurement_clkout set_prbs_soft_logic_enable 0 enable_rcfg_tx_digitalreset_release_ctrl 0 anlg_voltage 1_0V anlg_link sr tx_pma_analog_mode user_custom tx_pma_optimal_settings 1 tx_pma_output_swing_ctrl 12 tx_pma_pre_emp_sign_pre_tap_1t negative tx_pma_pre_emp_switching_ctrl_pre_tap_1t 0 tx_pma_pre_emp_sign_1st_post_tap negative tx_pma_pre_emp_switching_ctrl_1st_post_tap 0 tx_pma_slew_rate_ctrl 0 tx_pma_term_sel r_r1 tx_pma_compensation_en enable rx_pma_adapt_mode manual rx_pma_term_sel r_r1 rx_ctle_ac_gain 0 rx_ctle_eq_gain 0 rx_vga_dc_gain 0 enable_ports_adaptation 0 rx_pma_analog_mode user_custom  ovrd_tx_dv_mode 0 ovrd_rx_dv_mode 0 usr_tx_dv_mode enable usr_rx_dv_mode enable enable_background_cal_gui 0" />
  <parameter name="hssi_aibnd_rx_aib_outpdrv_r12" value="aib_pdrv12_setting1" />
  <parameter name="hssi_8g_tx_pcs_symbol_swap" value="dis_symbol_swap" />
  <parameter name="enable_port_rx_std_signaldetect" value="0" />
  <parameter name="tx_enable" value="1" />
  <parameter name="pma_adapt_sup_mode" value="user_mode" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_power_rail_eht" value="1800" />
  <parameter
     name="hssi_adapt_tx_fsr_hip_fsr_in_bit3_rst_val"
     value="reset_to_zero_hfsrin3" />
  <parameter name="rcfg_profile_data7" value="" />
  <parameter name="rcfg_profile_data6" value="" />
  <parameter name="hssi_pldadapt_rx_word_align_enable" value="enable" />
  <parameter name="rcfg_profile_data5" value="" />
  <parameter name="hssi_krfec_tx_pcs_ctrl_bit_reverse" value="ctrl_bit_reverse_en" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_prot_mode" value="basic_rx" />
  <parameter name="hssi_10g_tx_pcs_full_flag_type" value="full_wr_side" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_power_rail_er" value="1030" />
  <parameter name="pma_rx_dfe_tap15_sgn" value="tap15_sign_0" />
  <parameter name="rx_pma_term_sel" value="r_r2" />
  <parameter
     name="hssi_adapt_rx_rxfiford_post_ct_sel"
     value="rxfiford_sclk_post_ct" />
  <parameter name="cdr_pll_bypass_a_edge" value="bypass_a_edge_off" />
  <parameter name="hssi_adapt_rx_rxfifo_mode" value="rxphase_comp" />
  <parameter
     name="pma_adapt_adp_pat_spec_sign_force"
     value="radp_pat_spec_sign_force_generated_internally" />
  <parameter name="hssi_pldadapt_tx_frmgen_pipeln" value="frmgen_pipeln_en" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_lpbk_en"
     value="disable" />
  <parameter name="l_tile_type" value="htile" />
  <parameter name="pma_rx_dfe_dft_en" value="dft_disable" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_datawidth" value="32" />
  <parameter name="tx_pma_analog_mode" value="user_custom" />
  <parameter name="pma_tx_buf_term_code" value="rterm_code0" />
  <parameter name="hssi_10g_rx_pcs_empty_flag_type" value="empty_rd_side" />
  <parameter name="pma_tx_ser_ser_clk_divtx_user_sel" value="divtx_user_off" />
  <parameter name="hssi_adapt_tx_fifo_double_read" value="fifo_double_read_en" />
  <parameter name="hssi_pldadapt_tx_hrdrst_dcd_cal_done_bypass" value="disable" />
  <parameter name="hssi_8g_tx_pcs_txclk_freerun" value="en_freerun_tx" />
  <parameter name="cdr_pll_mcnt_div" value="16" />
  <parameter name="l_enable_rx_enh" value="1" />
  <parameter name="hssi_10g_rx_pcs_blksync_pipeln" value="blksync_pipeln_dis" />
  <parameter name="hssi_avmm1_if_hssiadapt_sr_sr_parity_en" value="disable" />
  <parameter name="rcfg_emb_strm_enable" value="0" />
  <parameter
     name="pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch0_src"
     value="cdr_clkin_scratch0_src_refclk_iqclk" />
  <parameter
     name="hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel"
     value="sel_sig_det" />
  <parameter name="hssi_adapt_tx_txfifo_full" value="full_dw" />
  <parameter name="pma_adapt_adp_dfe_onetime" value="radp_dfe_onetime_disable" />
  <parameter
     name="hssi_aibcr_rx_aib_red_rx_shiften"
     value="aib_red_rx_shift_disable" />
  <parameter name="cdr_pll_txpll_hclk_driver_enable" value="hclk_off" />
  <parameter name="hssi_gen3_tx_pcs_silicon_rev" value="14nm5bcr2eb" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_pma_dw_rx"
     value="pma_32b_rx" />
  <parameter
     name="hssi_pldadapt_tx_fifo_rd_clk_sel"
     value="fifo_rd_pma_aib_tx_clk" />
  <parameter
     name="hssi_common_pcs_pma_interface_force_freqdet"
     value="force_freqdet_dis" />
  <parameter
     name="hssi_pldadapt_rx_txfiford_post_ct_sel"
     value="txfiford_sclk_post_ct" />
  <parameter
     name="hssi_aibcr_tx_aib_red_dirclkn_shiften"
     value="aib_red_dirclkn_shift_disable" />
  <parameter name="enable_port_rx_pma_clkslip" value="0" />
  <parameter name="hssi_avmm1_if_topology" value="disabled_block" />
  <parameter name="pma_tx_buf_datarate_bps" value="10312500000" />
  <parameter name="enh_tx_polinv_enable" value="0" />
  <parameter name="pma_adapt_advanced_mode" value="false" />
  <parameter name="tx_pll_type" value="ATX" />
  <parameter name="pma_cgb_bonding_mode" value="bond_off" />
  <parameter name="hssi_adapt_rx_osc_clk_scg_en" value="disable" />
  <parameter name="hssi_pldadapt_rx_loopback_mode" value="disable" />
  <parameter name="hssi_pipe_gen1_2_prot_mode" value="disabled_prot_mode" />
  <parameter name="pma_rx_odi_initial_settings" value="true" />
  <parameter name="pma_rx_buf_sel_vcm_tia" value="vocm_tia_fixed" />
  <parameter name="hssi_adapt_tx_bonding_dft_val" value="dft_0" />
  <parameter name="hssi_adapt_rx_rxfifowr_pre_ct_sel" value="rxfifowr_sclk_pre_ct" />
  <parameter name="pma_rx_dfe_powermode_dc_dfe" value="powerdown_dfe" />
  <parameter name="cdr_pll_vco_overrange_voltage" value="vco_overrange_off" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_bonding_mode" value="x1_non_bonded" />
  <parameter name="pma_tx_buf_compensation_posttap_en" value="disable" />
  <parameter name="cdr_pll_lpfd_counter" value="2" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_frequency_rules_en"
     value="enable" />
  <parameter name="enable_port_rx_clkout2_hioint" value="0" />
  <parameter name="hssi_10g_tx_pcs_frmgen_pyld_ins" value="frmgen_pyld_ins_dis" />
  <parameter
     name="hssi_pldadapt_tx_fsr_hip_fsr_out_bit3_rst_val"
     value="reset_to_zero_hfsrout3" />
  <parameter name="hssi_8g_rx_pcs_fixed_pat_num" value="0" />
  <parameter name="pma_rx_buf_eq_bw_sel" value="eq_bw_1" />
  <parameter name="hssi_pldadapt_rx_low_latency_en" value="disable" />
  <parameter name="hssi_8g_rx_pcs_bit_reversal" value="dis_bit_reversal" />
  <parameter name="hssi_avmm1_if_func_mode" value="c3adpt_pmadir" />
  <parameter name="cdr_pll_pd_fastlock_mode" value="fast_lock_disable" />
  <parameter name="hssi_pldadapt_rx_us_last_chnl" value="us_last_chnl" />
  <parameter name="pma_adapt_adp_vga_en" value="radp_vga_en_disable" />
  <parameter name="enable_port_rx_std_bitslipboundarysel" value="1" />
  <parameter name="rcfg_use_clk_reset_only" value="0" />
  <parameter name="hssi_10g_rx_pcs_frmsync_clken" value="frmsync_clk_dis" />
  <parameter name="hssi_adapt_tx_compin_sel" value="compin_master" />
  <parameter name="hssi_10g_tx_pcs_crcgen_clken" value="crcgen_clk_dis" />
  <parameter name="pma_adapt_adp_dfe_en" value="radp_dfe_en_disable" />
  <parameter name="cdr_pll_loopback_mode" value="loopback_disabled" />
  <parameter name="hssi_pldadapt_rx_rxfifo_pfull" value="10" />
  <parameter name="hssi_pipe_gen1_2_elec_idle_delay_val" value="0" />
  <parameter name="hssi_aibnd_rx_aib_outpdrv_r56" value="aib_pdrv56_setting1" />
  <parameter
     name="pma_rx_buf_xrx_path_xcdr_deser_xcdr_loopback_mode"
     value="loopback_disabled" />
  <parameter name="pma_adapt_adp_dlev_bypass" value="radp_dlev_bypass_bypass" />
  <parameter name="set_data_rate" value="10312.5" />
  <parameter name="hssi_aibnd_tx_aib_tx_dcc_dft" value="aib_tx_dcc_dft_disable" />
  <parameter name="hssi_8g_tx_pcs_eightb_tenb_disp_ctrl" value="dis_disp_ctrl" />
  <parameter name="hssi_pipe_gen3_bypass_rx_preset" value="0" />
  <parameter name="hssi_krfec_tx_pcs_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_pldadapt_tx_dv_bond" value="dv_bond_dis" />
  <parameter name="hssi_8g_tx_pcs_phase_comp_rdptr" value="disable_rdptr" />
  <parameter name="device_die_revisions" value="HSSI_CRETE2E_REVB,MAIN_ND5_REVC" />
  <parameter name="dbg_odi_soft_logic_enable" value="0" />
  <parameter name="hssi_gen3_rx_pcs_rx_num_fixed_pat" value="0" />
  <parameter
     name="pma_adapt_adp_load_sig_sel"
     value="radp_load_sig_sel_from_interanl" />
  <parameter name="hssi_pldadapt_tx_txfifo_full" value="full_pc_dw" />
  <parameter name="pma_cgb_scratch1_x1_clock_src" value="not_used" />
  <parameter name="pma_adapt_powermode_ac_dfe_adapt" value="adapt_dfe_ac_off" />
  <parameter name="pma_adapt_adp_dc_ctle_mode2_h2_limit" value="7" />
  <parameter name="hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask" value="dis_rxvalid_mask" />
  <parameter name="hssi_pipe_gen1_2_sup_mode" value="user_mode" />
  <parameter name="hssi_pldadapt_tx_bonding_dft_en" value="dft_dis" />
  <parameter name="pma_rx_buf_dfe_err_sw_togg" value="dfe_err_tog_a" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_datawidth" value="32" />
  <parameter name="hssi_fifo_tx_pcs_silicon_rev" value="14nm5bcr2eb" />
  <parameter
     name="hssi_tx_pld_pcs_interface_pcs_tx_output_sel"
     value="teng_output" />
  <parameter name="pma_rx_dfe_vref_coeff" value="0" />
  <parameter name="hssi_krfec_rx_pcs_lpbk_mode" value="lpbk_dis" />
  <parameter name="enh_tx_dispgen_enable" value="0" />
  <parameter
     name="pma_adapt_adp_ac_ctle_initial_load"
     value="radp_ac_ctle_initial_load_0" />
  <parameter name="hssi_aibnd_rx_aib_outpdrv_r34" value="aib_pdrv34_setting1" />
  <parameter name="pma_cgb_prot_mode" value="basic_tx" />
  <parameter name="pma_cgb_pcie_gen" value="non_pcie" />
  <parameter name="tx_pma_optimal_settings" value="1" />
  <parameter name="pma_rx_buf_vga_halfbw_en" value="vga_half_bw_enabled" />
  <parameter name="hssi_tx_pcs_pma_interface_sup_mode" value="user_mode" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_clock_divider_ratio" value="1" />
  <parameter name="hssi_10g_rx_pcs_test_mode" value="test_off" />
  <parameter
     name="hssi_common_pld_pcs_interface_dft_clk_out_sel"
     value="teng_rx_dft_clk" />
  <parameter name="pma_rx_dfe_tap6_sgn" value="tap6_sign_0" />
  <parameter name="pcie_rate_match" value="Bypass" />
  <parameter name="hssi_aibcr_rx_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="pma_adapt_adp_po_gb_act2slp" value="radp_po_gb_act2slp_288ns" />
  <parameter name="pma_adapt_adp_tx_accum_depth" value="4" />
  <parameter name="pma_tx_buf_term_n_tune" value="rterm_n7" />
  <parameter name="pma_tx_buf_tx_rst_enable" value="enable" />
  <parameter name="pma_tx_buf_rx_det_output_sel" value="rx_det_pcie_out" />
  <parameter name="hssi_gen3_tx_pcs_tx_bitslip" value="0" />
  <parameter name="hssi_rx_pld_pcs_interface_hd_pcs10g_lpbk_en" value="disable" />
  <parameter name="hssi_krfec_rx_pcs_pipeln_syndrm" value="enable" />
  <parameter name="hssi_8g_rx_pcs_wa_renumber_data" value="3" />
  <parameter name="pma_tx_buf_uc_vcc_setting" value="vcc_setting1" />
  <parameter name="rcfg_jtag_enable" value="0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs10g_prot_mode_tx"
     value="teng_1588_mode_tx" />
  <parameter name="pma_adapt_adp_oc_en" value="radp_oc_en_disable" />
  <parameter name="cdr_pll_direct_fb" value="direct_fb" />
  <parameter name="l_pcs_channel_hip_en" value="0" />
  <parameter name="validation_rule_select" value="" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_swing_level" value="hv" />
  <parameter name="pma_tx_sequencer_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_gen3_rx_pcs_rate_match_fifo" value="bypass_rm_fifo" />
  <parameter name="enable_tx_coreclkin2" value="0" />
  <parameter
     name="pma_reset_sequencer_xrx_path_uc_cal_clk_bypass"
     value="cal_clk_0" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs10g_prot_mode_rx"
     value="teng_1588_mode_rx" />
  <parameter name="hssi_pldadapt_rx_fifo_double_read" value="fifo_double_read_en" />
  <parameter name="cannot_gen_exdesign_prot_msg" value="" />
  <parameter name="pma_rx_buf_rx_vga_oc_en" value="vga_cal_off" />
  <parameter name="hssi_8g_rx_pcs_wa_rosnumber_data" value="1" />
  <parameter name="l_std_tx_field_width" value="11" />
  <parameter name="cdr_pll_initial_settings" value="true" />
  <parameter name="pma_tx_ser_ser_clk_mon" value="disable_clk_mon" />
  <parameter name="hssi_pldadapt_rx_chnl_bonding" value="disable" />
  <parameter name="pma_cdr_refclk_xmux_refclk_src" value="refclk_iqclk" />
  <parameter name="hssi_common_pcs_pma_interface_bypass_txdetectrx" value="true" />
  <parameter
     name="pma_adapt_adp_dfe_tap1_initial_load"
     value="radp_dfe_tap1_initial_load_0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_8g_refclk_dig_nonatpg_mode_clk_hz"
     value="0" />
  <parameter name="hssi_adapt_tx_ctrl_plane_bonding" value="individual" />
  <parameter name="hssi_pipe_gen1_2_rvod_sel_c_val" value="0" />
  <parameter name="hssi_avmm1_if_hssiadapt_hip_mode" value="disable_hip" />
  <parameter name="pma_tx_buf_pm_cr2_tx_rx_mcgb_location_for_pcie" value="0" />
  <parameter
     name="hssi_adapt_rx_internal_clk1_sel"
     value="pld_pma_tx_clk_out_clk1" />
  <parameter
     name="rcfg_param_labels"
     value="rcfg_debug,Enable dynamic reconfiguration,Enable Native PHY Debug Master Endpoint,Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE,Enable avmm_busy port,Enable capability registers,Set user-defined IP identifier,Enable control and status registers,Protocol support mode,Transceiver channel type,Transceiver configuration rules,PMA configuration rules,Transceiver mode,Number of data channels,Data rate,Enable datapath and interface reconfiguration,Enable simplified data interface,Provide separate interface for each channel,Enable calibration,Enable double rate transfer mode,Enable background calibration,Enable direct reset control,Disable reset sequencer,Disable digital reset sequencer,TX channel bonding mode,PCS TX channel bonding master,PCS reset sequence,PCS TX channel bonding mode,PCS TX bonding compensation counter,TX HSSI AIB bonding mode,TX HSSI AIB compensation counter,TX Core AIB bonding mode,TX Core AIB compensation counter,RX HSSI AIB bonding mode,RX HSSI AIB compensation counter,RX Core AIB bonding mode,RX Core AIB compensation counter,TX HSSI AIB sychronous bonding setting,TX Core AIB sychronous bonding setting,RX HSSI AIB sychronous bonding setting,RX Core AIB sychronous bonding setting,TX local clock division factor,Number of TX PLL clock inputs per channel,Initial TX PLL clock input selection,Enable tx_pma_iqtxrx_clkout port,Enable tx_pma_elecidle port,Number of physical bonding clock ports to use.,Enable QPI mode,Use asynchronous QPI signals,Enable tx_pma_qpipullup port,Enable tx_pma_qpipulldn port,Enable tx_pma_rxfound port,Enable rx_pma_qpipulldn port,Enable tx_pma_txdetectrx port,Number of CDR reference clocks,Selected CDR reference clock,Selected CDR reference clock frequency,PPM detector threshold,Enable rx_pma_iqtxrx_clkout port,Enable rx_pma_clkslip port,Enable rx_is_lockedtodata port,Enable rx_is_lockedtoref port,Enable rx_set_locktodata and rx_set_locktoref ports,Enable PRBS verifier control and status ports,Enable rx_seriallpbken port,Standard PCS / PMA interface width,Enable &apos;Standard PCS&apos; low latency mode,Enable PCIe hard IP support,Enable hard reset controller (HIP),Enable PCIe hard IP calibration,PCIe channel HIP mode,PCIe HIP protocol mode,Number of PCIe HIP channels,Enable Ethernet Hard IP Support,Ethernet channel AVMM HIP mode,Ethernet channel Adapter HIP mode,TX byte serializer mode,RX byte deserializer mode,Enable TX 8B/10B encoder,Enable TX 8B/10B disparity control,Enable RX 8B/10B decoder,RX rate match FIFO mode,RX rate match insert/delete -ve pattern (hex),RX rate match insert/delete +ve pattern (hex),Enable rx_std_rmfifo_full port,Enable rx_std_rmfifo_empty port,PCI Express Gen 3 rate match FIFO mode,Enable TX bitslip,Enable tx_std_bitslipboundarysel port,RX word aligner mode,RX word aligner pattern length,RX word aligner pattern (hex),Number of word alignment patterns to achieve sync,Number of invalid data words to lose sync,Number of valid data words to decrement error count,Enable fast sync status reporting for deterministic latency SM,Enable rx_std_wa_patternalign port,Enable rx_std_wa_a1a2size port,Enable rx_std_bitslipboundarysel port,Enable rx_bitslip port,Enable TX bit reversal,Enable TX byte reversal,Enable TX polarity inversion,Enable tx_polinv port,Enable RX bit reversal,Enable rx_std_bitrev_ena port,Enable RX byte reversal,Enable rx_std_byterev_ena port,Enable RX polarity inversion,Enable rx_polinv port,Enable rx_std_signaldetect port,Enable PCIe dynamic datarate switch ports,Enable PCIe electrical idle control and status ports,Enable PCIe pipe_hclk_in and pipe_hclk_out ports,Enhanced PCS / PMA interface width,FPGA fabric / Enhanced PCS interface width,Enable &apos;Enhanced PCS&apos; low latency mode,Enable &apos;Enhanced PCS&apos; advanced user mode,Enable Interlaken frame generator,Frame generator metaframe length,Enable frame generator burst control,Enable tx_enh_frame port,Enable tx_enh_frame_diag_status port,Enable tx_enh_frame_burst_en port,Enable Interlaken frame synchronizer,Frame synchronizer metaframe length,Enable rx_enh_frame port,Enable rx_enh_frame_lock port,Enable rx_enh_frame_diag_status port,Enable Interlaken TX CRC-32 generator,Enable Interlaken TX CRC-32 generator error insertion,Enable Interlaken RX CRC-32 checker,Enable rx_enh_crc32_err port,Enable rx_enh_highber port (10GBASE-R),Enable rx_enh_highber_clr_cnt port (10GBASE-R),Enable rx_enh_clr_errblk_count port (10GBASE-R &amp; FEC),Enable TX 64b/66b encoder,Enable RX 64b/66b decoder,Enable TX sync header error insertion,Enable TX scrambler (10GBASE-R/Interlaken),TX scrambler seed (10GBASE-R/Interlaken),Enable RX descrambler (10GBASE-R/Interlaken),Enable Interlaken TX disparity generator,Enable Interlaken RX disparity checker,Enable Interlaken TX random disparity bit,Enable RX block synchronizer,Enable rx_enh_blk_lock port,Enable TX data bitslip,Enable TX data polarity inversion,Enable RX data bitslip,Enable RX data polarity inversion,Enable tx_enh_bitslip port,Enable rx_bitslip port,Enable RX KR-FEC error marking,Error marking type,Enable KR-FEC TX error insertion,KR-FEC TX error insertion spacing,Enable tx_enh_frame port,Enable rx_enh_frame port,Enable rx_enh_frame_diag_status port,PCS Direct interface width,Enable TX fast pipeline registers,Enable RX fast pipeline registers,Parallel loopback mode,Parallel loopback mode TX clock source selection,Enable PCS reset status ports,TX Core Interface FIFO mode,TX FIFO partially full threshold,TX FIFO partially empty threshold,Enable tx_fifo_full port,Enable tx_fifo_empty port,Enable tx_fifo_pfull port,Enable tx_fifo_pempty port,Enable tx_pcs_fifo_full port,Enable tx_pcs_fifo_empty port,Enable tx_dll_lock port,RX PCS-Core Interface FIFO mode (PCS FIFO-Core FIFO),RX FIFO partially full threshold,RX FIFO partially empty threshold,Enable RX FIFO alignment word deletion (Interlaken),Enable RX FIFO control word deletion (Interlaken),Enable rx_data_valid port,Enable rx_fifo_full port,Enable rx_fifo_empty port,Enable rx_fifo_pfull port,Enable rx_fifo_pempty port,Enable rx_fifo_del port (10GBASE-R),Enable rx_fifo_insert port (10GBASE-R),Enable rx_fifo_rd_en port,Enable rx_fifo_align_clr port (Interlaken),Enable rx_pcs_fifo_full port,Enable rx_pcs_fifo_empty port,Selected tx_clkout clock source,Enable tx_clkout2 port,Selected tx_clkout2 clock source,Enable tx_clkout_hioint port,Enable tx_clkout2_hioint port,TX pma_div_clkout division factor,Selected tx_coreclkin clock network,Selected TX PCS bonding clock network,Selected rx_clkout clock source,Enable rx_clkout2 port,Selected rx_clkout2 clock source,Enable rx_clkout_hioint port,Enable rx_clkout2_hioint port,RX pma_div_clkout division factor,Selected rx_coreclkin clock network,OSC clock division factor,Enable TX FIFO latency adjustment port,Enable RX FIFO latency adjustment port,Enable latency measurement ports,Enable clock delay measurement ports,Selected delay_measurement_clkout clock source,Selected delay_measurement_clkout2 clock source,Enable TX Data Valid Gen manual setting,Generate TX Data Valid by Core AIB FIFO,Enable RX Data Valid Rcv manual setting,Consume RX Data Valid by Core AIB FIFO,Enable prbs soft accumulators,Enable rcfg_tx_digitalreset_release_ctrl port,VCCR_GXB and VCCT_GXB supply voltage for the Transceiver,Tranceiver Link Type,Enable adaptation control ports,TX PMA analog mode rules,RX PMA analog mode rules,Use default TX PMA analog settings,Output Swing Level (VOD),Pre-Emphasis First Pre-Tap Polarity,Pre-Emphasis First Pre-Tap Magnitude,Pre-Emphasis First Post-Tap Polarity,Pre-Emphasis First Post-Tap Magnitude,Slew Rate Control,On-Chip Termination,High Speed Compensation,RX adaptation mode,RX On-chip Termination,CTLE AC Gain,CTLE EQ Gain,VGA DC Gain" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_st_new_dll2"
     value="aib_rx_dcc_new_dll2_setting0" />
  <parameter name="pma_rx_deser_deser_powerdown" value="deser_power_up" />
  <parameter name="pma_tx_ser_clk_divtx_deskew" value="deskew_delay0" />
  <parameter name="pma_rx_buf_power_mode" value="mid_power" />
  <parameter name="enable_port_rx_fifo_insert" value="0" />
  <parameter name="manual_rx_hssi_aib_indv" value="indv_en" />
  <parameter name="hssi_aibcr_rx_aib_iinclken" value="aib_inclken_setting3" />
  <parameter name="hssi_pldadapt_rx_fifo_wr_clk_del_sm_scg_en" value="enable" />
  <parameter
     name="hssi_8g_rx_pcs_rate_match_empty_thres"
     value="dis_rm_empty_thres" />
  <parameter name="hssi_aibcr_rx_dft_hssitestip_dll_dcc_en" value="disable_dft" />
  <parameter name="hssi_common_pcs_pma_interface_bypass_early_eios" value="true" />
  <parameter name="hssi_gen3_rx_pcs_rx_b4gb_par_lpbk" value="b4gb_par_lpbk_dis" />
  <parameter name="enable_port_rx_enh_highber" value="1" />
  <parameter name="enh_tx_krfec_burst_err_len" value="1" />
  <parameter name="enh_rx_crcchk_enable" value="0" />
  <parameter name="enable_mac_total_control" value="0" />
  <parameter name="hssi_10g_rx_pcs_frmsync_knum_sync" value="knum_sync_default" />
  <parameter name="pma_adapt_sequencer_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_pldadapt_tx_us_last_chnl" value="us_last_chnl" />
  <parameter name="pma_tx_buf_jtag_drv_sel" value="drv1" />
  <parameter name="l_rx_fifo_transfer_mode" value="x2" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_st_core_updnen"
     value="aib_dllstr_align_st_core_updnen_setting0" />
  <parameter name="pma_adapt_adp_vga_initial_load" value="radp_vga_initial_load_0" />
  <parameter name="enable_port_tx_enh_bitslip" value="0" />
  <parameter name="hssi_aibcr_tx_powermode_dc" value="powerup" />
  <parameter name="pma_rx_deser_clkdivrx_user_mode" value="clkdivrx_user_div33" />
  <parameter name="hssi_10g_tx_pcs_pfull_flag_type" value="pfull_wr_side" />
  <parameter name="rcfg_sdc_derived_profile_data6" value="" />
  <parameter
     name="hssi_pldadapt_rx_rx_pld_8g_eidleinfersel_polling_bypass"
     value="disable" />
  <parameter name="rcfg_sdc_derived_profile_data7" value="" />
  <parameter name="rcfg_sdc_derived_profile_data4" value="" />
  <parameter name="hssi_pldadapt_rx_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="rcfg_sdc_derived_profile_data5" value="" />
  <parameter name="pma_tx_buf_vreg_output" value="vccdreg_nominal" />
  <parameter name="generate_add_hdl_instance_example" value="1" />
  <parameter name="hssi_10g_rx_pcs_align_del" value="align_del_dis" />
  <parameter
     name="hssi_8g_rx_pcs_clock_gate_dw_rm_rd"
     value="en_dw_rm_rdclk_gating" />
  <parameter name="tx_pma_term_sel" value="r_r1" />
  <parameter
     name="pma_adapt_adp_ctle_bypass_ac"
     value="radp_ctle_bypass_ac_bypass" />
  <parameter name="rcfg_sdc_derived_profile_data2" value="" />
  <parameter name="enh_tx_scram_enable" value="1" />
  <parameter name="rcfg_sdc_derived_profile_data3" value="" />
  <parameter
     name="rcfg_sdc_derived_profile_data0"
     value="enable_multi_profile 1 disable_digital_reset_sequencer 0 dbg_embedded_debug_enable 0 dbg_capability_reg_enable 0 dbg_user_identifier 0 dbg_stat_soft_logic_enable 0 dbg_ctrl_soft_logic_enable 0 l_tx_transfer_clk_hz 515625000 l_rx_transfer_clk_hz 515625000 enable_background_cal 0 disable_reset_sequencer 0 l_tx_fifo_transfer_mode x2 l_rx_fifo_transfer_mode x2 l_num_tx_digitalreset 1 l_num_rx_digitalreset 1 l_enable_channel_bonding 0 l_enable_pma_bonding 0 l_enable_pcs_bonding 0 l_tx_hssi_aib_indv indv_en l_tx_core_aib_indv indv_en l_rx_hssi_aib_indv indv_en l_rx_core_aib_indv indv_en display_std_tx_pld_adapt_width 8 display_std_rx_pld_adapt_width 8 datapath_select Enhanced" />
  <parameter name="rcfg_sdc_derived_profile_data1" value="" />
  <parameter name="hssi_aibcr_tx_op_mode" value="tx_dll_enable" />
  <parameter
     name="hssi_pldadapt_tx_hdpldadapt_aib_fabric_pld_pma_hclk_hz"
     value="0" />
  <parameter name="hssi_aibcr_rx_aib_rx_dcc_en" value="aib_rx_dcc_enable" />
  <parameter name="pma_rx_buf_ctle_oc_ib_sel" value="ib_oc_bw3" />
  <parameter name="pma_rx_dfe_dft_osc_sel" value="dft_osc_even" />
  <parameter name="pma_rx_buf_initial_settings" value="true" />
  <parameter name="rcfg_multi_enable" value="1" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_clkdiv"
     value="aib_dllstr_align_clkdiv_setting1" />
  <parameter name="pma_adapt_datarate_bps" value="10312500000" />
  <parameter name="hssi_adapt_tx_stretch_num_stages" value="seven_stage" />
  <parameter name="hssi_adapt_tx_ds_last_chnl" value="ds_last_chnl" />
  <parameter name="hssi_adapt_rx_rx_usertest_sel" value="direct_tr_usertest3_sel" />
  <parameter name="hssi_adapt_tx_hrdrst_user_ctl_en" value="disable" />
  <parameter name="pma_cgb_pcie_gen3_bitwidth" value="pciegen3_wide" />
  <parameter name="hssi_10g_tx_pcs_master_clk_sel" value="master_tx_pma_clk" />
  <parameter name="hssi_avmm1_if_hssiadapt_sr_hip_mode" value="disable_hip" />
  <parameter name="pma_rx_deser_pm_cr2_tx_rx_pcie_gen" value="non_pcie" />
  <parameter name="hssi_adapt_rx_asn_wait_for_fifo_flush_cnt" value="32" />
  <parameter name="hssi_pldadapt_rx_asn_wait_for_fifo_flush_cnt" value="64" />
  <parameter name="hssi_pldadapt_tx_tx_usertest_sel" value="enable" />
  <parameter name="pma_rx_dfe_tap9_sgn" value="tap9_sign_0" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock"
     value="uhsif_filt_cntthr_b4lock_8" />
  <parameter name="pma_adapt_adp_odi_spec_sel" value="radp_odi_spec_sel_0" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter name="pma_adapt_adp_oc_onetime" value="radp_oc_onetime_disable" />
  <parameter name="enable_internal_options" value="0" />
  <parameter name="hssi_adapt_rx_us_bypass_pipeln" value="us_bypass_pipeln_dis" />
  <parameter name="pma_tx_buf_swing_level" value="hv" />
  <parameter name="cdr_pll_power_mode" value="mid_power" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_if_sup_mode"
     value="user_mode" />
  <parameter name="enable_insert_eios_err" value="0" />
  <parameter name="hssi_aibcr_tx_powermode_ac" value="txdatapath_high_speed_pwr" />
  <parameter name="tx_pma_compensation_en" value="enable" />
  <parameter name="hssi_adapt_rx_asn_bypass_clock_gate" value="disable" />
  <parameter name="pma_rx_buf_tia_sel" value="tia_sel_1" />
  <parameter name="l_pll_settings_key" value="644.531250" />
  <parameter name="enable_workaround_rules" value="0" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control"
     value="uhsif_dft_dz_det_val_0" />
  <parameter name="pma_cgb_vccdreg_output" value="vccdreg_nominal" />
  <parameter
     name="pma_cdr_refclk_inclk4_logical_to_physical_mapping"
     value="ref_iqclk0" />
  <parameter
     name="hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion"
     value="rx_dyn_polinv_dis" />
  <parameter name="pma_txpath_chnsequencer_sup_mode" value="sup_off" />
  <parameter name="hssi_pldadapt_rx_gb_rx_odwidth" value="odwidth_66" />
  <parameter
     name="hssi_krfec_tx_pcs_data_bit_reverse"
     value="data_bit_reverse_dis" />
  <parameter name="hssi_pldadapt_tx_us_bypass_pipeln" value="us_bypass_pipeln_dis" />
  <parameter name="cdr_pll_loop_filter_bias_select" value="lpflt_bias_7" />
  <parameter name="pma_rx_sd_powermode_ac_sd" value="ac_off_sd" />
  <parameter name="hssi_10g_rx_pcs_frmsync_enum_sync" value="enum_sync_default" />
  <parameter name="hssi_10g_tx_pcs_frmgen_pipeln" value="frmgen_pipeln_en" />
  <parameter name="hssi_pldadapt_tx_frmgen_wordslip" value="frmgen_wordslip_dis" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value"
     value="0" />
  <parameter name="hssi_10g_rx_pcs_pfull_flag_type" value="pfull_wr_side" />
  <parameter name="pma_adapt_adp_oc_initial_sign" value="radp_oc_initial_sign_0" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_st_core_updnen"
     value="aib_tx_dcc_st_core_updnen_setting0" />
  <parameter name="hssi_adapt_tx_hip_osc_clk_scg_en" value="enable" />
  <parameter
     name="hssi_common_pld_pcs_interface_pcs_testbus_block_sel"
     value="pma_if" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_g3pcs_prot_mode"
     value="disabled_prot_mode" />
  <parameter name="manual_rx_hssi_aib_bonding_mode" value="individual" />
  <parameter name="pma_tx_buf_powermode_dc_post_tap" value="powerdown_tx_post_tap" />
  <parameter name="hssi_10g_tx_pcs_frmgen_clken" value="frmgen_clk_dis" />
  <parameter
     name="hssi_8g_tx_pcs_ctrl_plane_bonding_compensation"
     value="dis_compensation" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_speed_grade"
     value="e2" />
  <parameter name="enable_qpi_mode" value="0" />
  <parameter name="hssi_10g_rx_pcs_phcomp_rd_del" value="phcomp_rd_del2" />
  <parameter name="hssi_rx_pld_pcs_interface_hd_pcs8g_sup_mode" value="user_mode" />
  <parameter name="hssi_gen3_rx_pcs_reconfig_settings" value="{}" />
  <parameter name="pma_cdr_refclk_silicon_rev" value="14nm5bcr2eb" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_test_clk_pll_en_n"
     value="aib_dllstr_align_test_clk_pll_en_n_disable" />
  <parameter name="hssi_10g_tx_pcs_reconfig_settings" value="{}" />
  <parameter
     name="hssi_8g_rx_pcs_ctrl_plane_bonding_compensation"
     value="dis_compensation" />
  <parameter name="pma_rx_sd_sd_pdb" value="sd_off" />
  <parameter name="hssi_aibnd_tx_op_mode" value="tx_dcc_enable" />
  <parameter name="pma_rx_dfe_tap10_sgn" value="tap10_sign_0" />
  <parameter name="enable_port_tx_clkout2_hioint" value="0" />
  <parameter name="hssi_pldadapt_tx_hdpldadapt_pld_sclk1_rowclk_hz" value="0" />
  <parameter name="hssi_8g_tx_pcs_txpcs_urst" value="en_txpcs_urst" />
  <parameter name="l_rcfg_datapath_message" value="0" />
  <parameter name="hssi_pipe_gen3_sup_mode" value="user_mode" />
  <parameter name="l_enable_pma_channel" value="1" />
  <parameter
     name="hssi_pldadapt_rx_fsr_pld_8g_sigdet_out_rst_val"
     value="reset_to_zero_sigdet" />
  <parameter name="enable_port_rx_pcs_fifo_full" value="0" />
  <parameter name="enable_debug_ports" value="0" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_power_rail_et" value="1030" />
  <parameter name="hssi_adapt_rx_rxfifo_pfull" value="5" />
  <parameter name="hssi_8g_tx_pcs_sup_mode" value="user_mode" />
  <parameter name="hssi_10g_tx_pcs_silicon_rev" value="14nm5bcr2eb" />
  <parameter
     name="hssi_adapt_rx_hd_hssiadapt_pld_pcs_rx_clk_out_hz"
     value="322265625" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter name="rcfg_h_file_enable" value="1" />
  <parameter name="pma_txpath_chnsequencer_prot_mode" value="basic_tx" />
  <parameter name="hssi_10g_rx_pcs_advanced_user_mode" value="disable" />
  <parameter name="hssi_rx_pcs_pma_interface_lpbk_en" value="disable" />
  <parameter name="rcfg_txt_file_enable" value="0" />
  <parameter name="hssi_rx_pld_pcs_interface_hd_pcs8g_fifo_mode_rx" value="reg_rx" />
  <parameter
     name="pma_adapt_adp_po_actslp_ratio"
     value="radp_po_actslp_ratio_10_percent" />
  <parameter
     name="hssi_pldadapt_tx_fsr_hip_fsr_in_bit1_rst_val"
     value="reset_to_one_hfsrin1" />
  <parameter name="enable_enh" value="1" />
  <parameter
     name="pma_adapt_adp_ctle_bypass_dc"
     value="radp_ctle_bypass_dc_bypass" />
  <parameter name="hssi_gen3_tx_pcs_mode" value="disable_pcs" />
  <parameter name="pma_rx_buf_act_isource_disable" value="isrc_dis" />
  <parameter name="pma_tx_buf_sense_amp_offset_cal_curr_p" value="0" />
  <parameter name="enable_port_rx_fifo_empty" value="0" />
  <parameter name="manual_rx_core_aib_bonding_comp_cnt" value="0" />
  <parameter name="pma_tx_buf_sense_amp_offset_cal_curr_n" value="sa_os_cal_in_0" />
  <parameter name="hssi_pldadapt_tx_tx_fastbond_rden" value="rden_ds_fast_us_fast" />
  <parameter name="hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en" value="disable" />
  <parameter name="hssi_adapt_tx_tx_osc_clock_setting" value="osc_clk_div_by1" />
  <parameter
     name="hssi_rx_pcs_pma_interface_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter
     name="hssi_common_pcs_pma_interface_ppm_cnt_rst"
     value="ppm_cnt_rst_dis" />
  <parameter name="hssi_pldadapt_rx_internal_clk2_sel2" value="pma_clks_clk2_mux2" />
  <parameter
     name="hssi_pldadapt_rx_internal_clk2_sel1"
     value="pma_clks_or_rxfifowr_post_ct_mux_clk2_mux1" />
  <parameter name="hssi_aibcr_tx_aib_outpdrv_r56" value="aib_pdrv56_setting1" />
  <parameter name="cdr_pll_clklow_mux_select" value="clklow_mux_cdr_fbclk" />
  <parameter name="hssi_adapt_rx_rx_rxeq_en" value="disable" />
  <parameter name="tx_fifo_mode" value="Phase compensation" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_analog_mode" value="user_custom" />
  <parameter name="hssi_rx_pld_pcs_interface_hd_pcs10g_sup_mode" value="user_mode" />
  <parameter name="pma_rx_deser_deser_factor" value="deser_32b" />
  <parameter
     name="hssi_common_pcs_pma_interface_ctrl_plane_bonding"
     value="individual" />
  <parameter
     name="hssi_avmm1_if_pldadapt_avmm_osc_clock_setting"
     value="osc_clk_div_by1" />
  <parameter name="cdr_pll_analog_mode" value="user_custom" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pcs_rx_pwr_scaling_clk"
     value="pma_rx_clk" />
  <parameter name="hssi_aibnd_tx_aib_tx_selflock" value="aib_tx_selflock_enable" />
  <parameter name="pma_rx_dfe_tap6_coeff" value="0" />
  <parameter name="hssi_tx_pld_pcs_interface_pcs_tx_clk_source" value="teng" />
  <parameter
     name="pma_adapt_adp_bist_datapath_en"
     value="radp_bist_datapath_en_disable" />
  <parameter name="hssi_8g_rx_pcs_eidle_entry_iei" value="dis_eidle_iei" />
  <parameter name="hssi_pldadapt_tx_fifo_rd_clk_scg_en" value="disable" />
  <parameter name="hssi_8g_rx_pcs_ibm_invalid_code" value="dis_ibm_invalid_code" />
  <parameter
     name="hssi_pldadapt_tx_hdpldadapt_pld_tx_clk2_dcm_hz"
     value="644531250" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_dll_entest"
     value="aib_tx_dcc_dll_test_disable" />
  <parameter name="hssi_adapt_rx_sup_mode" value="user_mode" />
  <parameter name="hssi_tx_pcs_pma_interface_reconfig_settings" value="{}" />
  <parameter name="cdr_pll_f_min_pfd" value="25000000" />
  <parameter
     name="hssi_pldadapt_tx_tx_hip_aib_ssr_in_polling_bypass"
     value="disable" />
  <parameter name="hssi_pipe_gen1_2_rvod_sel_e_val" value="0" />
  <parameter
     name="pma_cdr_refclk_pm_cr_tx_rx_scratch3_src"
     value="scratch3_power_down" />
  <parameter name="hssi_pldadapt_tx_ds_last_chnl" value="ds_last_chnl" />
  <parameter name="cdr_pll_lf_resistor_pfd" value="lf_pfd_setting2" />
  <parameter name="pma_tx_buf_cdr_cp_calibration_en" value="cdr_cp_cal_disable" />
  <parameter name="hssi_adapt_tx_fifo_width" value="fifo_double_width" />
  <parameter name="hssi_aibnd_tx_aib_tx_dcc_byp" value="aib_tx_dcc_byp_disable" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_shared_fifo_width_tx"
     value="single_tx" />
  <parameter name="pma_rx_dfe_tap5_coeff" value="0" />
  <parameter name="enable_double_rate_transfer" value="0" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx"
     value="disabled_prot_mode_rx" />
  <parameter
     name="hssi_aibcr_tx_aib_red_txferclkout_shiften"
     value="aib_red_txferclkout_shift_disable" />
  <parameter name="hssi_common_pcs_pma_interface_reconfig_settings" value="{}" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs10g_low_latency_en_tx"
     value="disable" />
  <parameter
     name="hssi_aibcr_tx_aib_red_drx_shiften"
     value="aib_red_drx_shift_disable" />
  <parameter name="hssi_8g_rx_pcs_rx_clk2" value="rcvd_clk_clk2" />
  <parameter name="hssi_aibcr_tx_aib_outpdrv_r34" value="aib_pdrv34_setting1" />
  <parameter name="hssi_tx_pcs_pma_interface_prbs9_dwidth" value="prbs9_64b" />
  <parameter name="hssi_adapt_rx_control_del" value="control_del_none" />
  <parameter name="hssi_tx_pld_pcs_interface_hd_pcs8g_lpbk_en" value="disable" />
  <parameter name="cdr_pll_set_cdr_vco_speed_fix" value="92" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_sup_mode"
     value="user_mode" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_dy_ctlsel"
     value="aib_dllstr_align_dy_ctlsel_setting0" />
  <parameter name="hssi_10g_tx_pcs_frmgen_mfrm_length" value="2048" />
  <parameter name="hssi_adapt_rx_fifo_stop_rd" value="rd_empty" />
  <parameter name="hssi_pldadapt_tx_frmgen_burst" value="frmgen_burst_dis" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_power_mode" value="mid_power" />
  <parameter name="enable_advanced_options" value="0" />
  <parameter name="hssi_8g_rx_pcs_eightb_tenb_decoder" value="en_8b10b_ibm" />
  <parameter name="hssi_10g_rx_pcs_blksync_bypass" value="blksync_bypass_dis" />
  <parameter name="enable_manual_bonding_settings" value="0" />
  <parameter name="pma_rx_sd_prot_mode" value="basic_rx" />
  <parameter name="hssi_adapt_rx_rx_invalid_no_change" value="disable" />
  <parameter name="hssi_pldadapt_rx_bonding_dft_en" value="dft_dis" />
  <parameter name="hssi_10g_tx_pcs_gb_tx_idwidth" value="idwidth_66" />
  <parameter name="hssi_pldadapt_tx_frmgen_pyld_ins" value="frmgen_pyld_ins_dis" />
  <parameter name="set_pcs_bonding_master" value="Auto" />
  <parameter name="lcl_enable_fast_sim_option" value="0" />
  <parameter name="hssi_10g_tx_pcs_tx_sm_pipeln" value="tx_sm_pipeln_en" />
  <parameter name="hssi_8g_tx_pcs_bonding_dft_en" value="dft_dis" />
  <parameter name="pma_adapt_adp_dfe_hold_en" value="radp_dfe_hold_en_not_hold" />
  <parameter name="enable_physical_bonding_clocks" value="0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs10g_ctrl_plane_bonding_tx"
     value="individual_tx" />
  <parameter name="cdr_pll_powermode_ac_txpll" value="txpll_ac_off" />
  <parameter name="hssi_krfec_rx_pcs_sup_mode" value="user_mode" />
  <parameter name="hssi_pldadapt_rx_us_bypass_pipeln" value="us_bypass_pipeln_dis" />
  <parameter
     name="pma_rx_buf_xrx_path_xcdr_deser_xcdr_cdr_d2a_enb"
     value="bti_d2a_disable" />
  <parameter name="set_user_identifier" value="0" />
  <parameter
     name="hssi_adapt_tx_fsr_hip_fsr_out_bit2_rst_val"
     value="reset_to_zero_hfsrout2" />
  <parameter name="hssi_8g_rx_pcs_rx_wr_clk" value="rx_clk2_div_1_2_4" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_st_lockreq_muxsel"
     value="aib_dllstr_align_st_lockreq_muxsel_setting0" />
  <parameter name="manual_tx_hssi_aib_indv" value="indv_en" />
  <parameter name="rx_enable" value="1" />
  <parameter name="hssi_aibcr_tx_aib_outpdrv_r12" value="aib_pdrv12_setting1" />
  <parameter name="hssi_adapt_rx_force_align" value="force_align_dis" />
  <parameter
     name="hssi_pipe_gen1_2_ind_error_reporting"
     value="dis_ind_error_reporting" />
  <parameter name="pma_adapt_adp_odi_rstn" value="radp_odi_rstn_1" />
  <parameter
     name="pma_adapt_adp_dc_ctle_onetime"
     value="radp_dc_ctle_onetime_disable" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_uc_cru_rstb" value="cdr_lf_reset_off" />
  <parameter
     name="hssi_aibcr_tx_aib_red_txferclkoutn_shiften"
     value="aib_red_txferclkoutn_shift_disable" />
  <parameter name="cdr_pll_f_max_cmu_out_freq" value="1" />
  <parameter name="l_enable_rx_pma_div_clkout" value="1" />
  <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
  <parameter name="hssi_aibnd_tx_aib_tx_halfcode" value="aib_tx_halfcode_enable" />
  <parameter name="hssi_avmm1_if_hssiadapt_osc_clk_scg_en" value="disable" />
  <parameter name="hssi_common_pcs_pma_interface_ppmsel" value="ppmsel_100" />
  <parameter name="rcfg_mif_file_enable" value="1" />
  <parameter name="hssi_10g_tx_pcs_fastpath" value="fastpath_dis" />
  <parameter
     name="hssi_aibnd_tx_aib_red_txferclkoutn_shiften"
     value="aib_red_txferclkoutn_shift_disable" />
  <parameter name="enable_bg_cal_debug" value="0" />
  <parameter name="std_rx_word_aligner_rvnumber" value="0" />
  <parameter name="hssi_10g_tx_pcs_dv_bond" value="dv_bond_dis" />
  <parameter name="pma_rx_dfe_tap12_sgn" value="tap12_sign_0" />
  <parameter name="rx_pma_adapt_mode" value="manual" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_dy_ctlsel"
     value="aib_tx_dcc_dy_ctlsel_setting0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_if_hrdrstctl_en"
     value="disable" />
  <parameter name="rx_coreclkin_clock_network" value="dedicated" />
  <parameter name="hssi_adapt_rx_fifo_stop_wr" value="n_wr_full" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_st_hps_ctrl_en"
     value="aib_dllstr_align_hps_ctrl_en_setting0" />
  <parameter name="pma_adapt_adp_vga_onetime" value="radp_vga_onetime_disable" />
  <parameter
     name="pma_adapt_adp_dlev_initial_load"
     value="radp_dlev_initial_load_0" />
  <parameter name="hssi_pldadapt_rx_hrdrst_align_bypass" value="enable" />
  <parameter name="hssi_adapt_rx_rx_eq_iteration" value="cycles_32" />
  <parameter name="hssi_krfec_rx_pcs_pipeln_gearbox" value="enable" />
  <parameter name="enable_port_tx_pcs_fifo_full" value="0" />
  <parameter name="pma_rx_dfe_oc_sa_cdr0o_sgn" value="oc_sa_cdr0o_sgn_0" />
  <parameter name="pma_cgb_tx_ucontrol_pcie" value="gen1" />
  <parameter name="hssi_adapt_rx_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_pipe_gen3_phy_status_delay_g3" value="0" />
  <parameter name="hssi_rx_pcs_pma_interface_rx_lpbk_en" value="lpbk_dis" />
  <parameter name="hssi_pldadapt_rx_gb_rx_idwidth" value="idwidth_32" />
  <parameter name="pcs_speedgrade" value="e2" />
  <parameter
     name="cannot_gen_exdesign_gen_msg"
     value="A design example is not available for current transceiver configuration rule. (Transceiver configuration rules:&quot;&lt;b&gt;&quot;10GBASE-R 1588&quot;&lt;/b&gt; (teng_1588_mode)&quot;)" />
  <parameter name="pma_rx_dfe_tap12_coeff" value="0" />
  <parameter name="pma_tx_buf_reserve_tx_channel" value="false" />
  <parameter
     name="hssi_8g_rx_pcs_clock_gate_cdr_eidle"
     value="en_cdr_eidle_clk_gating" />
  <parameter name="hssi_gen3_tx_pcs_reverse_lpbk" value="rev_lpbk_dis" />
  <parameter name="pma_rx_dfe_power_mode" value="mid_power" />
  <parameter name="core_speedgrade" value="e2" />
  <parameter name="cdr_pll_bandwidth_range_low" value="1" />
  <parameter name="hssi_8g_tx_pcs_gen3_tx_clk_sel" value="dis_tx_clk" />
  <parameter name="hssi_8g_rx_pcs_symbol_swap" value="dis_symbol_swap" />
  <parameter name="hssi_adapt_rx_rx_fifo_power_mode" value="full_width_full_depth" />
  <parameter name="hssi_fifo_tx_pcs_double_write_mode" value="double_write_dis" />
  <parameter name="hssi_10g_rx_pcs_fec_clken" value="fec_clk_dis" />
  <parameter name="hssi_common_pcs_pma_interface_pc_rst_counter" value="0" />
  <parameter
     name="hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk"
     value="en_dw_pc_wrclk_gating" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value"
     value="0" />
  <parameter name="hssi_pldadapt_rx_rxfifo_full" value="full_pc_dw" />
  <parameter name="pma_tx_buf_slew_rate_ctrl" value="slew_r5" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_st_dftmuxsel"
     value="aib_dllstr_align_st_dftmuxsel_setting0" />
  <parameter name="pma_rx_dfe_tap1_coeff" value="0" />
  <parameter name="pma_rx_buf_vcm_current_add" value="vcm_current_3" />
  <parameter name="std_rx_8b10b_enable" value="1" />
  <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_calibration_en" value="false" />
  <parameter name="pma_cdr_refclk_xpm_iqref_mux_iqclk_sel" value="power_down" />
  <parameter
     name="pma_tx_ser_control_clks_divtx_aibtx"
     value="no_dft_control_clkdivtx_clkaibtx" />
  <parameter name="pma_rx_dfe_tap13_coeff" value="0" />
  <parameter
     name="cdr_pll_chgpmp_dn_pd_trim_double"
     value="normal_dn_trim_current" />
  <parameter name="hssi_8g_rx_pcs_auto_error_replacement" value="dis_err_replace" />
  <parameter name="hssi_pldadapt_tx_hdpldadapt_pld_avmm2_clk_rowclk_hz" value="0" />
  <parameter name="hssi_adapt_rx_stretch_num_stages" value="seven_stage" />
  <parameter
     name="hssi_adapt_rx_rx_pld_pma_testbus_polling_bypass"
     value="disable" />
  <parameter name="pma_tx_buf_duty_cycle_cp_comp_en" value="cp_comp_off" />
  <parameter
     name="pma_tx_buf_powermode_dc_tx_vod_w_jitcomp"
     value="tx_vod_w_jitcomp_dc_l31" />
  <parameter name="hssi_aibcr_rx_sup_mode" value="user_mode" />
  <parameter name="l_rx_adapt_pcs_width" value="66" />
  <parameter name="l_release_aib_reset_first" value="1" />
  <parameter name="pma_rx_dfe_oc_sa_dno_sgn" value="oc_sa_dno_sgn_0" />
  <parameter name="hssi_pipe_gen1_2_rpre_emph_d_val" value="0" />
  <parameter
     name="hssi_pldadapt_rx_rxfifowr_post_ct_sel"
     value="rxfifowr_sclk_post_ct" />
  <parameter name="pma_cgb_uc_cgb_vreg_boost" value="no_voltage_boost" />
  <parameter name="pma_reset_sequencer_xrx_path_uc_cal_enable" value="rx_cal_off" />
  <parameter
     name="pma_rx_dfe_xrx_path_xcdr_deser_xcdr_cdr_d2a_enb"
     value="bti_d2a_disable" />
  <parameter
     name="pma_tx_buf_chgpmp_dn_trim_double"
     value="normal_dn_trim_current" />
  <parameter
     name="pma_cdr_refclk_pm_cr_tx_rx_scratch1_src"
     value="scratch1_power_down" />
  <parameter name="hssi_adapt_rx_rx_parity_sel" value="func_sel" />
  <parameter name="enable_port_tx_clkout2" value="0" />
  <parameter name="hssi_adapt_rx_bonding_dft_en" value="dft_dis" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_test_clk_pll_en_n"
     value="aib_tx_dcc_test_clk_pll_en_n_disable" />
  <parameter name="pma_adapt_adp_bist_mode_sel" value="radp_bist_mode_sel_prbs31" />
  <parameter name="hssi_aibcr_rx_aib_outpdrv_r56" value="aib_pdrv56_setting1" />
  <parameter name="hssi_tx_pcs_pma_interface_lpbk_en" value="disable" />
  <parameter name="enable_port_rx_enh_highber_clr_cnt" value="1" />
  <parameter name="hssi_aibcr_rx_aib_ddrctrl_gr1" value="aib_ddr1_setting1" />
  <parameter name="hssi_adapt_rx_hd_hssiadapt_aib_hssi_pld_sclk_hz" value="0" />
  <parameter name="hssi_krfec_tx_pcs_prot_mode" value="disable_mode" />
  <parameter name="disable_digital_reset_sequencer" value="0" />
  <parameter name="hssi_aibcr_rx_aib_ddrctrl_gr0" value="aib_ddr0_setting1" />
  <parameter name="pma_rx_dfe_tap9_coeff" value="0" />
  <parameter name="pma_tx_buf_user_fir_coeff_ctrl_sel" value="ram_ctl" />
  <parameter name="pma_adapt_adp_frame_capture" value="radp_frame_capture_0" />
  <parameter name="pma_tx_ser_ser_in_jitcomp" value="jitcomp_on" />
  <parameter name="hssi_adapt_rx_fsr_pld_ltr_rst_val" value="reset_to_zero_ltr" />
  <parameter name="enable_port_rx_clkout_hioint" value="0" />
  <parameter name="hssi_10g_tx_pcs_txfifo_pempty" value="2" />
  <parameter name="hssi_8g_tx_pcs_force_echar" value="dis_force_echar" />
  <parameter
     name="pma_tx_buf_chgpmp_up_trim_double"
     value="normal_up_trim_current" />
  <parameter
     name="hssi_pipe_gen1_2_pipe_byte_de_serializer_en"
     value="dont_care_bds" />
  <parameter name="cdr_pll_powermode_dc_bbpd" value="bbpd_dc_on" />
  <parameter name="hssi_aibnd_tx_powermode_dc" value="powerup" />
  <parameter name="tx_fifo_pempty" value="2" />
  <parameter
     name="pma_tx_buf_chgpmp_current_dn_trim"
     value="cp_current_trimming_dn_setting0" />
  <parameter
     name="hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel"
     value="teng_clk_out" />
  <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
  <parameter name="hssi_10g_rx_pcs_rd_clk_sel" value="rd_rx_pma_clk" />
  <parameter
     name="hssi_common_pcs_pma_interface_ph_fifo_reg_mode"
     value="phfifo_reg_mode_dis" />
  <parameter name="pma_tx_ser_pcie_gen" value="non_pcie" />
  <parameter name="hssi_pldadapt_rx_dv_mode" value="dv_mode_dis" />
  <parameter name="hssi_aibcr_tx_sup_mode" value="user_mode" />
  <parameter name="hssi_pldadapt_rx_hip_mode" value="disable_hip" />
  <parameter name="hssi_pldadapt_rx_rx_fastbond_rden" value="rden_ds_fast_us_fast" />
  <parameter
     name="hssi_pldadapt_tx_fpll_shared_direct_async_in_sel"
     value="fpll_shared_direct_async_in_rowclk" />
  <parameter
     name="hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl"
     value="delay1_path0" />
  <parameter name="hssi_10g_tx_pcs_dispgen_clken" value="dispgen_clk_dis" />
  <parameter
     name="hssi_adapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass"
     value="disable" />
  <parameter
     name="hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp"
     value="true" />
  <parameter name="hssi_adapt_rx_hd_hssiadapt_hip_aib_clk_hz" value="0" />
  <parameter name="hssi_aibnd_tx_powermode_ac" value="txdatapath_high_speed_pwr" />
  <parameter
     name="hssi_adapt_tx_fsr_hip_fsr_out_bit3_rst_val"
     value="reset_to_zero_hfsrout3" />
  <parameter
     name="hssi_8g_rx_pcs_wa_det_latency_sync_status_beh"
     value="dont_care_assert_sync" />
  <parameter name="hssi_adapt_tx_word_align" value="wa_en" />
  <parameter name="hssi_pldadapt_tx_compin_sel" value="compin_master" />
  <parameter name="pma_adapt_adp_po_initwait" value="radp_po_initwait_10sec" />
  <parameter name="hssi_10g_tx_pcs_dispgen_bypass" value="dispgen_bypass_en" />
  <parameter name="hssi_gen3_tx_pcs_sup_mode" value="user_mode" />
  <parameter name="hssi_aibcr_rx_aib_outpdrv_r78" value="aib_pdrv78_setting1" />
  <parameter name="set_capability_reg_enable" value="0" />
  <parameter name="hssi_8g_rx_pcs_test_bus_sel" value="tx_testbus" />
  <parameter name="pma_rx_dfe_tap4_coeff" value="0" />
  <parameter name="pcs_reset_sequencing_mode" value="not_bonded" />
  <parameter name="hssi_common_pcs_pma_interface_pma_done_counter" value="0" />
  <parameter name="set_csr_soft_logic_enable" value="0" />
  <parameter name="cdr_pll_ncnt_div" value="2" />
  <parameter name="hssi_krfec_rx_pcs_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="l_rx_pma_optimal_settings" value="true" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_pma_tx_divclk_hz" value="322265625" />
  <parameter name="hssi_pldadapt_rx_asn_en" value="disable" />
  <parameter
     name="hssi_adapt_rx_fifo_wr_clk_sel"
     value="fifo_wr_pld_pcs_rx_clk_out" />
  <parameter name="pma_rx_deser_optimal" value="true" />
  <parameter name="hssi_gen3_rx_pcs_block_sync" value="bypass_block_sync" />
  <parameter name="std_rx_word_aligner_rgnumber" value="3" />
  <parameter name="hssi_adapt_tx_hrdrst_rst_sm_dis" value="enable_tx_rst_sm" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_halfcode"
     value="aib_dllstr_align_halfcode_enable" />
  <parameter name="rx_ppm_detect_threshold" value="100" />
  <parameter name="hssi_pipe_gen3_reconfig_settings" value="{}" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_manual_up"
     value="aib_tx_dcc_manual_up0" />
  <parameter name="hssi_10g_rx_pcs_dft_clk_out_sel" value="rx_master_clk" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh"
     value="uhsif_dzt_cnt_thr_2" />
  <parameter name="bonded_mode" value="not_bonded" />
  <parameter name="hssi_adapt_rx_hd_hssiadapt_aib_hssi_rx_sr_clk_in_hz" value="0" />
  <parameter name="hssi_8g_rx_pcs_gen3_rx_clk_sel" value="rcvd_clk" />
  <parameter name="hssi_10g_rx_pcs_rx_sm_hiber" value="rx_sm_hiber_en" />
  <parameter
     name="hssi_aibcr_tx_aib_red_pinp_shiften"
     value="aib_red_pinp_shift_disable" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_clklow_clk_hz"
     value="322265625" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_byp_iocsr_unused"
     value="aib_tx_dcc_byp_disable_iocsr_unused" />
  <parameter name="enable_calibration" value="1" />
  <parameter name="enable_eios_rx_protect" value="0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs10g_shared_fifo_width_tx"
     value="single_tx" />
  <parameter name="pma_rx_dfe_tap7_coeff" value="0" />
  <parameter name="hssi_pldadapt_tx_hip_mode" value="disable_hip" />
  <parameter name="hssi_common_pld_pcs_interface_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_aibcr_rx_aib_outpdrv_r12" value="aib_pdrv12_setting1" />
  <parameter name="hssi_adapt_rx_fifo_double_write" value="fifo_double_write_en" />
  <parameter name="hssi_pldadapt_tx_fifo_wr_clk_scg_en" value="disable" />
  <parameter name="hssi_aibnd_tx_redundancy_en" value="disable" />
  <parameter name="hssi_adapt_tx_hd_hssiadapt_speed_grade" value="dash_2" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_prot_mode_tx"
     value="teng_mode_tx" />
  <parameter name="enable_fast_sim" value="0" />
  <parameter name="cdr_pll_n_counter" value="2" />
  <parameter name="display_std_rx_pld_adapt_width" value="8" />
  <parameter name="pma_adapt_adp_clkgate_enb" value="radp_clkgate_enb_disable" />
  <parameter name="pma_rx_buf_optimal" value="true" />
  <parameter name="pma_rx_sd_sd_threshold" value="sdlv_3" />
  <parameter name="pma_tx_ser_ser_aibck_x1_override" value="normal" />
  <parameter name="std_rx_word_aligner_renumber" value="3" />
  <parameter name="channels" value="1" />
  <parameter name="pma_rx_buf_vga_ib_max_en" value="vga_ib_max_disable" />
  <parameter
     name="hssi_pldadapt_tx_aib_clk2_sel"
     value="aib_clk2_pld_pcs_tx_clk_out" />
  <parameter name="pma_rx_odi_monitor_bw_sel" value="bw_4" />
  <parameter name="hssi_adapt_rx_dyn_clk_sw_en" value="disable" />
  <parameter name="std_rx_word_aligner_pattern_len" value="10" />
  <parameter name="hssi_adapt_rx_clock_del_measure_enable" value="disable" />
  <parameter name="hssi_10g_tx_pcs_dft_clk_out_sel" value="tx_master_clk" />
  <parameter name="pma_tx_buf_dcc_finestep_enin" value="disable" />
  <parameter name="hssi_common_pcs_pma_interface_bypass_pma_ltr" value="true" />
  <parameter name="tx_fifo_pfull" value="10" />
  <parameter name="cdr_pll_top_or_bottom" value="top_or_bot_off" />
  <parameter name="pma_rx_buf_powermode_dc_vcm" value="vcm_pwr_dc3" />
  <parameter name="pma_adapt_adp_dfe_accum_depth" value="8" />
  <parameter name="hssi_10g_rx_pcs_fifo_stop_rd" value="n_rd_empty" />
  <parameter
     name="l_pll_settings"
     value="343.750000 {refclk 343.750000 m 15 n 1 lpfd 2 lpd 2 fvco 10312.5} 687.500000 {refclk 687.500000 m 15 n 2 lpfd 2 lpd 2 fvco 10312.5} 322.265625 {refclk 322.265625 m 16 n 1 lpfd 2 lpd 2 fvco 10312.5} 644.531250 {refclk 644.531250 m 16 n 2 lpfd 2 lpd 2 fvco 10312.5} 303.308824 {refclk 303.308824 m 17 n 1 lpfd 2 lpd 2 fvco 10312.5} 606.617647 {refclk 606.617647 m 17 n 2 lpfd 2 lpd 2 fvco 10312.5} 286.458333 {refclk 286.458333 m 18 n 1 lpfd 2 lpd 2 fvco 10312.5} 572.916667 {refclk 572.916667 m 18 n 2 lpfd 2 lpd 2 fvco 10312.5} 271.381579 {refclk 271.381579 m 19 n 1 lpfd 2 lpd 2 fvco 10312.5} 542.763158 {refclk 542.763158 m 19 n 2 lpfd 2 lpd 2 fvco 10312.5} 257.812500 {refclk 257.812500 m 20 n 1 lpfd 2 lpd 2 fvco 10312.5} 515.625000 {refclk 515.625000 m 20 n 2 lpfd 2 lpd 2 fvco 10312.5} 245.535714 {refclk 245.535714 m 21 n 1 lpfd 2 lpd 2 fvco 10312.5} 491.071429 {refclk 491.071429 m 21 n 2 lpfd 2 lpd 2 fvco 10312.5} 234.375000 {refclk 234.375000 m 22 n 1 lpfd 2 lpd 2 fvco 10312.5} 468.750000 {refclk 468.750000 m 22 n 2 lpfd 2 lpd 2 fvco 10312.5} 224.184783 {refclk 224.184783 m 23 n 1 lpfd 2 lpd 2 fvco 10312.5} 448.369565 {refclk 448.369565 m 23 n 2 lpfd 2 lpd 2 fvco 10312.5} 214.843750 {refclk 214.843750 m 24 n 1 lpfd 2 lpd 2 fvco 10312.5} 429.687500 {refclk 429.687500 m 24 n 2 lpfd 2 lpd 2 fvco 10312.5} 206.250000 {refclk 206.250000 m 25 n 1 lpfd 2 lpd 2 fvco 10312.5} 412.500000 {refclk 412.500000 m 25 n 2 lpfd 2 lpd 2 fvco 10312.5} 198.317308 {refclk 198.317308 m 26 n 1 lpfd 2 lpd 2 fvco 10312.5} 396.634615 {refclk 396.634615 m 26 n 2 lpfd 2 lpd 2 fvco 10312.5} 793.269231 {refclk 793.269231 m 26 n 4 lpfd 2 lpd 2 fvco 10312.5} 190.972222 {refclk 190.972222 m 27 n 1 lpfd 2 lpd 2 fvco 10312.5} 381.944444 {refclk 381.944444 m 27 n 2 lpfd 2 lpd 2 fvco 10312.5} 763.888889 {refclk 763.888889 m 27 n 4 lpfd 2 lpd 2 fvco 10312.5} 184.151786 {refclk 184.151786 m 28 n 1 lpfd 2 lpd 2 fvco 10312.5} 368.303571 {refclk 368.303571 m 28 n 2 lpfd 2 lpd 2 fvco 10312.5} 736.607143 {refclk 736.607143 m 28 n 4 lpfd 2 lpd 2 fvco 10312.5} 177.801724 {refclk 177.801724 m 29 n 1 lpfd 2 lpd 2 fvco 10312.5} 355.603448 {refclk 355.603448 m 29 n 2 lpfd 2 lpd 2 fvco 10312.5} 711.206897 {refclk 711.206897 m 29 n 4 lpfd 2 lpd 2 fvco 10312.5} 171.875000 {refclk 171.875000 m 30 n 1 lpfd 2 lpd 2 fvco 10312.5} 166.330645 {refclk 166.330645 m 31 n 1 lpfd 2 lpd 2 fvco 10312.5} 332.661290 {refclk 332.661290 m 31 n 2 lpfd 2 lpd 2 fvco 10312.5} 665.322581 {refclk 665.322581 m 31 n 4 lpfd 2 lpd 2 fvco 10312.5} 161.132813 {refclk 161.132813 m 32 n 1 lpfd 2 lpd 2 fvco 10312.5} 156.250000 {refclk 156.250000 m 33 n 1 lpfd 2 lpd 2 fvco 10312.5} 312.500000 {refclk 312.500000 m 33 n 2 lpfd 2 lpd 2 fvco 10312.5} 625.000000 {refclk 625.000000 m 33 n 4 lpfd 2 lpd 2 fvco 10312.5} 151.654412 {refclk 151.654412 m 34 n 1 lpfd 2 lpd 2 fvco 10312.5} 147.321429 {refclk 147.321429 m 35 n 1 lpfd 2 lpd 2 fvco 10312.5} 294.642857 {refclk 294.642857 m 35 n 2 lpfd 2 lpd 2 fvco 10312.5} 589.285714 {refclk 589.285714 m 35 n 4 lpfd 2 lpd 2 fvco 10312.5} 143.229167 {refclk 143.229167 m 36 n 1 lpfd 2 lpd 2 fvco 10312.5} 139.358108 {refclk 139.358108 m 37 n 1 lpfd 2 lpd 2 fvco 10312.5} 278.716216 {refclk 278.716216 m 37 n 2 lpfd 2 lpd 2 fvco 10312.5} 557.432432 {refclk 557.432432 m 37 n 4 lpfd 2 lpd 2 fvco 10312.5} 135.690789 {refclk 135.690789 m 38 n 1 lpfd 2 lpd 2 fvco 10312.5} 132.211538 {refclk 132.211538 m 39 n 1 lpfd 2 lpd 2 fvco 10312.5} 264.423077 {refclk 264.423077 m 39 n 2 lpfd 2 lpd 2 fvco 10312.5} 528.846154 {refclk 528.846154 m 39 n 4 lpfd 2 lpd 2 fvco 10312.5} 128.906250 {refclk 128.906250 m 40 n 1 lpfd 2 lpd 2 fvco 10312.5} 125.762195 {refclk 125.762195 m 41 n 1 lpfd 2 lpd 2 fvco 10312.5} 251.524390 {refclk 251.524390 m 41 n 2 lpfd 2 lpd 2 fvco 10312.5} 503.048780 {refclk 503.048780 m 41 n 4 lpfd 2 lpd 2 fvco 10312.5} 122.767857 {refclk 122.767857 m 42 n 1 lpfd 2 lpd 2 fvco 10312.5} 119.912791 {refclk 119.912791 m 43 n 1 lpfd 2 lpd 2 fvco 10312.5} 239.825581 {refclk 239.825581 m 43 n 2 lpfd 2 lpd 2 fvco 10312.5} 479.651163 {refclk 479.651163 m 43 n 4 lpfd 2 lpd 2 fvco 10312.5} 117.187500 {refclk 117.187500 m 44 n 1 lpfd 2 lpd 2 fvco 10312.5} 114.583333 {refclk 114.583333 m 45 n 1 lpfd 2 lpd 2 fvco 10312.5} 229.166667 {refclk 229.166667 m 45 n 2 lpfd 2 lpd 2 fvco 10312.5} 458.333333 {refclk 458.333333 m 45 n 4 lpfd 2 lpd 2 fvco 10312.5} 112.092391 {refclk 112.092391 m 46 n 1 lpfd 2 lpd 2 fvco 10312.5} 109.707447 {refclk 109.707447 m 47 n 1 lpfd 2 lpd 2 fvco 10312.5} 219.414894 {refclk 219.414894 m 47 n 2 lpfd 2 lpd 2 fvco 10312.5} 438.829787 {refclk 438.829787 m 47 n 4 lpfd 2 lpd 2 fvco 10312.5} 107.421875 {refclk 107.421875 m 48 n 1 lpfd 2 lpd 2 fvco 10312.5} 105.229592 {refclk 105.229592 m 49 n 1 lpfd 2 lpd 2 fvco 10312.5} 210.459184 {refclk 210.459184 m 49 n 2 lpfd 2 lpd 2 fvco 10312.5} 420.918367 {refclk 420.918367 m 49 n 4 lpfd 2 lpd 2 fvco 10312.5} 103.125000 {refclk 103.125000 m 50 n 1 lpfd 2 lpd 2 fvco 10312.5} 101.102941 {refclk 101.102941 m 51 n 1 lpfd 2 lpd 2 fvco 10312.5} 202.205882 {refclk 202.205882 m 51 n 2 lpfd 2 lpd 2 fvco 10312.5} 404.411765 {refclk 404.411765 m 51 n 4 lpfd 2 lpd 2 fvco 10312.5} 99.158654 {refclk 99.158654 m 52 n 1 lpfd 2 lpd 2 fvco 10312.5} 97.287736 {refclk 97.287736 m 53 n 1 lpfd 2 lpd 2 fvco 10312.5} 194.575472 {refclk 194.575472 m 53 n 2 lpfd 2 lpd 2 fvco 10312.5} 389.150943 {refclk 389.150943 m 53 n 4 lpfd 2 lpd 2 fvco 10312.5} 778.301887 {refclk 778.301887 m 53 n 8 lpfd 2 lpd 2 fvco 10312.5} 95.486111 {refclk 95.486111 m 54 n 1 lpfd 2 lpd 2 fvco 10312.5} 93.750000 {refclk 93.750000 m 55 n 1 lpfd 2 lpd 2 fvco 10312.5} 187.500000 {refclk 187.500000 m 55 n 2 lpfd 2 lpd 2 fvco 10312.5} 375.000000 {refclk 375.000000 m 55 n 4 lpfd 2 lpd 2 fvco 10312.5} 750.000000 {refclk 750.000000 m 55 n 8 lpfd 2 lpd 2 fvco 10312.5} 92.075893 {refclk 92.075893 m 56 n 1 lpfd 2 lpd 2 fvco 10312.5} 90.460526 {refclk 90.460526 m 57 n 1 lpfd 2 lpd 2 fvco 10312.5} 180.921053 {refclk 180.921053 m 57 n 2 lpfd 2 lpd 2 fvco 10312.5} 361.842105 {refclk 361.842105 m 57 n 4 lpfd 2 lpd 2 fvco 10312.5} 723.684211 {refclk 723.684211 m 57 n 8 lpfd 2 lpd 2 fvco 10312.5} 88.900862 {refclk 88.900862 m 58 n 1 lpfd 2 lpd 2 fvco 10312.5} 87.394068 {refclk 87.394068 m 59 n 1 lpfd 2 lpd 2 fvco 10312.5} 174.788136 {refclk 174.788136 m 59 n 2 lpfd 2 lpd 2 fvco 10312.5} 349.576271 {refclk 349.576271 m 59 n 4 lpfd 2 lpd 2 fvco 10312.5} 699.152542 {refclk 699.152542 m 59 n 8 lpfd 2 lpd 2 fvco 10312.5} 85.937500 {refclk 85.937500 m 60 n 1 lpfd 2 lpd 2 fvco 10312.5} 84.528689 {refclk 84.528689 m 61 n 1 lpfd 2 lpd 2 fvco 10312.5} 169.057377 {refclk 169.057377 m 61 n 2 lpfd 2 lpd 2 fvco 10312.5} 338.114754 {refclk 338.114754 m 61 n 4 lpfd 2 lpd 2 fvco 10312.5} 676.229508 {refclk 676.229508 m 61 n 8 lpfd 2 lpd 2 fvco 10312.5} 83.165323 {refclk 83.165323 m 62 n 1 lpfd 2 lpd 2 fvco 10312.5} 81.845238 {refclk 81.845238 m 63 n 1 lpfd 2 lpd 2 fvco 10312.5} 163.690476 {refclk 163.690476 m 63 n 2 lpfd 2 lpd 2 fvco 10312.5} 327.380952 {refclk 327.380952 m 63 n 4 lpfd 2 lpd 2 fvco 10312.5} 654.761905 {refclk 654.761905 m 63 n 8 lpfd 2 lpd 2 fvco 10312.5} 80.566406 {refclk 80.566406 m 64 n 1 lpfd 2 lpd 2 fvco 10312.5} 79.326923 {refclk 79.326923 m 65 n 1 lpfd 2 lpd 2 fvco 10312.5} 158.653846 {refclk 158.653846 m 65 n 2 lpfd 2 lpd 2 fvco 10312.5} 317.307692 {refclk 317.307692 m 65 n 4 lpfd 2 lpd 2 fvco 10312.5} 634.615385 {refclk 634.615385 m 65 n 8 lpfd 2 lpd 2 fvco 10312.5} 78.125000 {refclk 78.125000 m 66 n 1 lpfd 2 lpd 2 fvco 10312.5} 76.958955 {refclk 76.958955 m 67 n 1 lpfd 2 lpd 2 fvco 10312.5} 153.917910 {refclk 153.917910 m 67 n 2 lpfd 2 lpd 2 fvco 10312.5} 307.835821 {refclk 307.835821 m 67 n 4 lpfd 2 lpd 2 fvco 10312.5} 615.671642 {refclk 615.671642 m 67 n 8 lpfd 2 lpd 2 fvco 10312.5} 75.827206 {refclk 75.827206 m 68 n 1 lpfd 2 lpd 2 fvco 10312.5} 74.728261 {refclk 74.728261 m 69 n 1 lpfd 2 lpd 2 fvco 10312.5} 149.456522 {refclk 149.456522 m 69 n 2 lpfd 2 lpd 2 fvco 10312.5} 298.913043 {refclk 298.913043 m 69 n 4 lpfd 2 lpd 2 fvco 10312.5} 597.826087 {refclk 597.826087 m 69 n 8 lpfd 2 lpd 2 fvco 10312.5} 73.660714 {refclk 73.660714 m 70 n 1 lpfd 2 lpd 2 fvco 10312.5} 72.623239 {refclk 72.623239 m 71 n 1 lpfd 2 lpd 2 fvco 10312.5} 145.246479 {refclk 145.246479 m 71 n 2 lpfd 2 lpd 2 fvco 10312.5} 290.492958 {refclk 290.492958 m 71 n 4 lpfd 2 lpd 2 fvco 10312.5} 580.985915 {refclk 580.985915 m 71 n 8 lpfd 2 lpd 2 fvco 10312.5} 71.614583 {refclk 71.614583 m 72 n 1 lpfd 2 lpd 2 fvco 10312.5} 70.633562 {refclk 70.633562 m 73 n 1 lpfd 2 lpd 2 fvco 10312.5} 141.267123 {refclk 141.267123 m 73 n 2 lpfd 2 lpd 2 fvco 10312.5} 282.534247 {refclk 282.534247 m 73 n 4 lpfd 2 lpd 2 fvco 10312.5} 565.068493 {refclk 565.068493 m 73 n 8 lpfd 2 lpd 2 fvco 10312.5} 69.679054 {refclk 69.679054 m 74 n 1 lpfd 2 lpd 2 fvco 10312.5} 68.750000 {refclk 68.750000 m 75 n 1 lpfd 2 lpd 2 fvco 10312.5} 137.500000 {refclk 137.500000 m 75 n 2 lpfd 2 lpd 2 fvco 10312.5} 275.000000 {refclk 275.000000 m 75 n 4 lpfd 2 lpd 2 fvco 10312.5} 550.000000 {refclk 550.000000 m 75 n 8 lpfd 2 lpd 2 fvco 10312.5} 67.845395 {refclk 67.845395 m 76 n 1 lpfd 2 lpd 2 fvco 10312.5} 66.964286 {refclk 66.964286 m 77 n 1 lpfd 2 lpd 2 fvco 10312.5} 133.928571 {refclk 133.928571 m 77 n 2 lpfd 2 lpd 2 fvco 10312.5} 267.857143 {refclk 267.857143 m 77 n 4 lpfd 2 lpd 2 fvco 10312.5} 535.714286 {refclk 535.714286 m 77 n 8 lpfd 2 lpd 2 fvco 10312.5} 66.105769 {refclk 66.105769 m 78 n 1 lpfd 2 lpd 2 fvco 10312.5} 65.268987 {refclk 65.268987 m 79 n 1 lpfd 2 lpd 2 fvco 10312.5} 130.537975 {refclk 130.537975 m 79 n 2 lpfd 2 lpd 2 fvco 10312.5} 261.075949 {refclk 261.075949 m 79 n 4 lpfd 2 lpd 2 fvco 10312.5} 522.151899 {refclk 522.151899 m 79 n 8 lpfd 2 lpd 2 fvco 10312.5} 64.453125 {refclk 64.453125 m 80 n 1 lpfd 2 lpd 2 fvco 10312.5} 63.657407 {refclk 63.657407 m 81 n 1 lpfd 2 lpd 2 fvco 10312.5} 127.314815 {refclk 127.314815 m 81 n 2 lpfd 2 lpd 2 fvco 10312.5} 254.629630 {refclk 254.629630 m 81 n 4 lpfd 2 lpd 2 fvco 10312.5} 509.259259 {refclk 509.259259 m 81 n 8 lpfd 2 lpd 2 fvco 10312.5} 62.881098 {refclk 62.881098 m 82 n 1 lpfd 2 lpd 2 fvco 10312.5} 62.123494 {refclk 62.123494 m 83 n 1 lpfd 2 lpd 2 fvco 10312.5} 124.246988 {refclk 124.246988 m 83 n 2 lpfd 2 lpd 2 fvco 10312.5} 248.493976 {refclk 248.493976 m 83 n 4 lpfd 2 lpd 2 fvco 10312.5} 496.987952 {refclk 496.987952 m 83 n 8 lpfd 2 lpd 2 fvco 10312.5} 61.383929 {refclk 61.383929 m 84 n 1 lpfd 2 lpd 2 fvco 10312.5} 60.661765 {refclk 60.661765 m 85 n 1 lpfd 2 lpd 2 fvco 10312.5} 121.323529 {refclk 121.323529 m 85 n 2 lpfd 2 lpd 2 fvco 10312.5} 242.647059 {refclk 242.647059 m 85 n 4 lpfd 2 lpd 2 fvco 10312.5} 485.294118 {refclk 485.294118 m 85 n 8 lpfd 2 lpd 2 fvco 10312.5} 59.956395 {refclk 59.956395 m 86 n 1 lpfd 2 lpd 2 fvco 10312.5} 59.267241 {refclk 59.267241 m 87 n 1 lpfd 2 lpd 2 fvco 10312.5} 118.534483 {refclk 118.534483 m 87 n 2 lpfd 2 lpd 2 fvco 10312.5} 237.068966 {refclk 237.068966 m 87 n 4 lpfd 2 lpd 2 fvco 10312.5} 474.137931 {refclk 474.137931 m 87 n 8 lpfd 2 lpd 2 fvco 10312.5} 58.593750 {refclk 58.593750 m 88 n 1 lpfd 2 lpd 2 fvco 10312.5} 57.935393 {refclk 57.935393 m 89 n 1 lpfd 2 lpd 2 fvco 10312.5} 115.870787 {refclk 115.870787 m 89 n 2 lpfd 2 lpd 2 fvco 10312.5} 231.741573 {refclk 231.741573 m 89 n 4 lpfd 2 lpd 2 fvco 10312.5} 463.483146 {refclk 463.483146 m 89 n 8 lpfd 2 lpd 2 fvco 10312.5} 57.291667 {refclk 57.291667 m 90 n 1 lpfd 2 lpd 2 fvco 10312.5} 56.662088 {refclk 56.662088 m 91 n 1 lpfd 2 lpd 2 fvco 10312.5} 113.324176 {refclk 113.324176 m 91 n 2 lpfd 2 lpd 2 fvco 10312.5} 226.648352 {refclk 226.648352 m 91 n 4 lpfd 2 lpd 2 fvco 10312.5} 453.296703 {refclk 453.296703 m 91 n 8 lpfd 2 lpd 2 fvco 10312.5} 56.046196 {refclk 56.046196 m 92 n 1 lpfd 2 lpd 2 fvco 10312.5} 55.443548 {refclk 55.443548 m 93 n 1 lpfd 2 lpd 2 fvco 10312.5} 110.887097 {refclk 110.887097 m 93 n 2 lpfd 2 lpd 2 fvco 10312.5} 221.774194 {refclk 221.774194 m 93 n 4 lpfd 2 lpd 2 fvco 10312.5} 443.548387 {refclk 443.548387 m 93 n 8 lpfd 2 lpd 2 fvco 10312.5} 54.853723 {refclk 54.853723 m 94 n 1 lpfd 2 lpd 2 fvco 10312.5} 54.276316 {refclk 54.276316 m 95 n 1 lpfd 2 lpd 2 fvco 10312.5} 108.552632 {refclk 108.552632 m 95 n 2 lpfd 2 lpd 2 fvco 10312.5} 217.105263 {refclk 217.105263 m 95 n 4 lpfd 2 lpd 2 fvco 10312.5} 434.210526 {refclk 434.210526 m 95 n 8 lpfd 2 lpd 2 fvco 10312.5} 53.710938 {refclk 53.710938 m 96 n 1 lpfd 2 lpd 2 fvco 10312.5} 53.157216 {refclk 53.157216 m 97 n 1 lpfd 2 lpd 2 fvco 10312.5} 106.314433 {refclk 106.314433 m 97 n 2 lpfd 2 lpd 2 fvco 10312.5} 212.628866 {refclk 212.628866 m 97 n 4 lpfd 2 lpd 2 fvco 10312.5} 425.257732 {refclk 425.257732 m 97 n 8 lpfd 2 lpd 2 fvco 10312.5} 52.614796 {refclk 52.614796 m 98 n 1 lpfd 2 lpd 2 fvco 10312.5} 52.083333 {refclk 52.083333 m 99 n 1 lpfd 2 lpd 2 fvco 10312.5} 104.166667 {refclk 104.166667 m 99 n 2 lpfd 2 lpd 2 fvco 10312.5} 208.333333 {refclk 208.333333 m 99 n 4 lpfd 2 lpd 2 fvco 10312.5} 416.666667 {refclk 416.666667 m 99 n 8 lpfd 2 lpd 2 fvco 10312.5} 51.562500 {refclk 51.562500 m 100 n 1 lpfd 2 lpd 2 fvco 10312.5} 51.051980 {refclk 51.051980 m 101 n 1 lpfd 2 lpd 2 fvco 10312.5} 102.103960 {refclk 102.103960 m 101 n 2 lpfd 2 lpd 2 fvco 10312.5} 204.207921 {refclk 204.207921 m 101 n 4 lpfd 2 lpd 2 fvco 10312.5} 408.415842 {refclk 408.415842 m 101 n 8 lpfd 2 lpd 2 fvco 10312.5} 50.551471 {refclk 50.551471 m 102 n 1 lpfd 2 lpd 2 fvco 10312.5} 50.060680 {refclk 50.060680 m 103 n 1 lpfd 2 lpd 2 fvco 10312.5} 100.121359 {refclk 100.121359 m 103 n 2 lpfd 2 lpd 2 fvco 10312.5} 200.242718 {refclk 200.242718 m 103 n 4 lpfd 2 lpd 2 fvco 10312.5} 400.485437 {refclk 400.485437 m 103 n 8 lpfd 2 lpd 2 fvco 10312.5} 49.579327 {refclk 49.579327 m 104 n 1 lpfd 2 lpd 2 fvco 10312.5} 49.107143 {refclk 49.107143 m 105 n 1 lpfd 2 lpd 2 fvco 10312.5} 98.214286 {refclk 98.214286 m 105 n 2 lpfd 2 lpd 2 fvco 10312.5} 196.428571 {refclk 196.428571 m 105 n 4 lpfd 2 lpd 2 fvco 10312.5} 392.857143 {refclk 392.857143 m 105 n 8 lpfd 2 lpd 2 fvco 10312.5} 48.643868 {refclk 48.643868 m 106 n 1 lpfd 2 lpd 2 fvco 10312.5} 48.189252 {refclk 48.189252 m 107 n 1 lpfd 2 lpd 2 fvco 10312.5} 96.378505 {refclk 96.378505 m 107 n 2 lpfd 2 lpd 2 fvco 10312.5} 192.757009 {refclk 192.757009 m 107 n 4 lpfd 2 lpd 2 fvco 10312.5} 385.514019 {refclk 385.514019 m 107 n 8 lpfd 2 lpd 2 fvco 10312.5} 47.743056 {refclk 47.743056 m 108 n 1 lpfd 2 lpd 2 fvco 10312.5} 47.305046 {refclk 47.305046 m 109 n 1 lpfd 2 lpd 2 fvco 10312.5} 94.610092 {refclk 94.610092 m 109 n 2 lpfd 2 lpd 2 fvco 10312.5} 189.220183 {refclk 189.220183 m 109 n 4 lpfd 2 lpd 2 fvco 10312.5} 378.440367 {refclk 378.440367 m 109 n 8 lpfd 2 lpd 2 fvco 10312.5} 46.875000 {refclk 46.875000 m 110 n 1 lpfd 2 lpd 2 fvco 10312.5} 46.452703 {refclk 46.452703 m 111 n 1 lpfd 2 lpd 2 fvco 10312.5} 92.905405 {refclk 92.905405 m 111 n 2 lpfd 2 lpd 2 fvco 10312.5} 185.810811 {refclk 185.810811 m 111 n 4 lpfd 2 lpd 2 fvco 10312.5} 371.621622 {refclk 371.621622 m 111 n 8 lpfd 2 lpd 2 fvco 10312.5} 46.037946 {refclk 46.037946 m 112 n 1 lpfd 2 lpd 2 fvco 10312.5} 45.630531 {refclk 45.630531 m 113 n 1 lpfd 2 lpd 2 fvco 10312.5} 91.261062 {refclk 91.261062 m 113 n 2 lpfd 2 lpd 2 fvco 10312.5} 182.522124 {refclk 182.522124 m 113 n 4 lpfd 2 lpd 2 fvco 10312.5} 365.044248 {refclk 365.044248 m 113 n 8 lpfd 2 lpd 2 fvco 10312.5} 45.230263 {refclk 45.230263 m 114 n 1 lpfd 2 lpd 2 fvco 10312.5} 44.836957 {refclk 44.836957 m 115 n 1 lpfd 2 lpd 2 fvco 10312.5} 89.673913 {refclk 89.673913 m 115 n 2 lpfd 2 lpd 2 fvco 10312.5} 179.347826 {refclk 179.347826 m 115 n 4 lpfd 2 lpd 2 fvco 10312.5} 358.695652 {refclk 358.695652 m 115 n 8 lpfd 2 lpd 2 fvco 10312.5} 44.450431 {refclk 44.450431 m 116 n 1 lpfd 2 lpd 2 fvco 10312.5} 44.070513 {refclk 44.070513 m 117 n 1 lpfd 2 lpd 2 fvco 10312.5} 88.141026 {refclk 88.141026 m 117 n 2 lpfd 2 lpd 2 fvco 10312.5} 176.282051 {refclk 176.282051 m 117 n 4 lpfd 2 lpd 2 fvco 10312.5} 352.564103 {refclk 352.564103 m 117 n 8 lpfd 2 lpd 2 fvco 10312.5} 43.697034 {refclk 43.697034 m 118 n 1 lpfd 2 lpd 2 fvco 10312.5} 43.329832 {refclk 43.329832 m 119 n 1 lpfd 2 lpd 2 fvco 10312.5} 86.659664 {refclk 86.659664 m 119 n 2 lpfd 2 lpd 2 fvco 10312.5} 173.319328 {refclk 173.319328 m 119 n 4 lpfd 2 lpd 2 fvco 10312.5} 346.638655 {refclk 346.638655 m 119 n 8 lpfd 2 lpd 2 fvco 10312.5} 42.968750 {refclk 42.968750 m 120 n 1 lpfd 2 lpd 2 fvco 10312.5} 42.613636 {refclk 42.613636 m 121 n 1 lpfd 2 lpd 2 fvco 10312.5} 85.227273 {refclk 85.227273 m 121 n 2 lpfd 2 lpd 2 fvco 10312.5} 170.454545 {refclk 170.454545 m 121 n 4 lpfd 2 lpd 2 fvco 10312.5} 340.909091 {refclk 340.909091 m 121 n 8 lpfd 2 lpd 2 fvco 10312.5} 42.264344 {refclk 42.264344 m 122 n 1 lpfd 2 lpd 2 fvco 10312.5} 41.920732 {refclk 41.920732 m 123 n 1 lpfd 2 lpd 2 fvco 10312.5} 83.841463 {refclk 83.841463 m 123 n 2 lpfd 2 lpd 2 fvco 10312.5} 167.682927 {refclk 167.682927 m 123 n 4 lpfd 2 lpd 2 fvco 10312.5} 335.365854 {refclk 335.365854 m 123 n 8 lpfd 2 lpd 2 fvco 10312.5} 41.582661 {refclk 41.582661 m 124 n 1 lpfd 2 lpd 2 fvco 10312.5} 41.250000 {refclk 41.250000 m 125 n 1 lpfd 2 lpd 2 fvco 10312.5} 82.500000 {refclk 82.500000 m 125 n 2 lpfd 2 lpd 2 fvco 10312.5} 165.000000 {refclk 165.000000 m 125 n 4 lpfd 2 lpd 2 fvco 10312.5} 330.000000 {refclk 330.000000 m 125 n 8 lpfd 2 lpd 2 fvco 10312.5} 40.922619 {refclk 40.922619 m 126 n 1 lpfd 2 lpd 2 fvco 10312.5} 40.600394 {refclk 40.600394 m 127 n 1 lpfd 2 lpd 2 fvco 10312.5} 81.200787 {refclk 81.200787 m 127 n 2 lpfd 2 lpd 2 fvco 10312.5} 162.401575 {refclk 162.401575 m 127 n 4 lpfd 2 lpd 2 fvco 10312.5} 324.803150 {refclk 324.803150 m 127 n 8 lpfd 2 lpd 2 fvco 10312.5} allowed_ranges {40.600394 40.922619 41.250000 41.582661 41.920732 42.264344 42.613636 42.968750 43.329832 43.697034 44.070513 44.450431 44.836957 45.230263 45.630531 46.037946 46.452703 46.875000 47.305046 47.743056 48.189252 48.643868 49.107143 49.579327 50.060680 50.551471 51.051980 51.562500 52.083333 52.614796 53.157216 53.710938 54.276316 54.853723 55.443548 56.046196 56.662088 57.291667 57.935393 58.593750 59.267241 59.956395 60.661765 61.383929 62.123494 62.881098 63.657407 64.453125 65.268987 66.105769 66.964286 67.845395 68.750000 69.679054 70.633562 71.614583 72.623239 73.660714 74.728261 75.827206 76.958955 78.125000 79.326923 80.566406 81.200787 81.845238 82.500000 83.165323 83.841463 84.528689 85.227273 85.937500 86.659664 87.394068 88.141026 88.900862 89.673913 90.460526 91.261062 92.075893 92.905405 93.750000 94.610092 95.486111 96.378505 97.287736 98.214286 99.158654 100.121359 101.102941 102.103960 103.125000 104.166667 105.229592 106.314433 107.421875 108.552632 109.707447 110.887097 112.092391 113.324176 114.583333 115.870787 117.187500 118.534483 119.912791 121.323529 122.767857 124.246988 125.762195 127.314815 128.906250 130.537975 132.211538 133.928571 135.690789 137.500000 139.358108 141.267123 143.229167 145.246479 147.321429 149.456522 151.654412 153.917910 156.250000 158.653846 161.132813 162.401575 163.690476 165.000000 166.330645 167.682927 169.057377 170.454545 171.875000 173.319328 174.788136 176.282051 177.801724 179.347826 180.921053 182.522124 184.151786 185.810811 187.500000 189.220183 190.972222 192.757009 194.575472 196.428571 198.317308 200.242718 202.205882 204.207921 206.250000 208.333333 210.459184 212.628866 214.843750 217.105263 219.414894 221.774194 224.184783 226.648352 229.166667 231.741573 234.375000 237.068966 239.825581 242.647059 245.535714 248.493976 251.524390 254.629630 257.812500 261.075949 264.423077 267.857143 271.381579 275.000000 278.716216 282.534247 286.458333 290.492958 294.642857 298.913043 303.308824 307.835821 312.500000 317.307692 322.265625 324.803150 327.380952 330.000000 332.661290 335.365854 338.114754 340.909091 343.750000 346.638655 349.576271 352.564103 355.603448 358.695652 361.842105 365.044248 368.303571 371.621622 375.000000 378.440367 381.944444 385.514019 389.150943 392.857143 396.634615 400.485437 404.411765 408.415842 412.500000 416.666667 420.918367 425.257732 429.687500 434.210526 438.829787 443.548387 448.369565 453.296703 458.333333 463.483146 468.750000 474.137931 479.651163 485.294118 491.071429 496.987952 503.048780 509.259259 515.625000 522.151899 528.846154 535.714286 542.763158 550.000000 557.432432 565.068493 572.916667 580.985915 589.285714 597.826087 606.617647 615.671642 625.000000 634.615385 644.531250 654.761905 665.322581 676.229508 687.500000 699.152542 711.206897 723.684211 736.607143 750.000000 763.888889 778.301887 793.269231}" />
  <parameter name="hssi_8g_rx_pcs_clkcmp_pattern_n" value="0" />
  <parameter name="cdr_pll_powermode_ac_bbpd" value="bbpd_ac_on" />
  <parameter name="hssi_8g_rx_pcs_clkcmp_pattern_p" value="0" />
  <parameter name="hssi_10g_tx_pcs_data_bit_reverse" value="data_bit_reverse_dis" />
  <parameter
     name="pma_cdr_refclk_inclk2_logical_to_physical_mapping"
     value="ref_iqclk0" />
  <parameter name="hssi_common_pcs_pma_interface_sigdet_wait_counter" value="0" />
  <parameter name="hssi_10g_tx_pcs_pempty_flag_type" value="pempty_rd_side" />
  <parameter name="pma_tx_ser_initial_settings" value="true" />
  <parameter name="pma_rx_buf_powermode_dc_vga" value="vga_pwr_dc_half" />
  <parameter name="hssi_krfec_rx_pcs_rx_testbus_sel" value="overall" />
  <parameter name="hssi_10g_rx_pcs_rx_testbus_sel" value="rx_fifo_testbus1" />
  <parameter name="hssi_aibcr_tx_aib_outpdrv_r78" value="aib_pdrv78_setting1" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_prot_mode_tx"
     value="teng_1588_baser_tx" />
  <parameter name="hssi_8g_rx_pcs_rx_rd_clk" value="rx_clk" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_st_rst_prgmnvrt"
     value="aib_dllstr_align_st_rst_prgmnvrt_setting0" />
  <parameter name="pma_tx_buf_uc_tx_cal" value="uc_tx_cal_on" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_sup_mode"
     value="user_mode" />
  <parameter name="pma_adapt_adp_oc_accum_depth" value="11" />
  <parameter name="hssi_common_pcs_pma_interface_block_sel" value="eight_g_pcs" />
  <parameter
     name="pma_adapt_adp_adapt_control_sel"
     value="radp_adapt_control_sel_from_cram" />
  <parameter name="pma_rx_buf_pm_cr2_tx_rx_pcie_gen" value="non_pcie" />
  <parameter name="hssi_rx_pld_pcs_interface_hd_pcs_channel_hclk_clk_hz" value="0" />
  <parameter
     name="hssi_pldadapt_rx_aib_clk1_sel"
     value="aib_clk1_pld_pcs_rx_clk_out" />
  <parameter name="hssi_pldadapt_rx_pld_clk1_delay_sel" value="delay_path13" />
  <parameter name="l_rx_transfer_clk_hz" value="644531250" />
  <parameter name="pma_tx_buf_ser_powerdown" value="normal_ser_on" />
  <parameter name="pma_rx_buf_link" value="link_off" />
  <parameter name="pma_adapt_prot_mode" value="basic_rx" />
  <parameter name="rcfg_sv_file_enable" value="1" />
  <parameter name="adme_prot_mode" value="teng_1588_mode" />
  <parameter name="hssi_pldadapt_rx_ds_master" value="ds_master_en" />
  <parameter
     name="hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock"
     value="knum_sh_cnt_prelock_10g" />
  <parameter
     name="pma_adapt_adp_vga_initial_value"
     value="radp_vga_initial_value_4" />
  <parameter name="pma_rx_buf_qpi_enable" value="non_qpi_mode" />
  <parameter name="pma_tx_ser_xtx_path_xtx_idle_ctrl" value="id_cpen_on" />
  <parameter
     name="hssi_pipe_gen1_2_phystatus_rst_toggle"
     value="dis_phystatus_rst_toggle" />
  <parameter name="hssi_avmm1_if_pldadapt_gate_dis" value="disable" />
  <parameter name="hssi_pldadapt_rx_clock_del_measure_enable" value="disable" />
  <parameter name="pma_tx_buf_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_10g_tx_pcs_scrm_bypass" value="scrm_bypass_dis" />
  <parameter name="hssi_adapt_rx_rx_use_rxvalid_for_rxeq" value="rxvalid" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_en_iocsr_unused"
     value="aib_rx_dcc_disable_iocsr_unused" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_ctrl_plane_bonding_rx"
     value="individual_rx" />
  <parameter name="pma_rx_buf_advanced_mode" value="false" />
  <parameter name="hssi_10g_rx_pcs_fifo_stop_wr" value="n_wr_full" />
  <parameter name="hssi_8g_rx_pcs_rate_match_ins_thres" value="dis_rm_ins_thres" />
  <parameter name="hssi_adapt_tx_phcomp_rd_del" value="phcomp_rd_del2" />
  <parameter name="hssi_adapt_rx_rx_rmfflag_stretch_enable" value="enable" />
  <parameter name="pma_rx_buf_rx_lfeq_enable" value="rx_lfeq_disable" />
  <parameter name="pma_rx_deser_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_pipe_gen3_bypass_rx_detection_enable" value="false" />
  <parameter name="hssi_adapt_rx_pma_hclk_scg_en" value="enable" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_tile_type" value="h" />
  <parameter name="hssi_10g_rx_pcs_full_flag_type" value="full_wr_side" />
  <parameter name="hssi_10g_tx_pcs_tx_scrm_width" value="bit64" />
  <parameter name="pma_cgb_scratch0_x1_clock_src" value="not_used" />
  <parameter name="hssi_pldadapt_tx_us_master" value="us_master_en" />
  <parameter name="enable_port_rx_enh_blk_lock" value="1" />
  <parameter name="cdr_pll_rstb" value="cdr_lf_reset_off" />
  <parameter name="pma_rx_buf_term_tri_enable" value="disable_tri" />
  <parameter name="hssi_10g_tx_pcs_phcomp_rd_del" value="phcomp_rd_del2" />
  <parameter name="pma_adapt_adp_oc_bypass" value="radp_oc_bypass_bypass" />
  <parameter
     name="hssi_pldadapt_tx_fsr_hip_fsr_in_bit2_rst_val"
     value="reset_to_one_hfsrin2" />
  <parameter name="hssi_10g_rx_pcs_rx_true_b2b" value="b2b" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_operating_voltage"
     value="standard" />
  <parameter name="enable_port_rx_enh_clr_errblk_count" value="1" />
  <parameter name="pma_cdr_refclk_receiver_detect_src" value="iqclk_src" />
  <parameter name="hssi_adapt_rx_ds_master" value="ds_master_en" />
  <parameter name="pma_rx_odi_phase_steps_sel" value="step33" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_prot_mode_rx"
     value="teng_mode_rx" />
  <parameter name="adapter_ehip_mode" value="disable_hip" />
  <parameter name="pma_cgb_tx_ucontrol_en" value="disable" />
  <parameter
     name="hssi_tx_pcs_pma_interface_master_clk_sel"
     value="master_tx_pma_clk" />
  <parameter name="hssi_8g_tx_pcs_phase_compensation_fifo" value="register_fifo" />
  <parameter name="cdr_pll_pd_l_counter" value="2" />
  <parameter name="hssi_gen3_rx_pcs_rate_match_fifo_latency" value="low_latency" />
  <parameter name="hssi_adapt_tx_us_last_chnl" value="us_last_chnl" />
  <parameter name="pma_adapt_adp_dc_ctle_en" value="radp_dc_ctle_en_disable" />
  <parameter name="pma_tx_ser_bti_protected" value="false" />
  <parameter name="pma_tx_ser_ser_aibck_enable" value="enable" />
  <parameter name="enable_advanced_avmm_options" value="0" />
  <parameter name="hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en" value="disable" />
  <parameter name="hssi_krfec_rx_pcs_pipeln_blksync" value="enable" />
  <parameter name="pma_reset_sequencer_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_avmm1_if_hssiadapt_sr_sr_osc_clk_div_sel" value="non_div" />
  <parameter name="set_hip_cal_en" value="0" />
  <parameter name="enh_tx_sh_err" value="0" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_entest"
     value="aib_dllstr_align_test_disable" />
  <parameter
     name="hssi_aibcr_tx_aib_red_rx_shiften"
     value="aib_red_rx_shift_disable" />
  <parameter name="hssi_pldadapt_rx_fifo_mode" value="phase_comp" />
  <parameter
     name="pma_rx_buf_pm_cr2_tx_rx_uc_odi_eye_left"
     value="uc_odi_eye_left_off" />
  <parameter name="pma_rx_odi_optimal" value="true" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_dy_ctl_static"
     value="aib_dllstr_align_dy_ctl_static_setting1" />
  <parameter name="hssi_adapt_rx_rx_datapath_tb_sel" value="cp_bond" />
  <parameter name="pma_tx_buf_duty_cycle_correction_bandwidth" value="dcc_bw_2" />
  <parameter name="enh_tx_scram_seed" value="288230376151711743" />
  <parameter name="l_std_rx_word_width" value="8" />
  <parameter name="hssi_common_pcs_pma_interface_cid_enable" value="dis_cid_mode" />
  <parameter name="tx_pma_output_swing_ctrl" value="12" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value"
     value="0" />
  <parameter name="pma_rx_deser_bitslip_bypass" value="bs_bypass_yes" />
  <parameter name="hssi_8g_rx_pcs_wa_disp_err_flag" value="en_disp_err_flag" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_optimal" value="true" />
  <parameter name="pma_adapt_adp_dfe_tap_sel_en" value="radp_dfe_tap_sel_en_no" />
  <parameter name="pma_adapt_adp_vga_hold_en" value="radp_vga_hold_en_not_hold" />
  <parameter name="l_enable_tx_pma_div_clkout" value="0" />
  <parameter name="hssi_10g_tx_pcs_bonding_dft_en" value="dft_dis" />
  <parameter name="cdr_pll_powermode_dc_txpll" value="powerdown_txpll" />
  <parameter name="l_channels" value="1" />
  <parameter
     name="pma_adapt_adp_pat_dlev_sign_value"
     value="radp_pat_dlev_sign_value_1" />
  <parameter
     name="hssi_pldadapt_tx_fsr_pld_txelecidle_rst_val"
     value="reset_to_zero_txelec" />
  <parameter name="hssi_pldadapt_rx_hdpldadapt_csr_clk_hz" value="0" />
  <parameter name="hssi_pldadapt_rx_hdpldadapt_pld_avmm2_clk_rowclk_hz" value="0" />
  <parameter name="hssi_pldadapt_tx_comp_cnt" value="0" />
  <parameter name="cdr_pll_pcie_gen" value="non_pcie" />
  <parameter
     name="hssi_pldadapt_tx_fifo_double_write"
     value="fifo_double_write_en" />
  <parameter name="rcfg_profile_select" value="0" />
  <parameter name="hssi_common_pcs_pma_interface_bypass_ppm_lock" value="false" />
  <parameter name="hssi_10g_tx_pcs_ctrl_bit_reverse" value="ctrl_bit_reverse_en" />
  <parameter name="hssi_8g_rx_pcs_gen3_clk_en" value="disable_clk" />
  <parameter name="pma_cgb_initial_settings" value="true" />
  <parameter name="pma_rx_buf_eq_isel" value="eq_isel_1" />
  <parameter
     name="hssi_common_pcs_pma_interface_cp_cons_sel"
     value="cp_cons_master" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_analog_mode" value="user_custom" />
  <parameter name="pma_tx_buf_low_power_en" value="disable" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_hrdrstctl_en"
     value="disable" />
  <parameter
     name="hssi_8g_rx_pcs_clock_gate_dw_rm_wr"
     value="en_dw_rm_wrclk_gating" />
  <parameter name="hssi_tx_pcs_pma_interface_tx_pma_data_sel" value="ten_g_pcs" />
  <parameter name="hssi_adapt_rx_phcomp_rd_del" value="phcomp_rd_del3" />
  <parameter name="cdr_pll_gpon_lck2ref_control" value="gpon_lck2ref_off" />
  <parameter
     name="pma_tx_buf_duty_cycle_correction_bandwidth_dn"
     value="dcd_bw_dn_2" />
  <parameter name="pma_tx_buf_rx_det" value="mode_0" />
  <parameter name="dbg_capability_reg_enable" value="0" />
  <parameter name="tx_clkout2_sel" value="pcs_clkout" />
  <parameter
     name="hssi_pldadapt_rx_rx_pld_pma_pcie_switch_polling_bypass"
     value="disable" />
  <parameter name="enh_pcs_pma_width" value="32" />
  <parameter name="reduced_reset_sim_time" value="0" />
  <parameter name="hssi_pldadapt_rx_fsr_pld_ltr_rst_val" value="reset_to_zero_ltr" />
  <parameter name="hssi_10g_tx_pcs_txfifo_full" value="full_default" />
  <parameter name="hssi_avmm1_if_hssiadapt_sr_sr_hip_en" value="disable" />
  <parameter name="std_rx_word_aligner_rknumber" value="3" />
  <parameter name="pma_adapt_adp_ac_ctle_en" value="radp_ac_ctle_en_disable" />
  <parameter name="pma_rx_deser_deser_aibck_en" value="enable" />
  <parameter name="hssi_adapt_tx_dyn_clk_sw_en" value="disable" />
  <parameter name="l_enable_pma_bonding" value="0" />
  <parameter name="hssi_8g_rx_pcs_pma_dw" value="ten_bit" />
  <parameter name="hssi_adapt_rx_rx_pma_rstn_en" value="disable" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size"
     value="uhsif_dzt_skipsz_4" />
  <parameter name="cdr_pll_pfd_l_counter" value="2" />
  <parameter
     name="delay_measurement_clkout_sel"
     value="clock_delay_measurement_clkout" />
  <parameter
     name="pma_adapt_adp_dc_ctle_onetime_threshold"
     value="radp_dc_ctle_onetime_threshold_256" />
  <parameter
     name="hssi_pldadapt_tx_fsr_mask_tx_pll_rst_val"
     value="reset_to_zero_maskpll" />
  <parameter name="pma_adapt_adp_adapt_start" value="radp_adapt_start_0" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_transparent_pcs_rx"
     value="disable" />
  <parameter name="pma_rx_deser_force_clkdiv_for_testing" value="normal_clkdiv" />
  <parameter name="hssi_8g_rx_pcs_err_flags_sel" value="err_flags_wa" />
  <parameter name="pma_adapt_adp_po_en" value="radp_po_en_disable" />
  <parameter
     name="hssi_common_pcs_pma_interface_pipe_if_g3pcs"
     value="pipe_if_8gpcs" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_st_en"
     value="aib_tx_dcc_st_en_setting1" />
  <parameter name="enable_ports_rx_prbs" value="0" />
  <parameter name="cdr_pll_f_max_pfd" value="350000000" />
  <parameter name="hssi_pldadapt_rx_ctrl_plane_bonding" value="individual" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_if_sup_mode"
     value="user_mode" />
  <parameter name="device_die_types" value="HSSI_CRETE2E,MAIN_ND5" />
  <parameter name="pma_tx_buf_duty_cycle_correction_reset_n" value="reset" />
  <parameter name="cdr_pll_speed_grade" value="e2" />
  <parameter name="enable_port_tx_fifo_latency_adj_ena" value="0" />
  <parameter name="l_tx_pma_optimal_settings" value="true" />
  <parameter name="hssi_adapt_tx_hrdrst_dcd_cal_done_bypass" value="disable" />
  <parameter name="pma_rx_buf_rx_refclk_divider" value="bypass_divider" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_speed_grade" value="e2" />
  <parameter name="enh_tx_frmgen_burst_enable" value="0" />
  <parameter name="hssi_krfec_rx_pcs_clr_ctrl" value="both_enabled" />
  <parameter name="hssi_tx_pcs_pma_interface_bypass_pma_txelecidle" value="true" />
  <parameter name="pma_rx_odi_step_ctrl_sel" value="dprio_mode" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_prot_mode_tx"
     value="teng_krfec_mode_tx" />
  <parameter name="pma_adapt_power_mode" value="powsav_disable" />
  <parameter name="hssi_adapt_tx_txfifo_pempty" value="2" />
  <parameter name="hssi_8g_tx_pcs_clock_gate_bs_enc" value="en_bs_enc_clk_gating" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel"
     value="uhsif_index_cram" />
  <parameter name="hssi_10g_rx_pcs_frmsync_flag_type" value="location_only" />
  <parameter name="pma_tx_ser_power_rail_er" value="1030" />
  <parameter name="pma_txpath_chnsequencer_txpath_chnseq_enable" value="disable" />
  <parameter
     name="hssi_adapt_tx_hd_hssiadapt_aib_hssi_tx_transfer_clk_hz"
     value="644531250" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_cont_cal_iocsr_unused"
     value="aib_rx_dcc_cal_single_iocsr_unused" />
  <parameter name="pma_rx_buf_term_sync_bypass" value="bypass_termsync" />
  <parameter name="pma_adapt_powermode_ac_deser_adapt" value="adapt_deser_ac_off" />
  <parameter name="hssi_10g_rx_pcs_rx_sm_bypass" value="rx_sm_bypass_dis" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_tx_pll_clk_hz" value="5156250000" />
  <parameter name="hssi_rx_pcs_pma_interface_block_sel" value="ten_g_pcs" />
  <parameter name="enable_port_rx_fifo_pfull" value="0" />
  <parameter name="hssi_adapt_rx_comp_cnt" value="0" />
  <parameter name="hssi_common_pcs_pma_interface_data_mask_count_multi" value="0" />
  <parameter name="hssi_pldadapt_tx_reconfig_settings" value="{}" />
  <parameter name="rx_fifo_align_del" value="0" />
  <parameter name="tx_coreclkin_clock_network" value="dedicated" />
  <parameter name="enable_port_tx_fifo_pfull" value="0" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_link" value="sr" />
  <parameter
     name="hssi_aibnd_tx_aib_red_dirclkp_shiften"
     value="aib_red_dirclkp_shift_disable" />
  <parameter name="hssi_rx_pcs_pma_interface_sup_mode" value="user_mode" />
  <parameter name="hssi_pldadapt_tx_pld_clk1_delay_sel" value="delay_path15" />
  <parameter name="pma_rx_dfe_tap3_sgn" value="tap3_sign_0" />
  <parameter name="cdr_pll_pma_width" value="32" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_gt_enabled" value="disable" />
  <parameter name="pma_rx_buf_powermode_dc_ctle" value="ctle_pwr_dc1" />
  <parameter name="hssi_aibnd_rx_silicon_rev" value="14nm5bcr2eb" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_g3pcs_prot_mode"
     value="disabled_prot_mode" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_sup_mode"
     value="user_mode" />
  <parameter name="hssi_aibnd_tx_silicon_rev" value="14nm5bcr2eb" />
  <parameter
     name="hssi_adapt_tx_fsr_hip_fsr_in_bit2_rst_val"
     value="reset_to_one_hfsrin2" />
  <parameter name="l_rcfg_addr_bits" value="11" />
  <parameter name="hssi_pldadapt_tx_pipe_mode" value="disable_pipe" />
  <parameter name="hssi_8g_rx_pcs_bonding_dft_val" value="dft_0" />
  <parameter name="hssi_gen3_rx_pcs_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="pma_adapt_adp_vga_accum_depth" value="9" />
  <parameter name="can_gen_exdesign_pcs_direct" value="1" />
  <parameter name="enable_multi_profile" value="1" />
  <parameter name="xcvr_speedgrade" value="e2" />
  <parameter name="hssi_10g_rx_pcs_blksync_bitslip_wait_type" value="bitslip_cnt" />
  <parameter
     name="hssi_common_pcs_pma_interface_ppm_post_eidle_delay"
     value="cnt_200_cycles" />
  <parameter name="hssi_pldadapt_rx_hrdrst_user_ctl_en" value="disable" />
  <parameter name="tile_type_suffix" value="" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_initial_settings" value="true" />
  <parameter name="hssi_pldadapt_rx_stretch_num_stages" value="four_stage" />
  <parameter name="pma_tx_buf_cpen_ctrl" value="cp_l1" />
  <parameter name="pma_tx_buf_powermode_dc_pre_tap" value="powerdown_tx_pre_tap" />
  <parameter
     name="hssi_pldadapt_rx_fifo_rd_clk_sel"
     value="fifo_rd_clk_pld_rx_clk1" />
  <parameter name="pma_rx_dfe_powermode_ac_dfe" value="ac_cdr_mode" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_jtag_lp" value="lp_off" />
  <parameter name="hssi_adapt_tx_hd_hssiadapt_pma_aib_tx_clk_hz" value="0" />
  <parameter name="cdr_pll_cgb_div" value="1" />
  <parameter name="pma_rx_dfe_oc_sa_vrefo_sgn" value="oc_sa_vrefo_sgn_0" />
  <parameter name="hssi_pldadapt_tx_powermode_dc" value="powerdown" />
  <parameter name="hssi_10g_tx_pcs_dispgen_err" value="dispgen_err_dis" />
  <parameter name="pma_rx_deser_powermode_ac_deser" value="deser_ac_32b_nobs" />
  <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
  <parameter name="hssi_aibcr_rx_aib_rx_dcc_dft_sel" value="aib_rx_dcc_dft_mode0" />
  <parameter name="hssi_rx_pcs_pma_interface_prbs_clken" value="prbs_clk_dis" />
  <parameter
     name="hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en"
     value="delay1_clk_disable" />
  <parameter name="l_enable_rx_std" value="0" />
  <parameter name="hssi_aibnd_tx_aib_outpdrv_r34" value="aib_pdrv34_setting1" />
  <parameter name="hssi_tx_pcs_pma_interface_prbs_gen_pat" value="prbs_gen_dis" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter name="pma_rx_buf_power_rail_er" value="0" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_uc_pcie_sw" value="uc_pcie_gen1" />
  <parameter name="hssi_pldadapt_tx_gb_tx_idwidth" value="idwidth_66" />
  <parameter name="enable_ports_pipe_hclk" value="0" />
  <parameter
     name="hssi_common_pcs_pma_interface_pcie_hip_mode"
     value="hip_disable" />
  <parameter name="cdr_pll_fref_mux_select" value="fref_mux_cdr_refclk" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock"
     value="uhsif_lkd_segsz_b4lock_16" />
  <parameter name="l_num_rx_digitalreset" value="1" />
  <parameter
     name="hssi_aibnd_rx_aib_ber_margining_ctrl"
     value="aib_ber_margining_setting0" />
  <parameter name="hssi_8g_rx_pcs_polinv_8b10b_dec" value="dis_polinv_8b10b_dec" />
  <parameter name="hssi_common_pcs_pma_interface_wait_send_syncp_fbkp" value="0" />
  <parameter name="pma_rx_buf_refclk_en" value="disable" />
  <parameter
     name="hssi_adapt_tx_datapath_mapping_mode"
     value="map_10g_2x2x_2x1x_fifo" />
  <parameter name="hssi_adapt_tx_tx_datapath_tb_sel" value="cp_bond" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_datarate_bps" value="10312500000" />
  <parameter
     name="hssi_pipe_gen3_ind_error_reporting"
     value="dis_ind_error_reporting" />
  <parameter
     name="hssi_tx_pcs_pma_interface_prot_mode_tx"
     value="teng_krfec_mode_tx" />
  <parameter name="hssi_tx_pcs_pma_interface_pmagate_en" value="pmagate_dis" />
  <parameter name="hssi_pldadapt_rx_rx_usertest_sel" value="enable" />
  <parameter name="pma_adapt_adp_pcs_option" value="radp_pcs_option_0" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_st_hps_ctrl_en"
     value="aib_tx_dcc_hps_ctrl_en_setting0" />
  <parameter name="pma_tx_buf_jtag_lp" value="lp_off" />
  <parameter
     name="pma_tx_ser_powermode_ac_ser"
     value="ac_clk_divtx_user_0_jitcomp1p0" />
  <parameter name="hssi_pldadapt_rx_hrdrst_rx_osc_clk_scg_en" value="disable" />
  <parameter name="hssi_adapt_tx_hd_hssiadapt_pld_pma_hclk_hz" value="0" />
  <parameter name="enh_rx_64b66b_enable" value="1" />
  <parameter name="l_std_rx_word_count" value="1" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_uhsif_tx_clk_hz"
     value="0" />
  <parameter name="cdr_pll_sup_mode" value="user_mode" />
  <parameter name="hssi_10g_rx_pcs_dis_signal_ok" value="dis_signal_ok_dis" />
  <parameter name="hssi_common_pcs_pma_interface_wait_clk_on_off_timer" value="0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx"
     value="disable" />
  <parameter name="cdr_pll_clk270_dfe_trise_adj" value="clk270_dfe_tr0" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_rst_prgmnvrt"
     value="aib_rx_dcc_st_rst_prgmnvrt_setting0" />
  <parameter name="pma_tx_buf_data_dcc_setting" value="ddcc_disable" />
  <parameter name="l_std_tx_word_count" value="1" />
  <parameter name="hssi_common_pcs_pma_interface_testout_sel" value="ppm_det_test" />
  <parameter name="hssi_10g_rx_pcs_rx_fifo_write_ctrl" value="blklock_stops" />
  <parameter name="hssi_pldadapt_tx_low_latency_en" value="disable" />
  <parameter name="protocol_mode" value="teng_1588_mode" />
  <parameter name="pma_rx_dfe_odi_bti_en" value="odi_bti_disable" />
  <parameter name="hssi_adapt_tx_hrdrst_rx_osc_clk_scg_en" value="disable" />
  <parameter name="rx_clkout_sel" value="pcs_clkout" />
  <parameter name="hssi_pldadapt_rx_indv" value="indv_en" />
  <parameter name="pma_tx_buf_vod_output_swing_ctrl" value="31" />
  <parameter name="design_environment" value="QSYS" />
  <parameter name="hssi_pldadapt_rx_hdpldadapt_pld_sclk1_rowclk_hz" value="0" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pcs_ac_pwr_rules_en"
     value="disable" />
  <parameter name="l_tx_core_aib_indv" value="indv_en" />
  <parameter name="tx_clkout_sel" value="pcs_clkout" />
  <parameter name="hssi_avmm1_if_pldadapt_hip_mode" value="disable_hip" />
  <parameter name="enable_port_rx_std_bitslip" value="0" />
  <parameter
     name="pma_cgb_select_done_master_or_slave"
     value="choose_slave_pcie_sw_done" />
  <parameter name="pma_rx_buf_qpi_afe_en" value="ctle_mode_en" />
  <parameter name="pma_cgb_vreg_sel_ref" value="sel_vccer_4ref" />
  <parameter name="hssi_krfec_rx_pcs_signal_ok_en" value="sig_ok_en" />
  <parameter
     name="hssi_aibcr_tx_aib_red_dirclkp_shiften"
     value="aib_red_dirclkp_shift_disable" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_io_std" value="io_off" />
  <parameter name="pma_rx_buf_rx_aoc_doc" value="lower_dac_l0" />
  <parameter name="hssi_adapt_tx_txfifo_mode" value="txphase_comp" />
  <parameter name="hssi_tx_pld_pcs_interface_hd_pcs8g_hip_mode" value="disable" />
  <parameter name="hssi_adapt_tx_aib_clk_sel" value="aib_clk_pma_aib_tx_clk" />
  <parameter name="hssi_tx_pld_pcs_interface_hd_pcs10g_sup_mode" value="user_mode" />
  <parameter name="hssi_krfec_tx_pcs_pipeln_encoder" value="enable" />
  <parameter name="hssi_8g_rx_pcs_rate_match_full_thres" value="dis_rm_full_thres" />
  <parameter name="pma_cgb_bti_protected" value="false" />
  <parameter name="hssi_10g_tx_pcs_tx_scrm_err" value="scrm_err_dis" />
  <parameter name="pma_rx_dfe_pdb_tap_10t15" value="tap10t15_dfe_powerdown" />
  <parameter
     name="hssi_adapt_rx_internal_clk1_sel0"
     value="pma_clks_or_txfifowr_post_ct_or_txfiford_pre_or_post_ct_mux_clk1_mux0" />
  <parameter
     name="hssi_adapt_rx_internal_clk1_sel1"
     value="pma_clks_or_txfiford_pre_or_post_ct_mux_clk1_mux1" />
  <parameter
     name="hssi_adapt_rx_internal_clk1_sel2"
     value="pma_clks_or_txfiford_pre_ct_mux_clk1_mux2" />
  <parameter name="hssi_adapt_rx_internal_clk1_sel3" value="pma_clks_clk1_mux3" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_clkdiv"
     value="aib_dllstr_align_clkdiv_setting1" />
  <parameter
     name="pma_adapt_adp_vga_onetime_threshold"
     value="radp_vga_onetime_threshold_512" />
  <parameter name="pma_rx_buf_pm_cr2_tx_rx_uc_rx_cal" value="uc_rx_cal_on" />
  <parameter name="hssi_10g_tx_pcs_txfifo_mode" value="register_mode" />
  <parameter name="pma_cgb_x1_div_m_sel" value="divbypass" />
  <parameter name="tx_pma_pre_emp_sign_1st_post_tap" value="negative" />
  <parameter name="hssi_8g_rx_pcs_reconfig_settings" value="{}" />
  <parameter name="rcfg_sdc_derived_param_vals4" value="" />
  <parameter name="rcfg_sdc_derived_param_vals5" value="" />
  <parameter name="rcfg_sdc_derived_param_vals6" value="" />
  <parameter name="hssi_adapt_tx_word_align_enable" value="enable" />
  <parameter name="rcfg_sdc_derived_param_vals7" value="" />
  <parameter
     name="rcfg_sdc_derived_param_vals0"
     value="1,0,0,0,0,0,515625000,515625000,0,x2,x2,1,1,0,0,0,indv_en,indv_en,indv_en,indv_en,8,8,Enhanced" />
  <parameter name="pma_rx_deser_tdr_mode" value="select_bbpd_data" />
  <parameter name="rcfg_sdc_derived_param_vals1" value="" />
  <parameter name="hssi_pldadapt_tx_sh_err" value="sh_err_dis" />
  <parameter name="hssi_tx_pld_pcs_interface_hd_krfec_sup_mode" value="user_mode" />
  <parameter name="rcfg_sdc_derived_param_vals2" value="" />
  <parameter name="hssi_pipe_gen1_2_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_pldadapt_rx_rx_fifo_power_mode" value="full_width_ps_dw" />
  <parameter name="rcfg_sdc_derived_param_vals3" value="" />
  <parameter name="pma_rx_deser_prot_mode" value="basic_rx" />
  <parameter name="pma_cgb_ser_mode" value="thirty_two_bit" />
  <parameter name="l_enable_tx_pcs_dir" value="0" />
  <parameter
     name="hssi_common_pld_pcs_interface_dft_clk_out_en"
     value="dft_clk_out_disable" />
  <parameter name="hssi_tx_pcs_pma_interface_pma_if_dft_en" value="dft_dis" />
  <parameter name="hssi_common_pcs_pma_interface_asn_enable" value="dis_asn" />
  <parameter name="hssi_10g_rx_pcs_reconfig_settings" value="{}" />
  <parameter name="hssi_10g_tx_pcs_wr_clk_sel" value="wr_tx_pma_clk" />
  <parameter name="hssi_8g_rx_pcs_wa_rvnumber_data" value="0" />
  <parameter name="hssi_adapt_tx_loopback_mode" value="loopback_disable" />
  <parameter name="pma_rx_dfe_tap1_sgn" value="tap1_sign_0" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_dw_rx"
     value="pma_32b_rx" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs8g_pma_dw_rx"
     value="pma_10b_rx" />
  <parameter name="cdr_refclk_cnt" value="1" />
  <parameter name="pma_rx_dfe_tap14_coeff" value="0" />
  <parameter name="tx_pma_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
  <parameter name="pma_rx_buf_vga_mode" value="vga_off" />
  <parameter name="pma_cgb_silicon_rev" value="14nm5bcr2eb" />
  <parameter
     name="hssi_rx_pld_pcs_interface_pcs_rx_output_sel"
     value="teng_output" />
  <parameter name="hssi_krfec_tx_pcs_enc_frame_query" value="enc_query_dis" />
  <parameter name="pma_rx_dfe_optimal" value="true" />
  <parameter name="hssi_aibnd_tx_aib_ddrctrl_gr0" value="aib_ddr0_setting1" />
  <parameter name="std_rx_rmfifo_mode" value="disabled" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_prot_mode_rx"
     value="teng_1588_baser_rx" />
  <parameter name="enable_debug_options" value="0" />
  <parameter name="hssi_adapt_rx_txeq_mode" value="eq_disable" />
  <parameter name="pma_cgb_tx_ucontrol_reset" value="disable" />
  <parameter name="hssi_8g_tx_pcs_byte_serializer" value="dis_bs" />
  <parameter
     name="hssi_adapt_tx_fsr_hip_fsr_out_bit1_rst_val"
     value="reset_to_one_hfsrout1" />
  <parameter name="hssi_adapt_rx_rx_txeq_time" value="64" />
  <parameter name="pma_rx_buf_powermode_ac_vga" value="vga_pwr_ac_half" />
  <parameter
     name="hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel"
     value="pcs_tx_clk" />
  <parameter name="set_cdr_refclk_receiver_detect_src" value="iqclk" />
  <parameter name="pma_adapt_adp_dfe_hold_sel" value="radp_dfe_hold_sel_no" />
  <parameter
     name="hssi_pldadapt_rx_hdpldadapt_aib_fabric_rx_transfer_clk_hz"
     value="644531250" />
  <parameter name="hssi_aibnd_rx_powerdown_mode" value="true" />
  <parameter name="pma_rx_deser_powermode_dc_deser" value="deser_dc_32b_nobs" />
  <parameter name="hssi_pldadapt_rx_pld_clk1_delay_en" value="enable" />
  <parameter name="hssi_pldadapt_rx_pma_hclk_scg_en" value="enable" />
  <parameter name="hssi_10g_tx_pcs_crcgen_err" value="crcgen_err_dis" />
  <parameter name="hssi_krfec_rx_pcs_prot_mode" value="disable_mode" />
  <parameter
     name="hssi_aibnd_tx_aib_red_tx_shiften"
     value="aib_red_tx_shift_disable" />
  <parameter name="hssi_rx_pcs_pma_interface_prbs_ver" value="prbs_off" />
  <parameter name="pll_select" value="0" />
  <parameter name="enable_tx_x2_coreclkin_port" value="0" />
  <parameter name="hssi_avmm1_if_pldadapt_osc_clk_scg_en" value="disable" />
  <parameter name="hssi_pldadapt_tx_hrdrst_rx_osc_clk_scg_en" value="disable" />
  <parameter name="hssi_gen3_rx_pcs_mode" value="disable_pcs" />
  <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
  <parameter
     name="hssi_8g_tx_pcs_data_selection_8b10b_encoder_input"
     value="normal_data_path" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs10g_ctrl_plane_bonding_rx"
     value="individual_rx" />
  <parameter name="hssi_10g_tx_pcs_empty_flag_type" value="empty_rd_side" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_manual_up"
     value="aib_rx_dcc_manual_up0" />
  <parameter
     name="hssi_pldadapt_tx_hdpldadapt_aib_fabric_tx_sr_clk_in_hz"
     value="0" />
  <parameter name="hssi_pldadapt_tx_frmgen_bypass" value="frmgen_bypass_en" />
  <parameter name="set_rcfg_emb_strm_enable" value="0" />
  <parameter name="hssi_aibnd_tx_sup_mode" value="user_mode" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_dft_ch_muxsel"
     value="aib_dllstr_align_dft_ch_muxsel_setting0" />
  <parameter name="cdr_pll_lf_resistor_pd" value="lf_pd_setting3" />
  <parameter name="pma_rx_buf_ctle_hires_bypass" value="ctle_hires_en" />
  <parameter name="hssi_adapt_tx_hd_hssiadapt_hip_aib_clk_2x_hz" value="0" />
  <parameter name="pma_adapt_adp_vga_dlev_target" value="15" />
  <parameter name="hssi_adapt_rx_fsr_pld_ltd_b_rst_val" value="reset_to_one_ltdb" />
  <parameter name="hssi_aibcr_rx_aib_rx_halfcode" value="aib_rx_halfcode_enable" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_dy_ctl_static"
     value="aib_tx_dcc_dy_ctl_static_setting1" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock"
     value="uhsif_lkd_segsz_aflock_512" />
  <parameter name="hssi_10g_tx_pcs_sh_err" value="sh_err_en" />
  <parameter name="hssi_pldadapt_rx_word_align" value="wa_en" />
  <parameter name="hssi_10g_tx_pcs_bonding_dft_val" value="dft_0" />
  <parameter name="hssi_adapt_rx_rx_pcspma_testbus_sel" value="enable" />
  <parameter name="tx_pma_clk_div" value="1" />
  <parameter name="hssi_adapt_tx_rxqpi_pullup_rst_val" value="reset_to_zero_rxqpi" />
  <parameter
     name="hssi_pldadapt_rx_aib_clk2_sel"
     value="aib_clk2_pld_pma_clkdiv_rx_user" />
  <parameter
     name="hssi_rx_pcs_pma_interface_master_clk_sel"
     value="master_rx_pma_clk" />
  <parameter name="pma_rx_dfe_oc_sa_cdr0e_sgn" value="oc_sa_cdr0e_sgn_0" />
  <parameter name="hssi_aibcr_rx_redundancy_en" value="disable" />
  <parameter name="hssi_8g_tx_pcs_bit_reversal" value="dis_bit_reversal" />
  <parameter name="pma_rx_buf_powermode_ac_vcm" value="vcm_pwr_ac3" />
  <parameter name="hssi_rx_pcs_pma_interface_prbs9_dwidth" value="prbs9_64b" />
  <parameter name="hssi_tx_pcs_pma_interface_uhsif_enable" value="uhsif_disable" />
  <parameter name="hssi_10g_rx_pcs_frmsync_pipeln" value="frmsync_pipeln_en" />
  <parameter name="ovrd_tx_dv_mode" value="0" />
  <parameter name="enh_tx_bitslip_enable" value="0" />
  <parameter name="dbg_ctrl_soft_logic_enable" value="0" />
  <parameter name="hssi_gen3_rx_pcs_block_sync_sm" value="disable_blk_sync_sm" />
  <parameter
     name="hssi_pldadapt_tx_tx_pld_pma_fpll_num_phase_shifts_polling_bypass"
     value="disable" />
  <parameter name="hssi_adapt_rx_asn_bypass_pma_pcie_sw_done" value="disable" />
  <parameter
     name="pma_adapt_adp_frame_out_sel"
     value="radp_frame_out_sel_select_a" />
  <parameter name="pma_rx_buf_bodybias_select" value="bodybias_sel1" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock"
     value="uhsif_filt_stepsz_b4lock_2" />
  <parameter name="early_spd_chng_t1" value="60" />
  <parameter name="early_spd_chng_t2" value="150" />
  <parameter name="set_enable_calibration" value="1" />
  <parameter name="core_speedgrade_no_temp" value="2" />
  <parameter name="early_spd_chng_t3" value="1000" />
  <parameter name="pma_rx_dfe_oc_sa_cdr0o" value="0" />
  <parameter name="pma_adapt_optimal" value="true" />
  <parameter name="pma_rx_deser_odi_adapt_bti_en" value="deser_bti_disable" />
  <parameter name="pma_rx_dfe_sel_probe_tstmx" value="probe_tstmx_none" />
  <parameter
     name="hssi_8g_rx_pcs_ctrl_plane_bonding_distribution"
     value="not_master_chnl_distr" />
  <parameter name="hssi_pldadapt_rx_asn_bypass_pma_pcie_sw_done" value="disable" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs10g_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter name="pma_rx_buf_pm_cr2_tx_rx_cvp_mode" value="cvp_off" />
  <parameter name="enable_hard_reset" value="0" />
  <parameter name="hssi_8g_rx_pcs_eidle_entry_sd" value="dis_eidle_sd" />
  <parameter name="pma_rx_buf_ctle_oc_coeff" value="0" />
  <parameter name="hssi_common_pcs_pma_interface_pma_if_dft_val" value="dft_0" />
  <parameter name="pma_rx_dfe_oc_sa_cdr0e" value="0" />
  <parameter name="l_tx_hssi_aib_indv" value="indv_en" />
  <parameter name="hssi_aibnd_tx_aib_outpdrv_r56" value="aib_pdrv56_setting1" />
  <parameter name="enable_transparent_pcs" value="0" />
  <parameter name="hssi_pipe_gen1_2_rx_pipe_enable" value="dis_pipe_rx" />
  <parameter name="enable_std" value="0" />
  <parameter
     name="hssi_common_pcs_pma_interface_prot_mode"
     value="other_protocols" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_st_new_dll2"
     value="aib_dllstr_align_new_dll2_setting0" />
  <parameter name="hssi_avmm1_if_pldadapt_uc_blocking_enable" value="enable" />
  <parameter name="pma_adapt_adp_tx_adp_en" value="radp_tx_adp_en_0" />
  <parameter name="cdr_pll_bandwidth_range_high" value="1" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pcs_rx_ac_pwr_uw_per_mhz"
     value="0" />
  <parameter name="hssi_10g_tx_pcs_bitslip_en" value="bitslip_dis" />
  <parameter
     name="hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx"
     value="other_prot_mode" />
  <parameter name="rx_ctle_eq_gain" value="0" />
  <parameter name="hssi_10g_rx_pcs_rx_sh_location" value="lsb" />
  <parameter name="hssi_common_pcs_pma_interface_cp_dwn_mstr" value="true" />
  <parameter name="hssi_8g_rx_pcs_wa_rgnumber_data" value="3" />
  <parameter name="pma_rx_deser_deser_aibck_x1" value="normal" />
  <parameter name="hssi_8g_rx_pcs_rx_clk_free_running" value="en_rx_clk_free_run" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_low_latency_en_rx"
     value="disable" />
  <parameter name="hssi_8g_rx_pcs_eidle_entry_eios" value="dis_eidle_eios" />
  <parameter
     name="hssi_adapt_tx_fifo_rd_clk_sel"
     value="fifo_rd_pld_pcs_tx_clk_out" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_en_iocsr_unused"
     value="aib_tx_dcc_disable_iocsr_unused" />
  <parameter name="pma_rx_dfe_tap2_coeff" value="0" />
  <parameter name="hssi_common_pld_pcs_interface_hrdrstctrl_en" value="hrst_dis" />
  <parameter name="hssi_10g_tx_pcs_comp_cnt" value="0" />
  <parameter name="pma_rx_deser_force_adaptation_outputs" value="normal_outputs" />
  <parameter name="cdr_pll_cdr_d2a_enb" value="bti_d2a_disable" />
  <parameter name="hssi_pldadapt_tx_hdpldadapt_pld_avmm1_clk_rowclk_hz" value="0" />
  <parameter name="hssi_adapt_tx_bonding_dft_en" value="dft_dis" />
  <parameter name="pma_adapt_adapt_mode" value="manual" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs8g_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter
     name="hssi_pipe_gen3_phystatus_rst_toggle_g12"
     value="dis_phystatus_rst_toggle" />
  <parameter name="hssi_adapt_rx_adapter_lpbk_mode" value="disable" />
  <parameter
     name="hssi_aibnd_tx_aib_red_dtx_shiften"
     value="aib_red_dtx_shift_disable" />
  <parameter name="hssi_8g_tx_pcs_pma_dw" value="ten_bit" />
  <parameter name="hssi_pipe_gen1_2_rpre_emph_b_val" value="0" />
  <parameter
     name="hssi_8g_rx_pcs_invalid_code_flag_only"
     value="dis_invalid_code_only" />
  <parameter name="pma_rx_dfe_sup_mode" value="user_mode" />
  <parameter
     name="hssi_pldadapt_tx_fsr_hip_fsr_out_bit1_rst_val"
     value="reset_to_one_hfsrout1" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_frequency_rules_en"
     value="enable" />
  <parameter name="cdr_refclk_select" value="0" />
  <parameter name="hssi_10g_rx_pcs_dec64b66b_clken" value="dec64b66b_clk_en" />
  <parameter name="hssi_aibnd_tx_aib_tx_dcc_dft_sel" value="aib_tx_dcc_dft_mode0" />
  <parameter name="hssi_pldadapt_tx_hdpldadapt_speed_grade" value="dash_2" />
  <parameter name="hssi_8g_tx_pcs_revloop_back_rm" value="dis_rev_loopback_rx_rm" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_st_core_up_prgmnvrt"
     value="aib_dllstr_align_st_core_up_prgmnvrt_setting0" />
  <parameter name="rx_pma_analog_mode" value="user_custom" />
  <parameter
     name="hssi_tx_pcs_pma_interface_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter name="l_tx_fifo_transfer_mode" value="x2" />
  <parameter name="hssi_10g_tx_pcs_fifo_reg_fast" value="fifo_reg_fast_dis" />
  <parameter name="l_enable_loopback_mode" value="0" />
  <parameter name="hssi_adapt_tx_ds_master" value="ds_master_en" />
  <parameter name="pma_rx_sd_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="pma_tx_sequencer_xrx_path_uc_cal_clk_bypass" value="cal_clk_0" />
  <parameter
     name="pma_cdr_refclk_inclk1_logical_to_physical_mapping"
     value="ref_iqclk0" />
  <parameter name="l_enable_tx_std" value="0" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_optimal" value="true" />
  <parameter name="hssi_aibcr_tx_aib_datasel_gr2" value="aib_datasel2_setting0" />
  <parameter name="hssi_aibcr_tx_aib_datasel_gr0" value="aib_datasel0_setting0" />
  <parameter name="enable_port_rx_data_valid" value="1" />
  <parameter name="hssi_aibcr_tx_aib_datasel_gr1" value="aib_datasel1_setting1" />
  <parameter name="hssi_rx_pcs_pma_interface_pma_dw_rx" value="pma_32b_rx" />
  <parameter name="hssi_tx_pld_pcs_interface_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="rcfg_shared" value="0" />
  <parameter name="hssi_adapt_rx_txeq_rst_sel" value="txeq_pcs_rx_pld_rst_n" />
  <parameter name="hip_mode" value="disable_hip" />
  <parameter name="hssi_pldadapt_rx_fifo_stop_rd" value="rd_empty" />
  <parameter name="pma_tx_buf_powermode_ac_post_tap" value="tx_post_tap_ac_off" />
  <parameter name="hssi_pldadapt_rx_hdpldadapt_pld_sclk2_rowclk_hz" value="0" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_st_dly_pst"
     value="aib_rx_dcc_st_dly_pst_setting0" />
  <parameter name="pma_rx_dfe_tap11_coeff" value="0" />
  <parameter name="hssi_8g_rx_pcs_clock_gate_dw_wa" value="en_dw_wa_clk_gating" />
  <parameter name="hssi_8g_rx_pcs_rate_match_del_thres" value="dis_rm_del_thres" />
  <parameter name="hssi_adapt_tx_chnl_bonding" value="disable" />
  <parameter name="hssi_gen3_tx_pcs_tx_gbox_byp" value="bypass_gbox" />
  <parameter name="enable_port_tx_fifo_full" value="0" />
  <parameter name="hssi_10g_rx_pcs_rxfifo_full" value="full_default" />
  <parameter name="hssi_10g_tx_pcs_scrm_mode" value="async" />
  <parameter name="enable_simple_interface" value="0" />
  <parameter
     name="hssi_8g_tx_pcs_tx_compliance_controlled_disparity"
     value="dis_txcompliance" />
  <parameter name="hssi_10g_rx_pcs_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_8g_tx_pcs_phfifo_write_clk_sel" value="tx_clk" />
  <parameter name="hssi_8g_tx_pcs_eightb_tenb_encoder" value="en_8b10b_ibm" />
  <parameter name="hssi_pldadapt_tx_pld_clk2_sel" value="pld_clk2_dcm" />
  <parameter name="hssi_aibnd_rx_redundancy_en" value="disable" />
  <parameter name="enh_advanced_user_mode" value="0" />
  <parameter name="pma_adapt_adp_dlev_accum_depth" value="6" />
  <parameter name="l_tx_transfer_clk_hz" value="644531250" />
  <parameter name="cdr_pll_chgpmp_testmode" value="cp_test_disable" />
  <parameter name="pma_tx_buf_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
  <parameter
     name="pma_adapt_adp_dlev_initial_value"
     value="radp_dlev_initial_value_38" />
  <parameter name="pcs_bonding_master" value="0" />
  <parameter
     name="hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok"
     value="force_sig_ok" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs8g_pma_dw_tx"
     value="pma_10b_tx" />
  <parameter name="disable_reset_sequencer" value="0" />
  <parameter name="enh_tx_randomdispbit_enable" value="0" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_link" value="sr" />
  <parameter name="pma_rx_dfe_tap7_sgn" value="tap7_sign_0" />
  <parameter name="hssi_pldadapt_rx_rx_true_b2b" value="b2b" />
  <parameter name="hssi_10g_tx_pcs_scrm_clken" value="scrm_clk_en" />
  <parameter name="hssi_aibnd_rx_aib_outctrl_gr2" value="aib_outen2_setting1" />
  <parameter name="fifo_depth_message" value="" />
  <parameter
     name="hssi_adapt_rx_rx_pld_pma_reser_in_polling_bypass"
     value="disable" />
  <parameter name="hssi_10g_rx_pcs_gb_rx_odwidth" value="odwidth_66" />
  <parameter
     name="pma_adapt_adp_dfe_fxtap_bypass"
     value="radp_dfe_fxtap_bypass_bypass" />
  <parameter name="pma_tx_buf_duty_cycle_setting_aux" value="dcc2_t32" />
  <parameter name="hssi_pldadapt_rx_hdpldadapt_pld_avmm1_clk_rowclk_hz" value="0" />
  <parameter name="hssi_8g_rx_pcs_wa_kchar" value="dis_kchar" />
  <parameter name="hssi_8g_rx_pcs_wa_pd" value="wa_pd_10" />
  <parameter name="hssi_10g_rx_pcs_gbexp_clken" value="gbexp_clk_en" />
  <parameter name="hssi_10g_tx_pcs_sop_mark" value="sop_mark_dis" />
  <parameter name="hssi_pldadapt_tx_loopback_mode" value="disable" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_st_core_up_prgmnvrt"
     value="aib_tx_dcc_st_core_up_prgmnvrt_setting0" />
  <parameter name="message_level" value="error" />
  <parameter name="hssi_10g_tx_pcs_stretch_num_stages" value="one_stage" />
  <parameter name="cdr_pll_atb_select_control" value="atb_off" />
  <parameter name="hssi_aibnd_rx_aib_outctrl_gr0" value="aib_outen0_setting1" />
  <parameter name="hssi_aibnd_rx_aib_outctrl_gr1" value="aib_outen1_setting1" />
  <parameter name="hssi_adapt_rx_rxfifo_full" value="full_dw" />
  <parameter name="hssi_common_pcs_pma_interface_data_mask_count" value="0" />
  <parameter name="parallel_loopback_mode" value="disable" />
  <parameter
     name="pma_adapt_adp_pat_trans_only_en"
     value="radp_pat_trans_only_en_enable" />
  <parameter name="enable_port_rx_pcs_fifo_empty" value="0" />
  <parameter name="pma_rx_dfe_datarate_bps" value="10312500000" />
  <parameter name="pma_tx_buf_pcie_gen" value="non_pcie" />
  <parameter name="hssi_gen3_rx_pcs_reverse_lpbk" value="rev_lpbk_dis" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable"
     value="uhsif_dzt_disable" />
  <parameter
     name="hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock"
     value="knum_sh_cnt_postlock_10g" />
  <parameter name="hssi_aibcr_tx_aib_outndrv_r12" value="aib_ndrv12_setting1" />
  <parameter name="pma_rx_dfe_tap14_sgn" value="tap14_sign_0" />
  <parameter name="pma_adapt_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_8g_rx_pcs_fixed_pat_det" value="dis_fixed_patdet" />
  <parameter name="hssi_adapt_rx_hd_hssiadapt_speed_grade" value="dash_2" />
  <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
  <parameter name="rcfg_enable" value="1" />
  <parameter name="hssi_pldadapt_tx_tx_fifo_read_latency_adjust" value="disable" />
  <parameter name="hssi_avmm1_if_pldadapt_avmm_clk_scg_en" value="disable" />
  <parameter name="cdr_pll_cdr_powerdown_mode" value="power_up" />
  <parameter name="hssi_pldadapt_rx_fifo_stop_wr" value="n_wr_full" />
  <parameter name="hssi_gen3_tx_pcs_reconfig_settings" value="{}" />
  <parameter name="hssi_10g_tx_pcs_pld_if_type" value="reg" />
  <parameter name="pma_rx_buf_const_gm_en" value="cgm_en_3" />
  <parameter name="pma_txpath_chnsequencer_silicon_rev" value="14nm5bcr2ea" />
  <parameter
     name="hssi_10g_tx_pcs_distup_bypass_pipeln"
     value="distup_bypass_pipeln_dis" />
  <parameter name="hssi_aibnd_tx_aib_tx_dcc_en" value="aib_tx_dcc_enable" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_st_core_dn_prgmnvrt"
     value="aib_rx_dcc_st_core_dn_prgmnvrt_setting0" />
  <parameter name="hssi_adapt_rx_asn_wait_for_dll_reset_cnt" value="32" />
  <parameter name="hssi_aibcr_rx_powermode_ac" value="rxdatapath_high_speed_pwr" />
  <parameter
     name="hssi_pldadapt_tx_tx_pld_10g_tx_bitslip_polling_bypass"
     value="disable" />
  <parameter name="pma_adapt_adp_status_sel" value="radp_status_sel_0" />
  <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
  <parameter
     name="pma_rx_buf_pm_cr2_rx_path_jtag_hys"
     value="hys_increase_disable" />
  <parameter name="number_physical_bonding_clocks" value="1" />
  <parameter name="hssi_pldadapt_tx_stretch_num_stages" value="four_stage" />
  <parameter name="pma_cdr_refclk_refclk_select" value="ref_iqclk0" />
  <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
  <parameter name="cdr_pll_powermode_ac_rvcotop" value="rvcotop_ac_div2" />
  <parameter name="hssi_adapt_rx_hd_hssiadapt_pma_aib_rx_clk_hz" value="0" />
  <parameter name="cdr_pll_chgpmp_current_dn_pd" value="cp_current_pd_dn_setting3" />
  <parameter name="hssi_pldadapt_tx_txfifo_mode" value="txphase_comp" />
  <parameter
     name="hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion"
     value="tx_dyn_polinv_dis" />
  <parameter name="rx_fifo_pfull" value="10" />
  <parameter name="hssi_krfec_rx_pcs_err_mark_type" value="err_mark_10g" />
  <parameter name="enable_de_hardware_debug" value="0" />
  <parameter
     name="pma_adapt_adp_dc_ctle_initial_value"
     value="radp_dc_ctle_initial_value_16" />
  <parameter name="pma_tx_ser_ser_preset_bti_en" value="ser_preset_bti_disable" />
  <parameter name="hssi_10g_rx_pcs_frmsync_enum_scrm" value="enum_scrm_default" />
  <parameter
     name="pma_tx_buf_powermode_ac_tx_vod_w_jitcomp"
     value="tx_vod_w_jitcomp_ac_l31" />
  <parameter name="hssi_pldadapt_rx_pld_clk1_inv_en" value="disable" />
  <parameter name="hssi_aibcr_tx_aib_outndrv_r34" value="aib_ndrv34_setting1" />
  <parameter
     name="pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch3_src"
     value="cdr_clkin_scratch3_src_refclk_iqclk" />
  <parameter
     name="hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl"
     value="delay2_path0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_sim_mode"
     value="disable" />
  <parameter name="hssi_adapt_rx_duplex_mode" value="enable" />
  <parameter name="hssi_pldadapt_tx_fifo_stop_rd" value="rd_empty" />
  <parameter name="hssi_avmm1_if_pcs_hip_cal_en" value="disable" />
  <parameter name="pma_tx_sequencer_xtx_path_xcgb_tx_ucontrol_en" value="disable" />
  <parameter
     name="hssi_avmm1_if_pldadapt_nfhssi_calibratio_feature_en"
     value="enable" />
  <parameter name="pma_rx_buf_ctle_ac_gain" value="0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter name="hssi_rx_pld_pcs_interface_pcs_rx_clk_sel" value="pcs_rx_clk" />
  <parameter name="enable_ports_adaptation" value="0" />
  <parameter name="hssi_adapt_tx_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_pldadapt_tx_powerdown_mode" value="powerup" />
  <parameter name="hssi_8g_rx_pcs_wa_sync_sm_ctrl" value="gige_sync_sm" />
  <parameter name="hssi_pldadapt_rx_fifo_rd_clk_scg_en" value="disable" />
  <parameter name="hssi_10g_tx_pcs_tx_sh_location" value="lsb" />
  <parameter name="hssi_10g_tx_pcs_test_mode" value="test_off" />
  <parameter
     name="hssi_adapt_rx_rxfifowr_post_ct_sel"
     value="rxfifowr_sclk_post_ct" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_sup_mode" value="user_mode" />
  <parameter name="hssi_10g_rx_pcs_bitslip_mode" value="bitslip_dis" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_if_prot_mode_rx"
     value="teng_reg_mode_rx" />
  <parameter name="hssi_avmm1_if_hssiadapt_sr_sr_reserved_out_en" value="enable" />
  <parameter name="enable_port_rx_fifo_del" value="0" />
  <parameter name="hssi_adapt_rx_chnl_bonding" value="disable" />
  <parameter name="pma_tx_ser_datarate_bps" value="0" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_test_clk_pll_en_n"
     value="aib_rx_dcc_test_clk_pll_en_n_disable" />
  <parameter name="hssi_8g_tx_pcs_dynamic_clk_switch" value="dis_dyn_clk_switch" />
  <parameter name="pma_rx_dfe_sel_oc_en" value="off_canc_disable" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs10g_advanced_user_mode_rx"
     value="disable" />
  <parameter name="hssi_aibcr_rx_powermode_dc" value="powerup" />
  <parameter
     name="hssi_adapt_rx_fsr_pld_rx_fifo_align_clr_rst_val"
     value="reset_to_zero_alignclr" />
  <parameter name="pma_rx_buf_powermode_ac_ctle" value="ctle_pwr_ac2" />
  <parameter name="hssi_pldadapt_tx_indv" value="indv_en" />
  <parameter name="enable_port_rx_std_byterev_ena" value="0" />
  <parameter name="hssi_avmm1_if_hssiadapt_avmm_clk_scg_en" value="disable" />
  <parameter name="pma_tx_buf_idle_ctrl" value="id_cpen_on" />
  <parameter name="hssi_rx_pcs_pma_interface_pma_if_dft_en" value="dft_dis" />
  <parameter name="hssi_krfec_rx_pcs_pipeln_trans_dec" value="disable" />
  <parameter name="hssi_avmm1_if_hssiadapt_write_resp_en" value="disable" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_dw_tx"
     value="pma_32b_tx" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_st_new_dll"
     value="aib_dllstr_align_new_dll_setting0" />
  <parameter name="pma_rx_buf_powermode_ac_aoc" value="aoc_pwr_ac_off" />
  <parameter
     name="hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk"
     value="en_sw_pc_wrclk_gating" />
  <parameter name="hssi_8g_tx_pcs_force_kchar" value="dis_force_kchar" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_manual_dn"
     value="aib_rx_dcc_manual_dn0" />
  <parameter name="pma_tx_ser_uc_vcc_setting" value="vcc_setting1" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_shared_fifo_width_rx"
     value="single_rx" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs8g_ctrl_plane_bonding_rx"
     value="individual_rx" />
  <parameter name="pma_tx_buf_calibration_resistor_value" value="res_setting0" />
  <parameter
     name="hssi_8g_rx_pcs_clock_observation_in_pld_core"
     value="internal_sw_wa_clk" />
  <parameter name="enable_tx_fast_pipeln_reg" value="0" />
  <parameter name="hssi_common_pcs_pma_interface_pma_if_dft_en" value="dft_dis" />
  <parameter name="cdr_pll_lpd_counter" value="2" />
  <parameter name="pma_tx_ser_ser_powerdown" value="normal_poweron_ser" />
  <parameter name="hssi_8g_rx_pcs_rx_pcs_urst" value="en_rx_pcs_urst" />
  <parameter name="std_rx_polinv_enable" value="0" />
  <parameter name="hssi_10g_rx_pcs_descrm_mode" value="async" />
  <parameter name="cdr_pll_is_cascaded_pll" value="false" />
  <parameter name="hssi_adapt_rx_fifo_wr_clk_scg_en" value="disable" />
  <parameter name="hssi_adapt_rx_rx_post_cursor_en" value="disable" />
  <parameter
     name="cdr_pll_chgpmp_current_dn_trim"
     value="cp_current_trimming_dn_setting0" />
  <parameter name="pma_adapt_initial_settings" value="true" />
  <parameter name="can_gen_exdesign_cpri_auto" value="1" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx"
     value="disable" />
  <parameter name="pma_rx_dfe_latch_xcouple_disable" value="latch_xcouple_enable" />
  <parameter name="use_tx_clkout2" value="0" />
  <parameter name="pma_adapt_adp_odi_start" value="radp_odi_start_0" />
  <parameter
     name="qsf_assignments_list"
     value="# These QSF assignments are provided for your reference.,# Normally you do not need these assignments. The IP will,# make these settings for you. Refer to the user guide for,# scenarios where you might want to override default IP settings.,# Replace your pin names in the pin lists below.,set tx_pin_list { &lt;tx_pin_0&gt; &lt;tx_pin_1&gt; },set rx_pin_list { &lt;rx_pin_0&gt; &lt;rx_pin_1&gt; },# TX pin assignments,foreach tx_pin $tx_pin_list {,set_instance_assignment -name HSSI_PARAMETER &quot;cdr_pll_power_mode=mid_power&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_pm_cr2_rx_path_pma_rx_divclk_hz=322265625&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_power_mode=mid_power&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_pm_cr2_rx_path_power_mode=mid_power&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_pm_cr2_rx_path_power_rail_er=1030&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_sel_vcm_ctle=vocm_eq_gndref&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_vcm_sel=vcm_l1&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_vcm_sel_vccref=5&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_power_mode=mid_power&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_odi_power_mode=mid_power&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_sd_power_mode=mid_power&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pm_cr2_tx_path_pma_tx_divclk_hz=322265625&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pm_cr2_tx_path_power_mode=mid_power&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pm_cr2_tx_path_power_rail_et=1030&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_uc_vcc_setting=vcc_setting1&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_power_rail_er=1030&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_powermode_ac_cgb=cgb_ac_off&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_powermode_dc_cgb=powerdown_cgb&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_uc_vcc_setting=vcc_setting1&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_ser_power_rail_er=1030&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_ser_powermode_ac_ser=ac_clk_divtx_user_0_jitcomp1p0&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_ser_powermode_dc_ser=dc_clk_divtx_user_0_jitcomp1p0&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_ser_uc_vcc_setting=vcc_setting1&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pm_cr2_tx_path_analog_mode=user_custom&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_compensation_en=enable&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_compensation_posttap_en=disable&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_cpen_ctrl=cp_l1&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pm_cr2_tx_path_datarate_bps=10312500000&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pm_cr2_tx_path_gt_enabled=disable&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_link=link_off&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pm_cr2_tx_path_link=sr&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_optimal=true&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pm_cr2_tx_path_optimal=true&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_powermode_ac_post_tap=tx_post_tap_ac_off&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_powermode_ac_pre_tap=tx_pre_tap_ac_off&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_powermode_ac_tx_vod_no_jitcomp=tx_vod_no_jitcomp_ac_l0&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_powermode_ac_tx_vod_w_jitcomp=tx_vod_w_jitcomp_ac_l31&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_powermode_dc_post_tap=powerdown_tx_post_tap&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_powermode_dc_pre_tap=powerdown_tx_pre_tap&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_powermode_dc_tx_vod_no_jitcomp=powerdown_tx_vod_no_jitcomp&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_powermode_dc_tx_vod_w_jitcomp=tx_vod_w_jitcomp_dc_l31&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pre_emp_sign_1st_post_tap=fir_post_1t_neg&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pre_emp_sign_pre_tap_1t=fir_pre_1t_neg&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pre_emp_switching_ctrl_1st_post_tap=0&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pre_emp_switching_ctrl_pre_tap_1t=0&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_slew_rate_ctrl=slew_r5&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_term_sel=r_r1&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_vod_output_swing_ctrl=31&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_vreg_output=vccdreg_nominal&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_bitslip_enable=disable_bitslip&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_datarate_bps=10312500000&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_uc_cgb_vreg_boost=no_voltage_boost&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_x1_clock_source_sel=lcpll_top&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_x1_div_m_sel=divbypass&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_ser_ser_clk_divtx_user_sel=divtx_user_off&quot; -to ${tx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_sequencer_tx_path_rstn_overrideb=use_sequencer&quot; -to ${tx_pin},},# RX pin assignments,foreach rx_pin $rx_pin_list {,set_instance_assignment -name HSSI_PARAMETER &quot;cdr_pll_power_mode=mid_power&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_pm_cr2_rx_path_pma_rx_divclk_hz=322265625&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_power_mode=mid_power&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_pm_cr2_rx_path_power_mode=mid_power&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_pm_cr2_rx_path_power_rail_er=1030&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_sel_vcm_ctle=vocm_eq_gndref&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_vcm_sel=vcm_l1&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_vcm_sel_vccref=5&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_power_mode=mid_power&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_odi_power_mode=mid_power&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_sd_power_mode=mid_power&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pm_cr2_tx_path_pma_tx_divclk_hz=322265625&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pm_cr2_tx_path_power_mode=mid_power&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_pm_cr2_tx_path_power_rail_et=1030&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_buf_uc_vcc_setting=vcc_setting1&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_power_rail_er=1030&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_powermode_ac_cgb=cgb_ac_off&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_powermode_dc_cgb=powerdown_cgb&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_cgb_uc_vcc_setting=vcc_setting1&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_ser_power_rail_er=1030&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_ser_powermode_ac_ser=ac_clk_divtx_user_0_jitcomp1p0&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_ser_powermode_dc_ser=dc_clk_divtx_user_0_jitcomp1p0&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_tx_ser_uc_vcc_setting=vcc_setting1&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adapt_mode=manual&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_ac_ctle_en=radp_ac_ctle_en_disable&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_ac_ctle_hold_en=radp_ac_ctle_hold_en_not_hold&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_ac_ctle_initial_value=radp_ac_ctle_initial_value_8&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_ac_ctle_mode_sel=radp_ac_ctle_mode_sel_concurrent&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_ctle_bypass_ac=radp_ctle_bypass_ac_bypass&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_ctle_bypass_dc=radp_ctle_bypass_dc_bypass&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dc_ctle_en=radp_dc_ctle_en_disable&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dc_ctle_mode0_win_size=radp_dc_ctle_mode0_win_size_4_taps&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dc_ctle_mode0_win_start=0&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dc_ctle_mode2_h2_limit=7&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dc_ctle_mode_sel=radp_dc_ctle_mode_sel_mode_2&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dc_ctle_onetime=radp_dc_ctle_onetime_disable&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dfe_en=radp_dfe_en_disable&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dfe_fxtap_bypass=radp_dfe_fxtap_bypass_bypass&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dfe_hold_sel=radp_dfe_hold_sel_no&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dfe_tap1_initial_value=radp_dfe_tap1_initial_value_0&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dfe_tap_sel_en=radp_dfe_tap_sel_en_no&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dlev_bypass=radp_dlev_bypass_bypass&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_dlev_en=radp_dlev_en_disable&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_vga_bypass=radp_vga_bypass_bypass&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_vga_ctle_low_limit=radp_vga_ctle_low_limit_0&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_vga_dlev_target=15&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_adp_vga_en=radp_vga_en_disable&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_optimal=true&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_powermode_ac_adaptation=adapt_ac_off&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_powermode_ac_deser_adapt=adapt_deser_ac_off&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_powermode_ac_dfe_adapt=adapt_dfe_ac_off&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_powermode_dc_adaptation=powerdown_adapt&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_powermode_dc_deser_adapt=powerdown_adapt_deser&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_adapt_powermode_dc_dfe_adapt=powerdown_adapt_dfe&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;cdr_pll_analog_mode=user_custom&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;cdr_pll_bypass_a_edge=bypass_a_edge_off&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;cdr_pll_optimal=true&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_pm_cr2_rx_path_analog_mode=user_custom&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_ctle_ac_gain=0&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_ctle_eq_gain=0&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_ctle_rf_cal=3&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_pm_cr2_rx_path_datarate_bps=10312500000&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_pm_cr2_rx_path_gt_enabled=disable&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_link=link_off&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_pm_cr2_rx_path_link=sr&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_optimal=true&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_pm_cr2_rx_path_optimal=true&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_rx_ltr_load_init=rx_load_original&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_term_sel=r_r4&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_vga_dc_gain=0&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_buf_vga_ib_max_en=vga_ib_max_disable&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_deser_datarate_bps=10312500000&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_deser_optimal=true&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_datarate_bps=10312500000&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_dfe_mode=cdr_mode&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_latch_xcouple_disable=latch_xcouple_enable&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_optimal=true&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_pdb_edge_pre_h1=cdr_pre_h1_enable&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_pdb_edge_pst_h1=cdr_pst_h1_disable&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_pdb_tap_10t15=tap10t15_dfe_powerdown&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_pdb_tap_4t9=tap4t9_dfe_powerdown&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_pdb_tapsum=tapsum_disable&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_powermode_ac_dfe=ac_cdr_mode&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_powermode_dc_dfe=powerdown_dfe&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_dfe_tapsum_bw_sel=tapsum_medbw&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_odi_datarate_bps=10312500000&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_odi_monitor_bw_sel=bw_4&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_odi_optimal=true&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_odi_xrx_path_x119_rx_path_rstn_overrideb=use_sequencer&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_odi_vreg_voltage_sel=vreg0&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_sd_link=sr&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_sd_optimal=true&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_rx_sd_sd_threshold=sdlv_3&quot; -to ${rx_pin},set_instance_assignment -name HSSI_PARAMETER &quot;pma_reset_sequencer_rx_path_rstn_overrideb=use_sequencer&quot; -to ${rx_pin},}" />
  <parameter name="pma_rx_dfe_tap5_sgn" value="tap5_sign_0" />
  <parameter name="pma_pcie_gen_switch_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="cdr_pll_vco_freq" value="10312500000" />
  <parameter name="l_pcs_pma_width" value="32" />
  <parameter name="pma_adapt_adp_oc_hold_en" value="radp_oc_hold_en_not_hold" />
  <parameter name="pma_rx_odi_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_aibcr_tx_dft_hssitestip_dll_dcc_en" value="disable_dft" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_hip_en"
     value="disable" />
  <parameter name="hssi_pipe_gen3_bypass_tx_coefficent_enable" value="false" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_st_dftmuxsel"
     value="aib_rx_dcc_st_dftmuxsel_setting0" />
  <parameter
     name="hssi_common_pcs_pma_interface_sigdet_wait_counter_multi"
     value="0" />
  <parameter name="hssi_pipe_gen1_2_rvod_sel_a_val" value="0" />
  <parameter name="rcfg_file_prefix" value="alt_mge_phy" />
  <parameter name="hssi_pldadapt_tx_fifo_stop_wr" value="wr_full" />
  <parameter name="cdr_pll_clk180_dfe_trise_adj" value="clk180_dfe_tr0" />
  <parameter name="hssi_adapt_tx_sup_mode" value="user_mode" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_sup_mode" value="user_mode" />
  <parameter name="hssi_pldadapt_tx_duplex_mode" value="enable" />
  <parameter
     name="hssi_rx_pcs_pma_interface_prot_mode_rx"
     value="teng_krfec_mode_rx" />
  <parameter name="hssi_pipe_gen3_bypass_tx_coefficent" value="0" />
  <parameter name="hssi_10g_tx_pcs_frmgen_burst" value="frmgen_burst_dis" />
  <parameter name="hssi_krfec_rx_pcs_parity_valid_num" value="4" />
  <parameter
     name="hssi_common_pcs_pma_interface_rxvalid_mask"
     value="rxvalid_mask_dis" />
  <parameter name="hssi_adapt_rx_hrdrst_rst_sm_dis" value="enable_rx_rst_sm" />
  <parameter name="pma_tx_buf_power_rail_er" value="0" />
  <parameter name="pma_adapt_powermode_dc_dfe_adapt" value="powerdown_adapt_dfe" />
  <parameter name="pma_adapt_adp_pcie_hold_sel" value="0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx"
     value="disabled_prot_mode_tx" />
  <parameter name="hssi_pipe_gen1_2_rxdetect_bypass" value="dis_rxdetect_bypass" />
  <parameter name="manual_pcs_bonding_mode" value="individual" />
  <parameter name="pma_rx_odi_sup_mode" value="user_mode" />
  <parameter
     name="hssi_adapt_tx_fsr_mask_tx_pll_rst_val"
     value="reset_to_zero_maskpll" />
  <parameter name="hssi_fifo_tx_pcs_prot_mode" value="teng_mode" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_pma_dw_tx"
     value="pma_32b_tx" />
  <parameter name="rx_vga_dc_gain" value="0" />
  <parameter name="hssi_adapt_tx_tx_fifo_read_latency_adjust" value="disable" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value"
     value="0" />
  <parameter name="adme_tx_power_mode" value="mid_power" />
  <parameter name="cdr_pll_lf_ripple_cap" value="lf_no_ripple" />
  <parameter name="hssi_adapt_rx_async_direct_hip_en" value="disable" />
  <parameter name="hssi_10g_tx_pcs_tx_testbus_sel" value="tx_fifo_testbus1" />
  <parameter
     name="hssi_pldadapt_rx_fsr_pld_rx_fifo_align_clr_rst_val"
     value="reset_to_zero_alignclr" />
  <parameter
     name="pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch1_src"
     value="cdr_clkin_scratch1_src_refclk_iqclk" />
  <parameter
     name="pma_adapt_adp_pat_spec_sign_value"
     value="radp_pat_spec_sign_value_0" />
  <parameter name="hssi_pldadapt_rx_rx_prbs_flags_sr_enable" value="disable" />
  <parameter
     name="pma_rx_odi_xrx_path_x119_rx_path_rstn_overrideb"
     value="use_sequencer" />
  <parameter name="pma_tx_buf_sup_mode" value="user_mode" />
  <parameter name="hssi_8g_rx_pcs_rate_match" value="dis_rm" />
  <parameter name="l_std_tx_pld_pcs_width" value="10" />
  <parameter name="enable_port_rx_fifo_align_clr" value="0" />
  <parameter name="hssi_adapt_tx_pma_aib_tx_clk_expected_setting" value="x2" />
  <parameter
     name="pma_adapt_adp_tx_adp_accumulate"
     value="radp_tx_adp_accumulate_0" />
  <parameter name="pma_rx_buf_clk_divrx_en" value="normal_clk" />
  <parameter name="enable_port_tx_pma_elecidle" value="0" />
  <parameter name="enable_qpi_async_transfer" value="0" />
  <parameter name="hssi_rx_pld_pcs_interface_hd_pcs8g_lpbk_en" value="disable" />
  <parameter name="enable_port_tx_polinv" value="0" />
  <parameter
     name="hssi_adapt_rx_internal_clk2_sel"
     value="pld_pma_tx_clk_out_clk2" />
  <parameter name="pma_adapt_powermode_ac_adaptation" value="adapt_ac_off" />
  <parameter
     name="hssi_pldadapt_rx_rx_pld_pma_reser_out_polling_bypass"
     value="disable" />
  <parameter
     name="hssi_common_pcs_pma_interface_wait_pipe_synchronizing"
     value="0" />
  <parameter name="pma_adapt_adp_oc_initial_value" value="0" />
  <parameter name="hssi_adapt_rx_txeq_clk_sel" value="txeq_pld_pcs_rx_clk_out" />
  <parameter name="hssi_pldadapt_tx_txfifo_pempty" value="2" />
  <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
  <parameter name="pma_cdr_refclk_powerdown_mode" value="powerup" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_bti_protected" value="false" />
  <parameter
     name="hssi_adapt_rx_fsr_pld_8g_sigdet_out_rst_val"
     value="reset_to_zero_sigdet" />
  <parameter name="hssi_adapt_tx_duplex_mode" value="enable" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs10g_shared_fifo_width_rx"
     value="single_rx" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_st_en"
     value="aib_dllstr_align_st_en_setting1" />
  <parameter name="hssi_10g_rx_pcs_prot_mode" value="teng_1588_mode" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_dly_pst"
     value="aib_dllstr_align_dly_pst_setting0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_tx_clk_hz"
     value="0" />
  <parameter name="pma_rx_buf_sup_mode" value="user_mode" />
  <parameter name="enable_split_interface" value="0" />
  <parameter name="enable_port_clock_delay_measurement" value="0" />
  <parameter name="manual_tx_core_aib_bonding_mode" value="individual" />
  <parameter name="enable_port_tx_pma_rxfound" value="0" />
  <parameter name="hssi_adapt_rx_pipe_mode" value="disable_pipe" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_fref_clk_hz"
     value="322265625" />
  <parameter name="cdr_pll_fref_clklow_div" value="2" />
  <parameter name="design_example_filename" value="top" />
  <parameter
     name="cdr_pll_chgpmp_current_up_trim"
     value="cp_current_trimming_up_setting0" />
  <parameter name="cdr_pll_reverse_serial_loopback" value="no_loopback" />
  <parameter name="pma_tx_buf_duty_cycle_input_polarity" value="dcc_input_pos" />
  <parameter name="hssi_aibnd_rx_op_mode" value="rx_dll_enable" />
  <parameter name="hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel" value="dis_tx_pipe_clk" />
  <parameter name="std_low_latency_bypass_enable" value="0" />
  <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
  <parameter name="hssi_10g_rx_pcs_crcflag_pipeln" value="crcflag_pipeln_en" />
  <parameter name="cdr_pll_vco_underrange_voltage" value="vco_underange_off" />
  <parameter
     name="pma_adapt_adp_dc_ctle_mode_sel"
     value="radp_dc_ctle_mode_sel_mode_2" />
  <parameter name="hssi_krfec_rx_pcs_pipeln_errtrap_pat" value="disable" />
  <parameter name="cdr_pll_iqclk_sel" value="power_down" />
  <parameter name="enable_backup_pma_adapt_modes" value="0" />
  <parameter name="hssi_pipe_gen1_2_error_replace_pad" value="replace_edb" />
  <parameter name="pma_rx_dfe_dft_hilospeed_sel" value="dft_osc_lospeed_path" />
  <parameter name="hssi_krfec_rx_pcs_pipeln_descrm" value="disable" />
  <parameter name="hssi_krfec_rx_pcs_pipeln_errcorrect" value="disable" />
  <parameter name="rcfg_enable_avmm_busy_port" value="0" />
  <parameter name="hssi_gen3_rx_pcs_lpbk_force" value="lpbk_frce_dis" />
  <parameter name="hssi_10g_tx_pcs_crcgen_bypass" value="crcgen_bypass_en" />
  <parameter name="hssi_adapt_rx_rx_pma_rstn_cycles" value="four_cycles" />
  <parameter name="hssi_adapt_tx_tx_qpi_mode_en" value="disable" />
  <parameter name="pma_rx_dfe_oc_sa_odio_sgn" value="oc_sa_odio_sgn_0" />
  <parameter name="pma_tx_buf_pre_emp_switching_ctrl_1st_post_tap" value="0" />
  <parameter
     name="cdr_pll_set_cdr_vco_speed_pciegen3"
     value="cdr_vco_max_speedbin_pciegen3" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_fifo_mode_rx"
     value="reg_rx" />
  <parameter name="hssi_avmm1_if_hssiadapt_sr_sr_osc_clk_scg_en" value="disable" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_datarate_bps" value="10312500000" />
  <parameter name="manual_rx_core_aib_indv" value="indv_en" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_st_en"
     value="aib_rx_dcc_st_en_setting1" />
  <parameter name="enable_port_rx_enh_crc32_err" value="0" />
  <parameter name="pma_adapt_adp_oc_initial_load" value="radp_oc_initial_load_0" />
  <parameter name="hssi_10g_tx_pcs_indv" value="indv_en" />
  <parameter name="hssi_10g_rx_pcs_wrfifo_clken" value="wrfifo_clk_en" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_rx_clk_hz"
     value="322265625" />
  <parameter name="hssi_adapt_tx_fifo_mode" value="phase_comp" />
  <parameter
     name="pma_tx_ser_powermode_dc_ser"
     value="dc_clk_divtx_user_0_jitcomp1p0" />
  <parameter name="pma_cgb_cgb_power_down" value="normal_cgb" />
  <parameter name="hssi_pldadapt_tx_pma_aib_tx_clk_expected_setting" value="x2" />
  <parameter name="hssi_8g_rx_pcs_byte_deserializer" value="dis_bds" />
  <parameter name="hssi_adapt_rx_bonding_dft_val" value="dft_0" />
  <parameter name="hssi_8g_rx_pcs_gen3_tx_clk_sel" value="tx_pma_clk" />
  <parameter
     name="pma_adapt_adp_ac_ctle_cocurrent_mode_sel"
     value="radp_ac_ctle_cocurrent_mode_sel_mode_1" />
  <parameter name="std_tx_byterev_enable" value="0" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_8g_refclk_dig_nonatpg_mode_clk_hz"
     value="0" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_initial_settings" value="true" />
  <parameter name="pma_cgb_observe_cgb_clocks" value="observe_nothing" />
  <parameter name="l_split_iface" value="0" />
  <parameter name="hssi_rx_pcs_pma_interface_pma_if_dft_val" value="dft_0" />
  <parameter name="tx_pll_refclk" value="644.53125" />
  <parameter name="hssi_rx_pld_pcs_interface_hd_g3pcs_sup_mode" value="user_mode" />
  <parameter name="hssi_aibnd_tx_powerdown_mode" value="true" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_if_hrdrstctl_en"
     value="disable" />
  <parameter name="hssi_10g_tx_pcs_wrfifo_clken" value="wrfifo_clk_en" />
  <parameter name="pma_rx_dfe_oc_sa_dpo_sgn" value="oc_sa_dpo_sgn_0" />
  <parameter name="hssi_tx_pcs_pma_interface_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="pma_tx_buf_tri_driver" value="tri_driver_disable" />
  <parameter name="hssi_10g_rx_pcs_descrm_bypass" value="descrm_bypass_dis" />
  <parameter name="cdr_pll_position" value="position0" />
  <parameter name="hssi_pldadapt_rx_us_master" value="us_master_en" />
  <parameter name="hssi_adapt_tx_indv" value="indv_en" />
  <parameter name="hssi_10g_rx_pcs_gb_rx_idwidth" value="idwidth_32" />
  <parameter name="hssi_10g_rx_pcs_crcchk_clken" value="crcchk_clk_dis" />
  <parameter name="cdr_pll_clk0_dfe_tfall_adj" value="clk0_dfe_tf0" />
  <parameter name="hssi_krfec_rx_pcs_bypass_gb" value="bypass_dis" />
  <parameter name="l_protocol_mode" value="teng_1588_mode" />
  <parameter name="cdr_pll_set_cdr_input_freq_range" value="149" />
  <parameter name="pma_tx_buf_rx_det_pdb" value="rx_det_off" />
  <parameter name="enh_rx_polinv_enable" value="0" />
  <parameter
     name="hssi_adapt_tx_txqpi_pullup_rst_val"
     value="reset_to_zero_txqpiu" />
  <parameter name="hssi_avmm1_if_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_common_pld_pcs_interface_reconfig_settings" value="{}" />
  <parameter name="hssi_adapt_rx_us_last_chnl" value="us_last_chnl" />
  <parameter name="hssi_adapt_tx_fifo_stop_wr" value="wr_full" />
  <parameter name="std_rx_rmfifo_pattern_n" value="0" />
  <parameter
     name="hssi_adapt_rx_txfifowr_from_aib_sel"
     value="txfifowr_sclk_from_aib" />
  <parameter name="std_rx_rmfifo_pattern_p" value="0" />
  <parameter name="pma_rx_dfe_oc_sa_cdrpe_sgn" value="oc_sa_cdrpe_sgn_0" />
  <parameter name="hssi_10g_tx_pcs_fec_enable" value="fec_dis" />
  <parameter name="hssi_8g_rx_pcs_bypass_pipeline_reg" value="dis_bypass_pipeline" />
  <parameter name="hssi_8g_tx_pcs_pcs_bypass" value="dis_pcs_bypass" />
  <parameter name="hssi_10g_rx_pcs_descrm_pipeln" value="enable" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_st_core_dn_prgmnvrt"
     value="aib_dllstr_align_st_core_dn_prgmnvrt_setting0" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs8g_prot_mode_rx"
     value="disabled_prot_mode_rx" />
  <parameter name="hssi_krfec_rx_pcs_blksync_cor_en" value="detect" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs8g_ctrl_plane_bonding_tx"
     value="individual_tx" />
  <parameter name="hssi_aibnd_tx_dfd_dll_dcc_en" value="disable_dfd" />
  <parameter name="tx_pma_slew_rate_ctrl" value="0" />
  <parameter name="hssi_aibnd_rx_aib_outndrv_r56" value="aib_ndrv56_setting1" />
  <parameter
     name="hssi_pldadapt_tx_hdpldadapt_sr_sr_testbus_sel"
     value="ssr_testbus" />
  <parameter name="hssi_adapt_rx_fifo_rd_clk_scg_en" value="disable" />
  <parameter name="pma_adapt_adp_odi_en" value="radp_odi_en_disable" />
  <parameter name="hssi_common_pcs_pma_interface_silicon_rev" value="14nm5bcr2eb" />
  <parameter
     name="rcfg_params"
     value="rcfg_debug,rcfg_enable,rcfg_jtag_enable,rcfg_separate_avmm_busy,rcfg_enable_avmm_busy_port,set_capability_reg_enable,set_user_identifier,set_csr_soft_logic_enable,support_mode,channel_type,protocol_mode,pma_mode,duplex_mode,channels,set_data_rate,rcfg_iface_enable,enable_simple_interface,enable_split_interface,set_enable_calibration,enable_double_rate_transfer,enable_background_cal_gui,enable_direct_reset_control,disable_reset_sequencer,disable_digital_reset_sequencer,bonded_mode,set_pcs_bonding_master,pcs_reset_sequencing_mode,manual_pcs_bonding_mode,manual_pcs_bonding_comp_cnt,manual_tx_hssi_aib_bonding_mode,manual_tx_hssi_aib_bonding_comp_cnt,manual_tx_core_aib_bonding_mode,manual_tx_core_aib_bonding_comp_cnt,manual_rx_hssi_aib_bonding_mode,manual_rx_hssi_aib_bonding_comp_cnt,manual_rx_core_aib_bonding_mode,manual_rx_core_aib_bonding_comp_cnt,manual_tx_hssi_aib_indv,manual_tx_core_aib_indv,manual_rx_hssi_aib_indv,manual_rx_core_aib_indv,tx_pma_clk_div,plls,pll_select,enable_port_tx_pma_iqtxrx_clkout,enable_port_tx_pma_elecidle,number_physical_bonding_clocks,enable_qpi_mode,enable_qpi_async_transfer,enable_port_tx_pma_qpipullup,enable_port_tx_pma_qpipulldn,enable_port_tx_pma_rxfound,enable_port_rx_pma_qpipulldn,enable_port_tx_pma_txdetectrx,cdr_refclk_cnt,cdr_refclk_select,set_cdr_refclk_freq,rx_ppm_detect_threshold,enable_port_rx_pma_iqtxrx_clkout,enable_port_rx_pma_clkslip,enable_port_rx_is_lockedtodata,enable_port_rx_is_lockedtoref,enable_ports_rx_manual_cdr_mode,enable_ports_rx_prbs,enable_port_rx_seriallpbken,std_pcs_pma_width,std_low_latency_bypass_enable,enable_hip,enable_hard_reset,set_hip_cal_en,hip_mode,hip_prot_mode,hip_channels,enable_ehip,avmm_ehip_mode,adapter_ehip_mode,std_tx_byte_ser_mode,std_rx_byte_deser_mode,std_tx_8b10b_enable,std_tx_8b10b_disp_ctrl_enable,std_rx_8b10b_enable,std_rx_rmfifo_mode,std_rx_rmfifo_pattern_n,std_rx_rmfifo_pattern_p,enable_port_rx_std_rmfifo_full,enable_port_rx_std_rmfifo_empty,pcie_rate_match,std_tx_bitslip_enable,enable_port_tx_std_bitslipboundarysel,std_rx_word_aligner_mode,std_rx_word_aligner_pattern_len,std_rx_word_aligner_pattern,std_rx_word_aligner_rknumber,std_rx_word_aligner_renumber,std_rx_word_aligner_rgnumber,std_rx_word_aligner_fast_sync_status_enable,enable_port_rx_std_wa_patternalign,enable_port_rx_std_wa_a1a2size,enable_port_rx_std_bitslipboundarysel,enable_port_rx_std_bitslip,std_tx_bitrev_enable,std_tx_byterev_enable,std_tx_polinv_enable,enable_port_tx_polinv,std_rx_bitrev_enable,enable_port_rx_std_bitrev_ena,std_rx_byterev_enable,enable_port_rx_std_byterev_ena,std_rx_polinv_enable,enable_port_rx_polinv,enable_port_rx_std_signaldetect,enable_ports_pipe_sw,enable_ports_pipe_rx_elecidle,enable_ports_pipe_hclk,enh_pcs_pma_width,enh_pld_pcs_width,enh_low_latency_enable,enh_advanced_user_mode,enh_tx_frmgen_enable,enh_tx_frmgen_mfrm_length,enh_tx_frmgen_burst_enable,enable_port_tx_enh_frame,enable_port_tx_enh_frame_diag_status,enable_port_tx_enh_frame_burst_en,enh_rx_frmsync_enable,enh_rx_frmsync_mfrm_length,enable_port_rx_enh_frame,enable_port_rx_enh_frame_lock,enable_port_rx_enh_frame_diag_status,enh_tx_crcgen_enable,enh_tx_crcerr_enable,enh_rx_crcchk_enable,enable_port_rx_enh_crc32_err,enable_port_rx_enh_highber,enable_port_rx_enh_highber_clr_cnt,enable_port_rx_enh_clr_errblk_count,enh_tx_64b66b_enable,enh_rx_64b66b_enable,enh_tx_sh_err,enh_tx_scram_enable,enh_tx_scram_seed,enh_rx_descram_enable,enh_tx_dispgen_enable,enh_rx_dispchk_enable,enh_tx_randomdispbit_enable,enh_rx_blksync_enable,enable_port_rx_enh_blk_lock,enh_tx_bitslip_enable,enh_tx_polinv_enable,enh_rx_bitslip_enable,enh_rx_polinv_enable,enable_port_tx_enh_bitslip,enable_port_rx_enh_bitslip,enh_rx_krfec_err_mark_enable,enh_rx_krfec_err_mark_type,enh_tx_krfec_burst_err_enable,enh_tx_krfec_burst_err_len,enable_port_krfec_tx_enh_frame,enable_port_krfec_rx_enh_frame,enable_port_krfec_rx_enh_frame_diag_status,pcs_direct_width,enable_tx_fast_pipeln_reg,enable_rx_fast_pipeln_reg,parallel_loopback_mode,loopback_tx_clk_sel,enable_debug_ports,tx_fifo_mode,tx_fifo_pfull,tx_fifo_pempty,enable_port_tx_fifo_full,enable_port_tx_fifo_empty,enable_port_tx_fifo_pfull,enable_port_tx_fifo_pempty,enable_port_tx_pcs_fifo_full,enable_port_tx_pcs_fifo_empty,enable_port_tx_dll_lock,rx_fifo_mode,rx_fifo_pfull,rx_fifo_pempty,rx_fifo_align_del,rx_fifo_control_del,enable_port_rx_data_valid,enable_port_rx_fifo_full,enable_port_rx_fifo_empty,enable_port_rx_fifo_pfull,enable_port_rx_fifo_pempty,enable_port_rx_fifo_del,enable_port_rx_fifo_insert,enable_port_rx_fifo_rd_en,enable_port_rx_fifo_align_clr,enable_port_rx_pcs_fifo_full,enable_port_rx_pcs_fifo_empty,tx_clkout_sel,enable_port_tx_clkout2,tx_clkout2_sel,enable_port_tx_clkout_hioint,enable_port_tx_clkout2_hioint,tx_pma_div_clkout_divider,tx_coreclkin_clock_network,tx_pcs_bonding_clock_network,rx_clkout_sel,enable_port_rx_clkout2,rx_clkout2_sel,enable_port_rx_clkout_hioint,enable_port_rx_clkout2_hioint,rx_pma_div_clkout_divider,rx_coreclkin_clock_network,osc_clk_divider,enable_port_tx_fifo_latency_adj_ena,enable_port_rx_fifo_latency_adj_ena,enable_port_latency_measurement,enable_port_clock_delay_measurement,delay_measurement_clkout_sel,delay_measurement_clkout2_sel,ovrd_tx_dv_mode,usr_tx_dv_mode,ovrd_rx_dv_mode,usr_rx_dv_mode,set_prbs_soft_logic_enable,enable_rcfg_tx_digitalreset_release_ctrl,anlg_voltage,anlg_link,enable_ports_adaptation,tx_pma_analog_mode,rx_pma_analog_mode,tx_pma_optimal_settings,tx_pma_output_swing_ctrl,tx_pma_pre_emp_sign_pre_tap_1t,tx_pma_pre_emp_switching_ctrl_pre_tap_1t,tx_pma_pre_emp_sign_1st_post_tap,tx_pma_pre_emp_switching_ctrl_1st_post_tap,tx_pma_slew_rate_ctrl,tx_pma_term_sel,tx_pma_compensation_en,rx_pma_adapt_mode,rx_pma_term_sel,rx_ctle_ac_gain,rx_ctle_eq_gain,rx_vga_dc_gain" />
  <parameter name="hssi_pipe_gen3_mode" value="disable_pcs" />
  <parameter name="rcfg_param_vals7" value="" />
  <parameter name="std_rx_byte_deser_mode" value="Disabled" />
  <parameter name="rcfg_param_vals5" value="" />
  <parameter name="rcfg_param_vals6" value="" />
  <parameter name="rcfg_param_vals3" value="" />
  <parameter name="rcfg_param_vals4" value="" />
  <parameter name="hssi_pldadapt_tx_bonding_dft_val" value="dft_0" />
  <parameter name="rcfg_param_vals1" value="" />
  <parameter name="rcfg_param_vals2" value="" />
  <parameter name="hssi_aibnd_rx_sup_mode" value="user_mode" />
  <parameter
     name="hssi_adapt_rx_txfiford_post_ct_sel"
     value="txfiford_sclk_post_ct" />
  <parameter
     name="hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass"
     value="dec_64b66b_rxsm_bypass_dis" />
  <parameter name="hssi_10g_rx_pcs_lpbk_mode" value="lpbk_dis" />
  <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
  <parameter
     name="hssi_pldadapt_rx_txfifowr_post_ct_sel"
     value="txfifowr_sclk_post_ct" />
  <parameter name="hssi_pldadapt_rx_rx_fastbond_wren" value="wren_ds_del_us_del" />
  <parameter name="pma_adapt_adp_po_gb_slp2act" value="radp_po_gb_slp2act_288ns" />
  <parameter name="cdr_pll_bti_protected" value="false" />
  <parameter name="enable_port_rx_seriallpbken" value="1" />
  <parameter name="pma_rx_dfe_tapsum_bw_sel" value="tapsum_medbw" />
  <parameter name="hssi_8g_rx_pcs_sup_mode" value="user_mode" />
  <parameter name="hssi_adapt_rx_fifo_rd_clk_sel" value="fifo_rd_pma_aib_rx_clk" />
  <parameter name="hssi_8g_rx_pcs_bonding_dft_en" value="dft_dis" />
  <parameter name="enable_port_latency_measurement" value="1" />
  <parameter name="pma_rx_dfe_dfe_bti_en" value="dfe_bti_disable" />
  <parameter name="hssi_adapt_rx_ds_last_chnl" value="ds_last_chnl" />
  <parameter name="enable_pcs_dir" value="0" />
  <parameter name="hssi_krfec_tx_pcs_low_latency_en" value="disable" />
  <parameter name="hssi_pldadapt_tx_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="pma_adapt_adp_odi_mode" value="radp_odi_mode_detect_errdata" />
  <parameter name="pma_rx_dfe_pdb_tapsum" value="tapsum_disable" />
  <parameter name="pma_rx_dfe_oc_sa_dne_sgn" value="oc_sa_dne_sgn_0" />
  <parameter name="enable_port_rx_enh_bitslip" value="0" />
  <parameter name="pma_rx_buf_rx_atb_select" value="atb_disable" />
  <parameter
     name="hssi_pldadapt_tx_fsr_hip_fsr_out_bit2_rst_val"
     value="reset_to_zero_hfsrout2" />
  <parameter name="enable_port_tx_pma_qpipullup" value="0" />
  <parameter name="hssi_adapt_rx_rx_pld_test_data_polling_bypass" value="disable" />
  <parameter
     name="hssi_pldadapt_tx_tx_pld_pma_fpll_cnt_sel_polling_bypass"
     value="disable" />
  <parameter name="plls" value="1" />
  <parameter name="enable_early_spd_chng" value="0" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_st_en"
     value="aib_dllstr_align_st_en_setting1" />
  <parameter name="adme_data_rate" value="10312500000" />
  <parameter name="hssi_adapt_tx_dv_gating" value="disable" />
  <parameter
     name="hssi_pldadapt_rx_fsr_pld_ltd_b_rst_val"
     value="reset_to_one_ltdb" />
  <parameter name="hssi_aibnd_rx_aib_outndrv_r78" value="aib_ndrv78_setting1" />
  <parameter name="hssi_adapt_tx_fifo_wr_clk_scg_en" value="disable" />
  <parameter name="pma_adapt_adp_pat_trans_filter" value="radp_pat_trans_filter_5" />
  <parameter name="cdr_pll_datarate_bps" value="10312500000" />
  <parameter name="pma_rx_dfe_odi_h1_sign" value="odi_h1_pos" />
  <parameter name="hssi_pldadapt_tx_word_mark" value="wm_en" />
  <parameter name="hssi_avmm1_if_hssiadapt_read_blocking_enable" value="enable" />
  <parameter name="hssi_tx_pld_pcs_interface_hd_pcs8g_sup_mode" value="user_mode" />
  <parameter name="rcfg_reduced_files_enable" value="1" />
  <parameter name="hssi_pipe_gen3_phy_status_delay_g12" value="0" />
  <parameter name="enable_port_rx_clkout2" value="1" />
  <parameter name="ovrd_rx_dv_mode" value="0" />
  <parameter name="cdr_pll_clk270_dfe_tfall_adj" value="clk270_dfe_tf0" />
  <parameter
     name="hssi_8g_tx_pcs_clock_observation_in_pld_core"
     value="internal_refclk_b" />
  <parameter name="hssi_10g_rx_pcs_stretch_num_stages" value="one_stage" />
  <parameter name="hssi_aibnd_tx_aib_tx_clkdiv" value="aib_tx_clkdiv_setting1" />
  <parameter name="hssi_adapt_tx_osc_clk_scg_en" value="disable" />
  <parameter
     name="hssi_8g_rx_pcs_force_signal_detect"
     value="en_force_signal_detect" />
  <parameter name="pma_rx_dfe_silicon_rev" value="14nm5bcr2eb" />
  <parameter
     name="hssi_adapt_rx_txfifowr_post_ct_sel"
     value="txfifowr_sclk_post_ct" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_sup_mode"
     value="user_mode" />
  <parameter
     name="pma_adapt_adp_dlev_onetime_threshold"
     value="radp_dlev_onetime_threshold_4096" />
  <parameter name="hssi_8g_tx_pcs_refclk_b_clk_sel" value="tx_pma_clock" />
  <parameter name="hssi_rx_pld_pcs_interface_reconfig_settings" value="{}" />
  <parameter name="hssi_pipe_gen1_2_rvod_sel_b_val" value="0" />
  <parameter
     name="rcfg_param_vals0"
     value="0,1,0,0,0,0,0,0,user_mode,GX,teng_1588_mode,basic,duplex,1,10312.5,0,0,0,1,0,0,0,0,0,not_bonded,Auto,not_bonded,individual,0,individual,0,individual,0,individual,0,individual,0,indv_en,indv_en,indv_en,indv_en,1,1,0,0,0,1,0,1,0,0,0,0,0,1,0,644.53125,100,0,0,1,0,0,0,1,10,0,0,0,0,disable_hip,gen1,x1,0,disable_hip,disable_hip,Disabled,Disabled,1,0,1,disabled,0,0,0,0,Bypass,0,0,synchronous state machine,10,0,3,3,3,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,66,0,0,0,2048,0,0,0,0,0,2048,0,0,0,0,0,0,0,1,1,1,1,1,0,1,288230376151711743,1,0,0,0,1,1,0,0,0,0,0,0,0,10G,0,1,0,0,0,8,0,0,disable,internal_clk,0,Phase compensation,10,2,0,0,0,0,0,0,0,Phase compensation,10,2,0,0,1,0,0,0,0,0,0,0,0,0,0,pcs_clkout,0,pcs_clkout,0,0,33,dedicated,dedicated,pcs_clkout,1,pma_div_clkout,0,0,33,dedicated,1,0,0,1,0,clock_delay_measurement_clkout,clock_delay_measurement_clkout,0,enable,0,enable,0,0,1_0V,sr,0,user_custom,user_custom,1,12,negative,0,negative,0,0,r_r1,enable,manual,r_r1,0,0,0" />
  <parameter name="manual_tx_core_aib_indv" value="indv_en" />
  <parameter name="pma_rx_sd_sup_mode" value="user_mode" />
  <parameter name="hssi_8g_rx_pcs_phase_compensation_fifo" value="register_fifo" />
  <parameter
     name="pma_tx_buf_chgpmp_current_up_trim"
     value="cp_current_trimming_up_setting0" />
  <parameter name="hssi_pldadapt_rx_rxfifo_mode" value="rxphase_comp" />
  <parameter name="hssi_adapt_tx_txfifo_empty" value="empty_default" />
  <parameter name="std_rx_bitrev_enable" value="0" />
  <parameter
     name="hssi_common_pcs_pma_interface_ppm_det_buckets"
     value="ppm_100_bucket" />
  <parameter name="hssi_krfec_tx_pcs_burst_err_len" value="burst_err_len1" />
  <parameter name="hssi_aibnd_rx_aib_outndrv_r12" value="aib_ndrv12_setting1" />
  <parameter name="hssi_adapt_rx_hd_hssiadapt_hip_aib_clk_2x_hz" value="0" />
  <parameter name="hssi_aibcr_tx_aib_outndrv_r56" value="aib_ndrv56_setting1" />
  <parameter name="hssi_10g_rx_pcs_fast_path" value="fast_path_dis" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_func_mode"
     value="enable" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_st_dftmuxsel"
     value="aib_dllstr_align_st_dftmuxsel_setting0" />
  <parameter name="pma_rx_buf_dfe_h1_sw_togg" value="dfe_h1_tog_neg" />
  <parameter
     name="hssi_10g_tx_pcs_fifo_double_write"
     value="fifo_double_write_dis" />
  <parameter name="pma_rx_odi_datarate_bps" value="10312500000" />
  <parameter name="hip_prot_mode" value="gen1" />
  <parameter name="hssi_avmm1_if_pcs_arbiter_ctrl" value="avmm1_arbiter_uc_sel" />
  <parameter name="hssi_8g_rx_pcs_sync_sm_idle_eios" value="dis_syncsm_idle" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_st_core_dn_prgmnvrt"
     value="aib_tx_dcc_st_core_dn_prgmnvrt_setting0" />
  <parameter name="pma_rx_dfe_adapt_bti_en" value="adapt_bti_disable" />
  <parameter name="cdr_pll_clk90_dfe_trise_adj" value="clk90_dfe_tr0" />
  <parameter name="pma_rx_dfe_tap11_sgn" value="tap11_sign_0" />
  <parameter name="std_tx_8b10b_enable" value="1" />
  <parameter
     name="hssi_8g_rx_pcs_rate_match_start_thres"
     value="dis_rm_start_thres" />
  <parameter name="cdr_pll_diag_loopback_enable" value="no_diag_rev_loopback" />
  <parameter
     name="hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel"
     value="one_ff_delay" />
  <parameter name="pma_adapt_adp_dlev_hold_en" value="radp_dlev_hold_en_not_hold" />
  <parameter name="hssi_aibnd_rx_aib_outndrv_r34" value="aib_ndrv34_setting1" />
  <parameter name="std_pcs_pma_width" value="10" />
  <parameter name="hssi_aibcr_tx_aib_outndrv_r78" value="aib_ndrv78_setting1" />
  <parameter name="enable_port_rx_fifo_full" value="0" />
  <parameter
     name="pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch4_src"
     value="cdr_clkin_scratch4_src_refclk_iqclk" />
  <parameter
     name="pma_adapt_adp_bist_errcount_rstn"
     value="radp_bist_errcount_rstn_0" />
  <parameter
     name="hssi_adapt_tx_hd_hssiadapt_pld_pcs_tx_clk_out_hz"
     value="322265625" />
  <parameter name="hssi_10g_rx_pcs_rxfifo_empty" value="empty_default" />
  <parameter
     name="hssi_krfec_rx_pcs_data_bit_reverse"
     value="data_bit_reverse_dis" />
  <parameter name="hssi_krfec_rx_pcs_pipeln_errtrap_loc" value="disable" />
  <parameter
     name="hssi_pldadapt_rx_hdpldadapt_sr_sr_testbus_sel"
     value="ssr_testbus" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_selflock"
     value="aib_dllstr_align_selflock_enable" />
  <parameter name="hssi_10g_tx_pcs_advanced_user_mode" value="disable" />
  <parameter name="hssi_pldadapt_rx_phcomp_rd_del" value="phcomp_rd_del2" />
  <parameter name="hssi_aibcr_rx_aib_rx_dcc_dft" value="aib_rx_dcc_dft_disable" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_speed_grade"
     value="e2" />
  <parameter name="pma_adapt_adp_ac_ctle_cal_win" value="radp_ac_ctle_cal_win_4" />
  <parameter name="hssi_adapt_rx_compin_sel" value="compin_master" />
  <parameter name="hssi_pldadapt_rx_sup_mode" value="user_mode" />
  <parameter name="hssi_tx_pld_pcs_interface_hd_g3pcs_sup_mode" value="user_mode" />
  <parameter name="hssi_pldadapt_rx_lpbk_mode" value="disable" />
  <parameter name="hssi_rx_pcs_pma_interface_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="enable_ports_pipe_sw" value="0" />
  <parameter name="hssi_pldadapt_rx_pipe_mode" value="disable_pipe" />
  <parameter name="hssi_10g_tx_pcs_txfifo_pfull" value="11" />
  <parameter name="l_std_tx_word_width" value="8" />
  <parameter name="hssi_pldadapt_tx_tx_datapath_tb_sel" value="cp_bond" />
  <parameter name="pma_cgb_xn_clock_source_sel" value="sel_cgb_loc" />
  <parameter name="hssi_rx_pld_pcs_interface_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_adapt_tx_powerdown_mode" value="powerup" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_dy_ctlsel"
     value="aib_rx_dcc_dy_ctlsel_setting0" />
  <parameter name="hssi_pldadapt_rx_asn_wait_for_pma_pcie_sw_done_cnt" value="64" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_fifo_mode_tx"
     value="reg_tx" />
  <parameter name="hssi_common_pcs_pma_interface_ppm_gen1_2_cnt" value="cnt_32k" />
  <parameter
     name="pma_tx_buf_duty_cycle_detector_cp_cal"
     value="dcd_cp_cal_disable" />
  <parameter name="hssi_rx_pcs_pma_interface_rx_prbs_mask" value="prbsmask128" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_dll_entest"
     value="aib_rx_dcc_dll_test_disable" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_st_dftmuxsel"
     value="aib_tx_dcc_st_dftmuxsel_setting0" />
  <parameter name="hssi_pldadapt_rx_duplex_mode" value="enable" />
  <parameter name="pma_rx_deser_rst_n_adapt_odi" value="no_rst_adapt_odi" />
  <parameter name="cdr_pll_disable_up_dn" value="normal_mode" />
  <parameter name="qsf_assignments_enable" value="1" />
  <parameter name="manual_rx_core_aib_bonding_mode" value="individual" />
  <parameter name="hssi_pipe_gen1_2_rvod_sel_d_val" value="0" />
  <parameter name="hssi_pldadapt_tx_ds_bypass_pipeln" value="ds_bypass_pipeln_dis" />
  <parameter name="loopback_tx_clk_sel" value="internal_clk" />
  <parameter name="hssi_adapt_tx_hip_mode" value="disable_hip" />
  <parameter name="pma_rx_buf_vcm_cal_i" value="4" />
  <parameter name="hssi_10g_rx_pcs_crcchk_bypass" value="crcchk_bypass_en" />
  <parameter name="hssi_krfec_rx_pcs_error_marking_en" value="err_mark_dis" />
  <parameter name="hssi_krfec_tx_pcs_tx_testbus_sel" value="overall" />
  <parameter name="pma_tx_ser_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_pldadapt_tx_fifo_mode" value="phase_comp" />
  <parameter name="hssi_rx_pcs_pma_interface_reconfig_settings" value="{}" />
  <parameter name="pma_tx_buf_pm_cr2_tx_path_speed_grade" value="e2" />
  <parameter name="hssi_pldadapt_rx_ds_last_chnl" value="ds_last_chnl" />
  <parameter name="cdr_pll_enable_idle_rx_channel_support" value="false" />
  <parameter name="hssi_adapt_rx_word_align_enable" value="enable" />
  <parameter name="pma_rx_buf_datarate_bps" value="10312500000" />
  <parameter
     name="pma_adapt_adp_pat_dlev_sign_avg_win"
     value="radp_pat_dlev_sign_avg_win_2x" />
  <parameter
     name="pma_adapt_adp_pat_spec_sign_avg_win"
     value="radp_pat_spec_sign_avg_win_256" />
  <parameter name="hssi_10g_rx_pcs_data_bit_reverse" value="data_bit_reverse_dis" />
  <parameter
     name="hssi_pldadapt_rx_hdpldadapt_aib_fabric_rx_sr_clk_in_hz"
     value="0" />
  <parameter name="cdr_pll_reference_clock_frequency" value="644531250" />
  <parameter name="pma_rx_buf_offset_rx_cal_en" value="rx_oc_dis" />
  <parameter name="hssi_adapt_tx_tx_fastbond_wren" value="wren_ds_del2_us_del2" />
  <parameter
     name="pma_adapt_adp_dfe_tap1_initial_value"
     value="radp_dfe_tap1_initial_value_0" />
  <parameter name="hssi_10g_tx_pcs_gbred_clken" value="gbred_clk_en" />
  <parameter
     name="hssi_aibnd_tx_aib_red_dirclkn_shiften"
     value="aib_red_dirclkn_shift_disable" />
  <parameter name="hssi_adapt_tx_fifo_stop_rd" value="rd_empty" />
  <parameter name="hssi_aibcr_tx_aib_outctrl_gr1" value="aib_outen1_setting1" />
  <parameter name="hssi_aibcr_tx_aib_outctrl_gr2" value="aib_outen2_setting1" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_st_new_dll"
     value="aib_tx_dcc_new_dll_setting0" />
  <parameter name="hssi_8g_rx_pcs_wait_cnt" value="0" />
  <parameter
     name="hssi_adapt_rx_rx_pld_8g_a1a2_k1k2_flag_polling_bypass"
     value="disable" />
  <parameter name="hssi_aibcr_tx_aib_outctrl_gr0" value="aib_outen0_setting1" />
  <parameter name="pma_cgb_powermode_ac_cgb" value="cgb_ac_off" />
  <parameter
     name="pma_cdr_refclk_pm_cr_tx_rx_scratch4_src"
     value="scratch4_power_down" />
  <parameter name="hssi_8g_rx_pcs_silicon_rev" value="14nm5bcr2eb" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_halfcode"
     value="aib_dllstr_align_halfcode_enable" />
  <parameter name="hssi_10g_rx_pcs_blksync_clken" value="blksync_clk_en" />
  <parameter name="hssi_10g_rx_pcs_pempty_flag_type" value="pempty_rd_side" />
  <parameter
     name="hssi_pldadapt_tx_hdpldadapt_pld_tx_clk2_rowclk_hz"
     value="644531250" />
  <parameter name="hssi_rx_pld_pcs_interface_hd_pcs10g_test_bus_mode" value="rx" />
  <parameter name="hssi_10g_rx_pcs_rx_signal_ok_sel" value="synchronized_ver" />
  <parameter
     name="hssi_aibcr_tx_aib_red_tx_shiften"
     value="aib_red_tx_shift_disable" />
  <parameter name="cdr_pll_uc_ro_cal_status" value="uc_ro_sta_off" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_sim_mode"
     value="disable" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_st_new_dll"
     value="aib_rx_dcc_new_dll_setting0" />
  <parameter name="pma_tx_buf_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
  <parameter name="pma_txpath_chnsequencer_pcie_gen" value="non_pcie" />
  <parameter name="cdr_pll_f_min_ref" value="25000000" />
  <parameter name="enh_low_latency_enable" value="0" />
  <parameter name="hssi_pipe_gen1_2_reconfig_settings" value="{}" />
  <parameter name="enh_tx_crcerr_enable" value="0" />
  <parameter
     name="pma_adapt_sequencer_rx_path_rstn_overrideb"
     value="use_sequencer" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs10g_low_latency_en_rx"
     value="disable" />
  <parameter name="hssi_adapt_tx_tx_rev_lpbk" value="disable" />
  <parameter name="enable_advanced_user_mode" value="0" />
  <parameter name="hssi_10g_rx_pcs_rand_clken" value="rand_clk_en" />
  <parameter name="cdr_pll_out_freq" value="5156250000" />
  <parameter name="hssi_krfec_tx_pcs_sup_mode" value="user_mode" />
  <parameter name="hssi_pldadapt_tx_hdpldadapt_csr_clk_hz" value="0" />
  <parameter name="hssi_pldadapt_tx_tx_osc_clock_setting" value="osc_clk_div_by1" />
  <parameter name="pma_rx_dfe_oc_sa_odie" value="0" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_byp_iocsr_unused"
     value="aib_rx_dcc_byp_disable_iocsr_unused" />
  <parameter name="usr_tx_dv_mode" value="enable" />
  <parameter name="rcfg_debug" value="0" />
  <parameter name="pma_rx_dfe_oc_sa_odio" value="0" />
  <parameter
     name="pma_tx_buf_powermode_dc_tx_vod_no_jitcomp"
     value="powerdown_tx_vod_no_jitcomp" />
  <parameter name="std_tx_bitrev_enable" value="0" />
  <parameter name="cdr_pll_clk180_dfe_tfall_adj" value="clk180_dfe_tf0" />
  <parameter name="pma_rx_dfe_atb_select" value="atb_disable" />
  <parameter
     name="hssi_adapt_tx_fsr_hip_fsr_in_bit0_rst_val"
     value="reset_to_one_hfsrin0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_shared_fifo_width_tx"
     value="single_tx" />
  <parameter name="pma_rx_deser_clkdiv_source" value="vco_bypass_normal" />
  <parameter name="std_tx_polinv_enable" value="0" />
  <parameter name="cdr_pll_chgpmp_current_pfd" value="cp_current_pfd_setting2" />
  <parameter name="hssi_adapt_rx_asn_wait_for_pma_pcie_sw_done_cnt" value="32" />
  <parameter
     name="hssi_gen3_rx_pcs_rx_ins_del_one_skip"
     value="ins_del_one_skip_dis" />
  <parameter name="pma_adapt_adp_reserved" value="0" />
  <parameter name="hssi_pldadapt_tx_hrdrst_rst_sm_dis" value="enable_tx_rst_sm" />
  <parameter name="pma_tx_buf_xtx_path_xcgb_tx_ucontrol_en" value="disable" />
  <parameter name="hssi_aibnd_rx_aib_red_shift_en" value="aib_red_shift_disable" />
  <parameter name="cdr_pll_chgpmp_current_up_pd" value="cp_current_pd_up_setting3" />
  <parameter name="tx_pcs_bonding_clock_network" value="dedicated" />
  <parameter
     name="pma_txpath_chnsequencer_txpath_chnseq_wakeup_bypass"
     value="bypass_off" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_st_dly_pst"
     value="aib_tx_dcc_st_dly_pst_setting0" />
  <parameter name="enh_pld_pcs_width" value="66" />
  <parameter name="hssi_pldadapt_rx_sclk_sel" value="sclk1_rowclk" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_sup_mode"
     value="user_mode" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs10g_pma_dw_tx"
     value="pma_32b_tx" />
  <parameter name="pma_rx_buf_bypass_ctle_rf_cal" value="use_dprio_rfcal" />
  <parameter name="pma_cgb_datarate_bps" value="10312500000" />
  <parameter
     name="hssi_rx_pcs_pma_interface_pldif_datawidth_mode"
     value="pldif_data_10bit" />
  <parameter name="pma_tx_buf_prot_mode" value="basic_tx" />
  <parameter name="manual_tx_hssi_aib_bonding_mode" value="individual" />
  <parameter
     name="hssi_10g_rx_pcs_ber_bit_err_total_cnt"
     value="bit_err_total_cnt_10g" />
  <parameter name="manual_rx_hssi_aib_bonding_comp_cnt" value="0" />
  <parameter name="pma_tx_buf_initial_settings" value="true" />
  <parameter name="pma_rx_dfe_oc_sa_cdrne_sgn" value="oc_sa_cdrne_sgn_0" />
  <parameter name="enable_hip" value="0" />
  <parameter name="hssi_common_pcs_pma_interface_cdr_control" value="dis_cdr_ctrl" />
  <parameter name="pma_rx_dfe_pdb_edge_pst_h1" value="cdr_pst_h1_disable" />
  <parameter name="cdr_pll_f_max_m_counter" value="1" />
  <parameter name="pma_rx_deser_datarate_bps" value="10312500000" />
  <parameter name="hssi_8g_rx_pcs_clock_gate_sw_wa" value="en_sw_wa_clk_gating" />
  <parameter name="cdr_pll_tx_pll_prot_mode" value="txpll_unused" />
  <parameter name="pma_rx_dfe_h1edge_bti_en" value="h1edge_bti_disable" />
  <parameter name="pma_adapt_adp_pcie_eqz" value="radp_pcie_eqz_non_pcie_mode" />
  <parameter name="hssi_adapt_rx_aib_lpbk_mode" value="disable" />
  <parameter
     name="pma_adapt_adp_vga_ctle_low_limit"
     value="radp_vga_ctle_low_limit_0" />
  <parameter
     name="hssi_pldadapt_tx_aib_clk1_sel"
     value="aib_clk1_pld_pcs_tx_clk_out" />
  <parameter name="hssi_8g_rx_pcs_wa_pd_polarity" value="dont_care_both_pol" />
  <parameter name="hssi_8g_rx_pcs_wa_boundary_lock_ctrl" value="sync_sm" />
  <parameter name="pma_cgb_powermode_dc_cgb" value="powerdown_cgb" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_lpbk_en"
     value="disable" />
  <parameter name="hssi_pipe_gen1_2_hip_mode" value="dis_hip" />
  <parameter name="pma_tx_buf_optimal" value="true" />
  <parameter
     name="pma_adapt_adp_frame_odi_sel"
     value="radp_frame_odi_sel_deser_err" />
  <parameter name="pma_rx_deser_powermode_dc_deser_bs" value="powerdown_deser_bs" />
  <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
  <parameter name="pma_rx_odi_phase_steps_64_vs_128" value="phase_steps_64" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode"
     value="tx_rx_pair_enabled" />
  <parameter
     name="hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel"
     value="teng_clk_out" />
  <parameter
     name="cdr_pll_pm_cr2_rx_path_cdr_clock_enable"
     value="cdr_clock_disable" />
  <parameter name="pma_pcie_gen_switch_rx_pci_switch_dly" value="0" />
  <parameter name="device" value="1SG165HU2F50E2VG" />
  <parameter name="hssi_aibcr_rx_aib_outctrl_gr3" value="aib_outen3_setting1" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_tile_type" value="h" />
  <parameter name="rx_fifo_control_del" value="0" />
  <parameter name="hssi_pldadapt_rx_osc_clk_scg_en" value="disable" />
  <parameter
     name="hssi_pldadapt_tx_fsr_hip_fsr_in_bit0_rst_val"
     value="reset_to_one_hfsrin0" />
  <parameter name="hssi_8g_rx_pcs_prot_mode" value="disabled_prot_mode" />
  <parameter name="hssi_10g_rx_pcs_master_clk_sel" value="master_rx_pma_clk" />
  <parameter name="hssi_aibcr_rx_aib_outctrl_gr2" value="aib_outen2_setting1" />
  <parameter name="hssi_aibcr_rx_aib_outctrl_gr1" value="aib_outen1_setting1" />
  <parameter name="pma_adapt_adp_odi_bit_sel" value="radp_odi_bit_sel_all_bits" />
  <parameter name="pma_tx_buf_dft_sel" value="dft_disabled" />
  <parameter name="hssi_pldadapt_tx_ctrl_plane_bonding" value="individual" />
  <parameter name="hssi_aibcr_rx_aib_outctrl_gr0" value="aib_outen0_setting1" />
  <parameter name="hssi_tx_pcs_pma_interface_sqwgen_clken" value="sqwgen_clk_dis" />
  <parameter name="l_enable_channel_bonding" value="0" />
  <parameter name="hssi_common_pcs_pma_interface_sup_mode" value="user_mode" />
  <parameter name="pma_rx_buf_offset_cancellation_coarse" value="coarse_setting_0" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pcs_tx_pwr_scaling_clk"
     value="pma_tx_clk" />
  <parameter name="set_cdr_refclk_freq" value="644.53125" />
  <parameter name="pma_rx_buf_ctle_rf_cal" value="3" />
  <parameter
     name="cannot_gen_exdesign_msg"
     value="Design example cannot be generated for the current configuration. Please check under Design Example tab and system message below for more detailed information." />
  <parameter name="hssi_pldadapt_tx_gb_tx_odwidth" value="odwidth_32" />
  <parameter name="hip_channels" value="x1" />
  <parameter name="hssi_10g_tx_pcs_dispgen_pipeln" value="dispgen_pipeln_dis" />
  <parameter name="pma_tx_sequencer_tx_path_rstn_overrideb" value="use_sequencer" />
  <parameter name="rcfg_iface_enable" value="0" />
  <parameter name="hssi_8g_tx_pcs_clock_gate_fiford" value="en_fiford_clk_gating" />
  <parameter name="hssi_10g_rx_pcs_blksync_bitslip_wait_cnt" value="1" />
  <parameter name="use_rx_clkout2" value="0" />
  <parameter
     name="hssi_adapt_tx_fsr_hip_fsr_out_bit0_rst_val"
     value="reset_to_one_hfsrout0" />
  <parameter name="pma_adapt_adp_frame_en" value="radp_frame_en_disable" />
  <parameter name="hssi_adapt_rx_loopback_mode" value="loopback_disable" />
  <parameter name="xcvr_speedgrade_no_temp" value="2" />
  <parameter name="l_adapt_mode_dfe" value="0" />
  <parameter name="hssi_fifo_rx_pcs_double_read_mode" value="double_read_dis" />
  <parameter name="enable_background_cal" value="0" />
  <parameter name="hssi_10g_tx_pcs_gb_pipeln_bypass" value="disable" />
  <parameter name="l_tx_pma_optimal_atom_settings" value="true" />
  <parameter name="hssi_krfec_rx_pcs_low_latency_en" value="disable" />
  <parameter name="hssi_avmm1_if_pcs_cal_done" value="avmm1_cal_done_deassert" />
  <parameter
     name="hssi_common_pcs_pma_interface_free_run_clk_enable"
     value="false" />
  <parameter name="hssi_10g_rx_pcs_fifo_double_read" value="fifo_double_read_dis" />
  <parameter name="hssi_adapt_tx_ds_bypass_pipeln" value="ds_bypass_pipeln_dis" />
  <parameter name="pma_rx_buf_dfe_err_cal_en" value="dfe_err_cal_enb" />
  <parameter name="hssi_pldadapt_tx_hrdrst_user_ctl_en" value="disable" />
  <parameter name="hssi_pldadapt_tx_hdpldadapt_pld_sclk2_rowclk_hz" value="0" />
  <parameter
     name="hssi_10g_tx_pcs_distdwn_bypass_pipeln"
     value="distdwn_bypass_pipeln_dis" />
  <parameter name="hssi_rx_pld_pcs_interface_hd_pcs8g_hip_mode" value="disable" />
  <parameter
     name="hssi_adapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass"
     value="disable" />
  <parameter name="hssi_10g_rx_pcs_blksync_bitslip_type" value="bitslip_comb" />
  <parameter
     name="hssi_8g_rx_pcs_clock_gate_sw_rm_rd"
     value="en_sw_rm_rdclk_gating" />
  <parameter name="hssi_avmm1_if_calibration_type" value="one_time" />
  <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
  <parameter name="hssi_10g_tx_pcs_ctrl_plane_bonding" value="individual" />
  <parameter
     name="pma_tx_buf_duty_cycle_detector_sa_cal"
     value="dcd_sa_cal_disable" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value"
     value="0" />
  <parameter name="pma_tx_buf_compensation_en" value="enable" />
  <parameter name="hssi_10g_rx_pcs_rdfifo_clken" value="rdfifo_clk_en" />
  <parameter name="hssi_adapt_rx_txeq_clk_scg_en" value="enable" />
  <parameter name="hssi_aibcr_tx_dfd_dll_dcc_en" value="disable_dfd" />
  <parameter name="std_tx_byte_ser_mode" value="Disabled" />
  <parameter name="hssi_8g_tx_pcs_prot_mode" value="disabled_prot_mode" />
  <parameter name="pma_tx_ser_sup_mode" value="user_mode" />
  <parameter name="pma_tx_buf_tx_powerdown" value="normal_tx_on" />
  <parameter name="hssi_pldadapt_tx_tx_fastbond_wren" value="wren_ds_fast_us_fast" />
  <parameter
     name="delay_measurement_clkout2_sel"
     value="clock_delay_measurement_clkout" />
  <parameter name="hssi_aibnd_tx_aib_datasel_gr3" value="aib_datasel3_setting1" />
  <parameter name="hssi_aibnd_tx_aib_datasel_gr2" value="aib_datasel2_setting1" />
  <parameter name="rcfg_profile_cnt" value="1" />
  <parameter name="hssi_10g_rx_pcs_rx_scrm_width" value="bit64" />
  <parameter name="hssi_aibnd_tx_aib_datasel_gr1" value="aib_datasel1_setting0" />
  <parameter name="hssi_aibnd_tx_aib_datasel_gr0" value="aib_datasel0_setting0" />
  <parameter
     name="hssi_aibnd_tx_aib_red_rx_shiften"
     value="aib_red_rx_shift_disable" />
  <parameter name="hssi_pldadapt_rx_rx_fifo_read_latency_adjust" value="disable" />
  <parameter
     name="pma_adapt_adp_dfe_onetime_threshold"
     value="radp_dfe_onetime_threshold_2048" />
  <parameter name="cdr_pll_lck2ref_delay_control" value="lck2ref_delay_2" />
  <parameter name="hssi_pldadapt_rx_reconfig_settings" value="{}" />
  <parameter
     name="pma_cdr_refclk_pm_cr_tx_rx_scratch2_src"
     value="scratch2_power_down" />
  <parameter name="cdr_pll_cdr_odi_select" value="sel_cdr" />
  <parameter name="hssi_gen3_rx_pcs_sup_mode" value="user_mode" />
  <parameter name="hssi_rx_pcs_pma_interface_rx_prbs_mode" value="teng_mode" />
  <parameter name="pma_rx_buf_prot_mode" value="basic_rx" />
  <parameter
     name="hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en"
     value="delay2_clk_disable" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_pcs_pair_ac_pwr_uw_per_mhz"
     value="0" />
  <parameter name="hssi_8g_tx_pcs_auto_speed_nego_gen2" value="dis_asn_g2" />
  <parameter name="hssi_pldadapt_tx_pld_clk1_delay_en" value="enable" />
  <parameter name="hssi_pipe_gen1_2_rpre_emph_e_val" value="0" />
  <parameter name="hssi_adapt_rx_hip_mode" value="disable_hip" />
  <parameter
     name="hssi_rx_pld_pcs_interface_hd_pcs_channel_hrdrstctl_en"
     value="disable" />
  <parameter name="l_num_tx_digitalreset" value="1" />
  <parameter name="hssi_adapt_rx_asn_en" value="disable" />
  <parameter name="hssi_fifo_rx_pcs_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="pma_adapt_adp_odi_dlev_sel" value="radp_odi_dlev_sel_0" />
  <parameter name="manual_pcs_bonding_comp_cnt" value="0" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control"
     value="uhsif_dft_up_val_0" />
  <parameter name="hssi_8g_rx_pcs_wa_pd_data" value="0" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_st_rst"
     value="aib_tx_dcc_st_rst_setting0" />
  <parameter name="rcfg_separate_avmm_busy" value="0" />
  <parameter name="hssi_aibnd_tx_aib_iinasyncen" value="aib_inasyncen_setting2" />
  <parameter name="hssi_adapt_rx_rx_fifo_read_latency_adjust" value="disable" />
  <parameter name="hssi_8g_rx_pcs_wa_pld_controlled" value="dis_pld_ctrl" />
  <parameter
     name="hssi_8g_rx_pcs_ctrl_plane_bonding_consumption"
     value="individual" />
  <parameter name="hssi_10g_tx_pcs_distup_master" value="distup_master_en" />
  <parameter name="rx_pma_div_clkout_divider" value="33" />
  <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
  <parameter name="enable_port_rx_fifo_latency_adj_ena" value="0" />
  <parameter name="hssi_10g_rx_pcs_clr_errblk_cnt_en" value="enable" />
  <parameter
     name="pma_adapt_adp_pat_dlev_sign_force"
     value="radp_pat_dlev_sign_force_determined_by_cram" />
  <parameter name="cdr_pll_optimal" value="true" />
  <parameter name="pma_tx_buf_duty_cycle_setting" value="dcc_t32" />
  <parameter
     name="hssi_pldadapt_tx_tx_pld_8g_tx_boundary_sel_polling_bypass"
     value="disable" />
  <parameter name="hssi_pldadapt_tx_hip_osc_clk_scg_en" value="enable" />
  <parameter
     name="pma_reset_sequencer_rx_path_rstn_overrideb"
     value="use_sequencer" />
  <parameter name="hssi_adapt_rx_slv_asn_en" value="disable" />
  <parameter name="pma_adapt_adp_pcie_adp_bypass" value="radp_pcie_adp_bypass_no" />
  <parameter name="pma_rx_dfe_oc_sa_cdrpo_sgn" value="oc_sa_cdrpo_sgn_0" />
  <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_cont_cal_iocsr_unused"
     value="aib_tx_dcc_cal_single_iocsr_unused" />
  <parameter name="pma_rx_odi_vert_threshold" value="vert_0" />
  <parameter name="hssi_tx_pld_pcs_interface_reconfig_settings" value="{}" />
  <parameter
     name="pma_adapt_adp_ac_ctle_initial_value"
     value="radp_ac_ctle_initial_value_8" />
  <parameter name="pma_rx_buf_loopback_modes" value="lpbk_disable" />
  <parameter name="cdr_pll_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="pma_cgb_cgb_bti_en" value="cgb_bti_disable" />
  <parameter
     name="hssi_common_pcs_pma_interface_ppm_deassert_early"
     value="deassert_early_dis" />
  <parameter name="hssi_10g_rx_pcs_frmsync_mfrm_length" value="2048" />
  <parameter name="hssi_adapt_tx_fifo_rd_clk_scg_en" value="disable" />
  <parameter name="pma_rx_deser_sd_clk" value="sd_clk_disabled" />
  <parameter name="osc_clk_divider" value="1" />
  <parameter name="l_enable_std_pipe" value="0" />
  <parameter name="hssi_adapt_rx_align_del" value="align_del_dis" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_dll_dft_sel"
     value="aib_tx_dcc_dll_dft_sel_setting0" />
  <parameter name="hssi_common_pcs_pma_interface_cp_up_mstr" value="true" />
  <parameter name="pma_tx_ser_ser_dftppm_clkselect" value="aib_dftppm" />
  <parameter name="enh_rx_descram_enable" value="1" />
  <parameter
     name="hssi_avmm1_if_hssiadapt_sr_sr_free_run_div_clk"
     value="out_of_reset_sync" />
  <parameter name="cdr_pll_f_min_vco" value="7000000000" />
  <parameter name="enable_port_tx_fifo_empty" value="0" />
  <parameter name="hssi_common_pcs_pma_interface_early_eios_counter" value="0" />
  <parameter name="hssi_adapt_rx_indv" value="indv_en" />
  <parameter name="hssi_tx_pld_pcs_interface_hd_pcs10g_lpbk_en" value="disable" />
  <parameter name="hssi_aibnd_tx_aib_outctrl_gr3" value="aib_outen3_setting1" />
  <parameter name="hssi_aibnd_tx_aib_outctrl_gr2" value="aib_outen2_setting1" />
  <parameter name="rcfg_files_as_common_package" value="0" />
  <parameter name="hssi_aibnd_tx_aib_outctrl_gr1" value="aib_outen1_setting1" />
  <parameter name="hssi_aibnd_tx_aib_outctrl_gr0" value="aib_outen0_setting1" />
  <parameter
     name="pma_rx_buf_pm_cr2_tx_rx_pcie_gen_bitwidth"
     value="pcie_gen3_32b" />
  <parameter name="suppress_design_example_messages" value="0" />
  <parameter name="hssi_aibnd_rx_powermode_ac" value="rxdatapath_high_speed_pwr" />
  <parameter
     name="hssi_aibnd_tx_aib_red_pout_shiften"
     value="aib_red_pout_shift_disable" />
  <parameter name="pma_tx_buf_lst" value="atb_disabled" />
  <parameter name="disable_bg_cal" value="0" />
  <parameter name="pma_cgb_power_rail_er" value="1030" />
  <parameter name="hssi_pldadapt_tx_pld_clk1_inv_en" value="disable" />
  <parameter name="cdr_pll_vco_bypass" value="false" />
  <parameter
     name="hssi_aibnd_rx_aib_dllstr_align_st_core_up_prgmnvrt"
     value="aib_dllstr_align_st_core_up_prgmnvrt_setting0" />
  <parameter name="hssi_pipe_gen3_test_out_sel" value="disable_test_out" />
  <parameter name="hssi_pldadapt_rx_powermode_dc" value="powerdown" />
  <parameter
     name="hssi_adapt_rx_rx_rmfflag_stretch_num_stages"
     value="rmfflag_two_stage" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_dcc_dll_dft_sel"
     value="aib_dllstr_align_dcc_dll_dft_sel_setting0" />
  <parameter name="enh_tx_crcgen_enable" value="0" />
  <parameter
     name="hssi_8g_tx_pcs_ctrl_plane_bonding_consumption"
     value="individual" />
  <parameter name="hssi_adapt_tx_free_run_div_clk" value="out_of_reset_sync" />
  <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
  <parameter name="hssi_pldadapt_tx_chnl_bonding" value="disable" />
  <parameter name="rx_clkout2_sel" value="pma_div_clkout" />
  <parameter name="hssi_pipe_gen1_2_tx_pipe_enable" value="dis_pipe_tx" />
  <parameter name="hssi_aibnd_tx_aib_iinclken" value="aib_inclken_setting3" />
  <parameter name="enable_background_cal_gui" value="0" />
  <parameter name="pma_rx_buf_ctle_oc_sign" value="add_i_2_p_eq" />
  <parameter name="hssi_aibcr_rx_aib_datasel_gr2" value="aib_datasel2_setting1" />
  <parameter name="pma_rx_sd_sd_output_off" value="clk_divrx_2" />
  <parameter name="hssi_aibcr_rx_aib_datasel_gr1" value="aib_datasel1_setting0" />
  <parameter name="hssi_aibcr_rx_aib_datasel_gr0" value="aib_datasel0_setting0" />
  <parameter name="hssi_aibnd_tx_dft_hssitestip_dll_dcc_en" value="disable_dft" />
  <parameter name="hssi_10g_rx_pcs_ctrl_bit_reverse" value="ctrl_bit_reverse_en" />
  <parameter name="hssi_adapt_rx_fifo_width" value="fifo_double_width" />
  <parameter name="cdr_pll_prot_mode" value="basic_rx" />
  <parameter name="hssi_adapt_rx_free_run_div_clk" value="out_of_reset_sync" />
  <parameter name="pma_rx_dfe_oc_sa_vrefe" value="0" />
  <parameter name="hssi_adapt_rx_us_master" value="us_master_en" />
  <parameter
     name="hssi_8g_rx_pcs_clock_gate_sw_rm_wr"
     value="en_sw_rm_wrclk_gating" />
  <parameter name="enh_rx_blksync_enable" value="1" />
  <parameter name="hssi_avmm1_if_hssiadapt_avmm_clk_dcg_en" value="disable" />
  <parameter name="pma_rx_dfe_oc_sa_vrefo" value="0" />
  <parameter name="enable_port_rx_fifo_rd_en" value="0" />
  <parameter name="hssi_adapt_rx_rxfifo_empty" value="empty_default" />
  <parameter name="cdr_pll_primary_use" value="cdr" />
  <parameter name="hssi_aibcr_rx_aib_rx_dcc_cont_cal" value="aib_rx_dcc_cal_cont" />
  <parameter
     name="hssi_aibnd_tx_aib_tx_dcc_st_lockreq_muxsel"
     value="aib_tx_dcc_st_lockreq_muxsel_setting0" />
  <parameter name="hssi_tx_pld_pcs_interface_hd_pcs_channel_hclk_clk_hz" value="0" />
  <parameter name="hssi_adapt_rx_hrdrst_rx_osc_clk_scg_en" value="disable" />
  <parameter name="hssi_10g_rx_pcs_ber_xus_timer_window" value="19530" />
  <parameter
     name="hssi_pldadapt_rx_rx_pld_pma_eye_monitor_polling_bypass"
     value="disable" />
  <parameter name="hssi_adapt_tx_hd_hssiadapt_aib_hssi_tx_sr_clk_in_hz" value="0" />
  <parameter name="pma_adapt_adp_dlev_onetime" value="radp_dlev_onetime_disable" />
  <parameter name="enable_port_rx_enh_frame" value="0" />
  <parameter name="hssi_10g_tx_pcs_pseudo_random" value="all_0" />
  <parameter name="hssi_pipe_gen3_elecidle_delay_g3" value="0" />
  <parameter name="hssi_adapt_tx_hd_hssiadapt_hip_aib_txeq_clk_out_hz" value="0" />
  <parameter name="hssi_pldadapt_rx_ds_bypass_pipeln" value="ds_bypass_pipeln_dis" />
  <parameter name="hssi_10g_tx_pcs_frmgen_bypass" value="frmgen_bypass_en" />
  <parameter name="pma_rx_buf_vcm_sel_vccref" value="5" />
  <parameter
     name="hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window"
     value="uhsif_dzt_obr_win_16" />
  <parameter name="hssi_common_pcs_pma_interface_asn_clk_enable" value="false" />
  <parameter name="pma_rx_buf_sel_vcm_ctle" value="vocm_eq_gndref" />
  <parameter name="manual_tx_hssi_aib_bonding_comp_cnt" value="0" />
  <parameter
     name="hssi_aibcr_rx_aib_rx_dcc_st_core_up_prgmnvrt"
     value="aib_rx_dcc_st_core_up_prgmnvrt_setting0" />
  <parameter name="hssi_adapt_tx_qpi_sr_enable" value="enable" />
  <parameter name="pma_rx_sd_sd_output_on" value="force_sd_output_on" />
  <parameter
     name="hssi_avmm1_if_pldadapt_avmm_testbus_sel"
     value="avmm1_transfer_testbus" />
  <parameter name="pma_rx_buf_rx_afe_oc_mode" value="normal_op" />
  <parameter name="hssi_aibnd_rx_powermode_dc" value="powerup" />
  <parameter name="hssi_gen3_rx_pcs_rx_force_balign" value="dis_force_balign" />
  <parameter name="hssi_pldadapt_rx_fifo_rd_clk_ins_sm_scg_en" value="enable" />
  <parameter name="set_prbs_soft_logic_enable" value="0" />
  <parameter name="hssi_10g_rx_pcs_force_align" value="force_align_dis" />
  <parameter name="cdr_pll_chgpmp_vccreg" value="vreg_fw0" />
  <parameter
     name="pma_adapt_adp_odi_count_threshold"
     value="radp_odi_count_threshold_1e6" />
  <parameter
     name="pma_cdr_refclk_pm_cr_tx_rx_scratch0_src"
     value="scratch0_power_down" />
  <parameter name="hssi_10g_tx_pcs_pseudo_seed_a" value="288230376151711743" />
  <parameter name="can_gen_exdesign_basic_std" value="1" />
  <parameter name="hssi_pldadapt_rx_hdpldadapt_speed_grade" value="dash_2" />
  <parameter name="hssi_10g_tx_pcs_pseudo_seed_b" value="288230376151711743" />
  <parameter name="hssi_adapt_rx_powerdown_mode" value="powerup" />
  <parameter name="hssi_adapt_tx_comp_cnt" value="0" />
  <parameter
     name="hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en"
     value="uhsif_lpbk_dis" />
  <parameter name="pma_rx_odi_enable_cdr_lpbk" value="disable_lpbk" />
  <parameter name="hssi_pldadapt_tx_txfifo_empty" value="empty_default" />
  <parameter name="l_std_rx_field_width" value="16" />
  <parameter name="pma_rx_sd_link" value="sr" />
  <parameter name="hssi_pldadapt_rx_rx_datapath_tb_sel" value="cp_bond" />
  <parameter name="pma_rx_dfe_prot_mode" value="basic_rx" />
  <parameter name="pma_cgb_scratch2_x1_clock_src" value="not_used" />
  <parameter name="hssi_aibcr_rx_aib_iinasyncen" value="aib_inasyncen_setting2" />
  <parameter name="rx_fifo_pempty" value="2" />
  <parameter name="hssi_aibnd_tx_aib_outndrv_r56" value="aib_ndrv56_setting1" />
  <parameter name="hssi_8g_rx_pcs_pcs_bypass" value="dis_pcs_bypass" />
  <parameter name="hssi_8g_tx_pcs_silicon_rev" value="14nm5bcr2eb" />
  <parameter name="hssi_adapt_rx_ds_bypass_pipeln" value="ds_bypass_pipeln_dis" />
  <parameter name="hssi_avmm1_if_pldadapt_read_blocking_enable" value="enable" />
  <parameter name="pma_txpath_chnsequencer_txpath_chnseq_stage_select" value="0" />
  <parameter name="hssi_pldadapt_rx_rx_fifo_write_ctrl" value="blklock_ignore" />
  <parameter name="tx_pma_pre_emp_sign_pre_tap_1t" value="negative" />
  <parameter name="hssi_10g_tx_pcs_tx_sm_bypass" value="tx_sm_bypass_dis" />
  <parameter name="l_enable_tx_enh" value="1" />
  <parameter name="hssi_pipe_gen3_silicon_rev" value="14nm5bcr2eb" />
  <parameter
     name="hssi_pldadapt_rx_fifo_wr_clk_sel"
     value="fifo_wr_clk_rx_transfer_clk" />
  <parameter name="hssi_pldadapt_tx_tx_fifo_write_latency_adjust" value="disable" />
  <parameter name="pma_rx_buf_rx_ltr_load_init" value="rx_load_original" />
  <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
  <parameter name="hssi_10g_tx_pcs_rdfifo_clken" value="rdfifo_clk_en" />
  <parameter name="cdr_pll_uc_ro_cal" value="uc_ro_cal_off" />
  <parameter
     name="hssi_pldadapt_rx_hdpldadapt_pld_rx_clk1_rowclk_hz"
     value="156250000" />
  <parameter
     name="cdr_pll_pm_cr2_tx_rx_uc_dyn_reconfig"
     value="uc_dyn_reconfig_off" />
  <parameter name="enable_port_tx_dll_lock" value="0" />
  <parameter name="hssi_avmm1_if_hssiadapt_uc_blocking_enable" value="enable" />
  <parameter
     name="hssi_rx_pcs_pma_interface_rx_static_polarity_inversion"
     value="rx_stat_polinv_dis" />
  <parameter name="hssi_krfec_tx_pcs_transmit_order" value="transmit_lsb" />
  <parameter name="hssi_10g_tx_pcs_crcgen_inv" value="crcgen_inv_en" />
  <parameter name="l_enable_pcs_channel" value="1" />
  <parameter name="hssi_10g_rx_pcs_rxfifo_pempty" value="2" />
  <parameter name="set_enable_eios_rx_protect" value="0" />
  <parameter name="channel_type" value="GX" />
  <parameter
     name="hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_lpbk_en"
     value="disable" />
  <parameter name="hssi_aibnd_rx_dft_hssitestip_dll_dcc_en" value="disable_dft" />
  <parameter name="pma_tx_ser_prot_mode" value="basic_tx" />
  <parameter name="hssi_aibcr_rx_aib_outndrv_r78" value="aib_ndrv78_setting1" />
  <parameter
     name="pma_adapt_adp_dc_ctle_mode0_win_size"
     value="radp_dc_ctle_mode0_win_size_4_taps" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_st_rst"
     value="aib_dllstr_align_st_rst_setting0" />
  <parameter name="pma_rx_dfe_pdb" value="dfe_enable" />
  <parameter name="hssi_aibnd_tx_aib_outndrv_r34" value="aib_ndrv34_setting1" />
  <parameter name="hssi_adapt_tx_tx_usertest_sel" value="enable" />
  <parameter name="pma_adapt_adp_dlev_en" value="radp_dlev_en_disable" />
  <parameter name="pma_rx_buf_pm_cr2_rx_path_power_rail_eht" value="0" />
  <parameter name="enable_rcfg_tx_digitalreset_release_ctrl" value="0" />
  <parameter name="hssi_pldadapt_tx_tx_fifo_power_mode" value="full_width_ps_dw" />
  <parameter name="hssi_adapt_tx_hd_hssiadapt_hip_aib_clk_hz" value="0" />
  <parameter name="hssi_adapt_rx_asn_wait_for_clock_gate_cnt" value="32" />
  <parameter name="hssi_pldadapt_rx_hrdrst_dll_lock_bypass" value="disable" />
  <parameter
     name="hssi_aibcr_tx_aib_dllstr_align_st_lockreq_muxsel"
     value="aib_dllstr_align_st_lockreq_muxsel_setting0" />
  <parameter name="hssi_aibnd_tx_aib_tx_dcc_cont_cal" value="aib_tx_dcc_cal_cont" />
  <parameter name="dbg_user_identifier" value="0" />
  <parameter name="pma_rx_buf_eq_cdgen_sel" value="eq_cdgen_2" />
  <parameter name="pcs_direct_width" value="8" />
  <parameter
     name="hssi_adapt_tx_txqpi_pulldn_rst_val"
     value="reset_to_zero_txqpid" />
  <parameter name="support_mode" value="user_mode" />
  <generatedFiles>
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_arbiter.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\altera_std_synchronizer_nocut.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_resync_std.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_reset_counter_s10.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\altera_xcvr_native_s10_functions_h.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\s10_avmm_h.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_avmm_csr.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_prbs_accum.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_odi_accel.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_rcfg_arb.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_early_spd_chng_s10_htile.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_anlg_reset_seq.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_dig_reset_seq.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_reset_seq.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_anlg_reset_seq_wrapper.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_re_cal_chnl.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_pcie_rx_eios_prot.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_rx_maib_wa.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\plain_files.txt"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\rcfg_timing_db\alt_usxgmii_phy_hssi_pldadapt_rx_rcfg_settings_x6s27ia.json"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\rcfg_timing_db\alt_usxgmii_phy_hssi_pldadapt_tx_rcfg_settings_x6s27ia.json"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_usxgmii_phy_ip_parameters_x6s27ia.tcl"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\reconfig\alt_mge_phy_reconfig_parameters_CFG0.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\reconfig\alt_mge_phy_reconfig_parameters_CFG0.h"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\reconfig\alt_mge_phy_reconfig_parameters_CFG0.mif"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\docs\alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia_parameters.csv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\docs\alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia_add_hdl_instance_example.tcl"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia.sdc"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_helper_functions_x6s27ia.tcl"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_global_constraints_x6s27ia.sdc"
       attributes="NO_SDC_PROMOTION" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_re_cal_chnl_x6s27ia.sdc"
       attributes="NO_SDC_PROMOTION" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_rcfg_opt_logic_x6s27ia.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\docs\alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia_overrides_example.tcl"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\docs\alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia.ip"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_arbiter.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\altera_std_synchronizer_nocut.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_resync_std.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_reset_counter_s10.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\altera_xcvr_native_s10_functions_h.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\s10_avmm_h.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_avmm_csr.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_prbs_accum.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_odi_accel.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_rcfg_arb.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_early_spd_chng_s10_htile.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_anlg_reset_seq.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_dig_reset_seq.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_reset_seq.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_anlg_reset_seq_wrapper.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_re_cal_chnl.v"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_pcie_rx_eios_prot.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_rx_maib_wa.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\plain_files.txt"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\rcfg_timing_db\alt_usxgmii_phy_hssi_pldadapt_rx_rcfg_settings_x6s27ia.json"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\rcfg_timing_db\alt_usxgmii_phy_hssi_pldadapt_tx_rcfg_settings_x6s27ia.json"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_usxgmii_phy_ip_parameters_x6s27ia.tcl"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\reconfig\alt_mge_phy_reconfig_parameters_CFG0.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\reconfig\alt_mge_phy_reconfig_parameters_CFG0.h"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\reconfig\alt_mge_phy_reconfig_parameters_CFG0.mif"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\docs\alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia_parameters.csv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\docs\alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia_add_hdl_instance_example.tcl"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia.sdc"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_helper_functions_x6s27ia.tcl"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_global_constraints_x6s27ia.sdc"
       attributes="NO_SDC_PROMOTION" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_re_cal_chnl_x6s27ia.sdc"
       attributes="NO_SDC_PROMOTION" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\alt_xcvr_native_rcfg_opt_logic_x6s27ia.sv"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\docs\alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia_overrides_example.tcl"
       attributes="" />
   <file
       path="C:\Users\mklee\AppData\Local\Temp\alt8290_6148029088922141087.dir\0002_alt_em10g32_0_gen\rtl\phy\alt_usxgmii_phy\altera_xcvr_native_s10_htile_1921\synth\docs\alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia.ip"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="J:/programme/quartus/ip/altera/alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10_htile/tcl/altera_xcvr_native_s10_htile_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="alt_usxgmii_phy_alt_mge_phy_1930_yuuknna"
     as="alt_mge_xcvr_native" />
  <messages>
   <message level="Info" culprit="alt_usxgmii_phy">"Generating: alt_usxgmii_phy_altera_xcvr_native_s10_htile_1921_x6s27ia"</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./altera_std_synchronizer_nocut.v VERILOG PATH ../../../../primitives/altera_std_synchronizer/altera_std_synchronizer_nocut.v</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_resync_std.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_generic/alt_xcvr_resync_std.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_reset_counter_s10.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_reset_control_s10/alt_xcvr_reset_counter_s10.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./altera_xcvr_native_s10_functions_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/altera_xcvr_native_s10_functions_h.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./s10_avmm_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/s10_avmm_h.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_avmm_csr.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_prbs_accum.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_prbs_accum.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_odi_accel.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_odi_accel.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_rcfg_arb.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_rcfg_arb.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_early_spd_chng_s10_htile.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_early_spd_chng_s10_htile.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_anlg_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_dig_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_dig_reset_seq.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_reset_seq.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_anlg_reset_seq_wrapper.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq_wrapper.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_re_cal_chnl.v VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_re_cal_chnl.v</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_pcie_rx_eios_prot.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_pcie_rx_eios_prot.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">add_fileset_file ./alt_xcvr_native_rx_maib_wa.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_rx_maib_wa.sv</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Building configuration data for reconfiguration profile 0</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Validating reconfiguration profile 0</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Current IP configuration matches reconfiguration profile 0</message>
   <message level="Info" culprit="alt_mge_xcvr_native">The TX PCS-Core Interface FIFO is operating in full-rate transfer mode.</message>
   <message level="Info" culprit="alt_mge_xcvr_native">The RX PCS-Core Interface FIFO is operating in full-rate transfer mode.</message>
   <message level="Info" culprit="alt_mge_xcvr_native">For the selected device(1SG165HU2F50E2VG), transceiver speed grade is 2 and core speed grade is 2.</message>
   <message level="Info" culprit="alt_mge_xcvr_native">For current configuration, TX PCS FIFO depth is "16" and TX Core FIFO depth is "16".</message>
   <message level="Info" culprit="alt_mge_xcvr_native">For current configuration, RX PCS FIFO depth is "16" and RX Core FIFO depth is "32".</message>
   <message level="Info" culprit="alt_mge_xcvr_native"><![CDATA[<b>"PCS clkout"</b> (pcs_clkout) is selected to drive tx_clkout port and the clock frequency is 322.265625 MHz.]]></message>
   <message level="Info" culprit="alt_mge_xcvr_native"><![CDATA[<b>"PCS clkout"</b> (pcs_clkout) is selected to drive rx_clkout port and the clock frequency is 322.265625 MHz.]]></message>
   <message level="Info" culprit="alt_mge_xcvr_native">"pma_div_clkout" is selected to drive rx_clkout2 port and it should not be used for register mode data transfers (Relevant parameter: "Selected rx_clkout2 clock source" (rx_clkout2_sel)).</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Design example cannot be generated for the current configuration. Please check under Design Example tab and system message below for more detailed information.</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Generating configuration files for reconfiguration profile 0</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Generating SystemVerilog configuration file</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Generating C header configuration file</message>
   <message level="Info" culprit="alt_mge_xcvr_native">Generating MIF configuration file</message>
  </messages>
 </entity>
</deploy>
