// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module  char10g1588_ram  (
    address,
    clock,
    data,
    wren,
    q);

    parameter LPM_HINT = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=INST";
    parameter INSTANCE_NAME = "INST";
    
    input  [11:0]  address;
    input    clock;
    input  [47:0]  data;
    input    wren;
    output [47:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
    tri1     clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

    wire [47:0] sub_wire0;
    wire [47:0] q = sub_wire0[47:0];

`ifdef ALTERA_RESERVED_QIS

    // Instantiate In System Memory Content Editor IP 
    wire reset_out;
    wire [11:0] ismce_addr;
    wire [5:0]ismce_byteena;
    wire [47:0] ismce_wdata;
    wire ismce_wren;
    wire ismce_rden;
    wire [47:0] ismce_rdata;
    wire ismce_waitrequest;
    wire tck_usr;

    //intel_mce_inst intel_mce_component (
      sld_mod_ram_rom #(
        .SLD_NODE_INFO        (270036480),
        .BYTE_ENABLE_WIDTH    (6),
        .FIFO_SIZE_DELAY      (5),
        .QUEUE_SIZE_WIDTH     (5),
        .LATENCY              (1),
        .WIDTH_WORD           (48),
        .NUMWORDS             (4096),
        .WIDTHAD              (12),
        .SHIFT_COUNT_BITS     (6),
        .CVALUE               (48'b000000000000000000000000000000000000000000000000),
        .IS_DATA_IN_RAM       (1),
        .IS_READABLE          (1),
        .BACKPRESSURE_ENABLED (1),
        .FIFO_SIZE            (16),
        .FIFO_SIZE_WIDTH      (4),
        .NODE_NAME            (INSTANCE_NAME)
    ) intel_mce_inst (
        .clock0            (clock),             //   input,   width = 1,    mm_clk.clk
        .reset_out         (reset_out),         //  output,   width = 1,     reset.reset
        .ismce_addr        (ismce_addr),        //  output,  width = 12, mm_master.address
        .ismce_byteena     (ismce_byteena),     //  output,   width = 6,          .byteenable
        .ismce_wdata       (ismce_wdata),       //  output,  width = 48,          .writedata
        .ismce_wren        (ismce_wren),        //  output,   width = 1,          .write
        .ismce_rden        (ismce_rden),        //  output,   width = 1,          .read
        .ismce_rdata       (ismce_rdata),       //   input,  width = 48,          .readdata
        .ismce_waitrequest (ismce_waitrequest), //   input,   width = 1,          .waitrequest
        .tck_usr           (tck_usr)            //  output,   width = 1,   clk_out.clk
    );

    // Instantiate Arbiter for ISMCE    
    wire [11:0] arb_addr;
    wire [5:0]arb_byteena;
    wire [47:0] arb_wdata;
    wire arb_wren;
    wire arb_rden;
    wire [47:0] arb_rdata;
    altera_sld_arbiter #(
        .LATENCY           (1),
        .DATA_WIDTH        (48),
        .WIDTHAD           (12),
        .BYTE_ENABLE_WIDTH (6)
    ) intel_mce_arb_inst (
        .clk              (clock            ),
        .reset            (reset_out        ),
        .uaddr            (address          ),
        .ubyteena         (6'h3f        ),
        .uwdata           (data             ),
        .urden            (1'b1           ),
        .uwren            (wren             ),
        .uaddressstall    (1'b0   ),
        .urdata           (sub_wire0        ),
        .ismce_addr       (ismce_addr       ),
        .ismce_byteena    (ismce_byteena    ),
        .ismce_wdata      (ismce_wdata      ),
        .ismce_wren       (ismce_wren       ),
        .ismce_rden       (ismce_rden       ),
        .ismce_rdata      (ismce_rdata      ),
        .ismce_waitrequest(ismce_waitrequest),
        .addr             (arb_addr         ),
        .byteena          (arb_byteena      ),
        .wdata            (arb_wdata        ),
        .rden             (arb_rden         ),
        .wren             (arb_wren         ),
        .addressstall     (arb_addressstall ),
        .rdata            (arb_rdata        ) 
    );

    altera_syncram  altera_syncram_component (
                .address_a (arb_addr),
                .clock0 (clock),
                .data_a (arb_wdata),
                .wren_a (arb_wren),
                .q_a (arb_rdata),
                .aclr0 (1'b0),
                .aclr1 (1'b0),
                .address2_a (1'b1),
                .address2_b (1'b1),
                .address_b (1'b1),
                .addressstall_a (1'b0),
                .addressstall_b (1'b0),
                .byteena_a (1'b1),
                .byteena_b (1'b1),
                .clock1 (1'b1),
                .clocken0 (1'b1),
                .clocken1 (1'b1),
                .clocken2 (1'b1),
                .clocken3 (1'b1),
                .data_b (1'b1),
                .eccencbypass (1'b0),
                .eccencparity (8'b0),
                .eccstatus ( ),
                .q_b ( ),
                .rden_a (1'b1),
                .rden_b (1'b1),
                .sclr (1'b0),
                .wren_b (1'b0));
    defparam
        altera_syncram_component.clock_enable_input_a  = "BYPASS",
        altera_syncram_component.clock_enable_output_a  = "BYPASS",
        altera_syncram_component.intended_device_family  = "Stratix 10",
        altera_syncram_component.lpm_type  = "altera_syncram",
        altera_syncram_component.numwords_a  = 4096,
        altera_syncram_component.operation_mode  = "SINGLE_PORT",
        altera_syncram_component.outdata_aclr_a  = "NONE",
        altera_syncram_component.outdata_sclr_a  = "NONE",
        altera_syncram_component.outdata_reg_a  = "CLOCK0",
        altera_syncram_component.enable_force_to_zero  = "FALSE",
        altera_syncram_component.power_up_uninitialized  = "FALSE",
        altera_syncram_component.ram_block_type  = "M20K",
        altera_syncram_component.read_during_write_mode_port_a  = "DONT_CARE",
        altera_syncram_component.widthad_a  = 12,
        altera_syncram_component.width_a  = 48,
        altera_syncram_component.width_byteena_a  = 1;

`else

    altera_syncram  altera_syncram_component (
                .address_a (address),
                .clock0 (clock),
                .data_a (data),
                .wren_a (wren),
                .q_a (sub_wire0),
                .aclr0 (1'b0),
                .aclr1 (1'b0),
                .address_b (1'b1),
                .addressstall_a (1'b0),
                .addressstall_b (1'b0),
                .byteena_a (1'b1),
                .byteena_b (1'b1),
                .clock1 (1'b1),
                .clocken0 (1'b1),
                .clocken1 (1'b1),
                .clocken2 (1'b1),
                .clocken3 (1'b1),
                .data_b (1'b1),
                .eccstatus ( ),
                .q_b ( ),
                .rden_a (1'b1),
                .rden_b (1'b1),
                .wren_b (1'b0));
    defparam
        altera_syncram_component.clock_enable_input_a  = "BYPASS",
        altera_syncram_component.clock_enable_output_a  = "BYPASS",
        altera_syncram_component.intended_device_family  = "Stratix 10",
        altera_syncram_component.lpm_hint  = LPM_HINT,
        altera_syncram_component.lpm_type  = "altera_syncram",
        altera_syncram_component.maximum_depth  = 4096,
        altera_syncram_component.numwords_a  = 4096,
        altera_syncram_component.operation_mode  = "SINGLE_PORT",
        altera_syncram_component.outdata_aclr_a  = "NONE",
        altera_syncram_component.outdata_reg_a  = "CLOCK0",
        altera_syncram_component.power_up_uninitialized  = "FALSE",
        altera_syncram_component.ram_block_type  = "M20K",
        altera_syncram_component.read_during_write_mode_port_a  = "DONT_CARE",
        altera_syncram_component.widthad_a  = 12,
        altera_syncram_component.width_a  = 48,
        altera_syncram_component.width_byteena_a  = 1;

`endif

endmodule


