qsys_system |

2019.07.30.09:58:53 | Datasheet

Overview

clk_0 | qsys_system

All Components
mm_slave_bfm_0 altera_avalon_mm_slave_bfm 18.0
Memory Map

| qsys_component_0
avalon_master_0
mm_slave_bfm_0 |
s0 | 0x00000000

## clk_0

clock_source v18.0

## Parameters

clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## mm_slave_bfm_0

altera_avalon_mm_slave_bfm v18.0

qsys_component_0 | avalon_master_0 | mm_slave_bfm_0
s0
clk_0 | clk
clk
clk_reset
clk_reset

## Parameters

AV_ADDRESS_W | 8
AV_SYMBOL_W | 8
AV_NUMSYMBOLS | 4
AV_BURSTCOUNT_W | 3
AV_READRESPONSE_W | 8
AV_WRITERESPONSE_W | 8
USE_READ | 0
USE_WRITE | 1
USE_ADDRESS | 1
USE_BYTE_ENABLE | 0
USE_BURSTCOUNT | 0
USE_READ_DATA | 0
USE_READ_DATA_VALID | 0
USE_WRITE_DATA | 1
USE_BEGIN_TRANSFER | 0
USE_BEGIN_BURST_TRANSFER | 0
USE_ARBITERLOCK | 0
USE_LOCK | 0
USE_DEBUGACCESS | 0
USE_WAIT_REQUEST | 0
USE_TRANSACTIONID | 0
USE_WRITERESPONSE | 0
USE_READRESPONSE | 0
USE_CLKEN | 0
ASSERT_HIGH_RESET | 1
ASSERT_HIGH_WAITREQUEST | 1
ASSERT_HIGH_READ | 1
ASSERT_HIGH_WRITE | 1
ASSERT_HIGH_BYTEENABLE | 1
ASSERT_HIGH_READDATAVALID | 1
ASSERT_HIGH_ARBITERLOCK | 1
ASSERT_HIGH_LOCK | 1
AV_BURST_LINEWRAP | 1
AV_BURST_BNDR_ONLY | 1
AV_MAX_PENDING_READS | 1
AV_MAX_PENDING_WRITES | 0
AV_FIX_READ_LATENCY | 0
AV_READ_WAIT_TIME | 1
AV_WRITE_WAIT_TIME | 0
REGISTER_WAITREQUEST | 0
AV_REGISTERINCOMINGSIGNALS | 0
ADDRESS_UNITS | WORDS
VHDL_ID | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## qsys_component_0

qsys_component v1.0

clk_0 | clk | qsys_component_0
clock
clk_reset
reset
|  | avalon_master_0 | mm_slave_bfm_0
|  | s0

## Parameters

counter_max | 15
write_address | 228
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

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