# system info qsys_system on 2019.07.30.09:58:50
system_info:
name,value
DEVICE,5CGXFC7C7F23C8
DEVICE_FAMILY,Cyclone V
GENERATION_ID,1564477126
#
#
# Files generated for qsys_system on 2019.07.30.09:58:50
files:
filepath,kind,attributes,module,is_top
simulation/qsys_system.vhd,VHDL,,qsys_system,true
simulation/submodules/mentor/verbosity_pkg.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_mentor_verbosity_pkg,altera_avalon_mm_slave_bfm_vhdl,false
simulation/submodules/mentor/avalon_mm_pkg.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_mentor_avalon_mm_pkg,altera_avalon_mm_slave_bfm_vhdl,false
simulation/submodules/mentor/avalon_utilities_pkg.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_mentor_avalon_utilities_pkg,altera_avalon_mm_slave_bfm_vhdl,false
simulation/submodules/mentor/altera_avalon_mm_slave_bfm.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_avalon_mm_slave_bfm_vhdl,false
simulation/submodules/mentor/altera_avalon_mm_slave_bfm_vhdl_wrapper.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_avalon_mm_slave_bfm_vhdl,false
simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC CADENCE_SPECIFIC SYNOPSYS_SPECIFIC COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_mm_slave_bfm_vhdl,false
simulation/submodules/avalon_mm_pkg.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC CADENCE_SPECIFIC SYNOPSYS_SPECIFIC COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_avalon_mm_pkg,altera_avalon_mm_slave_bfm_vhdl,false
simulation/submodules/avalon_utilities_pkg.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC CADENCE_SPECIFIC SYNOPSYS_SPECIFIC COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_avalon_utilities_pkg,altera_avalon_mm_slave_bfm_vhdl,false
simulation/submodules/altera_avalon_mm_slave_bfm.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC CADENCE_SPECIFIC SYNOPSYS_SPECIFIC,altera_avalon_mm_slave_bfm_vhdl,false
simulation/submodules/altera_avalon_mm_slave_bfm_vhdl_wrapper.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC CADENCE_SPECIFIC SYNOPSYS_SPECIFIC,altera_avalon_mm_slave_bfm_vhdl,false
simulation/submodules/altera_avalon_mm_slave_bfm_vhdl_pkg.vhd,VHDL,,altera_avalon_mm_slave_bfm_vhdl,false
simulation/submodules/altera_avalon_mm_slave_bfm_vhdl.vhd,VHDL,,altera_avalon_mm_slave_bfm_vhdl,false
simulation/submodules/qsys_component.vhdl,VHDL,,qsys_component,false
simulation/submodules/qsys_system_mm_interconnect_0.v,VERILOG,,qsys_system_mm_interconnect_0,false
simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
simulation/submodules/qsys_system_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,qsys_system_mm_interconnect_0_router,false
simulation/submodules/qsys_system_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,qsys_system_mm_interconnect_0_router_001,false
simulation/submodules/qsys_system_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,qsys_system_mm_interconnect_0_cmd_demux,false
simulation/submodules/qsys_system_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,qsys_system_mm_interconnect_0_cmd_mux,false
simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsys_system_mm_interconnect_0_cmd_mux,false
simulation/submodules/qsys_system_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,qsys_system_mm_interconnect_0_rsp_mux,false
simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsys_system_mm_interconnect_0_rsp_mux,false
simulation/submodules/qsys_system_mm_interconnect_0_avalon_st_adapter.vhd,VHDL,,qsys_system_mm_interconnect_0_avalon_st_adapter,false
simulation/submodules/qsys_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,qsys_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
qsys_system.mm_slave_bfm_0,altera_avalon_mm_slave_bfm_vhdl
qsys_system.qsys_component_0,qsys_component
qsys_system.mm_interconnect_0,qsys_system_mm_interconnect_0
qsys_system.mm_interconnect_0.qsys_component_0_avalon_master_0_translator,altera_merlin_master_translator
qsys_system.mm_interconnect_0.mm_slave_bfm_0_s0_translator,altera_merlin_slave_translator
qsys_system.mm_interconnect_0.qsys_component_0_avalon_master_0_agent,altera_merlin_master_agent
qsys_system.mm_interconnect_0.mm_slave_bfm_0_s0_agent,altera_merlin_slave_agent
qsys_system.mm_interconnect_0.mm_slave_bfm_0_s0_agent_rsp_fifo,altera_avalon_sc_fifo
qsys_system.mm_interconnect_0.router,qsys_system_mm_interconnect_0_router
qsys_system.mm_interconnect_0.router_001,qsys_system_mm_interconnect_0_router_001
qsys_system.mm_interconnect_0.cmd_demux,qsys_system_mm_interconnect_0_cmd_demux
qsys_system.mm_interconnect_0.rsp_demux,qsys_system_mm_interconnect_0_cmd_demux
qsys_system.mm_interconnect_0.cmd_mux,qsys_system_mm_interconnect_0_cmd_mux
qsys_system.mm_interconnect_0.rsp_mux,qsys_system_mm_interconnect_0_rsp_mux
qsys_system.mm_interconnect_0.avalon_st_adapter,qsys_system_mm_interconnect_0_avalon_st_adapter
qsys_system.mm_interconnect_0.avalon_st_adapter.error_adapter_0,qsys_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0
qsys_system.rst_controller,altera_reset_controller
