Info: Starting: Create simulation model
Info: qsys-generate C:\My_Designs\6594\qsys_test\qsys_system.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=C:\My_Designs\6594\qsys_test\qsys_system\simulation --family="Cyclone V" --part=5CGXFC7C7F23C8
Progress: Loading qsys_test/qsys_system.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 18.0]
Progress: Parameterizing module clk_0
Progress: Adding mm_slave_bfm_0 [altera_avalon_mm_slave_bfm 18.0]
Progress: Parameterizing module mm_slave_bfm_0
Progress: Adding qsys_component_0 [qsys_component 1.0]
Progress: Parameterizing module qsys_component_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: qsys_system.qsys_component: The SIM_VHDL fileset must specify the top-level module name.
Info: qsys_system: Generating qsys_system "qsys_system" for SIM_VHDL
Info: Interconnect is inserted between master qsys_component_0.avalon_master_0 and slave mm_slave_bfm_0.s0 because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide.
Info: mm_slave_bfm_0: "qsys_system" instantiated altera_avalon_mm_slave_bfm "mm_slave_bfm_0"
Info: qsys_component_0: "qsys_system" instantiated qsys_component "qsys_component_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "qsys_system" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: rst_controller: "qsys_system" instantiated altera_reset_controller "rst_controller"
Info: qsys_component_0_avalon_master_0_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "qsys_component_0_avalon_master_0_translator"
Info: mm_slave_bfm_0_s0_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "mm_slave_bfm_0_s0_translator"
Info: qsys_component_0_avalon_master_0_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "qsys_component_0_avalon_master_0_agent"
Info: mm_slave_bfm_0_s0_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "mm_slave_bfm_0_s0_agent"
Info: mm_slave_bfm_0_s0_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "mm_slave_bfm_0_s0_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/My_Designs/6594/qsys_test/qsys_system/simulation/submodules/altera_merlin_arbitrator.sv
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: qsys_system: Done "qsys_system" with 17 modules, 32 files
Info: qsys-generate succeeded.
Info: Finished: Create simulation model
Info: Starting: Create Modelsim Project.
Info: sim-script-gen --spd=C:\My_Designs\6594\qsys_test\qsys_system\qsys_system.spd --output-directory=C:/My_Designs/6594/qsys_test/qsys_system/simulation/ --use-relative-paths=true
Info: Doing: ip-make-simscript --spd=C:\My_Designs\6594\qsys_test\qsys_system\qsys_system.spd --output-directory=C:/My_Designs/6594/qsys_test/qsys_system/simulation/ --use-relative-paths=true
Info: Generating the following file(s) for MODELSIM simulator in C:/My_Designs/6594/qsys_test/qsys_system/simulation/ directory:
Info: 	mentor/msim_setup.tcl
Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
Info: Generating the following file(s) for VCSMX simulator in C:/My_Designs/6594/qsys_test/qsys_system/simulation/ directory:
Info: 	synopsys/vcsmx/synopsys_sim.setup
Info: 	synopsys/vcsmx/vcsmx_setup.sh
Info: Generating the following file(s) for NCSIM simulator in C:/My_Designs/6594/qsys_test/qsys_system/simulation/ directory:
Info: 	cadence/cds.lib
Info: 	cadence/hdl.var
Info: 	cadence/ncsim_setup.sh
Info: 	17 .cds.lib files in cadence/cds_libs/ directory
Info: Generating the following file(s) for RIVIERA simulator in C:/My_Designs/6594/qsys_test/qsys_system/simulation/ directory:
Info: 	aldec/rivierapro_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/My_Designs/6594/qsys_test/qsys_system/simulation/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create Modelsim Project.
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\My_Designs\6594\qsys_test\qsys_system.qsys --block-symbol-file --output-directory=C:\My_Designs\6594\qsys_test\qsys_system --family="Cyclone V" --part=5CGXFC7C7F23C8
Progress: Loading qsys_test/qsys_system.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 18.0]
Progress: Parameterizing module clk_0
Progress: Adding mm_slave_bfm_0 [altera_avalon_mm_slave_bfm 18.0]
Progress: Parameterizing module mm_slave_bfm_0
Progress: Adding qsys_component_0 [qsys_component 1.0]
Progress: Parameterizing module qsys_component_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: qsys_system.qsys_component: The SIM_VHDL fileset must specify the top-level module name.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\My_Designs\6594\qsys_test\qsys_system.qsys --synthesis=VHDL --output-directory=C:\My_Designs\6594\qsys_test\qsys_system\synthesis --family="Cyclone V" --part=5CGXFC7C7F23C8
Progress: Loading qsys_test/qsys_system.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 18.0]
Progress: Parameterizing module clk_0
Progress: Adding mm_slave_bfm_0 [altera_avalon_mm_slave_bfm 18.0]
Progress: Parameterizing module mm_slave_bfm_0
Progress: Adding qsys_component_0 [qsys_component 1.0]
Progress: Parameterizing module qsys_component_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: qsys_system.qsys_component: The SIM_VHDL fileset must specify the top-level module name.
Info: qsys_system: Generating qsys_system "qsys_system" for QUARTUS_SYNTH
Info: Interconnect is inserted between master qsys_component_0.avalon_master_0 and slave mm_slave_bfm_0.s0 because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide.
Info: mm_slave_bfm_0: "qsys_system" instantiated altera_avalon_mm_slave_bfm "mm_slave_bfm_0"
Info: qsys_component_0: "qsys_system" instantiated qsys_component "qsys_component_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "qsys_system" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: rst_controller: "qsys_system" instantiated altera_reset_controller "rst_controller"
Info: qsys_component_0_avalon_master_0_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "qsys_component_0_avalon_master_0_translator"
Info: mm_slave_bfm_0_s0_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "mm_slave_bfm_0_s0_translator"
Info: qsys_component_0_avalon_master_0_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "qsys_component_0_avalon_master_0_agent"
Info: mm_slave_bfm_0_s0_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "mm_slave_bfm_0_s0_agent"
Info: mm_slave_bfm_0_s0_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "mm_slave_bfm_0_s0_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/My_Designs/6594/qsys_test/qsys_system/synthesis/submodules/altera_merlin_arbitrator.sv
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: qsys_system: Done "qsys_system" with 17 modules, 24 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
