
library ieee;
use ieee.std_logic_1164.all;

entity qsys_component is
  generic (
    counter_max: integer range 15 to 65535 := 15;
	 write_address: std_logic_vector(31 downto 0) := (others=>'0')
  );
  port (
    clk: in std_logic;
	 reset_n: in std_logic;
	 
	 avm_write: out std_logic;
	 avm_wait_request: in std_logic;
	 avm_write_data: out std_logic_vector(31 downto 0);
	 avm_write_address: out std_logic_vector(7 downto 0)
  );
end entity;

architecture rtl of qsys_component is
  signal counter: integer;
  type qsys_component_state_t is (idle, writing);
  signal qsys_component_state: qsys_component_state_t;
begin

  process(clk)
  begin
    if rising_edge(clk) then
	   if reset_n = '0' then
	     counter <= 0;
	   else
		  if counter < counter_max then
		    counter <= counter + 1;
		  else
		    counter <= 0;
		  end if;
	   end if;
    end if;
  end process;
  
  process(clk)
  begin
    if rising_edge(clk) then
      if reset_n = '0' then
		  qsys_component_state <= idle;
		  avm_write <= '0';
		  avm_write_data <= (others=>'0');
		  avm_write_address <= (others=>'0');
		else
		  case qsys_component_state is
		    when idle =>
			   avm_write <= '0';
            avm_write_data <= (others=>'0');
		      avm_write_address <= (others=>'0');			 
			   if counter = counter_max then
				  qsys_component_state <= writing;
				end if;
			 when writing =>
		      avm_write <= '1'; 
				avm_write_data <= x"55AA55CC";
				avm_write_address <= write_address;
				if avm_wait_request = '0' then
				  qsys_component_state <= idle;
				end if;
		  end case;
		end if;
    end if;
  end process;

end architecture;