<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
 <file
   path="simulation/submodules/mentor/verbosity_pkg.sv"
   type="SYSTEM_VERILOG_ENCRYPT"
   library="altera_common_sv_packages"
   simulator="modelsim"
   systemVerilogPackageName="avalon_vip_mentor_verbosity_pkg" />
 <file
   path="simulation/submodules/mentor/avalon_mm_pkg.sv"
   type="SYSTEM_VERILOG_ENCRYPT"
   library="altera_common_sv_packages"
   simulator="modelsim"
   systemVerilogPackageName="avalon_vip_mentor_avalon_mm_pkg" />
 <file
   path="simulation/submodules/mentor/avalon_utilities_pkg.sv"
   type="SYSTEM_VERILOG_ENCRYPT"
   library="altera_common_sv_packages"
   simulator="modelsim"
   systemVerilogPackageName="avalon_vip_mentor_avalon_utilities_pkg" />
 <file
   path="simulation/submodules/verbosity_pkg.sv"
   type="SYSTEM_VERILOG_ENCRYPT"
   library="altera_common_sv_packages"
   simulator="riviera, ncsim, vcs"
   systemVerilogPackageName="avalon_vip_verbosity_pkg" />
 <file
   path="simulation/submodules/avalon_mm_pkg.sv"
   type="SYSTEM_VERILOG_ENCRYPT"
   library="altera_common_sv_packages"
   simulator="riviera, ncsim, vcs"
   systemVerilogPackageName="avalon_vip_avalon_mm_pkg" />
 <file
   path="simulation/submodules/avalon_utilities_pkg.sv"
   type="SYSTEM_VERILOG_ENCRYPT"
   library="altera_common_sv_packages"
   simulator="riviera, ncsim, vcs"
   systemVerilogPackageName="avalon_vip_avalon_utilities_pkg" />
 <file
   path="simulation/submodules/qsys_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
   type="SYSTEM_VERILOG"
   library="error_adapter_0" />
 <file
   path="simulation/submodules/qsys_system_mm_interconnect_0_avalon_st_adapter.vhd"
   type="VHDL"
   library="avalon_st_adapter" />
 <file
   path="simulation/submodules/qsys_system_mm_interconnect_0_rsp_mux.sv"
   type="SYSTEM_VERILOG"
   library="rsp_mux" />
 <file
   path="simulation/submodules/altera_merlin_arbitrator.sv"
   type="SYSTEM_VERILOG"
   library="rsp_mux" />
 <file
   path="simulation/submodules/qsys_system_mm_interconnect_0_cmd_mux.sv"
   type="SYSTEM_VERILOG"
   library="cmd_mux" />
 <file
   path="simulation/submodules/altera_merlin_arbitrator.sv"
   type="SYSTEM_VERILOG"
   library="cmd_mux" />
 <file
   path="simulation/submodules/qsys_system_mm_interconnect_0_cmd_demux.sv"
   type="SYSTEM_VERILOG"
   library="cmd_demux" />
 <file
   path="simulation/submodules/qsys_system_mm_interconnect_0_router_001.sv"
   type="SYSTEM_VERILOG"
   library="router_001" />
 <file
   path="simulation/submodules/qsys_system_mm_interconnect_0_router.sv"
   type="SYSTEM_VERILOG"
   library="router" />
 <file
   path="simulation/submodules/altera_avalon_sc_fifo.v"
   type="VERILOG"
   library="mm_slave_bfm_0_s0_agent_rsp_fifo" />
 <file
   path="simulation/submodules/altera_merlin_slave_agent.sv"
   type="SYSTEM_VERILOG"
   library="mm_slave_bfm_0_s0_agent" />
 <file
   path="simulation/submodules/altera_merlin_burst_uncompressor.sv"
   type="SYSTEM_VERILOG"
   library="mm_slave_bfm_0_s0_agent" />
 <file
   path="simulation/submodules/altera_merlin_master_agent.sv"
   type="SYSTEM_VERILOG"
   library="qsys_component_0_avalon_master_0_agent" />
 <file
   path="simulation/submodules/altera_merlin_slave_translator.sv"
   type="SYSTEM_VERILOG"
   library="mm_slave_bfm_0_s0_translator" />
 <file
   path="simulation/submodules/altera_merlin_master_translator.sv"
   type="SYSTEM_VERILOG"
   library="qsys_component_0_avalon_master_0_translator" />
 <file
   path="simulation/submodules/altera_reset_controller.v"
   type="VERILOG"
   library="rst_controller" />
 <file
   path="simulation/submodules/altera_reset_synchronizer.v"
   type="VERILOG"
   library="rst_controller" />
 <file
   path="simulation/submodules/altera_reset_controller.sdc"
   type="SDC"
   library="rst_controller" />
 <file
   path="simulation/submodules/qsys_system_mm_interconnect_0.v"
   type="VERILOG"
   library="mm_interconnect_0" />
 <file
   path="simulation/submodules/qsys_component.vhdl"
   type="VHDL"
   library="qsys_component_0" />
 <file
   path="simulation/submodules/mentor/altera_avalon_mm_slave_bfm.sv"
   type="SYSTEM_VERILOG_ENCRYPT"
   library="mm_slave_bfm_0"
   simulator="modelsim" />
 <file
   path="simulation/submodules/mentor/altera_avalon_mm_slave_bfm_vhdl_wrapper.sv"
   type="SYSTEM_VERILOG_ENCRYPT"
   library="mm_slave_bfm_0"
   simulator="modelsim" />
 <file
   path="simulation/submodules/altera_avalon_mm_slave_bfm.sv"
   type="SYSTEM_VERILOG_ENCRYPT"
   library="mm_slave_bfm_0"
   simulator="riviera, ncsim, vcs" />
 <file
   path="simulation/submodules/altera_avalon_mm_slave_bfm_vhdl_wrapper.sv"
   type="SYSTEM_VERILOG_ENCRYPT"
   library="mm_slave_bfm_0"
   simulator="riviera, ncsim, vcs" />
 <file
   path="simulation/submodules/altera_avalon_mm_slave_bfm_vhdl_pkg.vhd"
   type="VHDL"
   library="mm_slave_bfm_0" />
 <file
   path="simulation/submodules/altera_avalon_mm_slave_bfm_vhdl.vhd"
   type="VHDL"
   library="mm_slave_bfm_0" />
 <file path="simulation/qsys_system.vhd" type="VHDL" />
 <topLevel name="qsys_system" />
 <deviceFamily name="cyclonev" />
</simPackage>
