Slow 900mV -40C Model report for adc_input_test Wed Jan 22 16:10:01 2020 Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Slow 900mV -40C Model Fmax Summary 3. Slow 900mV -40C Model Setup Summary 4. Slow 900mV -40C Model Hold Summary 5. Slow 900mV -40C Model Recovery Summary 6. Slow 900mV -40C Model Removal Summary 7. Slow 900mV -40C Model Minimum Pulse Width Summary 8. Slow 900mV -40C Model Metastability Summary ---------------- ; Legal Notice ; ---------------- Copyright (C) 2018 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. +----------------------------------------------------------------+ ; Slow 900mV -40C Model Fmax Summary ; +------------+-----------------+--------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+--------------------------+------+ ; 96.55 MHz ; 96.55 MHz ; altera_reserved_tck ; ; ; 226.96 MHz ; 226.96 MHz ; iopll262|iopll_0|adc_clk ; ; +------------+-----------------+--------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. +---------------------------------------------------+ ; Slow 900mV -40C Model Setup Summary ; +--------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+--------+---------------+ ; iopll262|iopll_0|adc_clk ; -0.296 ; -5.351 ; ; altera_reserved_tck ; 11.488 ; 0.000 ; +--------------------------+--------+---------------+ +--------------------------------------------------+ ; Slow 900mV -40C Model Hold Summary ; +--------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+-------+---------------+ ; altera_reserved_tck ; 0.028 ; 0.000 ; ; iopll262|iopll_0|adc_clk ; 0.045 ; 0.000 ; +--------------------------+-------+---------------+ +----------------------------------------------+ ; Slow 900mV -40C Model Recovery Summary ; +---------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------+--------+---------------+ ; altera_reserved_tck ; 30.767 ; 0.000 ; +---------------------+--------+---------------+ +---------------------------------------------+ ; Slow 900mV -40C Model Removal Summary ; +---------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------+-------+---------------+ ; altera_reserved_tck ; 0.710 ; 0.000 ; +---------------------+-------+---------------+ +---------------------------------------------------+ ; Slow 900mV -40C Model Minimum Pulse Width Summary ; +--------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+--------+---------------+ ; iopll262|iopll_0|adc_clk ; 1.332 ; 0.000 ; ; SAMPLE_CLK_1 ; 1.767 ; 0.000 ; ; altera_reserved_tck ; 16.304 ; 0.000 ; +--------------------------+--------+---------------+ ----------------------------------------------- ; Slow 900mV -40C Model Metastability Summary ; ----------------------------------------------- The design MTBF is not calculated because there are no specified synchronizers in the design. Number of Synchronizer Chains Found: 14 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Worst Case Available Settling Time: 45.571 ns