## Generated SDC file "Gyro_x.sdc" ## Copyright (C) 2016 Intel Corporation. All rights reserved. ## Your use of Intel Corporation's design tools, logic functions ## and other software and tools, and its AMPP partner logic ## functions, and any output files from any of the foregoing ## (including device programming or simulation files), and any ## associated documentation or information are expressly subject ## to the terms and conditions of the Intel Program License ## Subscription Agreement, the Intel Quartus Prime License Agreement, ## the Intel MegaCore Function License Agreement, or other ## applicable license agreement, including, without limitation, ## that your use is for the sole purpose of programming logic ## devices manufactured by Intel and sold by Intel or its ## authorized distributors. Please refer to the applicable ## agreement for further details. ## VENDOR "Altera" ## PROGRAM "Quartus Prime" ## VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" ## DATE "Wed Mar 06 17:15:05 2019" ## ## DEVICE "EP4CE75F23C6" ## #************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}] create_clock -name {clk_100MHz} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk_100MHz}] #************************************************************** # Create Generated Clock #************************************************************** create_generated_clock -name {inst2|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 1 -phase 90 -master_clock {clk_100MHz} [get_pins {inst2|altpll_component|auto_generated|pll1|clk[0]}] create_generated_clock -name {inst2|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {inst2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 8 -phase 90 -master_clock {clk_100MHz} [get_pins {inst2|altpll_component|auto_generated|pll1|clk[1]}] #************************************************************** # Set Clock Latency #************************************************************** #************************************************************** # Set Clock Uncertainty #************************************************************** set_clock_uncertainty -rise_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] 0.020 set_clock_uncertainty -rise_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] 0.020 set_clock_uncertainty -rise_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {clk_100MHz}] 0.010 set_clock_uncertainty -rise_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {clk_100MHz}] 0.010 set_clock_uncertainty -rise_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] 0.020 set_clock_uncertainty -rise_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] 0.020 set_clock_uncertainty -fall_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] 0.020 set_clock_uncertainty -fall_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] 0.020 set_clock_uncertainty -fall_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {clk_100MHz}] 0.010 set_clock_uncertainty -fall_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {clk_100MHz}] 0.010 set_clock_uncertainty -fall_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] 0.020 set_clock_uncertainty -fall_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] 0.020 set_clock_uncertainty -rise_from [get_clocks {clk_100MHz}] -rise_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] 0.010 set_clock_uncertainty -rise_from [get_clocks {clk_100MHz}] -fall_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] 0.010 set_clock_uncertainty -rise_from [get_clocks {clk_100MHz}] -rise_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] 0.010 set_clock_uncertainty -rise_from [get_clocks {clk_100MHz}] -fall_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] 0.010 set_clock_uncertainty -fall_from [get_clocks {clk_100MHz}] -rise_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] 0.010 set_clock_uncertainty -fall_from [get_clocks {clk_100MHz}] -fall_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] 0.010 set_clock_uncertainty -fall_from [get_clocks {clk_100MHz}] -rise_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] 0.010 set_clock_uncertainty -fall_from [get_clocks {clk_100MHz}] -fall_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] 0.010 set_clock_uncertainty -rise_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] 0.020 set_clock_uncertainty -rise_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] 0.020 set_clock_uncertainty -rise_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {clk_100MHz}] 0.010 set_clock_uncertainty -rise_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {clk_100MHz}] 0.010 set_clock_uncertainty -rise_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] 0.020 set_clock_uncertainty -rise_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] 0.020 set_clock_uncertainty -fall_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] 0.020 set_clock_uncertainty -fall_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[1]}] 0.020 set_clock_uncertainty -fall_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {clk_100MHz}] 0.010 set_clock_uncertainty -fall_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {clk_100MHz}] 0.010 set_clock_uncertainty -fall_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] 0.020 set_clock_uncertainty -fall_from [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst2|altpll_component|auto_generated|pll1|clk[0]}] 0.020 set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] 0.020 set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] 0.020 set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] 0.020 set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] 0.020 #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {adc_sdo[0]}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {adc_sdo[0]}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {adc_sdo[1]}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {adc_sdo[1]}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {adc_sdo[2]}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {adc_sdo[2]}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {adc_sdo[3]}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {adc_sdo[3]}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {adc_sdo[4]}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {adc_sdo[4]}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {altera_reserved_tck}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {altera_reserved_tck}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {altera_reserved_tdi}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {altera_reserved_tdi}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {altera_reserved_tms}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {altera_reserved_tms}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {clk_100MHz}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {clk_100MHz}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {data0_to_the_epcs}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {data0_to_the_epcs}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {eprom_sda}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {eprom_sda}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {rxd_to_the_uart}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {rxd_to_the_uart}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {spi_clk}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {spi_clk}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {spi_cs}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {spi_cs}] set_input_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {spi_mosi}] set_input_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {spi_mosi}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {F/C}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {F/C}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {FLYBACK_FBC}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {FLYBACK_FBC}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {FLYBACK_FBV}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {FLYBACK_FBV}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {PWM_coarse_out}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {PWM_coarse_out}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {PWM_fine_out}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {PWM_fine_out}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {SW_Tmpr}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {SW_Tmpr}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {adc_cnv[0]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {adc_cnv[0]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {adc_cnv[1]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {adc_cnv[1]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {adc_sck[0]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {adc_sck[0]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {adc_sck[1]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {adc_sck[1]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {altera_reserved_tdo}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {altera_reserved_tdo}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {dac_clk[0]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {dac_clk[0]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {dac_clk[1]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {dac_clk[1]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {dac_cs_x[0]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {dac_cs_x[0]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {dac_cs_x[1]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {dac_cs_x[1]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {dac_sdi[0]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {dac_sdi[0]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {dac_sdi[1]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {dac_sdi[1]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {dac_sdi[2]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {dac_sdi[2]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {dac_sdi[3]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {dac_sdi[3]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {dac_sdi[4]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {dac_sdi[4]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {dac_sdi[5]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {dac_sdi[5]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {dac_sdi[6]}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {dac_sdi[6]}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {dclk_from_the_epcs}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {dclk_from_the_epcs}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {eprom_clk}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {eprom_clk}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {eprom_sda}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {eprom_sda}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {sce_from_the_epcs}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {sce_from_the_epcs}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {sdo_from_the_epcs}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {sdo_from_the_epcs}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {spi_miso}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {spi_miso}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {tdac_clk}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {tdac_clk}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {tdac_cs_x}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {tdac_cs_x}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {tdac_sdo}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {tdac_sdo}] set_output_delay -add_delay -max -clock [get_clocks {clk_100MHz}] 2.000 [get_ports {txd_from_the_uart}] set_output_delay -add_delay -min -clock [get_clocks {clk_100MHz}] 1.000 [get_ports {txd_from_the_uart}] #************************************************************** # Set Clock Groups #************************************************************** set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] #************************************************************** # Set False Path #************************************************************** set_false_path -to [get_pins -nocase -compatibility_mode {*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn}] set_false_path -from [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_nios2_oci_break:the_CPU_nios2_qsys_0_cpu_nios2_oci_break|break_readreg*}] -to [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_debug_slave_wrapper:the_CPU_nios2_qsys_0_cpu_debug_slave_wrapper|CPU_nios2_qsys_0_cpu_debug_slave_tck:the_CPU_nios2_qsys_0_cpu_debug_slave_tck|*sr*}] set_false_path -from [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_nios2_oci_debug:the_CPU_nios2_qsys_0_cpu_nios2_oci_debug|*resetlatch}] -to [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_debug_slave_wrapper:the_CPU_nios2_qsys_0_cpu_debug_slave_wrapper|CPU_nios2_qsys_0_cpu_debug_slave_tck:the_CPU_nios2_qsys_0_cpu_debug_slave_tck|*sr[33]}] set_false_path -from [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_nios2_oci_debug:the_CPU_nios2_qsys_0_cpu_nios2_oci_debug|monitor_ready}] -to [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_debug_slave_wrapper:the_CPU_nios2_qsys_0_cpu_debug_slave_wrapper|CPU_nios2_qsys_0_cpu_debug_slave_tck:the_CPU_nios2_qsys_0_cpu_debug_slave_tck|*sr[0]}] set_false_path -from [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_nios2_oci_debug:the_CPU_nios2_qsys_0_cpu_nios2_oci_debug|monitor_error}] -to [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_debug_slave_wrapper:the_CPU_nios2_qsys_0_cpu_debug_slave_wrapper|CPU_nios2_qsys_0_cpu_debug_slave_tck:the_CPU_nios2_qsys_0_cpu_debug_slave_tck|*sr[34]}] set_false_path -from [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_nios2_ocimem:the_CPU_nios2_qsys_0_cpu_nios2_ocimem|*MonDReg*}] -to [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_debug_slave_wrapper:the_CPU_nios2_qsys_0_cpu_debug_slave_wrapper|CPU_nios2_qsys_0_cpu_debug_slave_tck:the_CPU_nios2_qsys_0_cpu_debug_slave_tck|*sr*}] set_false_path -from [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_debug_slave_wrapper:the_CPU_nios2_qsys_0_cpu_debug_slave_wrapper|CPU_nios2_qsys_0_cpu_debug_slave_tck:the_CPU_nios2_qsys_0_cpu_debug_slave_tck|*sr*}] -to [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_debug_slave_wrapper:the_CPU_nios2_qsys_0_cpu_debug_slave_wrapper|CPU_nios2_qsys_0_cpu_debug_slave_sysclk:the_CPU_nios2_qsys_0_cpu_debug_slave_sysclk|*jdo*}] set_false_path -from [get_keepers {sld_hub:*|irf_reg*}] -to [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_debug_slave_wrapper:the_CPU_nios2_qsys_0_cpu_debug_slave_wrapper|CPU_nios2_qsys_0_cpu_debug_slave_sysclk:the_CPU_nios2_qsys_0_cpu_debug_slave_sysclk|ir*}] set_false_path -from [get_keepers {sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1]}] -to [get_keepers {*CPU_nios2_qsys_0_cpu:*|CPU_nios2_qsys_0_cpu_nios2_oci:the_CPU_nios2_qsys_0_cpu_nios2_oci|CPU_nios2_qsys_0_cpu_nios2_oci_debug:the_CPU_nios2_qsys_0_cpu_nios2_oci_debug|monitor_go}] set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] #************************************************************** # Set Multicycle Path #************************************************************** #************************************************************** # Set Maximum Delay #************************************************************** set_max_delay -from [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] -to [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] 100.000 set_max_delay -from [get_registers *] -to [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] 100.000 #************************************************************** # Set Minimum Delay #************************************************************** set_min_delay -from [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] -to [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] -100.000 set_min_delay -from [get_registers *] -to [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] -100.000 #************************************************************** # Set Input Transition #************************************************************** #************************************************************** # Set Net Delay #************************************************************** set_net_delay -max 2.000 -from [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] -to [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] set_net_delay -max 2.000 -from [get_registers *] -to [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}]