Summary (Recovery) report for ngt_stator Tue Feb 26 14:47:32 2019 Quartus Prime Version 16.1.2 Build 203 01/18/2017 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Multi Corner Summary (4/4 corners) 3. Slow 1100mV 100C Model 4. Slow 1100mV -40C Model 5. Fast 1100mV 100C Model 6. Fast 1100mV -40C Model ---------------- ; Legal Notice ; ---------------- Copyright (C) 2017 Intel Corporation. All rights reserved. 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Corners in summary: Slow 1100mV 100C Model Slow 1100mV -40C Model Fast 1100mV 100C Model Fast 1100mV -40C Model +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multi Corner Summary (4/4 corners) ; +------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+---------------+ ; Worst-case Corner ; Clock ; Slack ; End Point TNS ; +------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+---------------+ ; Slow 1100mV 100C Model ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; -13.838 ; -537.096 ; ; Slow 1100mV 100C Model ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; -11.997 ; -624.824 ; ; Slow 1100mV 100C Model ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_cpu_subsystem:cpu_subsystem|ngt_stator_system_cpu_subsystem_hps:hps|ngt_stator_system_cpu_subsystem_hps_hps_io:hps_io|ngt_stator_system_cpu_subsystem_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk_write_clk ; 3.040 ; 0.000 ; ; Slow 1100mV 100C Model ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; 5.425 ; 0.000 ; ; Slow 1100mV 100C Model ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 10.238 ; 0.000 ; ; Slow 1100mV 100C Model ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk ; 19.721 ; 0.000 ; ; Slow 1100mV 100C Model ; FPGA_SYNC_CLK_V2_0 ; 44.707 ; 0.000 ; +------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+---------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1100mV 100C Model ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+---------------+ ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; -13.838 ; -537.096 ; ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; -11.997 ; -624.824 ; ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_cpu_subsystem:cpu_subsystem|ngt_stator_system_cpu_subsystem_hps:hps|ngt_stator_system_cpu_subsystem_hps_hps_io:hps_io|ngt_stator_system_cpu_subsystem_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk_write_clk ; 3.040 ; 0.000 ; ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; 5.425 ; 0.000 ; ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 10.238 ; 0.000 ; ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk ; 19.721 ; 0.000 ; ; FPGA_SYNC_CLK_V2_0 ; 44.707 ; 0.000 ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+---------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1100mV -40C Model ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+---------------+ ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; -13.186 ; -514.996 ; ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; -11.012 ; -572.096 ; ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_cpu_subsystem:cpu_subsystem|ngt_stator_system_cpu_subsystem_hps:hps|ngt_stator_system_cpu_subsystem_hps_hps_io:hps_io|ngt_stator_system_cpu_subsystem_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk_write_clk ; 3.130 ; 0.000 ; ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; 5.607 ; 0.000 ; ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 10.491 ; 0.000 ; ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk ; 19.988 ; 0.000 ; ; FPGA_SYNC_CLK_V2_0 ; 44.781 ; 0.000 ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+---------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1100mV 100C Model ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+---------------+ ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; -8.055 ; -289.269 ; ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; -7.540 ; -396.676 ; ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_cpu_subsystem:cpu_subsystem|ngt_stator_system_cpu_subsystem_hps:hps|ngt_stator_system_cpu_subsystem_hps_hps_io:hps_io|ngt_stator_system_cpu_subsystem_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk_write_clk ; 3.731 ; 0.000 ; ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; 7.146 ; 0.000 ; ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 12.712 ; 0.000 ; ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk ; 21.468 ; 0.000 ; ; FPGA_SYNC_CLK_V2_0 ; 45.384 ; 0.000 ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+---------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1100mV -40C Model ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+---------------+ ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; -7.009 ; -263.586 ; ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; -5.953 ; -310.398 ; ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_cpu_subsystem:cpu_subsystem|ngt_stator_system_cpu_subsystem_hps:hps|ngt_stator_system_cpu_subsystem_hps_hps_io:hps_io|ngt_stator_system_cpu_subsystem_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk_write_clk ; 3.843 ; 0.000 ; ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk ; 7.686 ; 0.000 ; ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 13.320 ; 0.000 ; ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk ; 22.034 ; 0.000 ; ; FPGA_SYNC_CLK_V2_0 ; 45.445 ; 0.000 ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+---------------+