Recovery: ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk report for ngt_stator Tue Feb 26 14:47:01 2019 Quartus Prime Version 16.1.2 Build 203 01/18/2017 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Corner Information 3. Summary of Paths 4. Path #2: Recovery slack is -13.838 (VIOLATED) 5. Path #1: Recovery slack is -13.838 (VIOLATED) 6. Path #3: Recovery slack is -13.833 (VIOLATED) 7. Path #4: Recovery slack is -13.833 (VIOLATED) 8. Path #5: Recovery slack is -13.833 (VIOLATED) 9. Path #6: Recovery slack is -13.832 (VIOLATED) 10. Path #7: Recovery slack is -13.832 (VIOLATED) 11. Path #8: Recovery slack is -13.816 (VIOLATED) 12. Path #9: Recovery slack is -13.816 (VIOLATED) 13. Path #10: Recovery slack is -13.814 (VIOLATED) 14. Path #11: Recovery slack is -13.186 (VIOLATED) 15. Path #12: Recovery slack is -13.186 (VIOLATED) 16. Path #13: Recovery slack is -13.181 (VIOLATED) 17. Path #14: Recovery slack is -13.181 (VIOLATED) 18. Path #15: Recovery slack is -13.181 (VIOLATED) 19. Path #16: Recovery slack is -13.180 (VIOLATED) 20. Path #17: Recovery slack is -13.180 (VIOLATED) 21. Path #18: Recovery slack is -13.168 (VIOLATED) 22. Path #19: Recovery slack is -13.168 (VIOLATED) 23. Path #20: Recovery slack is -13.168 (VIOLATED) 24. Path #21: Recovery slack is -8.055 (VIOLATED) 25. Path #22: Recovery slack is -8.055 (VIOLATED) 26. Path #23: Recovery slack is -8.054 (VIOLATED) 27. Path #24: Recovery slack is -8.054 (VIOLATED) 28. Path #25: Recovery slack is -8.054 (VIOLATED) 29. Path #26: Recovery slack is -8.053 (VIOLATED) 30. Path #27: Recovery slack is -8.053 (VIOLATED) 31. Path #28: Recovery slack is -8.050 (VIOLATED) 32. Path #29: Recovery slack is -8.050 (VIOLATED) 33. Path #30: Recovery slack is -8.049 (VIOLATED) 34. Path #31: Recovery slack is -7.009 (VIOLATED) 35. Path #32: Recovery slack is -7.009 (VIOLATED) 36. Path #33: Recovery slack is -7.008 (VIOLATED) 37. Path #34: Recovery slack is -7.008 (VIOLATED) 38. Path #35: Recovery slack is -7.008 (VIOLATED) 39. Path #36: Recovery slack is -7.007 (VIOLATED) 40. Path #37: Recovery slack is -7.007 (VIOLATED) 41. Path #38: Recovery slack is -7.005 (VIOLATED) 42. Path #39: Recovery slack is -7.005 (VIOLATED) 43. Path #40: Recovery slack is -7.004 (VIOLATED) 44. Command Info 45. Summary of Paths 46. Path #1: Recovery slack is -13.838 (VIOLATED) 47. Path #2: Recovery slack is -13.838 (VIOLATED) 48. Path #3: Recovery slack is -13.833 (VIOLATED) 49. Path #4: Recovery slack is -13.833 (VIOLATED) 50. Path #5: Recovery slack is -13.833 (VIOLATED) 51. Path #6: Recovery slack is -13.832 (VIOLATED) 52. Path #7: Recovery slack is -13.832 (VIOLATED) 53. Path #8: Recovery slack is -13.816 (VIOLATED) 54. Path #9: Recovery slack is -13.816 (VIOLATED) 55. Path #10: Recovery slack is -13.814 (VIOLATED) 56. Command Info 57. Summary of Paths 58. Path #1: Recovery slack is -13.186 (VIOLATED) 59. Path #2: Recovery slack is -13.186 (VIOLATED) 60. Path #3: Recovery slack is -13.181 (VIOLATED) 61. Path #4: Recovery slack is -13.181 (VIOLATED) 62. Path #5: Recovery slack is -13.181 (VIOLATED) 63. Path #6: Recovery slack is -13.180 (VIOLATED) 64. Path #7: Recovery slack is -13.180 (VIOLATED) 65. Path #8: Recovery slack is -13.168 (VIOLATED) 66. Path #9: Recovery slack is -13.168 (VIOLATED) 67. Path #10: Recovery slack is -13.168 (VIOLATED) 68. Command Info 69. Summary of Paths 70. Path #1: Recovery slack is -8.055 (VIOLATED) 71. Path #2: Recovery slack is -8.055 (VIOLATED) 72. Path #3: Recovery slack is -8.054 (VIOLATED) 73. Path #4: Recovery slack is -8.054 (VIOLATED) 74. Path #5: Recovery slack is -8.054 (VIOLATED) 75. Path #6: Recovery slack is -8.053 (VIOLATED) 76. Path #7: Recovery slack is -8.053 (VIOLATED) 77. Path #8: Recovery slack is -8.050 (VIOLATED) 78. Path #9: Recovery slack is -8.050 (VIOLATED) 79. Path #10: Recovery slack is -8.049 (VIOLATED) 80. Command Info 81. Summary of Paths 82. Path #1: Recovery slack is -7.009 (VIOLATED) 83. Path #2: Recovery slack is -7.009 (VIOLATED) 84. Path #3: Recovery slack is -7.008 (VIOLATED) 85. Path #4: Recovery slack is -7.008 (VIOLATED) 86. Path #5: Recovery slack is -7.008 (VIOLATED) 87. Path #6: Recovery slack is -7.007 (VIOLATED) 88. Path #7: Recovery slack is -7.007 (VIOLATED) 89. Path #8: Recovery slack is -7.005 (VIOLATED) 90. Path #9: Recovery slack is -7.005 (VIOLATED) 91. Path #10: Recovery slack is -7.004 (VIOLATED) ---------------- ; Legal Notice ; ---------------- Copyright (C) 2017 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. ---------------------- ; Corner Information ; ---------------------- Corners in summary: Slow 1100mV 100C Model Slow 1100mV -40C Model Fast 1100mV 100C Model Fast 1100mV -40C Model +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Summary of Paths ; +------------------------+---------+---------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+------------+------------+ ; Corner ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +------------------------+---------+---------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+------------+------------+ ; Slow 1100mV 100C Model ; -13.838 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.830 ; 6.780 ; ; Slow 1100mV 100C Model ; -13.838 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.830 ; 6.780 ; ; Slow 1100mV 100C Model ; -13.833 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.825 ; 6.780 ; ; Slow 1100mV 100C Model ; -13.833 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.825 ; 6.780 ; ; Slow 1100mV 100C Model ; -13.833 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.825 ; 6.780 ; ; Slow 1100mV 100C Model ; -13.832 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.824 ; 6.780 ; ; Slow 1100mV 100C Model ; -13.832 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.824 ; 6.780 ; ; Slow 1100mV 100C Model ; -13.816 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.808 ; 6.780 ; ; Slow 1100mV 100C Model ; -13.816 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|delayed_wrptr_g[3] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.808 ; 6.780 ; ; Slow 1100mV 100C Model ; -13.814 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.806 ; 6.780 ; ; Slow 1100mV -40C Model ; -13.186 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.634 ; 6.324 ; ; Slow 1100mV -40C Model ; -13.186 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.634 ; 6.324 ; ; Slow 1100mV -40C Model ; -13.181 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.629 ; 6.324 ; ; Slow 1100mV -40C Model ; -13.181 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.629 ; 6.324 ; ; Slow 1100mV -40C Model ; -13.181 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.629 ; 6.324 ; ; Slow 1100mV -40C Model ; -13.180 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.628 ; 6.324 ; ; Slow 1100mV -40C Model ; -13.180 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.628 ; 6.324 ; ; Slow 1100mV -40C Model ; -13.168 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.616 ; 6.324 ; ; Slow 1100mV -40C Model ; -13.168 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a5 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.616 ; 6.324 ; ; Slow 1100mV -40C Model ; -13.168 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -6.616 ; 6.324 ; ; Fast 1100mV 100C Model ; -8.055 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.460 ; 4.367 ; ; Fast 1100mV 100C Model ; -8.055 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.460 ; 4.367 ; ; Fast 1100mV 100C Model ; -8.054 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.459 ; 4.367 ; ; Fast 1100mV 100C Model ; -8.054 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.459 ; 4.367 ; ; Fast 1100mV 100C Model ; -8.054 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.459 ; 4.367 ; ; Fast 1100mV 100C Model ; -8.053 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.458 ; 4.367 ; ; Fast 1100mV 100C Model ; -8.053 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.458 ; 4.367 ; ; Fast 1100mV 100C Model ; -8.050 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.455 ; 4.367 ; ; Fast 1100mV 100C Model ; -8.050 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|delayed_wrptr_g[3] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.455 ; 4.367 ; ; Fast 1100mV 100C Model ; -8.049 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.454 ; 4.367 ; ; Fast 1100mV -40C Model ; -7.009 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.304 ; 3.477 ; ; Fast 1100mV -40C Model ; -7.009 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.304 ; 3.477 ; ; Fast 1100mV -40C Model ; -7.008 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.303 ; 3.477 ; ; Fast 1100mV -40C Model ; -7.008 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.303 ; 3.477 ; ; Fast 1100mV -40C Model ; -7.008 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.303 ; 3.477 ; ; Fast 1100mV -40C Model ; -7.007 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.302 ; 3.477 ; ; Fast 1100mV -40C Model ; -7.007 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.302 ; 3.477 ; ; Fast 1100mV -40C Model ; -7.005 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.300 ; 3.477 ; ; Fast 1100mV -40C Model ; -7.005 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|delayed_wrptr_g[3] ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.300 ; 3.477 ; ; Fast 1100mV -40C Model ; -7.004 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.002 ; -3.299 ; 3.477 ; +------------------------+---------+---------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+------------+------------+ Path #2: Recovery slack is -13.838 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.619 ; ; Data Required Time ; 16040.781 ; ; Slack ; -13.838 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.830 ; ; ; ; ; ; ; Data Delay ; 6.780 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.498 ; 57 ; 0.000 ; 2.374 ; ; Cell ; ; 5 ; 4.162 ; 43 ; 0.322 ; 1.745 ; ; PLL Compensation ; ; 1 ; -1.819 ; 0 ; -1.819 ; -1.819 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 6.117 ; 90 ; 0.284 ; 5.833 ; ; Cell ; ; 3 ; 0.663 ; 10 ; 0.000 ; 0.582 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.001 ; 59 ; 0.000 ; 1.849 ; ; Cell ; ; 5 ; 2.805 ; 41 ; 0.272 ; 1.467 ; ; PLL Compensation ; ; 1 ; -5.795 ; 0 ; -5.795 ; -5.795 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.839 ; 7.841 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.189 ; 1.191 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.517 ; 1.328 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.850 ; 0.333 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.850 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16041.031 ; -1.819 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16041.031 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.776 ; 1.745 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.572 ; 1.796 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.894 ; 0.322 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.268 ; 2.374 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.839 ; 0.571 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.619 ; 6.780 ; ; ; ; ; data path ; ; 16047.839 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.839 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.123 ; 0.284 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.204 ; 0.081 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16054.037 ; 5.833 ; FF ; IC ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[5]|clrn ; ; 16054.619 ; 0.582 ; FR ; CELL ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.011 ; 1.011 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.256 ; 0.256 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.528 ; 0.272 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.421 ; 0.893 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.726 ; 0.305 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.726 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.931 ; -5.795 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.931 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.398 ; 1.467 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.401 ; 1.003 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.680 ; 0.279 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.529 ; 1.849 ; RR ; IC ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[5]|clk ; ; 16041.011 ; 0.482 ; RR ; CELL ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; ; 16040.781 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.781 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #1: Recovery slack is -13.838 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.619 ; ; Data Required Time ; 16040.781 ; ; Slack ; -13.838 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.830 ; ; ; ; ; ; ; Data Delay ; 6.780 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.498 ; 57 ; 0.000 ; 2.374 ; ; Cell ; ; 5 ; 4.162 ; 43 ; 0.322 ; 1.745 ; ; PLL Compensation ; ; 1 ; -1.819 ; 0 ; -1.819 ; -1.819 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 6.117 ; 90 ; 0.284 ; 5.833 ; ; Cell ; ; 3 ; 0.663 ; 10 ; 0.000 ; 0.582 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.001 ; 59 ; 0.000 ; 1.849 ; ; Cell ; ; 5 ; 2.805 ; 41 ; 0.272 ; 1.467 ; ; PLL Compensation ; ; 1 ; -5.795 ; 0 ; -5.795 ; -5.795 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.839 ; 7.841 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.189 ; 1.191 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.517 ; 1.328 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.850 ; 0.333 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.850 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16041.031 ; -1.819 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16041.031 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.776 ; 1.745 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.572 ; 1.796 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.894 ; 0.322 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.268 ; 2.374 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.839 ; 0.571 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.619 ; 6.780 ; ; ; ; ; data path ; ; 16047.839 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.839 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.123 ; 0.284 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.204 ; 0.081 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16054.037 ; 5.833 ; FF ; IC ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]|clrn ; ; 16054.619 ; 0.582 ; FR ; CELL ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.011 ; 1.011 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.256 ; 0.256 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.528 ; 0.272 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.421 ; 0.893 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.726 ; 0.305 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.726 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.931 ; -5.795 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.931 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.398 ; 1.467 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.401 ; 1.003 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.680 ; 0.279 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.529 ; 1.849 ; RR ; IC ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]|clk ; ; 16041.011 ; 0.482 ; RR ; CELL ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; ; 16040.781 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.781 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #3: Recovery slack is -13.833 (VIOLATED) =============================================================================== +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.619 ; ; Data Required Time ; 16040.786 ; ; Slack ; -13.833 (VIOLATED) ; +--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.825 ; ; ; ; ; ; ; Data Delay ; 6.780 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.498 ; 57 ; 0.000 ; 2.374 ; ; Cell ; ; 5 ; 4.162 ; 43 ; 0.322 ; 1.745 ; ; PLL Compensation ; ; 1 ; -1.819 ; 0 ; -1.819 ; -1.819 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 6.117 ; 90 ; 0.284 ; 5.833 ; ; Cell ; ; 3 ; 0.663 ; 10 ; 0.000 ; 0.582 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.001 ; 59 ; 0.000 ; 1.849 ; ; Cell ; ; 5 ; 2.810 ; 41 ; 0.272 ; 1.467 ; ; PLL Compensation ; ; 1 ; -5.795 ; 0 ; -5.795 ; -5.795 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.839 ; 7.841 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.189 ; 1.191 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.517 ; 1.328 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.850 ; 0.333 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.850 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16041.031 ; -1.819 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16041.031 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.776 ; 1.745 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.572 ; 1.796 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.894 ; 0.322 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.268 ; 2.374 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.839 ; 0.571 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.619 ; 6.780 ; ; ; ; ; data path ; ; 16047.839 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.839 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.123 ; 0.284 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.204 ; 0.081 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16054.037 ; 5.833 ; FF ; IC ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|parity9|clrn ; ; 16054.619 ; 0.582 ; FR ; CELL ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; +-------------+-----------+----+------+--------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.016 ; 1.016 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.256 ; 0.256 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.528 ; 0.272 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.421 ; 0.893 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.726 ; 0.305 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.726 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.931 ; -5.795 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.931 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.398 ; 1.467 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.401 ; 1.003 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.680 ; 0.279 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.529 ; 1.849 ; RR ; IC ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|parity9|clk ; ; 16041.016 ; 0.487 ; RR ; CELL ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; ; 16040.786 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.786 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; +-------------+-----------+----+------+--------+---------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #4: Recovery slack is -13.833 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.619 ; ; Data Required Time ; 16040.786 ; ; Slack ; -13.833 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.825 ; ; ; ; ; ; ; Data Delay ; 6.780 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.498 ; 57 ; 0.000 ; 2.374 ; ; Cell ; ; 5 ; 4.162 ; 43 ; 0.322 ; 1.745 ; ; PLL Compensation ; ; 1 ; -1.819 ; 0 ; -1.819 ; -1.819 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 6.117 ; 90 ; 0.284 ; 5.833 ; ; Cell ; ; 3 ; 0.663 ; 10 ; 0.000 ; 0.582 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.001 ; 59 ; 0.000 ; 1.849 ; ; Cell ; ; 5 ; 2.810 ; 41 ; 0.272 ; 1.467 ; ; PLL Compensation ; ; 1 ; -5.795 ; 0 ; -5.795 ; -5.795 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.839 ; 7.841 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.189 ; 1.191 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.517 ; 1.328 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.850 ; 0.333 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.850 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16041.031 ; -1.819 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16041.031 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.776 ; 1.745 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.572 ; 1.796 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.894 ; 0.322 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.268 ; 2.374 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.839 ; 0.571 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.619 ; 6.780 ; ; ; ; ; data path ; ; 16047.839 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.839 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.123 ; 0.284 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.204 ; 0.081 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16054.037 ; 5.833 ; FF ; IC ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[4]|clrn ; ; 16054.619 ; 0.582 ; FR ; CELL ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.016 ; 1.016 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.256 ; 0.256 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.528 ; 0.272 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.421 ; 0.893 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.726 ; 0.305 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.726 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.931 ; -5.795 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.931 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.398 ; 1.467 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.401 ; 1.003 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.680 ; 0.279 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.529 ; 1.849 ; RR ; IC ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[4]|clk ; ; 16041.016 ; 0.487 ; RR ; CELL ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; ; 16040.786 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.786 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #5: Recovery slack is -13.833 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.619 ; ; Data Required Time ; 16040.786 ; ; Slack ; -13.833 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.825 ; ; ; ; ; ; ; Data Delay ; 6.780 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.498 ; 57 ; 0.000 ; 2.374 ; ; Cell ; ; 5 ; 4.162 ; 43 ; 0.322 ; 1.745 ; ; PLL Compensation ; ; 1 ; -1.819 ; 0 ; -1.819 ; -1.819 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 6.117 ; 90 ; 0.284 ; 5.833 ; ; Cell ; ; 3 ; 0.663 ; 10 ; 0.000 ; 0.582 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.001 ; 59 ; 0.000 ; 1.849 ; ; Cell ; ; 5 ; 2.810 ; 41 ; 0.272 ; 1.467 ; ; PLL Compensation ; ; 1 ; -5.795 ; 0 ; -5.795 ; -5.795 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.839 ; 7.841 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.189 ; 1.191 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.517 ; 1.328 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.850 ; 0.333 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.850 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16041.031 ; -1.819 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16041.031 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.776 ; 1.745 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.572 ; 1.796 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.894 ; 0.322 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.268 ; 2.374 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.839 ; 0.571 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.619 ; 6.780 ; ; ; ; ; data path ; ; 16047.839 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.839 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.123 ; 0.284 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.204 ; 0.081 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16054.037 ; 5.833 ; FF ; IC ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[2]|clrn ; ; 16054.619 ; 0.582 ; FR ; CELL ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.016 ; 1.016 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.256 ; 0.256 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.528 ; 0.272 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.421 ; 0.893 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.726 ; 0.305 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.726 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.931 ; -5.795 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.931 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.398 ; 1.467 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.401 ; 1.003 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.680 ; 0.279 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.529 ; 1.849 ; RR ; IC ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[2]|clk ; ; 16041.016 ; 0.487 ; RR ; CELL ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; ; 16040.786 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.786 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #6: Recovery slack is -13.832 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.619 ; ; Data Required Time ; 16040.787 ; ; Slack ; -13.832 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.824 ; ; ; ; ; ; ; Data Delay ; 6.780 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.498 ; 57 ; 0.000 ; 2.374 ; ; Cell ; ; 5 ; 4.162 ; 43 ; 0.322 ; 1.745 ; ; PLL Compensation ; ; 1 ; -1.819 ; 0 ; -1.819 ; -1.819 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 6.117 ; 90 ; 0.284 ; 5.833 ; ; Cell ; ; 3 ; 0.663 ; 10 ; 0.000 ; 0.582 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.001 ; 59 ; 0.000 ; 1.849 ; ; Cell ; ; 5 ; 2.811 ; 41 ; 0.272 ; 1.467 ; ; PLL Compensation ; ; 1 ; -5.795 ; 0 ; -5.795 ; -5.795 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.839 ; 7.841 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.189 ; 1.191 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.517 ; 1.328 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.850 ; 0.333 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.850 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16041.031 ; -1.819 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16041.031 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.776 ; 1.745 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.572 ; 1.796 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.894 ; 0.322 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.268 ; 2.374 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.839 ; 0.571 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.619 ; 6.780 ; ; ; ; ; data path ; ; 16047.839 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.839 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.123 ; 0.284 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.204 ; 0.081 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16054.037 ; 5.833 ; FF ; IC ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|sub_parity10a[1]|clrn ; ; 16054.619 ; 0.582 ; FR ; CELL ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.017 ; 1.017 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.256 ; 0.256 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.528 ; 0.272 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.421 ; 0.893 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.726 ; 0.305 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.726 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.931 ; -5.795 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.931 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.398 ; 1.467 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.401 ; 1.003 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.680 ; 0.279 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.529 ; 1.849 ; RR ; IC ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|sub_parity10a[1]|clk ; ; 16041.017 ; 0.488 ; RR ; CELL ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; ; 16040.787 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.787 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #7: Recovery slack is -13.832 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.619 ; ; Data Required Time ; 16040.787 ; ; Slack ; -13.832 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.824 ; ; ; ; ; ; ; Data Delay ; 6.780 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.498 ; 57 ; 0.000 ; 2.374 ; ; Cell ; ; 5 ; 4.162 ; 43 ; 0.322 ; 1.745 ; ; PLL Compensation ; ; 1 ; -1.819 ; 0 ; -1.819 ; -1.819 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 6.117 ; 90 ; 0.284 ; 5.833 ; ; Cell ; ; 3 ; 0.663 ; 10 ; 0.000 ; 0.582 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.001 ; 59 ; 0.000 ; 1.849 ; ; Cell ; ; 5 ; 2.811 ; 41 ; 0.272 ; 1.467 ; ; PLL Compensation ; ; 1 ; -5.795 ; 0 ; -5.795 ; -5.795 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.839 ; 7.841 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.189 ; 1.191 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.517 ; 1.328 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.850 ; 0.333 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.850 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16041.031 ; -1.819 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16041.031 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.776 ; 1.745 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.572 ; 1.796 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.894 ; 0.322 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.268 ; 2.374 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.839 ; 0.571 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.619 ; 6.780 ; ; ; ; ; data path ; ; 16047.839 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.839 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.123 ; 0.284 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.204 ; 0.081 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16054.037 ; 5.833 ; FF ; IC ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]~DUPLICATE|clrn ; ; 16054.619 ; 0.582 ; FR ; CELL ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.017 ; 1.017 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.256 ; 0.256 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.528 ; 0.272 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.421 ; 0.893 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.726 ; 0.305 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.726 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.931 ; -5.795 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.931 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.398 ; 1.467 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.401 ; 1.003 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.680 ; 0.279 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.529 ; 1.849 ; RR ; IC ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]~DUPLICATE|clk ; ; 16041.017 ; 0.488 ; RR ; CELL ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; ; 16040.787 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.787 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #8: Recovery slack is -13.816 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.619 ; ; Data Required Time ; 16040.803 ; ; Slack ; -13.816 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.808 ; ; ; ; ; ; ; Data Delay ; 6.780 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.498 ; 57 ; 0.000 ; 2.374 ; ; Cell ; ; 5 ; 4.162 ; 43 ; 0.322 ; 1.745 ; ; PLL Compensation ; ; 1 ; -1.819 ; 0 ; -1.819 ; -1.819 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 6.117 ; 90 ; 0.284 ; 5.833 ; ; Cell ; ; 3 ; 0.663 ; 10 ; 0.000 ; 0.582 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.001 ; 59 ; 0.000 ; 1.849 ; ; Cell ; ; 5 ; 2.827 ; 41 ; 0.272 ; 1.467 ; ; PLL Compensation ; ; 1 ; -5.795 ; 0 ; -5.795 ; -5.795 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.839 ; 7.841 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.189 ; 1.191 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.517 ; 1.328 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.850 ; 0.333 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.850 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16041.031 ; -1.819 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16041.031 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.776 ; 1.745 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.572 ; 1.796 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.894 ; 0.322 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.268 ; 2.374 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.839 ; 0.571 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.619 ; 6.780 ; ; ; ; ; data path ; ; 16047.839 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.839 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.123 ; 0.284 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.204 ; 0.081 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16054.037 ; 5.833 ; FF ; IC ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a6|clrn ; ; 16054.619 ; 0.582 ; FR ; CELL ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.033 ; 1.033 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.256 ; 0.256 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.528 ; 0.272 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.421 ; 0.893 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.726 ; 0.305 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.726 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.931 ; -5.795 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.931 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.398 ; 1.467 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.401 ; 1.003 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.680 ; 0.279 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.529 ; 1.849 ; RR ; IC ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a6|clk ; ; 16041.033 ; 0.504 ; RR ; CELL ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; ; 16040.803 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.803 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #9: Recovery slack is -13.816 (VIOLATED) =============================================================================== +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|delayed_wrptr_g[3] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.619 ; ; Data Required Time ; 16040.803 ; ; Slack ; -13.816 (VIOLATED) ; +--------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.808 ; ; ; ; ; ; ; Data Delay ; 6.780 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.498 ; 57 ; 0.000 ; 2.374 ; ; Cell ; ; 5 ; 4.162 ; 43 ; 0.322 ; 1.745 ; ; PLL Compensation ; ; 1 ; -1.819 ; 0 ; -1.819 ; -1.819 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 6.117 ; 90 ; 0.284 ; 5.833 ; ; Cell ; ; 3 ; 0.663 ; 10 ; 0.000 ; 0.582 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.001 ; 59 ; 0.000 ; 1.849 ; ; Cell ; ; 5 ; 2.827 ; 41 ; 0.272 ; 1.467 ; ; PLL Compensation ; ; 1 ; -5.795 ; 0 ; -5.795 ; -5.795 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.839 ; 7.841 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.189 ; 1.191 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.517 ; 1.328 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.850 ; 0.333 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.850 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16041.031 ; -1.819 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16041.031 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.776 ; 1.745 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.572 ; 1.796 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.894 ; 0.322 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.268 ; 2.374 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.839 ; 0.571 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.619 ; 6.780 ; ; ; ; ; data path ; ; 16047.839 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.839 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.123 ; 0.284 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.204 ; 0.081 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16054.037 ; 5.833 ; FF ; IC ; 1 ; FF_X50_Y22_N16 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|delayed_wrptr_g[3]|clrn ; ; 16054.619 ; 0.582 ; FR ; CELL ; 1 ; FF_X50_Y22_N16 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|delayed_wrptr_g[3] ; +-------------+-----------+----+------+--------+----------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.033 ; 1.033 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.256 ; 0.256 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.528 ; 0.272 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.421 ; 0.893 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.726 ; 0.305 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.726 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.931 ; -5.795 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.931 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.398 ; 1.467 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.401 ; 1.003 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.680 ; 0.279 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.529 ; 1.849 ; RR ; IC ; 1 ; FF_X50_Y22_N16 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|delayed_wrptr_g[3]|clk ; ; 16041.033 ; 0.504 ; RR ; CELL ; 1 ; FF_X50_Y22_N16 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|delayed_wrptr_g[3] ; ; 16040.803 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.803 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N16 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|delayed_wrptr_g[3] ; +-------------+-----------+----+------+--------+---------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #10: Recovery slack is -13.814 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.619 ; ; Data Required Time ; 16040.805 ; ; Slack ; -13.814 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.806 ; ; ; ; ; ; ; Data Delay ; 6.780 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.498 ; 57 ; 0.000 ; 2.374 ; ; Cell ; ; 5 ; 4.162 ; 43 ; 0.322 ; 1.745 ; ; PLL Compensation ; ; 1 ; -1.819 ; 0 ; -1.819 ; -1.819 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 6.117 ; 90 ; 0.284 ; 5.833 ; ; Cell ; ; 3 ; 0.663 ; 10 ; 0.000 ; 0.582 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.001 ; 59 ; 0.000 ; 1.849 ; ; Cell ; ; 5 ; 2.829 ; 41 ; 0.272 ; 1.467 ; ; PLL Compensation ; ; 1 ; -5.795 ; 0 ; -5.795 ; -5.795 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.839 ; 7.841 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.189 ; 1.191 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.517 ; 1.328 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.850 ; 0.333 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.850 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16041.031 ; -1.819 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16041.031 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.776 ; 1.745 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.572 ; 1.796 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.894 ; 0.322 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.268 ; 2.374 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.839 ; 0.571 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.619 ; 6.780 ; ; ; ; ; data path ; ; 16047.839 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.839 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.123 ; 0.284 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.204 ; 0.081 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16054.037 ; 5.833 ; FF ; IC ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a3|clrn ; ; 16054.619 ; 0.582 ; FR ; CELL ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.035 ; 1.035 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.256 ; 0.256 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.528 ; 0.272 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.421 ; 0.893 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.726 ; 0.305 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.726 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.931 ; -5.795 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.931 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.398 ; 1.467 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.401 ; 1.003 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.680 ; 0.279 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.529 ; 1.849 ; RR ; IC ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a3|clk ; ; 16041.035 ; 0.506 ; RR ; CELL ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; ; 16040.805 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.805 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #11: Recovery slack is -13.186 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.104 ; ; Data Required Time ; 16040.918 ; ; Slack ; -13.186 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.634 ; ; ; ; ; ; ; Data Delay ; 6.324 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.594 ; 57 ; 0.000 ; 2.508 ; ; Cell ; ; 5 ; 4.136 ; 43 ; 0.330 ; 1.663 ; ; PLL Compensation ; ; 1 ; -1.948 ; 0 ; -1.948 ; -1.948 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 5.659 ; 89 ; 0.248 ; 5.411 ; ; Cell ; ; 3 ; 0.665 ; 11 ; 0.000 ; 0.577 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.211 ; 60 ; 0.000 ; 1.973 ; ; Cell ; ; 5 ; 2.841 ; 40 ; 0.306 ; 1.463 ; ; PLL Compensation ; ; 1 ; -5.904 ; 0 ; -5.904 ; -5.904 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.780 ; 7.782 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.260 ; 1.262 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.575 ; 1.315 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.905 ; 0.330 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.905 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.957 ; -1.948 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.957 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.620 ; 1.663 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.391 ; 1.771 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.745 ; 0.354 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.253 ; 2.508 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.780 ; 0.527 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.104 ; 6.324 ; ; ; ; ; data path ; ; 16047.780 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.780 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.028 ; 0.248 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.116 ; 0.088 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16053.527 ; 5.411 ; FF ; IC ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]|clrn ; ; 16054.104 ; 0.577 ; FR ; CELL ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.148 ; 1.148 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.247 ; 0.247 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.553 ; 0.306 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.520 ; 0.967 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.828 ; 0.308 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.828 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.924 ; -5.904 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.924 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.387 ; 1.463 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.411 ; 1.024 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.724 ; 0.313 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.697 ; 1.973 ; RR ; IC ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]|clk ; ; 16041.148 ; 0.451 ; RR ; CELL ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; ; 16040.918 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.918 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #12: Recovery slack is -13.186 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.104 ; ; Data Required Time ; 16040.918 ; ; Slack ; -13.186 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.634 ; ; ; ; ; ; ; Data Delay ; 6.324 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.594 ; 57 ; 0.000 ; 2.508 ; ; Cell ; ; 5 ; 4.136 ; 43 ; 0.330 ; 1.663 ; ; PLL Compensation ; ; 1 ; -1.948 ; 0 ; -1.948 ; -1.948 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 5.659 ; 89 ; 0.248 ; 5.411 ; ; Cell ; ; 3 ; 0.665 ; 11 ; 0.000 ; 0.577 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.211 ; 60 ; 0.000 ; 1.973 ; ; Cell ; ; 5 ; 2.841 ; 40 ; 0.306 ; 1.463 ; ; PLL Compensation ; ; 1 ; -5.904 ; 0 ; -5.904 ; -5.904 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.780 ; 7.782 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.260 ; 1.262 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.575 ; 1.315 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.905 ; 0.330 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.905 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.957 ; -1.948 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.957 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.620 ; 1.663 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.391 ; 1.771 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.745 ; 0.354 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.253 ; 2.508 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.780 ; 0.527 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.104 ; 6.324 ; ; ; ; ; data path ; ; 16047.780 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.780 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.028 ; 0.248 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.116 ; 0.088 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16053.527 ; 5.411 ; FF ; IC ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[5]|clrn ; ; 16054.104 ; 0.577 ; FR ; CELL ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.148 ; 1.148 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.247 ; 0.247 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.553 ; 0.306 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.520 ; 0.967 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.828 ; 0.308 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.828 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.924 ; -5.904 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.924 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.387 ; 1.463 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.411 ; 1.024 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.724 ; 0.313 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.697 ; 1.973 ; RR ; IC ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[5]|clk ; ; 16041.148 ; 0.451 ; RR ; CELL ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; ; 16040.918 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.918 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #13: Recovery slack is -13.181 (VIOLATED) =============================================================================== +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.104 ; ; Data Required Time ; 16040.923 ; ; Slack ; -13.181 (VIOLATED) ; +--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.629 ; ; ; ; ; ; ; Data Delay ; 6.324 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.594 ; 57 ; 0.000 ; 2.508 ; ; Cell ; ; 5 ; 4.136 ; 43 ; 0.330 ; 1.663 ; ; PLL Compensation ; ; 1 ; -1.948 ; 0 ; -1.948 ; -1.948 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 5.659 ; 89 ; 0.248 ; 5.411 ; ; Cell ; ; 3 ; 0.665 ; 11 ; 0.000 ; 0.577 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.211 ; 60 ; 0.000 ; 1.973 ; ; Cell ; ; 5 ; 2.846 ; 40 ; 0.306 ; 1.463 ; ; PLL Compensation ; ; 1 ; -5.904 ; 0 ; -5.904 ; -5.904 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.780 ; 7.782 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.260 ; 1.262 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.575 ; 1.315 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.905 ; 0.330 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.905 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.957 ; -1.948 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.957 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.620 ; 1.663 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.391 ; 1.771 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.745 ; 0.354 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.253 ; 2.508 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.780 ; 0.527 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.104 ; 6.324 ; ; ; ; ; data path ; ; 16047.780 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.780 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.028 ; 0.248 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.116 ; 0.088 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16053.527 ; 5.411 ; FF ; IC ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|parity9|clrn ; ; 16054.104 ; 0.577 ; FR ; CELL ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; +-------------+-----------+----+------+--------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.153 ; 1.153 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.247 ; 0.247 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.553 ; 0.306 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.520 ; 0.967 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.828 ; 0.308 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.828 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.924 ; -5.904 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.924 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.387 ; 1.463 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.411 ; 1.024 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.724 ; 0.313 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.697 ; 1.973 ; RR ; IC ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|parity9|clk ; ; 16041.153 ; 0.456 ; RR ; CELL ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; ; 16040.923 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.923 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; +-------------+-----------+----+------+--------+---------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #14: Recovery slack is -13.181 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.104 ; ; Data Required Time ; 16040.923 ; ; Slack ; -13.181 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.629 ; ; ; ; ; ; ; Data Delay ; 6.324 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.594 ; 57 ; 0.000 ; 2.508 ; ; Cell ; ; 5 ; 4.136 ; 43 ; 0.330 ; 1.663 ; ; PLL Compensation ; ; 1 ; -1.948 ; 0 ; -1.948 ; -1.948 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 5.659 ; 89 ; 0.248 ; 5.411 ; ; Cell ; ; 3 ; 0.665 ; 11 ; 0.000 ; 0.577 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.211 ; 60 ; 0.000 ; 1.973 ; ; Cell ; ; 5 ; 2.846 ; 40 ; 0.306 ; 1.463 ; ; PLL Compensation ; ; 1 ; -5.904 ; 0 ; -5.904 ; -5.904 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.780 ; 7.782 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.260 ; 1.262 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.575 ; 1.315 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.905 ; 0.330 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.905 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.957 ; -1.948 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.957 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.620 ; 1.663 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.391 ; 1.771 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.745 ; 0.354 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.253 ; 2.508 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.780 ; 0.527 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.104 ; 6.324 ; ; ; ; ; data path ; ; 16047.780 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.780 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.028 ; 0.248 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.116 ; 0.088 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16053.527 ; 5.411 ; FF ; IC ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[4]|clrn ; ; 16054.104 ; 0.577 ; FR ; CELL ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.153 ; 1.153 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.247 ; 0.247 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.553 ; 0.306 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.520 ; 0.967 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.828 ; 0.308 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.828 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.924 ; -5.904 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.924 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.387 ; 1.463 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.411 ; 1.024 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.724 ; 0.313 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.697 ; 1.973 ; RR ; IC ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[4]|clk ; ; 16041.153 ; 0.456 ; RR ; CELL ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; ; 16040.923 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.923 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #15: Recovery slack is -13.181 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.104 ; ; Data Required Time ; 16040.923 ; ; Slack ; -13.181 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.629 ; ; ; ; ; ; ; Data Delay ; 6.324 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.594 ; 57 ; 0.000 ; 2.508 ; ; Cell ; ; 5 ; 4.136 ; 43 ; 0.330 ; 1.663 ; ; PLL Compensation ; ; 1 ; -1.948 ; 0 ; -1.948 ; -1.948 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 5.659 ; 89 ; 0.248 ; 5.411 ; ; Cell ; ; 3 ; 0.665 ; 11 ; 0.000 ; 0.577 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.211 ; 60 ; 0.000 ; 1.973 ; ; Cell ; ; 5 ; 2.846 ; 40 ; 0.306 ; 1.463 ; ; PLL Compensation ; ; 1 ; -5.904 ; 0 ; -5.904 ; -5.904 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.780 ; 7.782 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.260 ; 1.262 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.575 ; 1.315 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.905 ; 0.330 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.905 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.957 ; -1.948 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.957 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.620 ; 1.663 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.391 ; 1.771 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.745 ; 0.354 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.253 ; 2.508 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.780 ; 0.527 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.104 ; 6.324 ; ; ; ; ; data path ; ; 16047.780 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.780 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.028 ; 0.248 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.116 ; 0.088 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16053.527 ; 5.411 ; FF ; IC ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[2]|clrn ; ; 16054.104 ; 0.577 ; FR ; CELL ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.153 ; 1.153 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.247 ; 0.247 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.553 ; 0.306 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.520 ; 0.967 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.828 ; 0.308 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.828 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.924 ; -5.904 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.924 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.387 ; 1.463 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.411 ; 1.024 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.724 ; 0.313 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.697 ; 1.973 ; RR ; IC ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[2]|clk ; ; 16041.153 ; 0.456 ; RR ; CELL ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; ; 16040.923 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.923 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #16: Recovery slack is -13.180 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.104 ; ; Data Required Time ; 16040.924 ; ; Slack ; -13.180 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.628 ; ; ; ; ; ; ; Data Delay ; 6.324 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.594 ; 57 ; 0.000 ; 2.508 ; ; Cell ; ; 5 ; 4.136 ; 43 ; 0.330 ; 1.663 ; ; PLL Compensation ; ; 1 ; -1.948 ; 0 ; -1.948 ; -1.948 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 5.659 ; 89 ; 0.248 ; 5.411 ; ; Cell ; ; 3 ; 0.665 ; 11 ; 0.000 ; 0.577 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.211 ; 60 ; 0.000 ; 1.973 ; ; Cell ; ; 5 ; 2.847 ; 40 ; 0.306 ; 1.463 ; ; PLL Compensation ; ; 1 ; -5.904 ; 0 ; -5.904 ; -5.904 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.780 ; 7.782 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.260 ; 1.262 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.575 ; 1.315 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.905 ; 0.330 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.905 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.957 ; -1.948 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.957 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.620 ; 1.663 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.391 ; 1.771 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.745 ; 0.354 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.253 ; 2.508 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.780 ; 0.527 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.104 ; 6.324 ; ; ; ; ; data path ; ; 16047.780 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.780 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.028 ; 0.248 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.116 ; 0.088 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16053.527 ; 5.411 ; FF ; IC ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|sub_parity10a[1]|clrn ; ; 16054.104 ; 0.577 ; FR ; CELL ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.154 ; 1.154 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.247 ; 0.247 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.553 ; 0.306 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.520 ; 0.967 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.828 ; 0.308 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.828 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.924 ; -5.904 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.924 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.387 ; 1.463 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.411 ; 1.024 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.724 ; 0.313 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.697 ; 1.973 ; RR ; IC ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|sub_parity10a[1]|clk ; ; 16041.154 ; 0.457 ; RR ; CELL ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; ; 16040.924 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.924 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #17: Recovery slack is -13.180 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.104 ; ; Data Required Time ; 16040.924 ; ; Slack ; -13.180 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.628 ; ; ; ; ; ; ; Data Delay ; 6.324 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.594 ; 57 ; 0.000 ; 2.508 ; ; Cell ; ; 5 ; 4.136 ; 43 ; 0.330 ; 1.663 ; ; PLL Compensation ; ; 1 ; -1.948 ; 0 ; -1.948 ; -1.948 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 5.659 ; 89 ; 0.248 ; 5.411 ; ; Cell ; ; 3 ; 0.665 ; 11 ; 0.000 ; 0.577 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.211 ; 60 ; 0.000 ; 1.973 ; ; Cell ; ; 5 ; 2.847 ; 40 ; 0.306 ; 1.463 ; ; PLL Compensation ; ; 1 ; -5.904 ; 0 ; -5.904 ; -5.904 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.780 ; 7.782 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.260 ; 1.262 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.575 ; 1.315 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.905 ; 0.330 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.905 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.957 ; -1.948 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.957 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.620 ; 1.663 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.391 ; 1.771 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.745 ; 0.354 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.253 ; 2.508 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.780 ; 0.527 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.104 ; 6.324 ; ; ; ; ; data path ; ; 16047.780 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.780 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.028 ; 0.248 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.116 ; 0.088 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16053.527 ; 5.411 ; FF ; IC ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]~DUPLICATE|clrn ; ; 16054.104 ; 0.577 ; FR ; CELL ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.154 ; 1.154 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.247 ; 0.247 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.553 ; 0.306 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.520 ; 0.967 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.828 ; 0.308 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.828 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.924 ; -5.904 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.924 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.387 ; 1.463 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.411 ; 1.024 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.724 ; 0.313 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.697 ; 1.973 ; RR ; IC ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]~DUPLICATE|clk ; ; 16041.154 ; 0.457 ; RR ; CELL ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; ; 16040.924 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.924 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #18: Recovery slack is -13.168 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.104 ; ; Data Required Time ; 16040.936 ; ; Slack ; -13.168 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.616 ; ; ; ; ; ; ; Data Delay ; 6.324 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.594 ; 57 ; 0.000 ; 2.508 ; ; Cell ; ; 5 ; 4.136 ; 43 ; 0.330 ; 1.663 ; ; PLL Compensation ; ; 1 ; -1.948 ; 0 ; -1.948 ; -1.948 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 5.659 ; 89 ; 0.248 ; 5.411 ; ; Cell ; ; 3 ; 0.665 ; 11 ; 0.000 ; 0.577 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.211 ; 60 ; 0.000 ; 1.973 ; ; Cell ; ; 5 ; 2.859 ; 40 ; 0.306 ; 1.463 ; ; PLL Compensation ; ; 1 ; -5.904 ; 0 ; -5.904 ; -5.904 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.780 ; 7.782 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.260 ; 1.262 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.575 ; 1.315 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.905 ; 0.330 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.905 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.957 ; -1.948 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.957 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.620 ; 1.663 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.391 ; 1.771 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.745 ; 0.354 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.253 ; 2.508 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.780 ; 0.527 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.104 ; 6.324 ; ; ; ; ; data path ; ; 16047.780 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.780 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.028 ; 0.248 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.116 ; 0.088 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16053.527 ; 5.411 ; FF ; IC ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a3|clrn ; ; 16054.104 ; 0.577 ; FR ; CELL ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.166 ; 1.166 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.247 ; 0.247 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.553 ; 0.306 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.520 ; 0.967 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.828 ; 0.308 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.828 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.924 ; -5.904 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.924 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.387 ; 1.463 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.411 ; 1.024 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.724 ; 0.313 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.697 ; 1.973 ; RR ; IC ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a3|clk ; ; 16041.166 ; 0.469 ; RR ; CELL ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; ; 16040.936 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.936 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #19: Recovery slack is -13.168 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a5 ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.104 ; ; Data Required Time ; 16040.936 ; ; Slack ; -13.168 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.616 ; ; ; ; ; ; ; Data Delay ; 6.324 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.594 ; 57 ; 0.000 ; 2.508 ; ; Cell ; ; 5 ; 4.136 ; 43 ; 0.330 ; 1.663 ; ; PLL Compensation ; ; 1 ; -1.948 ; 0 ; -1.948 ; -1.948 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 5.659 ; 89 ; 0.248 ; 5.411 ; ; Cell ; ; 3 ; 0.665 ; 11 ; 0.000 ; 0.577 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.211 ; 60 ; 0.000 ; 1.973 ; ; Cell ; ; 5 ; 2.859 ; 40 ; 0.306 ; 1.463 ; ; PLL Compensation ; ; 1 ; -5.904 ; 0 ; -5.904 ; -5.904 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.780 ; 7.782 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.260 ; 1.262 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.575 ; 1.315 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.905 ; 0.330 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.905 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.957 ; -1.948 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.957 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.620 ; 1.663 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.391 ; 1.771 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.745 ; 0.354 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.253 ; 2.508 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.780 ; 0.527 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.104 ; 6.324 ; ; ; ; ; data path ; ; 16047.780 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.780 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.028 ; 0.248 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.116 ; 0.088 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16053.527 ; 5.411 ; FF ; IC ; 1 ; FF_X50_Y22_N20 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a5|clrn ; ; 16054.104 ; 0.577 ; FR ; CELL ; 1 ; FF_X50_Y22_N20 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a5 ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.166 ; 1.166 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.247 ; 0.247 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.553 ; 0.306 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.520 ; 0.967 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.828 ; 0.308 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.828 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.924 ; -5.904 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.924 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.387 ; 1.463 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.411 ; 1.024 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.724 ; 0.313 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.697 ; 1.973 ; RR ; IC ; 1 ; FF_X50_Y22_N20 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a5|clk ; ; 16041.166 ; 0.469 ; RR ; CELL ; 1 ; FF_X50_Y22_N20 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a5 ; ; 16040.936 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.936 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N20 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a5 ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #20: Recovery slack is -13.168 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16054.104 ; ; Data Required Time ; 16040.936 ; ; Slack ; -13.168 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -6.616 ; ; ; ; ; ; ; Data Delay ; 6.324 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 5.594 ; 57 ; 0.000 ; 2.508 ; ; Cell ; ; 5 ; 4.136 ; 43 ; 0.330 ; 1.663 ; ; PLL Compensation ; ; 1 ; -1.948 ; 0 ; -1.948 ; -1.948 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 5.659 ; 89 ; 0.248 ; 5.411 ; ; Cell ; ; 3 ; 0.665 ; 11 ; 0.000 ; 0.577 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 4.211 ; 60 ; 0.000 ; 1.973 ; ; Cell ; ; 5 ; 2.859 ; 40 ; 0.306 ; 1.463 ; ; PLL Compensation ; ; 1 ; -5.904 ; 0 ; -5.904 ; -5.904 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16047.780 ; 7.782 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16041.260 ; 1.262 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16042.575 ; 1.315 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16042.905 ; 0.330 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16042.905 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.957 ; -1.948 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.957 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16042.620 ; 1.663 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16044.391 ; 1.771 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16044.745 ; 0.354 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16047.253 ; 2.508 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16047.780 ; 0.527 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16054.104 ; 6.324 ; ; ; ; ; data path ; ; 16047.780 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.780 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16048.028 ; 0.248 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16048.116 ; 0.088 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16053.527 ; 5.411 ; FF ; IC ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a6|clrn ; ; 16054.104 ; 0.577 ; FR ; CELL ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16041.166 ; 1.166 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.247 ; 0.247 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.553 ; 0.306 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16041.520 ; 0.967 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16041.828 ; 0.308 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.828 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16035.924 ; -5.904 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16035.924 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16037.387 ; 1.463 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16038.411 ; 1.024 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16038.724 ; 0.313 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.697 ; 1.973 ; RR ; IC ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a6|clk ; ; 16041.166 ; 0.469 ; RR ; CELL ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; ; 16040.936 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.936 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #21: Recovery slack is -8.055 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16048.241 ; ; Data Required Time ; 16040.186 ; ; Slack ; -8.055 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.460 ; ; ; ; ; ; ; Data Delay ; 4.367 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.633 ; 54 ; 0.000 ; 1.190 ; ; Cell ; ; 5 ; 2.255 ; 46 ; 0.157 ; 0.970 ; ; PLL Compensation ; ; 1 ; -1.012 ; 0 ; -1.012 ; -1.012 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 4.093 ; 94 ; 0.149 ; 3.944 ; ; Cell ; ; 3 ; 0.274 ; 6 ; 0.000 ; 0.234 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.038 ; 58 ; 0.000 ; 0.943 ; ; Cell ; ; 5 ; 1.461 ; 42 ; 0.137 ; 0.829 ; ; PLL Compensation ; ; 1 ; -3.083 ; 0 ; -3.083 ; -3.083 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.874 ; 3.876 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.733 ; 0.735 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.349 ; 0.616 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.508 ; 0.159 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.508 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.496 ; -1.012 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.496 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.466 ; 0.970 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.293 ; 0.827 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.450 ; 0.157 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.640 ; 1.190 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.874 ; 0.234 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16048.241 ; 4.367 ; ; ; ; ; data path ; ; 16043.874 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.874 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16044.023 ; 0.149 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16044.063 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16048.007 ; 3.944 ; FF ; IC ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]|clrn ; ; 16048.241 ; 0.234 ; FR ; CELL ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.416 ; 0.416 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.108 ; 0.108 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.245 ; 0.137 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.733 ; 0.488 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.881 ; 0.148 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.881 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.798 ; -3.083 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.798 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.627 ; 0.829 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.126 ; 0.499 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.267 ; 0.141 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.210 ; 0.943 ; RR ; IC ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]|clk ; ; 16040.416 ; 0.206 ; RR ; CELL ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; ; 16040.186 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.186 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #22: Recovery slack is -8.055 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16048.241 ; ; Data Required Time ; 16040.186 ; ; Slack ; -8.055 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.460 ; ; ; ; ; ; ; Data Delay ; 4.367 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.633 ; 54 ; 0.000 ; 1.190 ; ; Cell ; ; 5 ; 2.255 ; 46 ; 0.157 ; 0.970 ; ; PLL Compensation ; ; 1 ; -1.012 ; 0 ; -1.012 ; -1.012 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 4.093 ; 94 ; 0.149 ; 3.944 ; ; Cell ; ; 3 ; 0.274 ; 6 ; 0.000 ; 0.234 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.038 ; 58 ; 0.000 ; 0.943 ; ; Cell ; ; 5 ; 1.461 ; 42 ; 0.137 ; 0.829 ; ; PLL Compensation ; ; 1 ; -3.083 ; 0 ; -3.083 ; -3.083 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.874 ; 3.876 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.733 ; 0.735 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.349 ; 0.616 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.508 ; 0.159 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.508 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.496 ; -1.012 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.496 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.466 ; 0.970 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.293 ; 0.827 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.450 ; 0.157 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.640 ; 1.190 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.874 ; 0.234 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16048.241 ; 4.367 ; ; ; ; ; data path ; ; 16043.874 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.874 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16044.023 ; 0.149 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16044.063 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16048.007 ; 3.944 ; FF ; IC ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[5]|clrn ; ; 16048.241 ; 0.234 ; FR ; CELL ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.416 ; 0.416 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.108 ; 0.108 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.245 ; 0.137 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.733 ; 0.488 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.881 ; 0.148 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.881 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.798 ; -3.083 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.798 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.627 ; 0.829 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.126 ; 0.499 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.267 ; 0.141 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.210 ; 0.943 ; RR ; IC ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[5]|clk ; ; 16040.416 ; 0.206 ; RR ; CELL ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; ; 16040.186 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.186 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #23: Recovery slack is -8.054 (VIOLATED) =============================================================================== +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16048.241 ; ; Data Required Time ; 16040.187 ; ; Slack ; -8.054 (VIOLATED) ; +--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.459 ; ; ; ; ; ; ; Data Delay ; 4.367 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.633 ; 54 ; 0.000 ; 1.190 ; ; Cell ; ; 5 ; 2.255 ; 46 ; 0.157 ; 0.970 ; ; PLL Compensation ; ; 1 ; -1.012 ; 0 ; -1.012 ; -1.012 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 4.093 ; 94 ; 0.149 ; 3.944 ; ; Cell ; ; 3 ; 0.274 ; 6 ; 0.000 ; 0.234 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.038 ; 58 ; 0.000 ; 0.943 ; ; Cell ; ; 5 ; 1.462 ; 42 ; 0.137 ; 0.829 ; ; PLL Compensation ; ; 1 ; -3.083 ; 0 ; -3.083 ; -3.083 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.874 ; 3.876 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.733 ; 0.735 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.349 ; 0.616 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.508 ; 0.159 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.508 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.496 ; -1.012 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.496 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.466 ; 0.970 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.293 ; 0.827 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.450 ; 0.157 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.640 ; 1.190 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.874 ; 0.234 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16048.241 ; 4.367 ; ; ; ; ; data path ; ; 16043.874 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.874 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16044.023 ; 0.149 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16044.063 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16048.007 ; 3.944 ; FF ; IC ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|parity9|clrn ; ; 16048.241 ; 0.234 ; FR ; CELL ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; +-------------+-----------+----+------+--------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.417 ; 0.417 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.108 ; 0.108 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.245 ; 0.137 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.733 ; 0.488 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.881 ; 0.148 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.881 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.798 ; -3.083 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.798 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.627 ; 0.829 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.126 ; 0.499 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.267 ; 0.141 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.210 ; 0.943 ; RR ; IC ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|parity9|clk ; ; 16040.417 ; 0.207 ; RR ; CELL ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; ; 16040.187 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.187 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; +-------------+-----------+----+------+--------+---------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #24: Recovery slack is -8.054 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16048.241 ; ; Data Required Time ; 16040.187 ; ; Slack ; -8.054 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.459 ; ; ; ; ; ; ; Data Delay ; 4.367 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.633 ; 54 ; 0.000 ; 1.190 ; ; Cell ; ; 5 ; 2.255 ; 46 ; 0.157 ; 0.970 ; ; PLL Compensation ; ; 1 ; -1.012 ; 0 ; -1.012 ; -1.012 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 4.093 ; 94 ; 0.149 ; 3.944 ; ; Cell ; ; 3 ; 0.274 ; 6 ; 0.000 ; 0.234 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.038 ; 58 ; 0.000 ; 0.943 ; ; Cell ; ; 5 ; 1.462 ; 42 ; 0.137 ; 0.829 ; ; PLL Compensation ; ; 1 ; -3.083 ; 0 ; -3.083 ; -3.083 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.874 ; 3.876 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.733 ; 0.735 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.349 ; 0.616 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.508 ; 0.159 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.508 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.496 ; -1.012 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.496 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.466 ; 0.970 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.293 ; 0.827 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.450 ; 0.157 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.640 ; 1.190 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.874 ; 0.234 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16048.241 ; 4.367 ; ; ; ; ; data path ; ; 16043.874 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.874 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16044.023 ; 0.149 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16044.063 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16048.007 ; 3.944 ; FF ; IC ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[4]|clrn ; ; 16048.241 ; 0.234 ; FR ; CELL ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.417 ; 0.417 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.108 ; 0.108 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.245 ; 0.137 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.733 ; 0.488 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.881 ; 0.148 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.881 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.798 ; -3.083 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.798 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.627 ; 0.829 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.126 ; 0.499 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.267 ; 0.141 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.210 ; 0.943 ; RR ; IC ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[4]|clk ; ; 16040.417 ; 0.207 ; RR ; CELL ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; ; 16040.187 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.187 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #25: Recovery slack is -8.054 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16048.241 ; ; Data Required Time ; 16040.187 ; ; Slack ; -8.054 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.459 ; ; ; ; ; ; ; Data Delay ; 4.367 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.633 ; 54 ; 0.000 ; 1.190 ; ; Cell ; ; 5 ; 2.255 ; 46 ; 0.157 ; 0.970 ; ; PLL Compensation ; ; 1 ; -1.012 ; 0 ; -1.012 ; -1.012 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 4.093 ; 94 ; 0.149 ; 3.944 ; ; Cell ; ; 3 ; 0.274 ; 6 ; 0.000 ; 0.234 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.038 ; 58 ; 0.000 ; 0.943 ; ; Cell ; ; 5 ; 1.462 ; 42 ; 0.137 ; 0.829 ; ; PLL Compensation ; ; 1 ; -3.083 ; 0 ; -3.083 ; -3.083 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.874 ; 3.876 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.733 ; 0.735 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.349 ; 0.616 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.508 ; 0.159 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.508 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.496 ; -1.012 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.496 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.466 ; 0.970 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.293 ; 0.827 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.450 ; 0.157 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.640 ; 1.190 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.874 ; 0.234 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16048.241 ; 4.367 ; ; ; ; ; data path ; ; 16043.874 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.874 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16044.023 ; 0.149 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16044.063 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16048.007 ; 3.944 ; FF ; IC ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[2]|clrn ; ; 16048.241 ; 0.234 ; FR ; CELL ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.417 ; 0.417 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.108 ; 0.108 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.245 ; 0.137 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.733 ; 0.488 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.881 ; 0.148 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.881 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.798 ; -3.083 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.798 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.627 ; 0.829 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.126 ; 0.499 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.267 ; 0.141 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.210 ; 0.943 ; RR ; IC ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[2]|clk ; ; 16040.417 ; 0.207 ; RR ; CELL ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; ; 16040.187 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.187 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #26: Recovery slack is -8.053 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16048.241 ; ; Data Required Time ; 16040.188 ; ; Slack ; -8.053 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.458 ; ; ; ; ; ; ; Data Delay ; 4.367 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.633 ; 54 ; 0.000 ; 1.190 ; ; Cell ; ; 5 ; 2.255 ; 46 ; 0.157 ; 0.970 ; ; PLL Compensation ; ; 1 ; -1.012 ; 0 ; -1.012 ; -1.012 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 4.093 ; 94 ; 0.149 ; 3.944 ; ; Cell ; ; 3 ; 0.274 ; 6 ; 0.000 ; 0.234 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.038 ; 58 ; 0.000 ; 0.943 ; ; Cell ; ; 5 ; 1.463 ; 42 ; 0.137 ; 0.829 ; ; PLL Compensation ; ; 1 ; -3.083 ; 0 ; -3.083 ; -3.083 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.874 ; 3.876 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.733 ; 0.735 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.349 ; 0.616 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.508 ; 0.159 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.508 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.496 ; -1.012 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.496 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.466 ; 0.970 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.293 ; 0.827 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.450 ; 0.157 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.640 ; 1.190 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.874 ; 0.234 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16048.241 ; 4.367 ; ; ; ; ; data path ; ; 16043.874 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.874 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16044.023 ; 0.149 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16044.063 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16048.007 ; 3.944 ; FF ; IC ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|sub_parity10a[1]|clrn ; ; 16048.241 ; 0.234 ; FR ; CELL ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.418 ; 0.418 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.108 ; 0.108 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.245 ; 0.137 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.733 ; 0.488 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.881 ; 0.148 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.881 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.798 ; -3.083 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.798 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.627 ; 0.829 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.126 ; 0.499 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.267 ; 0.141 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.210 ; 0.943 ; RR ; IC ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|sub_parity10a[1]|clk ; ; 16040.418 ; 0.208 ; RR ; CELL ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; ; 16040.188 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.188 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #27: Recovery slack is -8.053 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16048.241 ; ; Data Required Time ; 16040.188 ; ; Slack ; -8.053 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.458 ; ; ; ; ; ; ; Data Delay ; 4.367 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.633 ; 54 ; 0.000 ; 1.190 ; ; Cell ; ; 5 ; 2.255 ; 46 ; 0.157 ; 0.970 ; ; PLL Compensation ; ; 1 ; -1.012 ; 0 ; -1.012 ; -1.012 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 4.093 ; 94 ; 0.149 ; 3.944 ; ; Cell ; ; 3 ; 0.274 ; 6 ; 0.000 ; 0.234 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.038 ; 58 ; 0.000 ; 0.943 ; ; Cell ; ; 5 ; 1.463 ; 42 ; 0.137 ; 0.829 ; ; PLL Compensation ; ; 1 ; -3.083 ; 0 ; -3.083 ; -3.083 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.874 ; 3.876 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.733 ; 0.735 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.349 ; 0.616 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.508 ; 0.159 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.508 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.496 ; -1.012 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.496 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.466 ; 0.970 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.293 ; 0.827 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.450 ; 0.157 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.640 ; 1.190 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.874 ; 0.234 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16048.241 ; 4.367 ; ; ; ; ; data path ; ; 16043.874 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.874 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16044.023 ; 0.149 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16044.063 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16048.007 ; 3.944 ; FF ; IC ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]~DUPLICATE|clrn ; ; 16048.241 ; 0.234 ; FR ; CELL ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.418 ; 0.418 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.108 ; 0.108 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.245 ; 0.137 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.733 ; 0.488 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.881 ; 0.148 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.881 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.798 ; -3.083 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.798 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.627 ; 0.829 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.126 ; 0.499 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.267 ; 0.141 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.210 ; 0.943 ; RR ; IC ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]~DUPLICATE|clk ; ; 16040.418 ; 0.208 ; RR ; CELL ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; ; 16040.188 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.188 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #28: Recovery slack is -8.050 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16048.241 ; ; Data Required Time ; 16040.191 ; ; Slack ; -8.050 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.455 ; ; ; ; ; ; ; Data Delay ; 4.367 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.633 ; 54 ; 0.000 ; 1.190 ; ; Cell ; ; 5 ; 2.255 ; 46 ; 0.157 ; 0.970 ; ; PLL Compensation ; ; 1 ; -1.012 ; 0 ; -1.012 ; -1.012 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 4.093 ; 94 ; 0.149 ; 3.944 ; ; Cell ; ; 3 ; 0.274 ; 6 ; 0.000 ; 0.234 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.038 ; 58 ; 0.000 ; 0.943 ; ; Cell ; ; 5 ; 1.466 ; 42 ; 0.137 ; 0.829 ; ; PLL Compensation ; ; 1 ; -3.083 ; 0 ; -3.083 ; -3.083 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.874 ; 3.876 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.733 ; 0.735 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.349 ; 0.616 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.508 ; 0.159 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.508 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.496 ; -1.012 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.496 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.466 ; 0.970 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.293 ; 0.827 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.450 ; 0.157 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.640 ; 1.190 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.874 ; 0.234 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16048.241 ; 4.367 ; ; ; ; ; data path ; ; 16043.874 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.874 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16044.023 ; 0.149 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16044.063 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16048.007 ; 3.944 ; FF ; IC ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a6|clrn ; ; 16048.241 ; 0.234 ; FR ; CELL ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.421 ; 0.421 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.108 ; 0.108 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.245 ; 0.137 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.733 ; 0.488 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.881 ; 0.148 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.881 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.798 ; -3.083 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.798 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.627 ; 0.829 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.126 ; 0.499 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.267 ; 0.141 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.210 ; 0.943 ; RR ; IC ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a6|clk ; ; 16040.421 ; 0.211 ; RR ; CELL ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; ; 16040.191 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.191 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #29: Recovery slack is -8.050 (VIOLATED) =============================================================================== +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|delayed_wrptr_g[3] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16048.241 ; ; Data Required Time ; 16040.191 ; ; Slack ; -8.050 (VIOLATED) ; +--------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.455 ; ; ; ; ; ; ; Data Delay ; 4.367 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.633 ; 54 ; 0.000 ; 1.190 ; ; Cell ; ; 5 ; 2.255 ; 46 ; 0.157 ; 0.970 ; ; PLL Compensation ; ; 1 ; -1.012 ; 0 ; -1.012 ; -1.012 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 4.093 ; 94 ; 0.149 ; 3.944 ; ; Cell ; ; 3 ; 0.274 ; 6 ; 0.000 ; 0.234 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.038 ; 58 ; 0.000 ; 0.943 ; ; Cell ; ; 5 ; 1.466 ; 42 ; 0.137 ; 0.829 ; ; PLL Compensation ; ; 1 ; -3.083 ; 0 ; -3.083 ; -3.083 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.874 ; 3.876 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.733 ; 0.735 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.349 ; 0.616 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.508 ; 0.159 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.508 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.496 ; -1.012 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.496 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.466 ; 0.970 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.293 ; 0.827 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.450 ; 0.157 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.640 ; 1.190 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.874 ; 0.234 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16048.241 ; 4.367 ; ; ; ; ; data path ; ; 16043.874 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.874 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16044.023 ; 0.149 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16044.063 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16048.007 ; 3.944 ; FF ; IC ; 1 ; FF_X50_Y22_N16 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|delayed_wrptr_g[3]|clrn ; ; 16048.241 ; 0.234 ; FR ; CELL ; 1 ; FF_X50_Y22_N16 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|delayed_wrptr_g[3] ; +-------------+-----------+----+------+--------+----------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.421 ; 0.421 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.108 ; 0.108 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.245 ; 0.137 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.733 ; 0.488 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.881 ; 0.148 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.881 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.798 ; -3.083 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.798 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.627 ; 0.829 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.126 ; 0.499 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.267 ; 0.141 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.210 ; 0.943 ; RR ; IC ; 1 ; FF_X50_Y22_N16 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|delayed_wrptr_g[3]|clk ; ; 16040.421 ; 0.211 ; RR ; CELL ; 1 ; FF_X50_Y22_N16 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|delayed_wrptr_g[3] ; ; 16040.191 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.191 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N16 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|delayed_wrptr_g[3] ; +-------------+-----------+----+------+--------+---------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #30: Recovery slack is -8.049 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16048.241 ; ; Data Required Time ; 16040.192 ; ; Slack ; -8.049 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.454 ; ; ; ; ; ; ; Data Delay ; 4.367 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.633 ; 54 ; 0.000 ; 1.190 ; ; Cell ; ; 5 ; 2.255 ; 46 ; 0.157 ; 0.970 ; ; PLL Compensation ; ; 1 ; -1.012 ; 0 ; -1.012 ; -1.012 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 4.093 ; 94 ; 0.149 ; 3.944 ; ; Cell ; ; 3 ; 0.274 ; 6 ; 0.000 ; 0.234 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.038 ; 58 ; 0.000 ; 0.943 ; ; Cell ; ; 5 ; 1.467 ; 42 ; 0.137 ; 0.829 ; ; PLL Compensation ; ; 1 ; -3.083 ; 0 ; -3.083 ; -3.083 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.874 ; 3.876 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.733 ; 0.735 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.349 ; 0.616 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.508 ; 0.159 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.508 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.496 ; -1.012 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.496 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.466 ; 0.970 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.293 ; 0.827 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.450 ; 0.157 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.640 ; 1.190 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.874 ; 0.234 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16048.241 ; 4.367 ; ; ; ; ; data path ; ; 16043.874 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.874 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16044.023 ; 0.149 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16044.063 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16048.007 ; 3.944 ; FF ; IC ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a3|clrn ; ; 16048.241 ; 0.234 ; FR ; CELL ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.422 ; 0.422 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.108 ; 0.108 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.245 ; 0.137 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.733 ; 0.488 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.881 ; 0.148 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.881 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.798 ; -3.083 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.798 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.627 ; 0.829 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.126 ; 0.499 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.267 ; 0.141 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.210 ; 0.943 ; RR ; IC ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a3|clk ; ; 16040.422 ; 0.212 ; RR ; CELL ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; ; 16040.192 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.192 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N56 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a3 ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #31: Recovery slack is -7.009 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16047.151 ; ; Data Required Time ; 16040.142 ; ; Slack ; -7.009 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.304 ; ; ; ; ; ; ; Data Delay ; 3.477 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.582 ; 55 ; 0.000 ; 1.169 ; ; Cell ; ; 5 ; 2.097 ; 45 ; 0.150 ; 0.898 ; ; PLL Compensation ; ; 1 ; -1.003 ; 0 ; -1.003 ; -1.003 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 3.225 ; 93 ; 0.123 ; 3.102 ; ; Cell ; ; 3 ; 0.252 ; 7 ; 0.000 ; 0.212 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.003 ; 60 ; 0.000 ; 0.918 ; ; Cell ; ; 5 ; 1.363 ; 40 ; 0.135 ; 0.782 ; ; PLL Compensation ; ; 1 ; -2.994 ; 0 ; -2.994 ; -2.994 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.674 ; 3.676 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.701 ; 0.703 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.305 ; 0.604 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.455 ; 0.150 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.455 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.452 ; -1.003 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.452 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.350 ; 0.898 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.159 ; 0.809 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.313 ; 0.154 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.482 ; 1.169 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.674 ; 0.192 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.151 ; 3.477 ; ; ; ; ; data path ; ; 16043.674 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.674 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16043.797 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16043.837 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16046.939 ; 3.102 ; FF ; IC ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]|clrn ; ; 16047.151 ; 0.212 ; FR ; CELL ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.372 ; 0.372 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.105 ; 0.105 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.240 ; 0.135 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.730 ; 0.490 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.868 ; 0.138 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.868 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.874 ; -2.994 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.874 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.656 ; 0.782 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.146 ; 0.490 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.284 ; 0.138 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.202 ; 0.918 ; RR ; IC ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]|clk ; ; 16040.372 ; 0.170 ; RR ; CELL ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; ; 16040.142 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.142 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N10 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #32: Recovery slack is -7.009 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16047.151 ; ; Data Required Time ; 16040.142 ; ; Slack ; -7.009 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.304 ; ; ; ; ; ; ; Data Delay ; 3.477 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.582 ; 55 ; 0.000 ; 1.169 ; ; Cell ; ; 5 ; 2.097 ; 45 ; 0.150 ; 0.898 ; ; PLL Compensation ; ; 1 ; -1.003 ; 0 ; -1.003 ; -1.003 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 3.225 ; 93 ; 0.123 ; 3.102 ; ; Cell ; ; 3 ; 0.252 ; 7 ; 0.000 ; 0.212 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.003 ; 60 ; 0.000 ; 0.918 ; ; Cell ; ; 5 ; 1.363 ; 40 ; 0.135 ; 0.782 ; ; PLL Compensation ; ; 1 ; -2.994 ; 0 ; -2.994 ; -2.994 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.674 ; 3.676 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.701 ; 0.703 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.305 ; 0.604 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.455 ; 0.150 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.455 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.452 ; -1.003 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.452 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.350 ; 0.898 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.159 ; 0.809 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.313 ; 0.154 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.482 ; 1.169 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.674 ; 0.192 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.151 ; 3.477 ; ; ; ; ; data path ; ; 16043.674 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.674 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16043.797 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16043.837 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16046.939 ; 3.102 ; FF ; IC ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[5]|clrn ; ; 16047.151 ; 0.212 ; FR ; CELL ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.372 ; 0.372 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.105 ; 0.105 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.240 ; 0.135 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.730 ; 0.490 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.868 ; 0.138 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.868 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.874 ; -2.994 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.874 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.656 ; 0.782 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.146 ; 0.490 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.284 ; 0.138 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.202 ; 0.918 ; RR ; IC ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[5]|clk ; ; 16040.372 ; 0.170 ; RR ; CELL ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; ; 16040.142 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.142 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N34 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[5] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #33: Recovery slack is -7.008 (VIOLATED) =============================================================================== +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16047.151 ; ; Data Required Time ; 16040.143 ; ; Slack ; -7.008 (VIOLATED) ; +--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.303 ; ; ; ; ; ; ; Data Delay ; 3.477 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.582 ; 55 ; 0.000 ; 1.169 ; ; Cell ; ; 5 ; 2.097 ; 45 ; 0.150 ; 0.898 ; ; PLL Compensation ; ; 1 ; -1.003 ; 0 ; -1.003 ; -1.003 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 3.225 ; 93 ; 0.123 ; 3.102 ; ; Cell ; ; 3 ; 0.252 ; 7 ; 0.000 ; 0.212 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.003 ; 59 ; 0.000 ; 0.918 ; ; Cell ; ; 5 ; 1.364 ; 41 ; 0.135 ; 0.782 ; ; PLL Compensation ; ; 1 ; -2.994 ; 0 ; -2.994 ; -2.994 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.674 ; 3.676 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.701 ; 0.703 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.305 ; 0.604 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.455 ; 0.150 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.455 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.452 ; -1.003 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.452 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.350 ; 0.898 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.159 ; 0.809 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.313 ; 0.154 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.482 ; 1.169 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.674 ; 0.192 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.151 ; 3.477 ; ; ; ; ; data path ; ; 16043.674 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.674 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16043.797 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16043.837 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16046.939 ; 3.102 ; FF ; IC ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|parity9|clrn ; ; 16047.151 ; 0.212 ; FR ; CELL ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; +-------------+-----------+----+------+--------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.373 ; 0.373 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.105 ; 0.105 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.240 ; 0.135 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.730 ; 0.490 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.868 ; 0.138 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.868 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.874 ; -2.994 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.874 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.656 ; 0.782 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.146 ; 0.490 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.284 ; 0.138 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.202 ; 0.918 ; RR ; IC ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|parity9|clk ; ; 16040.373 ; 0.171 ; RR ; CELL ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; ; 16040.143 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.143 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N31 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9 ; +-------------+-----------+----+------+--------+---------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #34: Recovery slack is -7.008 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16047.151 ; ; Data Required Time ; 16040.143 ; ; Slack ; -7.008 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.303 ; ; ; ; ; ; ; Data Delay ; 3.477 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.582 ; 55 ; 0.000 ; 1.169 ; ; Cell ; ; 5 ; 2.097 ; 45 ; 0.150 ; 0.898 ; ; PLL Compensation ; ; 1 ; -1.003 ; 0 ; -1.003 ; -1.003 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 3.225 ; 93 ; 0.123 ; 3.102 ; ; Cell ; ; 3 ; 0.252 ; 7 ; 0.000 ; 0.212 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.003 ; 59 ; 0.000 ; 0.918 ; ; Cell ; ; 5 ; 1.364 ; 41 ; 0.135 ; 0.782 ; ; PLL Compensation ; ; 1 ; -2.994 ; 0 ; -2.994 ; -2.994 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.674 ; 3.676 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.701 ; 0.703 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.305 ; 0.604 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.455 ; 0.150 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.455 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.452 ; -1.003 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.452 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.350 ; 0.898 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.159 ; 0.809 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.313 ; 0.154 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.482 ; 1.169 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.674 ; 0.192 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.151 ; 3.477 ; ; ; ; ; data path ; ; 16043.674 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.674 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16043.797 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16043.837 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16046.939 ; 3.102 ; FF ; IC ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[4]|clrn ; ; 16047.151 ; 0.212 ; FR ; CELL ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.373 ; 0.373 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.105 ; 0.105 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.240 ; 0.135 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.730 ; 0.490 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.868 ; 0.138 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.868 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.874 ; -2.994 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.874 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.656 ; 0.782 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.146 ; 0.490 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.284 ; 0.138 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.202 ; 0.918 ; RR ; IC ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[4]|clk ; ; 16040.373 ; 0.171 ; RR ; CELL ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; ; 16040.143 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.143 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N7 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[4] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #35: Recovery slack is -7.008 (VIOLATED) =============================================================================== +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16047.151 ; ; Data Required Time ; 16040.143 ; ; Slack ; -7.008 (VIOLATED) ; +--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.303 ; ; ; ; ; ; ; Data Delay ; 3.477 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.582 ; 55 ; 0.000 ; 1.169 ; ; Cell ; ; 5 ; 2.097 ; 45 ; 0.150 ; 0.898 ; ; PLL Compensation ; ; 1 ; -1.003 ; 0 ; -1.003 ; -1.003 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 3.225 ; 93 ; 0.123 ; 3.102 ; ; Cell ; ; 3 ; 0.252 ; 7 ; 0.000 ; 0.212 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.003 ; 59 ; 0.000 ; 0.918 ; ; Cell ; ; 5 ; 1.364 ; 41 ; 0.135 ; 0.782 ; ; PLL Compensation ; ; 1 ; -2.994 ; 0 ; -2.994 ; -2.994 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.674 ; 3.676 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.701 ; 0.703 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.305 ; 0.604 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.455 ; 0.150 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.455 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.452 ; -1.003 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.452 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.350 ; 0.898 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.159 ; 0.809 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.313 ; 0.154 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.482 ; 1.169 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.674 ; 0.192 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.151 ; 3.477 ; ; ; ; ; data path ; ; 16043.674 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.674 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16043.797 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16043.837 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16046.939 ; 3.102 ; FF ; IC ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[2]|clrn ; ; 16047.151 ; 0.212 ; FR ; CELL ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; +-------------+-----------+----+------+--------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.373 ; 0.373 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.105 ; 0.105 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.240 ; 0.135 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.730 ; 0.490 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.868 ; 0.138 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.868 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.874 ; -2.994 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.874 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.656 ; 0.782 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.146 ; 0.490 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.284 ; 0.138 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.202 ; 0.918 ; RR ; IC ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[2]|clk ; ; 16040.373 ; 0.171 ; RR ; CELL ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; ; 16040.143 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.143 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N25 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[2] ; +-------------+-----------+----+------+--------+---------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #36: Recovery slack is -7.007 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16047.151 ; ; Data Required Time ; 16040.144 ; ; Slack ; -7.007 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.302 ; ; ; ; ; ; ; Data Delay ; 3.477 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.582 ; 55 ; 0.000 ; 1.169 ; ; Cell ; ; 5 ; 2.097 ; 45 ; 0.150 ; 0.898 ; ; PLL Compensation ; ; 1 ; -1.003 ; 0 ; -1.003 ; -1.003 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 3.225 ; 93 ; 0.123 ; 3.102 ; ; Cell ; ; 3 ; 0.252 ; 7 ; 0.000 ; 0.212 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.003 ; 59 ; 0.000 ; 0.918 ; ; Cell ; ; 5 ; 1.365 ; 41 ; 0.135 ; 0.782 ; ; PLL Compensation ; ; 1 ; -2.994 ; 0 ; -2.994 ; -2.994 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.674 ; 3.676 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.701 ; 0.703 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.305 ; 0.604 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.455 ; 0.150 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.455 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.452 ; -1.003 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.452 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.350 ; 0.898 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.159 ; 0.809 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.313 ; 0.154 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.482 ; 1.169 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.674 ; 0.192 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.151 ; 3.477 ; ; ; ; ; data path ; ; 16043.674 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.674 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16043.797 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16043.837 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16046.939 ; 3.102 ; FF ; IC ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|sub_parity10a[1]|clrn ; ; 16047.151 ; 0.212 ; FR ; CELL ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.374 ; 0.374 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.105 ; 0.105 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.240 ; 0.135 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.730 ; 0.490 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.868 ; 0.138 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.868 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.874 ; -2.994 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.874 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.656 ; 0.782 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.146 ; 0.490 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.284 ; 0.138 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.202 ; 0.918 ; RR ; IC ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|sub_parity10a[1]|clk ; ; 16040.374 ; 0.172 ; RR ; CELL ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; ; 16040.144 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.144 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N53 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|sub_parity10a[1] ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #37: Recovery slack is -7.007 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16047.151 ; ; Data Required Time ; 16040.144 ; ; Slack ; -7.007 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.302 ; ; ; ; ; ; ; Data Delay ; 3.477 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.582 ; 55 ; 0.000 ; 1.169 ; ; Cell ; ; 5 ; 2.097 ; 45 ; 0.150 ; 0.898 ; ; PLL Compensation ; ; 1 ; -1.003 ; 0 ; -1.003 ; -1.003 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 3.225 ; 93 ; 0.123 ; 3.102 ; ; Cell ; ; 3 ; 0.252 ; 7 ; 0.000 ; 0.212 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.003 ; 59 ; 0.000 ; 0.918 ; ; Cell ; ; 5 ; 1.365 ; 41 ; 0.135 ; 0.782 ; ; PLL Compensation ; ; 1 ; -2.994 ; 0 ; -2.994 ; -2.994 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.674 ; 3.676 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.701 ; 0.703 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.305 ; 0.604 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.455 ; 0.150 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.455 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.452 ; -1.003 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.452 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.350 ; 0.898 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.159 ; 0.809 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.313 ; 0.154 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.482 ; 1.169 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.674 ; 0.192 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.151 ; 3.477 ; ; ; ; ; data path ; ; 16043.674 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.674 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16043.797 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16043.837 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16046.939 ; 3.102 ; FF ; IC ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]~DUPLICATE|clrn ; ; 16047.151 ; 0.212 ; FR ; CELL ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.374 ; 0.374 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.105 ; 0.105 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.240 ; 0.135 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.730 ; 0.490 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.868 ; 0.138 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.868 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.874 ; -2.994 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.874 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.656 ; 0.782 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.146 ; 0.490 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.284 ; 0.138 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.202 ; 0.918 ; RR ; IC ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g[6]~DUPLICATE|clk ; ; 16040.374 ; 0.172 ; RR ; CELL ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; ; 16040.144 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.144 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N11 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|wrptr_g[6]~DUPLICATE ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #38: Recovery slack is -7.005 (VIOLATED) =============================================================================== +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16047.151 ; ; Data Required Time ; 16040.146 ; ; Slack ; -7.005 (VIOLATED) ; +--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.300 ; ; ; ; ; ; ; Data Delay ; 3.477 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.582 ; 55 ; 0.000 ; 1.169 ; ; Cell ; ; 5 ; 2.097 ; 45 ; 0.150 ; 0.898 ; ; PLL Compensation ; ; 1 ; -1.003 ; 0 ; -1.003 ; -1.003 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 3.225 ; 93 ; 0.123 ; 3.102 ; ; Cell ; ; 3 ; 0.252 ; 7 ; 0.000 ; 0.212 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.003 ; 59 ; 0.000 ; 0.918 ; ; Cell ; ; 5 ; 1.367 ; 41 ; 0.135 ; 0.782 ; ; PLL Compensation ; ; 1 ; -2.994 ; 0 ; -2.994 ; -2.994 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time ; ; 16043.674 ; 3.676 ; ; ; ; ; clock path ; ; 16039.998 ; 0.000 ; ; ; ; ; source latency ; ; 16039.998 ; 0.000 ; ; ; 1 ; PIN_E11 ; LVDS_CLK_IN ; ; 16039.998 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|i ; ; 16040.701 ; 0.703 ; RR ; CELL ; 2 ; IOIBUF_X32_Y81_N1 ; LVDS_CLK_IN~input|o ; ; 16041.305 ; 0.604 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0] ; ; 16041.455 ; 0.150 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y80_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16041.455 ; 0.000 ; RR ; IC ; 11 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16040.452 ; -1.003 ; RR ; COMP ; 5 ; FRACTIONALPLL_X0_Y74_N0 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16040.452 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16041.350 ; 0.898 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y77_N1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16042.159 ; 0.809 ; RR ; IC ; 1 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|inclk ; ; 16042.313 ; 0.154 ; RR ; CELL ; 333 ; CLKCTRL_G1 ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|outclk_wire[4]~CLKENA0|outclk ; ; 16043.482 ; 1.169 ; RR ; IC ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|clk ; ; 16043.674 ; 0.192 ; RR ; CELL ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16047.151 ; 3.477 ; ; ; ; ; data path ; ; 16043.674 ; 0.000 ; ; uTco ; 1 ; FF_X50_Y22_N41 ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; 16043.674 ; 0.000 ; FF ; CELL ; 284 ; FF_X50_Y22_N41 ; ngt_stator_system_i|reset_synchronizer_122m88|output_pipeline_reg[0]|q ; ; 16043.797 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|dataf ; ; 16043.837 ; 0.040 ; FF ; CELL ; 89 ; LABCELL_X50_Y22_N27 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|comb~0|combout ; ; 16046.939 ; 3.102 ; FF ; IC ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a6|clrn ; ; 16047.151 ; 0.212 ; FR ; CELL ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; +-------------+-----------+----+------+--------+----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16040.000 ; 16040.000 ; ; ; ; ; latch edge time ; ; 16040.376 ; 0.376 ; ; ; ; ; clock path ; ; 16040.000 ; 0.000 ; ; ; ; ; source latency ; ; 16040.000 ; 0.000 ; ; ; 1 ; HPSINTERFACECLOCKSRESETS_X52_Y78_N111 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|clocks_resets|h2f_user0_clk ; ; 16040.105 ; 0.105 ; RR ; IC ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|inclk ; ; 16040.240 ; 0.135 ; RR ; CELL ; 1 ; CLKCTRL_G15 ; ngt_stator_system_i|cpu_subsystem|hps|fpga_interfaces|h2f_user0_clk[0]~CLKENA0|outclk ; ; 16040.730 ; 0.490 ; RR ; IC ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|coreclkin ; ; 16040.868 ; 0.138 ; RR ; CELL ; 1 ; PLLREFCLKSELECT_X0_Y7_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout ; ; 16040.868 ; 0.000 ; RR ; IC ; 10 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; ; 16037.874 ; -2.994 ; RR ; COMP ; 3 ; FRACTIONALPLL_X0_Y1_N0 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; ; 16037.874 ; 0.000 ; RR ; IC ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; ; 16038.656 ; 0.782 ; RR ; CELL ; 1 ; PLLOUTPUTCOUNTER_X0_Y8_N1 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 16039.146 ; 0.490 ; RR ; IC ; 1 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|inclk ; ; 16039.284 ; 0.138 ; RR ; CELL ; 3740 ; CLKCTRL_G4 ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|outclk_wire[2]~CLKENA0|outclk ; ; 16040.202 ; 0.918 ; RR ; IC ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system_i|fifo_uplink|the_dcfifo_with_controls|the_dcfifo|dual_clock_fifo|auto_generated|wrptr_g1p|counter8a6|clk ; ; 16040.376 ; 0.174 ; RR ; CELL ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; ; 16040.146 ; -0.230 ; ; ; ; ; clock uncertainty ; ; 16040.146 ; 0.000 ; ; uTsu ; 1 ; FF_X50_Y22_N22 ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a6 ; +-------------+-----------+----+------+--------+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export. Path #39: Recovery slack is -7.005 (VIOLATED) =============================================================================== +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; ngt_stator_system:ngt_stator_system_i|reset_synchronizer_ext:reset_synchronizer_122m88|output_pipeline_reg[0] ; ; To Node ; ngt_stator_system:ngt_stator_system_i|ngt_stator_system_fifo_uplink:fifo_uplink|ngt_stator_system_fifo_uplink_dcfifo_with_controls:the_dcfifo_with_controls|ngt_stator_system_fifo_uplink_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_m1v1:auto_generated|delayed_wrptr_g[3] ; ; Launch Clock ; ngt_stator_system_i|pll_regulated_clocks|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Latch Clock ; ngt_stator_system_i|pll_fixed_clocks|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk ; ; Data Arrival Time ; 16047.151 ; ; Data Required Time ; 16040.146 ; ; Slack ; -7.005 (VIOLATED) ; +--------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+--------+--------+ ; Recovery Relationship ; 0.002 ; ; ; ; ; ; ; Clock Skew ; -3.300 ; ; ; ; ; ; ; Data Delay ; 3.477 ; ; ; ; ; ; ; Number of Logic Levels ; ; 1 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.582 ; 55 ; 0.000 ; 1.169 ; ; Cell ; ; 5 ; 2.097 ; 45 ; 0.150 ; 0.898 ; ; PLL Compensation ; ; 1 ; -1.003 ; 0 ; -1.003 ; -1.003 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 2 ; 3.225 ; 93 ; 0.123 ; 3.102 ; ; Cell ; ; 3 ; 0.252 ; 7 ; 0.000 ; 0.212 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 6 ; 2.003 ; 59 ; 0.000 ; 0.918 ; ; Cell ; ; 5 ; 1.367 ; 41 ; 0.135 ; 0.782 ; ; PLL Compensation ; ; 1 ; -2.994 ; 0 ; -2.994 ; -2.994 ; +------------------------+--------+-------+-------------+------------+--------+--------+ Note: Negative delays are omitted from totals when calculating percentages +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +-------------+-----------+----+------+--------+----------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +-------------+-----------+----+------+--------+----------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 16039.998 ; 16039.998 ; ; ; ; ; launch edge time