Info: DDR3: Variation language : Verilog
Info: DDR3: Output directory : C:\gen2dom-fw\deggmb_rev2_fw_psu\ipcores\DDR3
Info: DDR3: Generating variation file C:\gen2dom-fw\deggmb_rev2_fw_psu\ipcores\DDR3\DDR3.v
Info: DDR3: Generating synthesis files
Info: Generating altera_mem_if_ddr3_emif "DDR3" for QUARTUS_SYNTH
Info: "DDR3" instantiated altera_mem_if_ddr3_emif "DDR3"
Info: "DDR3" instantiated altera_mem_if_ddr3_pll "pll0"
Info: Generating clock pair generator
Info: Generating DDR3_p0_altdqdqs
Info:
Info: *****************************
Info:
Info: Remember to run the DDR3_p0_pin_assignments.tcl
Info: script after running Synthesis and before Fitting.
Info:
Info: *****************************
Info:
Info: "DDR3" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
Error: Error during execution of "{C:/intelfpga_lite/18.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga_lite/18.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: ]2;Altera Nios II EDS 18.1 [gcc4]C:/intelfpga_lite/18.1/quartus//bin64/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3_s0_AC_ROM.hex -inst_rom ../DDR3_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000100001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100100000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0001000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001000001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011000000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0001000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=0 -DFULL_RATE=1 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=1
Error: UniPHY Sequencer Microcode Compiler
Error: Copyright (C) 2019 Intel Corporation. All rights reserved.
Error: Info: Reading sequencer_mc/ac_rom.s ...
Error: Info: Reading sequencer_mc/inst_rom.s ...
Error: Info: Writing ../DDR3_s0_AC_ROM.hex ...
Error: Info: Writing ../DDR3_s0_inst_ROM.hex ...
Error: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing ../sequencer_auto_h.sv ...
Error: Info: Microcode compilation successful
Error: C:/intelfpga_lite/18.1/quartus//../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: child process exited abnormally
Error: Cannot find sequencer/sequencer.elf
Error: An error occurred
while executing
"error "An error occurred""
(procedure "_error" line 8)
invoked from within
"_error "Cannot find $seq_file""
("if" then script line 2)
invoked from within
"if {[file exists $seq_file] == 0} {
_error "Cannot find $seq_file"
}"
(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
("if" then script line 2)
invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
(procedure "generate_qsys_sequencer_sw" line 924)
invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."
invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."
("if" else script line 2)
invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
(procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
set file_name [file tail $genera..."
(procedure "generate_synth" line 8)
invoked from within
"generate_synth DDR3_s0"
Info: "DDR3" instantiated altera_mem_if_ddr3_qseq "s0"
Error: Generation stopped, 5 or more modules remaining
Info: Done "DDR3" with 10 modules, 24 files
Info: DDR3: Generating example design
Info: Generating altera_mem_if_ddr3_emif "DDR3" for EXAMPLE_DESIGN
Info: Generating simulation example design
Info: Generating synthesizable example design
Error: Error during execution of script generate_ed.tcl: s0: Error during execution of "{C:/intelfpga_lite/18.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Error during execution of script generate_ed.tcl: s0: Execution of command "{C:/intelfpga_lite/18.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: Error during execution of script generate_ed.tcl: s0: ]2;Altera Nios II EDS 18.1 [gcc4]C:/intelfpga_lite/18.1/quartus/bin64/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3_example_if0_s0_AC_ROM.hex -inst_rom ../DDR3_example_if0_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000100001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100100000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0001000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001000001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011000000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0001000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=0 -DFULL_RATE=1 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=1
Error: Error during execution of script generate_ed.tcl: s0: UniPHY Sequencer Microcode Compiler
Error: Error during execution of script generate_ed.tcl: s0: Copyright (C) 2019 Intel Corporation. All rights reserved.
Error: Error during execution of script generate_ed.tcl: s0: Info: Reading sequencer_mc/ac_rom.s ...
Error: Error during execution of script generate_ed.tcl: s0: Info: Reading sequencer_mc/inst_rom.s ...
Error: Error during execution of script generate_ed.tcl: s0: Info: Writing ../DDR3_example_if0_s0_AC_ROM.hex ...
Error: Error during execution of script generate_ed.tcl: s0: Info: Writing ../DDR3_example_if0_s0_inst_ROM.hex ...
Error: Error during execution of script generate_ed.tcl: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: Error during execution of script generate_ed.tcl: s0: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: Error during execution of script generate_ed.tcl: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: Error during execution of script generate_ed.tcl: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: Error during execution of script generate_ed.tcl: s0: Info: Writing ../sequencer_auto_h.sv ...
Error: Error during execution of script generate_ed.tcl: s0: Info: Microcode compilation successful
Error: Error during execution of script generate_ed.tcl: s0: C:/intelfpga_lite/18.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: Error during execution of script generate_ed.tcl: s0: child process exited abnormally
Error: Error during execution of script generate_ed.tcl: s0: Cannot find sequencer/sequencer.elf
Error: Error during execution of script generate_ed.tcl: s0: An error occurred
Error: Error during execution of script generate_ed.tcl: Generation stopped, 8 or more modules remaining
Error: Execution of script generate_ed.tcl failed
Error: ERROR: Cannot find sequencer/sequencer.elf
Error: 2019.08.14.09:25:46 Info:
Error: ********************************************************************************************************************
Error:
Error: Use qsys-generate for a simpler command-line interface for generating IP.
Error:
Error: Run ip-generate with switch --remove-qsys-generate-warning to prevent this notice from appearing in subsequent runs.
Error:
Error: ********************************************************************************************************************
Error: 2019.08.14.09:26:05 Warning: DDR3_example: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
Error: 2019.08.14.09:26:05 Warning: DDR3_example.if0.pll_bridge: pll_bridge.pll_sharing cannot be both connected and exported
Error: 2019.08.14.09:26:05 Warning: DDR3_example.if0: if0.pll_sharing must be exported, or connected to a matching conduit.
Error: 2019.08.14.09:26:05 Warning: DDR3_example.pll0: pll0.pll_locked must be exported, or connected to a matching conduit.
Error: 2019.08.14.09:26:05 Info: DDR3_example: Generating alt_mem_if_ddr3_tg_ed "DDR3_example" for QUARTUS_SYNTH
Error: 2019.08.14.09:26:10 Info: Interconnect is inserted between master d0.avl and slave if0.avl_0 because the master has address signal 28 bit wide, but the slave is 26 bit wide.
Error: 2019.08.14.09:26:21 Info: if0: "DDR3_example" instantiated altera_mem_if_ddr3_emif "if0"
Error: 2019.08.14.09:26:21 Info: pll0: "DDR3_example" instantiated altera_mem_if_single_clock_pll "pll0"
Error: 2019.08.14.09:26:23 Info: d0: "DDR3_example" instantiated altera_avalon_mm_traffic_generator "d0"
Error: 2019.08.14.09:26:25 Info: mm_interconnect_0: "DDR3_example" instantiated altera_mm_interconnect "mm_interconnect_0"
Error: 2019.08.14.09:26:25 Info: rst_controller: "DDR3_example" instantiated altera_reset_controller "rst_controller"
Error: 2019.08.14.09:26:25 Info: pll0: "if0" instantiated altera_mem_if_ddr3_pll "pll0"
Error: 2019.08.14.09:26:25 Info: p0: Generating clock pair generator
Error: 2019.08.14.09:26:26 Info: p0: Generating DDR3_example_if0_p0_altdqdqs
Error: 2019.08.14.09:26:37 Info: p0:
Error: 2019.08.14.09:26:37 Info: p0: *****************************
Error: 2019.08.14.09:26:37 Info: p0:
Error: 2019.08.14.09:26:37 Info: p0: Remember to run the DDR3_example_if0_p0_pin_assignments.tcl
Error: 2019.08.14.09:26:37 Info: p0: script after running Synthesis and before Fitting.
Error: 2019.08.14.09:26:37 Info: p0:
Error: 2019.08.14.09:26:37 Info: p0: *****************************
Error: 2019.08.14.09:26:37 Info: p0:
Error: 2019.08.14.09:26:37 Info: p0: "if0" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
Error: 2019.08.14.09:26:40 Error: s0: Error during execution of "{C:/intelfpga_lite/18.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: 2019.08.14.09:26:40 Error: s0: Execution of command "{C:/intelfpga_lite/18.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: 2019.08.14.09:26:40 Error: s0: ]2;Altera Nios II EDS 18.1 [gcc4]C:/intelfpga_lite/18.1/quartus/bin64/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3_example_if0_s0_AC_ROM.hex -inst_rom ../DDR3_example_if0_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000100001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100100000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0001000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001000001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011000000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0001000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=0 -DFULL_RATE=1 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=1
Error: 2019.08.14.09:26:40 Error: s0: UniPHY Sequencer Microcode Compiler
Error: 2019.08.14.09:26:40 Error: s0: Copyright (C) 2019 Intel Corporation. All rights reserved.
Error: 2019.08.14.09:26:40 Error: s0: Info: Reading sequencer_mc/ac_rom.s ...
Error: 2019.08.14.09:26:40 Error: s0: Info: Reading sequencer_mc/inst_rom.s ...
Error: 2019.08.14.09:26:40 Error: s0: Info: Writing ../DDR3_example_if0_s0_AC_ROM.hex ...
Error: 2019.08.14.09:26:40 Error: s0: Info: Writing ../DDR3_example_if0_s0_inst_ROM.hex ...
Error: 2019.08.14.09:26:40 Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: 2019.08.14.09:26:40 Error: s0: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: 2019.08.14.09:26:40 Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: 2019.08.14.09:26:40 Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: 2019.08.14.09:26:40 Error: s0: Info: Writing ../sequencer_auto_h.sv ...
Error: 2019.08.14.09:26:40 Error: s0: Info: Microcode compilation successful
Error: 2019.08.14.09:26:40 Error: s0: C:/intelfpga_lite/18.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: 2019.08.14.09:26:40 Error: s0: child process exited abnormally
Error: 2019.08.14.09:26:40 Error: s0: Cannot find sequencer/sequencer.elf
Error: 2019.08.14.09:26:40 Error: s0: An error occurred
Error: while executing
Error: "error "An error occurred""
Error: (procedure "_error" line 8)
Error: invoked from within
Error: "_error "Cannot find $seq_file""
Error: ("if" then script line 2)
Error: invoked from within
Error: "if {[file exists $seq_file] == 0} {
Error: _error "Cannot find $seq_file"
Error: }"
Error: (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
Error: invoked from within
Error: "alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
Error: invoked from within
Error: "set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
Error: ("if" then script line 2)
Error: invoked from within
Error: "if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
Error: set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
Error: (procedure "generate_qsys_sequencer_sw" line 924)
Error: invoked from within
Error: "generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."
Error: invoked from within
Error: "set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."
Error: ("if" else script line 2)
Error: invoked from within
Error: "if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
Error: set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
Error: (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)
Error: invoked from within
Error: "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
Error: invoked from within
Error: "set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
Error: (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
Error: invoked from within
Error: "alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
Error: invoked from within
Error: "foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
Error: set file_name [file tail $genera..."
Error: (procedure "generate_synth" line 8)
Error: invoked from within
Error: "generate_synth DDR3_example_if0_s0"
Error: 2019.08.14.09:26:40 Info: s0: "if0" instantiated altera_mem_if_ddr3_qseq "s0"
Error: 2019.08.14.09:26:40 Error: Generation stopped, 8 or more modules remaining
Error: 2019.08.14.09:26:40 Info: DDR3_example: Done "DDR3_example" with 17 modules, 30 files
Info: Creating Quartus project
Info: Done "DDR3" with 1 modules, 43 files
Info: DDR3: Generating simulation model
Info: Generating altera_mem_if_ddr3_emif "DDR3" for SIM_VERILOG
Info: "DDR3" instantiated altera_mem_if_ddr3_emif "DDR3"
Info: "DDR3" instantiated altera_mem_if_ddr3_pll "pll0"
Info: Generating clock pair generator
Info: Generating DDR3_p0_altdqdqs
Info: "DDR3" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
Error: Error during execution of "{C:/intelfpga_lite/18.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga_lite/18.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: ]2;Altera Nios II EDS 18.1 [gcc4]C:/intelfpga_lite/18.1/quartus//bin64/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3_s0_AC_ROM.hex -inst_rom ../DDR3_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000100001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100100000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0001000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001000001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011000000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0001000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=0 -DFULL_RATE=1 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=1
Error: UniPHY Sequencer Microcode Compiler
Error: Copyright (C) 2019 Intel Corporation. All rights reserved.
Error: Info: Reading sequencer_mc/ac_rom.s ...
Error: Info: Reading sequencer_mc/inst_rom.s ...
Error: Info: Writing ../DDR3_s0_AC_ROM.hex ...
Error: Info: Writing ../DDR3_s0_inst_ROM.hex ...
Error: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing ../sequencer_auto_h.sv ...
Error: Info: Microcode compilation successful
Error: C:/intelfpga_lite/18.1/quartus//../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: child process exited abnormally
Error: Cannot find sequencer/sequencer.elf
Error: An error occurred
while executing
"error "An error occurred""
(procedure "_error" line 8)
invoked from within
"_error "Cannot find $seq_file""
("if" then script line 2)
invoked from within
"if {[file exists $seq_file] == 0} {
_error "Cannot find $seq_file"
}"
(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
("if" then script line 2)
invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
(procedure "generate_qsys_sequencer_sw" line 924)
invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."
invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."
("if" else script line 2)
invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
(procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG"
invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG] {
set file_name [file tail $generate..."
(procedure "generate_verilog_sim" line 7)
invoked from within
"generate_verilog_sim DDR3_s0"
Info: "DDR3" instantiated altera_mem_if_ddr3_qseq "s0"
Error: Generation stopped, 5 or more modules remaining
Info: Done "DDR3" with 10 modules, 16 files
Info: Generated simulation scripts for Modelsim in C:/gen2dom-fw/deggmb_rev2_fw_psu/ipcores/DDR3/DDR3_sim/mentor directory.
Info: Generated simulation scripts for VCS and VCS MX in C:/gen2dom-fw/deggmb_rev2_fw_psu/ipcores/DDR3/DDR3_sim/synopsys directory.
Info: Generated simulation scripts for NCSIM in C:/gen2dom-fw/deggmb_rev2_fw_psu/ipcores/DDR3/DDR3_sim/cadence directory.
Info: Generated simulation scripts for Riviera-PRO in C:/gen2dom-fw/deggmb_rev2_fw_psu/ipcores/DDR3/DDR3_sim/aldec directory.