| HIDDEN_CUSTOM_ELABORATION |
altpll_avalon_elaboration |
| HIDDEN_CUSTOM_POST_EDIT |
altpll_avalon_post_edit |
| INTENDED_DEVICE_FAMILY |
MAX 10 |
| WIDTH_CLOCK |
5 |
| WIDTH_PHASECOUNTERSELECT |
|
| PRIMARY_CLOCK |
|
| INCLK0_INPUT_FREQUENCY |
10000 |
| INCLK1_INPUT_FREQUENCY |
|
| OPERATION_MODE |
NORMAL |
| PLL_TYPE |
AUTO |
| QUALIFY_CONF_DONE |
|
| COMPENSATE_CLOCK |
CLK0 |
| SCAN_CHAIN |
|
| GATE_LOCK_SIGNAL |
|
| GATE_LOCK_COUNTER |
|
| LOCK_HIGH |
|
| LOCK_LOW |
|
| VALID_LOCK_MULTIPLIER |
|
| INVALID_LOCK_MULTIPLIER |
|
| SWITCH_OVER_ON_LOSSCLK |
|
| SWITCH_OVER_ON_GATED_LOCK |
|
| ENABLE_SWITCH_OVER_COUNTER |
|
| SKIP_VCO |
|
| SWITCH_OVER_COUNTER |
|
| SWITCH_OVER_TYPE |
|
| FEEDBACK_SOURCE |
|
| BANDWIDTH |
|
| BANDWIDTH_TYPE |
AUTO |
| SPREAD_FREQUENCY |
|
| DOWN_SPREAD |
|
| SELF_RESET_ON_GATED_LOSS_LOCK |
|
| SELF_RESET_ON_LOSS_LOCK |
|
| CLK0_MULTIPLY_BY |
1 |
| CLK1_MULTIPLY_BY |
|
| CLK2_MULTIPLY_BY |
|
| CLK3_MULTIPLY_BY |
|
| CLK4_MULTIPLY_BY |
|
| CLK5_MULTIPLY_BY |
|
| CLK6_MULTIPLY_BY |
|
| CLK7_MULTIPLY_BY |
|
| CLK8_MULTIPLY_BY |
|
| CLK9_MULTIPLY_BY |
|
| EXTCLK0_MULTIPLY_BY |
|
| EXTCLK1_MULTIPLY_BY |
|
| EXTCLK2_MULTIPLY_BY |
|
| EXTCLK3_MULTIPLY_BY |
|
| CLK0_DIVIDE_BY |
1 |
| CLK1_DIVIDE_BY |
|
| CLK2_DIVIDE_BY |
|
| CLK3_DIVIDE_BY |
|
| CLK4_DIVIDE_BY |
|
| CLK5_DIVIDE_BY |
|
| CLK6_DIVIDE_BY |
|
| CLK7_DIVIDE_BY |
|
| CLK8_DIVIDE_BY |
|
| CLK9_DIVIDE_BY |
|
| EXTCLK0_DIVIDE_BY |
|
| EXTCLK1_DIVIDE_BY |
|
| EXTCLK2_DIVIDE_BY |
|
| EXTCLK3_DIVIDE_BY |
|
| CLK0_PHASE_SHIFT |
0 |
| CLK1_PHASE_SHIFT |
|
| CLK2_PHASE_SHIFT |
|
| CLK3_PHASE_SHIFT |
|
| CLK4_PHASE_SHIFT |
|
| CLK5_PHASE_SHIFT |
|
| CLK6_PHASE_SHIFT |
|
| CLK7_PHASE_SHIFT |
|
| CLK8_PHASE_SHIFT |
|
| CLK9_PHASE_SHIFT |
|
| EXTCLK0_PHASE_SHIFT |
|
| EXTCLK1_PHASE_SHIFT |
|
| EXTCLK2_PHASE_SHIFT |
|
| EXTCLK3_PHASE_SHIFT |
|
| CLK0_DUTY_CYCLE |
50 |
| CLK1_DUTY_CYCLE |
|
| CLK2_DUTY_CYCLE |
|
| CLK3_DUTY_CYCLE |
|
| CLK4_DUTY_CYCLE |
|
| CLK5_DUTY_CYCLE |
|
| CLK6_DUTY_CYCLE |
|
| CLK7_DUTY_CYCLE |
|
| CLK8_DUTY_CYCLE |
|
| CLK9_DUTY_CYCLE |
|
| EXTCLK0_DUTY_CYCLE |
|
| EXTCLK1_DUTY_CYCLE |
|
| EXTCLK2_DUTY_CYCLE |
|
| EXTCLK3_DUTY_CYCLE |
|
| PORT_clkena0 |
PORT_UNUSED |
| PORT_clkena1 |
PORT_UNUSED |
| PORT_clkena2 |
PORT_UNUSED |
| PORT_clkena3 |
PORT_UNUSED |
| PORT_clkena4 |
PORT_UNUSED |
| PORT_clkena5 |
PORT_UNUSED |
| PORT_extclkena0 |
|
| PORT_extclkena1 |
|
| PORT_extclkena2 |
|
| PORT_extclkena3 |
|
| PORT_extclk0 |
PORT_UNUSED |
| PORT_extclk1 |
PORT_UNUSED |
| PORT_extclk2 |
PORT_UNUSED |
| PORT_extclk3 |
PORT_UNUSED |
| PORT_CLKBAD0 |
PORT_UNUSED |
| PORT_CLKBAD1 |
PORT_UNUSED |
| PORT_clk0 |
PORT_USED |
| PORT_clk1 |
PORT_UNUSED |
| PORT_clk2 |
PORT_UNUSED |
| PORT_clk3 |
PORT_UNUSED |
| PORT_clk4 |
PORT_UNUSED |
| PORT_clk5 |
PORT_UNUSED |
| PORT_clk6 |
|
| PORT_clk7 |
|
| PORT_clk8 |
|
| PORT_clk9 |
|
| PORT_SCANDATA |
PORT_UNUSED |
| PORT_SCANDATAOUT |
PORT_UNUSED |
| PORT_SCANDONE |
PORT_UNUSED |
| PORT_SCLKOUT1 |
|
| PORT_SCLKOUT0 |
|
| PORT_ACTIVECLOCK |
PORT_UNUSED |
| PORT_CLKLOSS |
PORT_UNUSED |
| PORT_INCLK1 |
PORT_UNUSED |
| PORT_INCLK0 |
PORT_USED |
| PORT_FBIN |
PORT_UNUSED |
| PORT_PLLENA |
PORT_UNUSED |
| PORT_CLKSWITCH |
PORT_UNUSED |
| PORT_ARESET |
PORT_USED |
| PORT_PFDENA |
PORT_UNUSED |
| PORT_SCANCLK |
PORT_UNUSED |
| PORT_SCANACLR |
PORT_UNUSED |
| PORT_SCANREAD |
PORT_UNUSED |
| PORT_SCANWRITE |
PORT_UNUSED |
| PORT_ENABLE0 |
|
| PORT_ENABLE1 |
|
| PORT_LOCKED |
PORT_USED |
| PORT_CONFIGUPDATE |
PORT_UNUSED |
| PORT_FBOUT |
|
| PORT_PHASEDONE |
PORT_UNUSED |
| PORT_PHASESTEP |
PORT_UNUSED |
| PORT_PHASEUPDOWN |
PORT_UNUSED |
| PORT_SCANCLKENA |
PORT_UNUSED |
| PORT_PHASECOUNTERSELECT |
PORT_UNUSED |
| PORT_VCOOVERRANGE |
|
| PORT_VCOUNDERRANGE |
|
| DPA_MULTIPLY_BY |
|
| DPA_DIVIDE_BY |
|
| DPA_DIVIDER |
|
| VCO_MULTIPLY_BY |
|
| VCO_DIVIDE_BY |
|
| SCLKOUT0_PHASE_SHIFT |
|
| SCLKOUT1_PHASE_SHIFT |
|
| VCO_FREQUENCY_CONTROL |
|
| VCO_PHASE_SHIFT_STEP |
|
| USING_FBMIMICBIDIR_PORT |
|
| SCAN_CHAIN_MIF_FILE |
|
| AVALON_USE_SEPARATE_SYSCLK |
NO |
| HIDDEN_CONSTANTS |
CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 10000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#PORT_LOCKED PORT_USED |
| HIDDEN_PRIVATES |
PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 100.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1556356930253833.mif PT#ACTIVECLK_CHECK 0 |
| HIDDEN_USED_PORTS |
UP#locked used UP#c0 used UP#areset used UP#inclk0 used |
| HIDDEN_IS_NUMERIC |
IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 |
| HIDDEN_MF_PORTS |
MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 |
| HIDDEN_IF_PORTS |
IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0} |
| HIDDEN_IS_FIRST_EDIT |
0 |
| AUTO_DEVICE_FAMILY |
MAX10FPGA |
| AUTO_INCLK_INTERFACE_CLOCK_RATE |
50000000 |
| deviceFamily |
MAX 10 |
| generateLegacySim |
false |