// Copyright (C) 1991-2015 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, the Altera Quartus Prime License Agreement, // the Altera MegaCore Function License Agreement, or other // applicable license agreement, including, without limitation, // that your use is for the sole purpose of programming logic // devices manufactured by Altera and sold by Altera or its // authorized distributors. Please refer to the applicable // agreement for further details. // PROGRAM "Quartus Prime" // VERSION "Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition" // CREATED "Sat Jun 29 14:59:30 2019" module a( phy_mgmt_clk, pll_ref_clk, rx_serial_data, reconfig_busy, tx_ready, rx_ready, tx_serial_data, pll_locked, rx_patterndetect, rx_syncstatus, rx_datak, rx_parallel_data ); input wire phy_mgmt_clk; input wire pll_ref_clk; input wire rx_serial_data; output wire reconfig_busy; output wire tx_ready; output wire rx_ready; output wire tx_serial_data; output wire pll_locked; output wire rx_patterndetect; output wire rx_syncstatus; output wire rx_datak; output wire [7:0] rx_parallel_data; wire rx_ltr; wire SYNTHESIZED_WIRE_9; reg DFF_inst5; wire SYNTHESIZED_WIRE_1; wire [8:0] SYNTHESIZED_WIRE_2; wire [31:0] SYNTHESIZED_WIRE_3; wire [139:0] SYNTHESIZED_WIRE_4; wire [7:0] SYNTHESIZED_WIRE_5; wire [91:0] SYNTHESIZED_WIRE_7; wire SYNTHESIZED_WIRE_8; assign SYNTHESIZED_WIRE_9 = 0; assign SYNTHESIZED_WIRE_1 = 1; assign SYNTHESIZED_WIRE_8 = 1; custom0 b2v_inst( .phy_mgmt_clk(phy_mgmt_clk), .phy_mgmt_clk_reset(SYNTHESIZED_WIRE_9), .phy_mgmt_write(DFF_inst5), .pll_ref_clk(pll_ref_clk), .rx_serial_data(rx_serial_data), .tx_datak(SYNTHESIZED_WIRE_1), .phy_mgmt_address(SYNTHESIZED_WIRE_2), .phy_mgmt_writedata(SYNTHESIZED_WIRE_3), .reconfig_to_xcvr(SYNTHESIZED_WIRE_4), .tx_parallel_data(SYNTHESIZED_WIRE_5), .tx_ready(tx_ready), .rx_ready(rx_ready), .tx_serial_data(tx_serial_data), .pll_locked(pll_locked), .rx_is_lockedtoref(rx_ltr), .rx_patterndetect(rx_patterndetect), .rx_syncstatus(rx_syncstatus), .rx_datak(rx_datak), .reconfig_from_xcvr(SYNTHESIZED_WIRE_7), .rx_parallel_data(rx_parallel_data)); reconfig0 b2v_inst1( .mgmt_clk_clk(phy_mgmt_clk), .mgmt_rst_reset(SYNTHESIZED_WIRE_9), .reconfig_from_xcvr(SYNTHESIZED_WIRE_7), .reconfig_busy(reconfig_busy), .reconfig_to_xcvr(SYNTHESIZED_WIRE_4)); constant0 b2v_inst3( .result(SYNTHESIZED_WIRE_2)); constant1 b2v_inst4( .result(SYNTHESIZED_WIRE_3)); always@(posedge rx_ltr) begin begin DFF_inst5 <= SYNTHESIZED_WIRE_8; end end constant2 b2v_inst8( .result(SYNTHESIZED_WIRE_5)); endmodule