Info: Saving generation log to C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/soc_system_generation.rpt Info: Starting: Create simulation model Info: qsys-generate C:\Users\cpalakrx\Downloads\DE10-Standard_v.1.2.9_SystemCD\Demonstration\SoC_FPGA\DE10_Standard_GHRD\soc_system.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=C:\Users\cpalakrx\Downloads\DE10-Standard_v.1.2.9_SystemCD\Demonstration\SoC_FPGA\DE10_Standard_GHRD\soc_system\simulation --family="Cyclone V" --part=5CSXFC6D6F31C6 Progress: Loading DE10_Standard_GHRD/soc_system.qsys Progress: Reading input file Progress: Adding ILC [interrupt_latency_counter 18.1] Progress: Parameterizing module ILC Progress: Adding button_pio [altera_avalon_pio 18.1] Progress: Parameterizing module button_pio Progress: Adding clk_0 [clock_source 18.1] Progress: Parameterizing module clk_0 Progress: Adding dipsw_pio [altera_avalon_pio 18.1] Progress: Parameterizing module dipsw_pio Progress: Adding f2sdram_only_master [altera_jtag_avalon_master 18.1] Progress: Parameterizing module f2sdram_only_master Progress: Adding fpga_only_master [altera_jtag_avalon_master 18.1] Progress: Parameterizing module fpga_only_master Progress: Adding hps_0 [altera_hps 18.1] Progress: Parameterizing module hps_0 Progress: Adding hps_only_master [altera_jtag_avalon_master 18.1] Progress: Parameterizing module hps_only_master Progress: Adding jtag_uart [altera_avalon_jtag_uart 18.1] Progress: Parameterizing module jtag_uart Progress: Adding led_pio [altera_avalon_pio 18.1] Progress: Parameterizing module led_pio Progress: Adding mm_bridge_0 [altera_avalon_mm_bridge 18.1] Progress: Parameterizing module mm_bridge_0 Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 18.1] Progress: Parameterizing module sysid_qsys Progress: Building connections Progress: Parameterizing connections Progress: Validating Progress: Done reading input file Info: soc_system.button_pio: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: soc_system.dipsw_pio: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: soc_system.hps_0: HPS Main PLL counter settings: n = 0 m = 73 Info: soc_system.hps_0: HPS peripherial PLL counter settings: n = 0 m = 39 Warning: soc_system.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz Warning: soc_system.hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz Warning: soc_system.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. Info: soc_system.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: soc_system.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: soc_system.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: soc_system: Generating soc_system "soc_system" for SIM_VERILOG Info: Interconnect is inserted between master hps_0.h2f_lw_axi_master and slave mm_bridge_0.s0 because the master is of type axi and the slave is of type avalon. Info: Interconnect is inserted between master hps_only_master.master and slave hps_0.f2h_axi_slave because the master is of type avalon and the slave is of type axi. Info: Interconnect is inserted between master f2sdram_only_master.master and slave hps_0.f2h_sdram0_data because the master has address signal 32 bit wide, but the slave is 27 bit wide. Info: Interconnect is inserted between master f2sdram_only_master.master and slave hps_0.f2h_sdram0_data because the master has readdata signal 32 bit wide, but the slave is 256 bit wide. Info: Interconnect is inserted between master f2sdram_only_master.master and slave hps_0.f2h_sdram0_data because the master has writedata signal 32 bit wide, but the slave is 256 bit wide. Info: Interconnect is inserted between master f2sdram_only_master.master and slave hps_0.f2h_sdram0_data because the master has byteenable signal 4 bit wide, but the slave is 32 bit wide. Warning: hps_0.f2h_irq0: Cannot connect clock for irq_mapper_001.sender Warning: hps_0.f2h_irq0: Cannot connect reset for irq_mapper_001.sender Warning: hps_0.f2h_irq1: Cannot connect clock for irq_mapper_002.sender Warning: hps_0.f2h_irq1: Cannot connect reset for irq_mapper_002.sender Info: ILC: "soc_system" instantiated interrupt_latency_counter "ILC" Info: button_pio: Starting RTL generation for module 'soc_system_button_pio' Info: button_pio: Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_button_pio --dir=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0003_button_pio_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0003_button_pio_gen//soc_system_button_pio_component_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0003_button_pio_gen/ ] Info: button_pio: Done RTL generation for module 'soc_system_button_pio' Info: button_pio: "soc_system" instantiated altera_avalon_pio "button_pio" Info: dipsw_pio: Starting RTL generation for module 'soc_system_dipsw_pio' Info: dipsw_pio: Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_dipsw_pio --dir=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0004_dipsw_pio_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0004_dipsw_pio_gen//soc_system_dipsw_pio_component_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0004_dipsw_pio_gen/ ] Info: dipsw_pio: Done RTL generation for module 'soc_system_dipsw_pio' Info: dipsw_pio: "soc_system" instantiated altera_avalon_pio "dipsw_pio" Info: f2sdram_only_master: "soc_system" instantiated altera_jtag_avalon_master "f2sdram_only_master" Info: hps_0: "Running for module: hps_0" Info: hps_0: HPS Main PLL counter settings: n = 0 m = 73 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 39 Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz Warning: hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. Info: hps_0: "soc_system" instantiated altera_hps "hps_0" Info: jtag_uart: Starting RTL generation for module 'soc_system_jtag_uart' Info: jtag_uart: Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=soc_system_jtag_uart --dir=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0005_jtag_uart_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0005_jtag_uart_gen//soc_system_jtag_uart_component_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0005_jtag_uart_gen/ ] Info: jtag_uart: Done RTL generation for module 'soc_system_jtag_uart' Info: jtag_uart: "soc_system" instantiated altera_avalon_jtag_uart "jtag_uart" Info: led_pio: Starting RTL generation for module 'soc_system_led_pio' Info: led_pio: Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_led_pio --dir=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0006_led_pio_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0006_led_pio_gen//soc_system_led_pio_component_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0006_led_pio_gen/ ] Info: led_pio: Done RTL generation for module 'soc_system_led_pio' Info: led_pio: "soc_system" instantiated altera_avalon_pio "led_pio" Info: mm_bridge_0: "soc_system" instantiated altera_avalon_mm_bridge "mm_bridge_0" Info: sysid_qsys: "soc_system" instantiated altera_avalon_sysid_qsys "sysid_qsys" Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 Info: mm_interconnect_0: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_0" Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0 Info: mm_interconnect_1: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_1" Info: mm_interconnect_2: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_2" Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 Info: mm_interconnect_3: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_3" Info: irq_mapper: "soc_system" instantiated altera_irq_mapper "irq_mapper" Info: irq_mapper_001: "soc_system" instantiated altera_irq_mapper "irq_mapper_001" Info: irq_mapper_002: "soc_system" instantiated altera_irq_mapper "irq_mapper_002" Info: rst_controller: "soc_system" instantiated altera_reset_controller "rst_controller" Info: jtag_phy_embedded_in_jtag_master: "f2sdram_only_master" instantiated altera_jtag_dc_streaming "jtag_phy_embedded_in_jtag_master" Info: timing_adt: "f2sdram_only_master" instantiated timing_adapter "timing_adt" Info: fifo: "f2sdram_only_master" instantiated altera_avalon_sc_fifo "fifo" Info: b2p: "f2sdram_only_master" instantiated altera_avalon_st_bytes_to_packets "b2p" Info: p2b: "f2sdram_only_master" instantiated altera_avalon_st_packets_to_bytes "p2b" Info: transacto: "f2sdram_only_master" instantiated altera_avalon_packets_to_master "transacto" Info: b2p_adapter: "f2sdram_only_master" instantiated channel_adapter "b2p_adapter" Info: p2b_adapter: "f2sdram_only_master" instantiated channel_adapter "p2b_adapter" Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_avalon_sc_fifo.v Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_avalon_st_pipeline_base.v Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_avalon_st_pipeline_stage.sv Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io" Info: mm_bridge_0_s0_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "mm_bridge_0_s0_translator" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_slave_translator.sv Info: hps_0_h2f_lw_axi_master_agent: "mm_interconnect_0" instantiated altera_merlin_axi_master_ni "hps_0_h2f_lw_axi_master_agent" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_address_alignment.sv Info: mm_bridge_0_s0_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "mm_bridge_0_s0_agent" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_slave_agent.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_burst_uncompressor.sv Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router" Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002" Info: mm_bridge_0_s0_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "mm_bridge_0_s0_burst_adapter" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_burst_adapter.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_burst_adapter_uncmpr.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_burst_adapter_13_1.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_burst_adapter_new.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_incr_burst_converter.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_wrap_burst_converter.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_default_burst_converter.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_address_alignment.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_avalon_st_pipeline_stage.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_avalon_st_pipeline_base.v Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux" Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_arbitrator.sv Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux" Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_arbitrator.sv Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter" Info: mm_bridge_0_m0_translator: "mm_interconnect_1" instantiated altera_merlin_master_translator "mm_bridge_0_m0_translator" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_master_translator.sv Info: mm_bridge_0_m0_agent: "mm_interconnect_1" instantiated altera_merlin_master_agent "mm_bridge_0_m0_agent" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_master_agent.sv Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router" Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002" Info: mm_bridge_0_m0_limiter: "mm_interconnect_1" instantiated altera_merlin_traffic_limiter "mm_bridge_0_m0_limiter" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_avalon_sc_fifo.v Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_avalon_st_pipeline_base.v Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux" Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_arbitrator.sv Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux" Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_arbitrator.sv Info: hps_0_f2h_axi_slave_agent: "mm_interconnect_2" instantiated altera_merlin_axi_slave_ni "hps_0_f2h_axi_slave_agent" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_burst_uncompressor.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_avalon_sc_fifo.v Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_address_alignment.sv Info: router: "mm_interconnect_2" instantiated altera_merlin_router "router" Info: router_001: "mm_interconnect_2" instantiated altera_merlin_router "router_001" Info: cmd_demux: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "cmd_demux" Info: cmd_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "cmd_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_arbitrator.sv Info: rsp_demux: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "rsp_demux" Info: rsp_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "rsp_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_arbitrator.sv Info: hps_0_f2h_axi_slave_wr_cmd_width_adapter: "mm_interconnect_2" instantiated altera_merlin_width_adapter "hps_0_f2h_axi_slave_wr_cmd_width_adapter" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_address_alignment.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_burst_uncompressor.sv Info: router: "mm_interconnect_3" instantiated altera_merlin_router "router" Info: router_001: "mm_interconnect_3" instantiated altera_merlin_router "router_001" Info: cmd_demux: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "cmd_demux" Info: cmd_mux: "mm_interconnect_3" instantiated altera_merlin_multiplexer "cmd_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_arbitrator.sv Info: rsp_mux: "mm_interconnect_3" instantiated altera_merlin_multiplexer "rsp_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_merlin_arbitrator.sv Info: avalon_st_adapter: "mm_interconnect_3" instantiated altera_avalon_st_adapter "avalon_st_adapter" Info: border: "hps_io" instantiated altera_interface_generator "border" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/verbosity_pkg.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/avalon_utilities_pkg.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/avalon_mm_pkg.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_avalon_mm_slave_bfm.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_avalon_interrupt_sink.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_avalon_clock_source.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/submodules/altera_avalon_reset_source.sv Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" Info: soc_system: Done "soc_system" with 65 modules, 192 files Info: qsys-generate succeeded. Info: Finished: Create simulation model Info: Starting: Create Modelsim Project. Info: sim-script-gen --spd=C:\Users\cpalakrx\Downloads\DE10-Standard_v.1.2.9_SystemCD\Demonstration\SoC_FPGA\DE10_Standard_GHRD\soc_system\soc_system.spd --output-directory=C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/ --use-relative-paths=true Info: Doing: ip-make-simscript --spd=C:\Users\cpalakrx\Downloads\DE10-Standard_v.1.2.9_SystemCD\Demonstration\SoC_FPGA\DE10_Standard_GHRD\soc_system\soc_system.spd --output-directory=C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/ --use-relative-paths=true Info: Generating the following file(s) for MODELSIM simulator in C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/ directory: Info: mentor/msim_setup.tcl Info: Generating the following file(s) for VCS simulator in C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/ directory: Info: synopsys/vcs/vcs_setup.sh Info: Generating the following file(s) for VCSMX simulator in C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/ directory: Info: synopsys/vcsmx/synopsys_sim.setup Info: synopsys/vcsmx/vcsmx_setup.sh Info: Generating the following file(s) for NCSIM simulator in C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/ directory: Info: cadence/cds.lib Info: cadence/hdl.var Info: cadence/ncsim_setup.sh Info: 47 .cds.lib files in cadence/cds_libs/ directory Info: Generating the following file(s) for RIVIERA simulator in C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/ directory: Info: aldec/rivierapro_setup.tcl Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/simulation/. Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. Info: Finished: Create Modelsim Project. Info: Starting: Create block symbol file (.bsf) Info: qsys-generate C:\Users\cpalakrx\Downloads\DE10-Standard_v.1.2.9_SystemCD\Demonstration\SoC_FPGA\DE10_Standard_GHRD\soc_system.qsys --block-symbol-file --output-directory=C:\Users\cpalakrx\Downloads\DE10-Standard_v.1.2.9_SystemCD\Demonstration\SoC_FPGA\DE10_Standard_GHRD\soc_system --family="Cyclone V" --part=5CSXFC6D6F31C6 Progress: Loading DE10_Standard_GHRD/soc_system.qsys Progress: Reading input file Progress: Adding ILC [interrupt_latency_counter 18.1] Progress: Parameterizing module ILC Progress: Adding button_pio [altera_avalon_pio 18.1] Progress: Parameterizing module button_pio Progress: Adding clk_0 [clock_source 18.1] Progress: Parameterizing module clk_0 Progress: Adding dipsw_pio [altera_avalon_pio 18.1] Progress: Parameterizing module dipsw_pio Progress: Adding f2sdram_only_master [altera_jtag_avalon_master 18.1] Progress: Parameterizing module f2sdram_only_master Progress: Adding fpga_only_master [altera_jtag_avalon_master 18.1] Progress: Parameterizing module fpga_only_master Progress: Adding hps_0 [altera_hps 18.1] Progress: Parameterizing module hps_0 Progress: Adding hps_only_master [altera_jtag_avalon_master 18.1] Progress: Parameterizing module hps_only_master Progress: Adding jtag_uart [altera_avalon_jtag_uart 18.1] Progress: Parameterizing module jtag_uart Progress: Adding led_pio [altera_avalon_pio 18.1] Progress: Parameterizing module led_pio Progress: Adding mm_bridge_0 [altera_avalon_mm_bridge 18.1] Progress: Parameterizing module mm_bridge_0 Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 18.1] Progress: Parameterizing module sysid_qsys Progress: Building connections Progress: Parameterizing connections Progress: Validating Progress: Done reading input file Info: soc_system.button_pio: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: soc_system.dipsw_pio: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: soc_system.hps_0: HPS Main PLL counter settings: n = 0 m = 73 Info: soc_system.hps_0: HPS peripherial PLL counter settings: n = 0 m = 39 Warning: soc_system.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz Warning: soc_system.hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz Warning: soc_system.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. Info: soc_system.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: soc_system.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: soc_system.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Info: Starting: Create HDL design files for synthesis Info: qsys-generate C:\Users\cpalakrx\Downloads\DE10-Standard_v.1.2.9_SystemCD\Demonstration\SoC_FPGA\DE10_Standard_GHRD\soc_system.qsys --synthesis=VERILOG --output-directory=C:\Users\cpalakrx\Downloads\DE10-Standard_v.1.2.9_SystemCD\Demonstration\SoC_FPGA\DE10_Standard_GHRD\soc_system\synthesis --family="Cyclone V" --part=5CSXFC6D6F31C6 Progress: Loading DE10_Standard_GHRD/soc_system.qsys Progress: Reading input file Progress: Adding ILC [interrupt_latency_counter 18.1] Progress: Parameterizing module ILC Progress: Adding button_pio [altera_avalon_pio 18.1] Progress: Parameterizing module button_pio Progress: Adding clk_0 [clock_source 18.1] Progress: Parameterizing module clk_0 Progress: Adding dipsw_pio [altera_avalon_pio 18.1] Progress: Parameterizing module dipsw_pio Progress: Adding f2sdram_only_master [altera_jtag_avalon_master 18.1] Progress: Parameterizing module f2sdram_only_master Progress: Adding fpga_only_master [altera_jtag_avalon_master 18.1] Progress: Parameterizing module fpga_only_master Progress: Adding hps_0 [altera_hps 18.1] Progress: Parameterizing module hps_0 Progress: Adding hps_only_master [altera_jtag_avalon_master 18.1] Progress: Parameterizing module hps_only_master Progress: Adding jtag_uart [altera_avalon_jtag_uart 18.1] Progress: Parameterizing module jtag_uart Progress: Adding led_pio [altera_avalon_pio 18.1] Progress: Parameterizing module led_pio Progress: Adding mm_bridge_0 [altera_avalon_mm_bridge 18.1] Progress: Parameterizing module mm_bridge_0 Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 18.1] Progress: Parameterizing module sysid_qsys Progress: Building connections Progress: Parameterizing connections Progress: Validating Progress: Done reading input file Info: soc_system.button_pio: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: soc_system.dipsw_pio: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: soc_system.hps_0: HPS Main PLL counter settings: n = 0 m = 73 Info: soc_system.hps_0: HPS peripherial PLL counter settings: n = 0 m = 39 Warning: soc_system.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz Warning: soc_system.hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz Warning: soc_system.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. Info: soc_system.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: soc_system.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: soc_system.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: soc_system: Generating soc_system "soc_system" for QUARTUS_SYNTH Info: Interconnect is inserted between master hps_0.h2f_lw_axi_master and slave mm_bridge_0.s0 because the master is of type axi and the slave is of type avalon. Info: Interconnect is inserted between master hps_only_master.master and slave hps_0.f2h_axi_slave because the master is of type avalon and the slave is of type axi. Info: Interconnect is inserted between master f2sdram_only_master.master and slave hps_0.f2h_sdram0_data because the master has address signal 32 bit wide, but the slave is 27 bit wide. Info: Interconnect is inserted between master f2sdram_only_master.master and slave hps_0.f2h_sdram0_data because the master has readdata signal 32 bit wide, but the slave is 256 bit wide. Info: Interconnect is inserted between master f2sdram_only_master.master and slave hps_0.f2h_sdram0_data because the master has writedata signal 32 bit wide, but the slave is 256 bit wide. Info: Interconnect is inserted between master f2sdram_only_master.master and slave hps_0.f2h_sdram0_data because the master has byteenable signal 4 bit wide, but the slave is 32 bit wide. Warning: hps_0.f2h_irq0: Cannot connect clock for irq_mapper_001.sender Warning: hps_0.f2h_irq0: Cannot connect reset for irq_mapper_001.sender Warning: hps_0.f2h_irq1: Cannot connect clock for irq_mapper_002.sender Warning: hps_0.f2h_irq1: Cannot connect reset for irq_mapper_002.sender Info: ILC: "soc_system" instantiated interrupt_latency_counter "ILC" Info: button_pio: Starting RTL generation for module 'soc_system_button_pio' Info: button_pio: Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_button_pio --dir=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0059_button_pio_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0059_button_pio_gen//soc_system_button_pio_component_configuration.pl --do_build_sim=0 ] Info: button_pio: Done RTL generation for module 'soc_system_button_pio' Info: button_pio: "soc_system" instantiated altera_avalon_pio "button_pio" Info: dipsw_pio: Starting RTL generation for module 'soc_system_dipsw_pio' Info: dipsw_pio: Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_dipsw_pio --dir=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0060_dipsw_pio_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0060_dipsw_pio_gen//soc_system_dipsw_pio_component_configuration.pl --do_build_sim=0 ] Info: dipsw_pio: Done RTL generation for module 'soc_system_dipsw_pio' Info: dipsw_pio: "soc_system" instantiated altera_avalon_pio "dipsw_pio" Info: f2sdram_only_master: "soc_system" instantiated altera_jtag_avalon_master "f2sdram_only_master" Info: hps_0: "Running for module: hps_0" Info: hps_0: HPS Main PLL counter settings: n = 0 m = 73 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 39 Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz Warning: hps_0: "QSPI clock frequency" (desired_qspi_clk_mhz) requested 400.0 MHz, but only achieved 370.0 MHz Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. Info: hps_0: "soc_system" instantiated altera_hps "hps_0" Info: jtag_uart: Starting RTL generation for module 'soc_system_jtag_uart' Info: jtag_uart: Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=soc_system_jtag_uart --dir=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0061_jtag_uart_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0061_jtag_uart_gen//soc_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] Info: jtag_uart: Done RTL generation for module 'soc_system_jtag_uart' Info: jtag_uart: "soc_system" instantiated altera_avalon_jtag_uart "jtag_uart" Info: led_pio: Starting RTL generation for module 'soc_system_led_pio' Info: led_pio: Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_led_pio --dir=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0062_led_pio_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/cpalakrx/AppData/Local/Temp/alt7942_1692654568842957211.dir/0062_led_pio_gen//soc_system_led_pio_component_configuration.pl --do_build_sim=0 ] Info: led_pio: Done RTL generation for module 'soc_system_led_pio' Info: led_pio: "soc_system" instantiated altera_avalon_pio "led_pio" Info: mm_bridge_0: "soc_system" instantiated altera_avalon_mm_bridge "mm_bridge_0" Info: sysid_qsys: "soc_system" instantiated altera_avalon_sysid_qsys "sysid_qsys" Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 Info: mm_interconnect_0: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_0" Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0 Info: mm_interconnect_1: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_1" Info: mm_interconnect_2: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_2" Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 Info: mm_interconnect_3: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_3" Info: irq_mapper: "soc_system" instantiated altera_irq_mapper "irq_mapper" Info: irq_mapper_001: "soc_system" instantiated altera_irq_mapper "irq_mapper_001" Info: irq_mapper_002: "soc_system" instantiated altera_irq_mapper "irq_mapper_002" Info: rst_controller: "soc_system" instantiated altera_reset_controller "rst_controller" Info: jtag_phy_embedded_in_jtag_master: "f2sdram_only_master" instantiated altera_jtag_dc_streaming "jtag_phy_embedded_in_jtag_master" Info: timing_adt: "f2sdram_only_master" instantiated timing_adapter "timing_adt" Info: fifo: "f2sdram_only_master" instantiated altera_avalon_sc_fifo "fifo" Info: b2p: "f2sdram_only_master" instantiated altera_avalon_st_bytes_to_packets "b2p" Info: p2b: "f2sdram_only_master" instantiated altera_avalon_st_packets_to_bytes "p2b" Info: transacto: "f2sdram_only_master" instantiated altera_avalon_packets_to_master "transacto" Info: b2p_adapter: "f2sdram_only_master" instantiated channel_adapter "b2p_adapter" Info: p2b_adapter: "f2sdram_only_master" instantiated channel_adapter "p2b_adapter" Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces" Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io" Info: mm_bridge_0_s0_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "mm_bridge_0_s0_translator" Info: hps_0_h2f_lw_axi_master_agent: "mm_interconnect_0" instantiated altera_merlin_axi_master_ni "hps_0_h2f_lw_axi_master_agent" Info: mm_bridge_0_s0_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "mm_bridge_0_s0_agent" Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router" Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002" Info: mm_bridge_0_s0_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "mm_bridge_0_s0_burst_adapter" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux" Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux" Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux" Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter" Info: mm_bridge_0_m0_translator: "mm_interconnect_1" instantiated altera_merlin_master_translator "mm_bridge_0_m0_translator" Info: mm_bridge_0_m0_agent: "mm_interconnect_1" instantiated altera_merlin_master_agent "mm_bridge_0_m0_agent" Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router" Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002" Info: mm_bridge_0_m0_limiter: "mm_interconnect_1" instantiated altera_merlin_traffic_limiter "mm_bridge_0_m0_limiter" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux" Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux" Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Info: hps_0_f2h_axi_slave_agent: "mm_interconnect_2" instantiated altera_merlin_axi_slave_ni "hps_0_f2h_axi_slave_agent" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv Info: router: "mm_interconnect_2" instantiated altera_merlin_router "router" Info: router_001: "mm_interconnect_2" instantiated altera_merlin_router "router_001" Info: cmd_demux: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "cmd_demux" Info: cmd_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "cmd_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Info: rsp_demux: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "rsp_demux" Info: rsp_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "rsp_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Info: hps_0_f2h_axi_slave_wr_cmd_width_adapter: "mm_interconnect_2" instantiated altera_merlin_width_adapter "hps_0_f2h_axi_slave_wr_cmd_width_adapter" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv Info: router: "mm_interconnect_3" instantiated altera_merlin_router "router" Info: router_001: "mm_interconnect_3" instantiated altera_merlin_router "router_001" Info: cmd_demux: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "cmd_demux" Info: cmd_mux: "mm_interconnect_3" instantiated altera_merlin_multiplexer "cmd_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Info: rsp_mux: "mm_interconnect_3" instantiated altera_merlin_multiplexer "rsp_mux" Info: Reusing file C:/Users/cpalakrx/Downloads/DE10-Standard_v.1.2.9_SystemCD/Demonstration/SoC_FPGA/DE10_Standard_GHRD/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Info: avalon_st_adapter: "mm_interconnect_3" instantiated altera_avalon_st_adapter "avalon_st_adapter" Info: border: "hps_io" instantiated altera_interface_generator "border" Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" Info: soc_system: Done "soc_system" with 65 modules, 133 files Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis